./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe030_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe030_pso.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a4926ac2dce683c4edbf3416b646f7aec42cebb1 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:20:08,147 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:20:08,148 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:20:08,156 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:20:08,156 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:20:08,157 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:20:08,158 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:20:08,159 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:20:08,160 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:20:08,161 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:20:08,161 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:20:08,162 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:20:08,162 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:20:08,163 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:20:08,164 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:20:08,165 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:20:08,165 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:20:08,166 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:20:08,167 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:20:08,169 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:20:08,170 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:20:08,171 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:20:08,171 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:20:08,172 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:20:08,174 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:20:08,174 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:20:08,174 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:20:08,175 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:20:08,175 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:20:08,175 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:20:08,176 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:20:08,176 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:20:08,176 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:20:08,177 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:20:08,177 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:20:08,178 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:20:08,178 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:20:08,178 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:20:08,178 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:20:08,179 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:20:08,179 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:20:08,180 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:20:08,189 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:20:08,189 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:20:08,190 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:20:08,190 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:20:08,190 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:20:08,190 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:20:08,190 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:20:08,191 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:20:08,192 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:20:08,192 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:20:08,193 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:20:08,193 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:20:08,193 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:20:08,193 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:20:08,193 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:20:08,193 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:20:08,194 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:20:08,194 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a4926ac2dce683c4edbf3416b646f7aec42cebb1 [2019-12-07 18:20:08,298 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:20:08,305 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:20:08,308 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:20:08,308 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:20:08,309 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:20:08,309 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe030_pso.opt.i [2019-12-07 18:20:08,348 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/data/311323e59/f8585bff67324061bbdff37107029585/FLAGe66a4a886 [2019-12-07 18:20:08,789 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:20:08,789 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/sv-benchmarks/c/pthread-wmm/safe030_pso.opt.i [2019-12-07 18:20:08,799 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/data/311323e59/f8585bff67324061bbdff37107029585/FLAGe66a4a886 [2019-12-07 18:20:09,116 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/data/311323e59/f8585bff67324061bbdff37107029585 [2019-12-07 18:20:09,122 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:20:09,125 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:20:09,127 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:20:09,128 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:20:09,135 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:20:09,137 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,143 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@296938c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09, skipping insertion in model container [2019-12-07 18:20:09,144 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,160 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:20:09,237 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:20:09,482 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:20:09,490 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:20:09,531 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:20:09,574 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:20:09,575 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09 WrapperNode [2019-12-07 18:20:09,575 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:20:09,575 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:20:09,575 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:20:09,575 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:20:09,581 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,593 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,614 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:20:09,614 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:20:09,614 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:20:09,614 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:20:09,620 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,620 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,623 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,624 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,630 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,633 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,635 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... [2019-12-07 18:20:09,638 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:20:09,638 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:20:09,639 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:20:09,639 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:20:09,639 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:20:09,678 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:20:09,679 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:20:09,679 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:20:09,679 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:20:09,679 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:20:09,680 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:20:09,681 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:20:10,027 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:20:10,028 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:20:10,028 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:20:10 BoogieIcfgContainer [2019-12-07 18:20:10,029 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:20:10,029 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:20:10,029 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:20:10,031 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:20:10,031 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:20:09" (1/3) ... [2019-12-07 18:20:10,032 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb955a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:20:10, skipping insertion in model container [2019-12-07 18:20:10,032 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:20:09" (2/3) ... [2019-12-07 18:20:10,032 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb955a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:20:10, skipping insertion in model container [2019-12-07 18:20:10,032 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:20:10" (3/3) ... [2019-12-07 18:20:10,033 INFO L109 eAbstractionObserver]: Analyzing ICFG safe030_pso.opt.i [2019-12-07 18:20:10,039 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:20:10,039 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:20:10,044 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:20:10,045 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:20:10,067 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,067 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,067 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,067 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,068 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,068 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,068 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,069 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,070 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,070 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,070 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,070 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,070 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,071 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,072 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,073 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,073 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,073 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,073 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,074 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,074 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,074 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,075 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,076 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,077 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,078 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,079 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:20:10,094 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:20:10,110 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:20:10,111 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:20:10,111 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:20:10,111 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:20:10,111 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:20:10,111 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:20:10,111 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:20:10,111 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:20:10,124 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 161 places, 192 transitions [2019-12-07 18:20:10,126 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:20:10,175 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:20:10,175 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:20:10,183 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:20:10,194 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:20:10,220 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:20:10,220 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:20:10,224 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:20:10,233 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 18:20:10,233 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:20:12,996 WARN L192 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-12-07 18:20:13,078 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46210 [2019-12-07 18:20:13,078 INFO L214 etLargeBlockEncoding]: Total number of compositions: 110 [2019-12-07 18:20:13,080 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 81 places, 86 transitions [2019-12-07 18:20:13,766 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15658 states. [2019-12-07 18:20:13,768 INFO L276 IsEmpty]: Start isEmpty. Operand 15658 states. [2019-12-07 18:20:13,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:20:13,773 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:13,774 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:13,774 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:13,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:13,778 INFO L82 PathProgramCache]: Analyzing trace with hash 430910871, now seen corresponding path program 1 times [2019-12-07 18:20:13,784 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:13,784 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986991763] [2019-12-07 18:20:13,784 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:13,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:13,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:13,963 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986991763] [2019-12-07 18:20:13,963 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:13,963 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:20:13,964 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369261224] [2019-12-07 18:20:13,967 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:20:13,967 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:13,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:20:13,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:13,978 INFO L87 Difference]: Start difference. First operand 15658 states. Second operand 3 states. [2019-12-07 18:20:14,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:14,178 INFO L93 Difference]: Finished difference Result 15586 states and 57554 transitions. [2019-12-07 18:20:14,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:20:14,180 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:20:14,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:14,290 INFO L225 Difference]: With dead ends: 15586 [2019-12-07 18:20:14,290 INFO L226 Difference]: Without dead ends: 15248 [2019-12-07 18:20:14,291 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:14,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15248 states. [2019-12-07 18:20:14,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15248 to 15248. [2019-12-07 18:20:14,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15248 states. [2019-12-07 18:20:14,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15248 states to 15248 states and 56345 transitions. [2019-12-07 18:20:14,869 INFO L78 Accepts]: Start accepts. Automaton has 15248 states and 56345 transitions. Word has length 7 [2019-12-07 18:20:14,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:14,870 INFO L462 AbstractCegarLoop]: Abstraction has 15248 states and 56345 transitions. [2019-12-07 18:20:14,870 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:20:14,870 INFO L276 IsEmpty]: Start isEmpty. Operand 15248 states and 56345 transitions. [2019-12-07 18:20:14,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:20:14,874 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:14,874 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:14,874 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:14,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:14,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1550259791, now seen corresponding path program 1 times [2019-12-07 18:20:14,874 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:14,875 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988682569] [2019-12-07 18:20:14,875 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:14,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:14,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:14,946 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988682569] [2019-12-07 18:20:14,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:14,946 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:20:14,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959390380] [2019-12-07 18:20:14,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:20:14,948 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:14,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:20:14,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:20:14,948 INFO L87 Difference]: Start difference. First operand 15248 states and 56345 transitions. Second operand 4 states. [2019-12-07 18:20:15,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:15,294 INFO L93 Difference]: Finished difference Result 24364 states and 86703 transitions. [2019-12-07 18:20:15,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:20:15,295 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:20:15,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:15,395 INFO L225 Difference]: With dead ends: 24364 [2019-12-07 18:20:15,395 INFO L226 Difference]: Without dead ends: 24350 [2019-12-07 18:20:15,396 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:20:15,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24350 states. [2019-12-07 18:20:15,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24350 to 21678. [2019-12-07 18:20:15,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21678 states. [2019-12-07 18:20:15,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21678 states to 21678 states and 78082 transitions. [2019-12-07 18:20:15,929 INFO L78 Accepts]: Start accepts. Automaton has 21678 states and 78082 transitions. Word has length 13 [2019-12-07 18:20:15,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:15,929 INFO L462 AbstractCegarLoop]: Abstraction has 21678 states and 78082 transitions. [2019-12-07 18:20:15,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:20:15,929 INFO L276 IsEmpty]: Start isEmpty. Operand 21678 states and 78082 transitions. [2019-12-07 18:20:15,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:20:15,932 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:15,932 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:15,932 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:15,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:15,932 INFO L82 PathProgramCache]: Analyzing trace with hash -1785022215, now seen corresponding path program 1 times [2019-12-07 18:20:15,932 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:15,933 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673497793] [2019-12-07 18:20:15,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:15,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:15,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:15,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673497793] [2019-12-07 18:20:15,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:15,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:20:15,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475900264] [2019-12-07 18:20:15,971 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:20:15,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:15,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:20:15,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:15,971 INFO L87 Difference]: Start difference. First operand 21678 states and 78082 transitions. Second operand 3 states. [2019-12-07 18:20:16,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:16,007 INFO L93 Difference]: Finished difference Result 12388 states and 38538 transitions. [2019-12-07 18:20:16,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:20:16,008 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 18:20:16,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:16,031 INFO L225 Difference]: With dead ends: 12388 [2019-12-07 18:20:16,031 INFO L226 Difference]: Without dead ends: 12388 [2019-12-07 18:20:16,032 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:16,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12388 states. [2019-12-07 18:20:16,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12388 to 12388. [2019-12-07 18:20:16,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12388 states. [2019-12-07 18:20:16,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12388 states to 12388 states and 38538 transitions. [2019-12-07 18:20:16,277 INFO L78 Accepts]: Start accepts. Automaton has 12388 states and 38538 transitions. Word has length 13 [2019-12-07 18:20:16,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:16,278 INFO L462 AbstractCegarLoop]: Abstraction has 12388 states and 38538 transitions. [2019-12-07 18:20:16,278 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:20:16,278 INFO L276 IsEmpty]: Start isEmpty. Operand 12388 states and 38538 transitions. [2019-12-07 18:20:16,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2019-12-07 18:20:16,279 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:16,279 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:16,279 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:16,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:16,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1922152669, now seen corresponding path program 1 times [2019-12-07 18:20:16,279 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:16,279 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499259402] [2019-12-07 18:20:16,279 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:16,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:16,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:16,322 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499259402] [2019-12-07 18:20:16,323 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:16,323 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:20:16,323 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217351700] [2019-12-07 18:20:16,323 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:20:16,323 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:16,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:20:16,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:20:16,324 INFO L87 Difference]: Start difference. First operand 12388 states and 38538 transitions. Second operand 4 states. [2019-12-07 18:20:16,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:16,339 INFO L93 Difference]: Finished difference Result 1903 states and 4374 transitions. [2019-12-07 18:20:16,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:20:16,339 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2019-12-07 18:20:16,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:16,340 INFO L225 Difference]: With dead ends: 1903 [2019-12-07 18:20:16,340 INFO L226 Difference]: Without dead ends: 1903 [2019-12-07 18:20:16,341 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:20:16,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1903 states. [2019-12-07 18:20:16,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1903 to 1903. [2019-12-07 18:20:16,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1903 states. [2019-12-07 18:20:16,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1903 states to 1903 states and 4374 transitions. [2019-12-07 18:20:16,361 INFO L78 Accepts]: Start accepts. Automaton has 1903 states and 4374 transitions. Word has length 14 [2019-12-07 18:20:16,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:16,361 INFO L462 AbstractCegarLoop]: Abstraction has 1903 states and 4374 transitions. [2019-12-07 18:20:16,361 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:20:16,361 INFO L276 IsEmpty]: Start isEmpty. Operand 1903 states and 4374 transitions. [2019-12-07 18:20:16,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 18:20:16,362 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:16,362 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:16,362 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:16,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:16,363 INFO L82 PathProgramCache]: Analyzing trace with hash -560054606, now seen corresponding path program 1 times [2019-12-07 18:20:16,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:16,363 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339317362] [2019-12-07 18:20:16,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:16,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:16,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:16,504 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339317362] [2019-12-07 18:20:16,504 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:16,504 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:20:16,505 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075155829] [2019-12-07 18:20:16,505 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:20:16,505 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:16,505 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:20:16,505 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:20:16,506 INFO L87 Difference]: Start difference. First operand 1903 states and 4374 transitions. Second operand 7 states. [2019-12-07 18:20:16,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:16,741 INFO L93 Difference]: Finished difference Result 2325 states and 5181 transitions. [2019-12-07 18:20:16,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:20:16,741 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2019-12-07 18:20:16,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:16,743 INFO L225 Difference]: With dead ends: 2325 [2019-12-07 18:20:16,743 INFO L226 Difference]: Without dead ends: 2325 [2019-12-07 18:20:16,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:20:16,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states. [2019-12-07 18:20:16,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2120. [2019-12-07 18:20:16,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2120 states. [2019-12-07 18:20:16,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2120 states to 2120 states and 4797 transitions. [2019-12-07 18:20:16,764 INFO L78 Accepts]: Start accepts. Automaton has 2120 states and 4797 transitions. Word has length 26 [2019-12-07 18:20:16,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:16,764 INFO L462 AbstractCegarLoop]: Abstraction has 2120 states and 4797 transitions. [2019-12-07 18:20:16,765 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:20:16,765 INFO L276 IsEmpty]: Start isEmpty. Operand 2120 states and 4797 transitions. [2019-12-07 18:20:16,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 18:20:16,767 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:16,767 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:16,767 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:16,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:16,768 INFO L82 PathProgramCache]: Analyzing trace with hash 1431449310, now seen corresponding path program 1 times [2019-12-07 18:20:16,768 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:16,768 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782318913] [2019-12-07 18:20:16,768 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:16,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:16,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:16,919 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782318913] [2019-12-07 18:20:16,920 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:16,920 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:20:16,920 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485132751] [2019-12-07 18:20:16,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:20:16,920 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:16,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:20:16,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:20:16,921 INFO L87 Difference]: Start difference. First operand 2120 states and 4797 transitions. Second operand 8 states. [2019-12-07 18:20:17,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:17,187 INFO L93 Difference]: Finished difference Result 2411 states and 5397 transitions. [2019-12-07 18:20:17,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:20:17,187 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2019-12-07 18:20:17,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:17,189 INFO L225 Difference]: With dead ends: 2411 [2019-12-07 18:20:17,189 INFO L226 Difference]: Without dead ends: 2410 [2019-12-07 18:20:17,189 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:20:17,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2410 states. [2019-12-07 18:20:17,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2410 to 2191. [2019-12-07 18:20:17,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2191 states. [2019-12-07 18:20:17,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2191 states to 2191 states and 4962 transitions. [2019-12-07 18:20:17,215 INFO L78 Accepts]: Start accepts. Automaton has 2191 states and 4962 transitions. Word has length 40 [2019-12-07 18:20:17,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:17,216 INFO L462 AbstractCegarLoop]: Abstraction has 2191 states and 4962 transitions. [2019-12-07 18:20:17,216 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:20:17,216 INFO L276 IsEmpty]: Start isEmpty. Operand 2191 states and 4962 transitions. [2019-12-07 18:20:17,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:20:17,220 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:17,221 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:17,221 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:17,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:17,221 INFO L82 PathProgramCache]: Analyzing trace with hash 2147243273, now seen corresponding path program 1 times [2019-12-07 18:20:17,221 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:17,221 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923943178] [2019-12-07 18:20:17,222 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:17,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:17,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:17,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923943178] [2019-12-07 18:20:17,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:17,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:20:17,261 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272214096] [2019-12-07 18:20:17,261 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:20:17,261 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:17,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:20:17,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:17,262 INFO L87 Difference]: Start difference. First operand 2191 states and 4962 transitions. Second operand 3 states. [2019-12-07 18:20:17,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:17,293 INFO L93 Difference]: Finished difference Result 2554 states and 5774 transitions. [2019-12-07 18:20:17,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:20:17,293 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 43 [2019-12-07 18:20:17,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:17,295 INFO L225 Difference]: With dead ends: 2554 [2019-12-07 18:20:17,295 INFO L226 Difference]: Without dead ends: 2554 [2019-12-07 18:20:17,295 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:17,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2554 states. [2019-12-07 18:20:17,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2554 to 2409. [2019-12-07 18:20:17,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2409 states. [2019-12-07 18:20:17,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2409 states to 2409 states and 5479 transitions. [2019-12-07 18:20:17,317 INFO L78 Accepts]: Start accepts. Automaton has 2409 states and 5479 transitions. Word has length 43 [2019-12-07 18:20:17,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:17,317 INFO L462 AbstractCegarLoop]: Abstraction has 2409 states and 5479 transitions. [2019-12-07 18:20:17,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:20:17,317 INFO L276 IsEmpty]: Start isEmpty. Operand 2409 states and 5479 transitions. [2019-12-07 18:20:17,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 18:20:17,319 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:17,320 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:17,320 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:17,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:17,320 INFO L82 PathProgramCache]: Analyzing trace with hash -739088727, now seen corresponding path program 1 times [2019-12-07 18:20:17,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:17,320 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569622474] [2019-12-07 18:20:17,320 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:17,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:17,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:17,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569622474] [2019-12-07 18:20:17,371 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:17,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:20:17,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596861384] [2019-12-07 18:20:17,371 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:20:17,371 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:17,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:20:17,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:20:17,372 INFO L87 Difference]: Start difference. First operand 2409 states and 5479 transitions. Second operand 5 states. [2019-12-07 18:20:17,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:17,662 INFO L93 Difference]: Finished difference Result 3227 states and 7239 transitions. [2019-12-07 18:20:17,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:20:17,663 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 43 [2019-12-07 18:20:17,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:17,665 INFO L225 Difference]: With dead ends: 3227 [2019-12-07 18:20:17,665 INFO L226 Difference]: Without dead ends: 3227 [2019-12-07 18:20:17,665 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:20:17,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3227 states. [2019-12-07 18:20:17,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3227 to 2956. [2019-12-07 18:20:17,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2956 states. [2019-12-07 18:20:17,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2956 states to 2956 states and 6692 transitions. [2019-12-07 18:20:17,695 INFO L78 Accepts]: Start accepts. Automaton has 2956 states and 6692 transitions. Word has length 43 [2019-12-07 18:20:17,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:17,696 INFO L462 AbstractCegarLoop]: Abstraction has 2956 states and 6692 transitions. [2019-12-07 18:20:17,696 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:20:17,696 INFO L276 IsEmpty]: Start isEmpty. Operand 2956 states and 6692 transitions. [2019-12-07 18:20:17,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 18:20:17,699 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:17,699 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:17,699 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:17,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:17,699 INFO L82 PathProgramCache]: Analyzing trace with hash -461664182, now seen corresponding path program 1 times [2019-12-07 18:20:17,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:17,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801312186] [2019-12-07 18:20:17,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:17,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:17,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:17,743 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801312186] [2019-12-07 18:20:17,743 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:17,743 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:20:17,743 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827676696] [2019-12-07 18:20:17,744 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:20:17,744 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:17,744 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:20:17,744 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:17,744 INFO L87 Difference]: Start difference. First operand 2956 states and 6692 transitions. Second operand 3 states. [2019-12-07 18:20:17,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:17,758 INFO L93 Difference]: Finished difference Result 2956 states and 6618 transitions. [2019-12-07 18:20:17,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:20:17,758 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 44 [2019-12-07 18:20:17,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:17,760 INFO L225 Difference]: With dead ends: 2956 [2019-12-07 18:20:17,760 INFO L226 Difference]: Without dead ends: 2956 [2019-12-07 18:20:17,761 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:17,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2956 states. [2019-12-07 18:20:17,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2956 to 2948. [2019-12-07 18:20:17,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2948 states. [2019-12-07 18:20:17,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2948 states to 2948 states and 6602 transitions. [2019-12-07 18:20:17,787 INFO L78 Accepts]: Start accepts. Automaton has 2948 states and 6602 transitions. Word has length 44 [2019-12-07 18:20:17,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:17,787 INFO L462 AbstractCegarLoop]: Abstraction has 2948 states and 6602 transitions. [2019-12-07 18:20:17,787 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:20:17,787 INFO L276 IsEmpty]: Start isEmpty. Operand 2948 states and 6602 transitions. [2019-12-07 18:20:17,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 18:20:17,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:17,790 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:17,790 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:17,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:17,790 INFO L82 PathProgramCache]: Analyzing trace with hash -1572873003, now seen corresponding path program 1 times [2019-12-07 18:20:17,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:17,791 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798074459] [2019-12-07 18:20:17,791 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:17,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:17,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:17,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798074459] [2019-12-07 18:20:17,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:17,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:20:17,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893837872] [2019-12-07 18:20:17,876 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:20:17,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:17,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:20:17,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:20:17,877 INFO L87 Difference]: Start difference. First operand 2948 states and 6602 transitions. Second operand 6 states. [2019-12-07 18:20:18,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:18,018 INFO L93 Difference]: Finished difference Result 5947 states and 13130 transitions. [2019-12-07 18:20:18,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:20:18,018 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 18:20:18,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:18,022 INFO L225 Difference]: With dead ends: 5947 [2019-12-07 18:20:18,022 INFO L226 Difference]: Without dead ends: 3530 [2019-12-07 18:20:18,023 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:20:18,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3530 states. [2019-12-07 18:20:18,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3530 to 3095. [2019-12-07 18:20:18,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3095 states. [2019-12-07 18:20:18,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3095 states to 3095 states and 6521 transitions. [2019-12-07 18:20:18,069 INFO L78 Accepts]: Start accepts. Automaton has 3095 states and 6521 transitions. Word has length 44 [2019-12-07 18:20:18,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:18,069 INFO L462 AbstractCegarLoop]: Abstraction has 3095 states and 6521 transitions. [2019-12-07 18:20:18,069 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:20:18,069 INFO L276 IsEmpty]: Start isEmpty. Operand 3095 states and 6521 transitions. [2019-12-07 18:20:18,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:20:18,074 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:18,074 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:18,074 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:18,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:18,074 INFO L82 PathProgramCache]: Analyzing trace with hash -1276122028, now seen corresponding path program 1 times [2019-12-07 18:20:18,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:18,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707512929] [2019-12-07 18:20:18,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:18,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:18,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:18,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707512929] [2019-12-07 18:20:18,201 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:18,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:20:18,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14241745] [2019-12-07 18:20:18,201 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:20:18,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:18,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:20:18,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:20:18,202 INFO L87 Difference]: Start difference. First operand 3095 states and 6521 transitions. Second operand 6 states. [2019-12-07 18:20:18,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:18,288 INFO L93 Difference]: Finished difference Result 4924 states and 10496 transitions. [2019-12-07 18:20:18,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:20:18,288 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 45 [2019-12-07 18:20:18,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:18,290 INFO L225 Difference]: With dead ends: 4924 [2019-12-07 18:20:18,290 INFO L226 Difference]: Without dead ends: 2048 [2019-12-07 18:20:18,290 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:20:18,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2048 states. [2019-12-07 18:20:18,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2048 to 1885. [2019-12-07 18:20:18,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1885 states. [2019-12-07 18:20:18,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1885 states to 1885 states and 4005 transitions. [2019-12-07 18:20:18,305 INFO L78 Accepts]: Start accepts. Automaton has 1885 states and 4005 transitions. Word has length 45 [2019-12-07 18:20:18,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:18,306 INFO L462 AbstractCegarLoop]: Abstraction has 1885 states and 4005 transitions. [2019-12-07 18:20:18,306 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:20:18,306 INFO L276 IsEmpty]: Start isEmpty. Operand 1885 states and 4005 transitions. [2019-12-07 18:20:18,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:20:18,307 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:18,307 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:18,307 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:18,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:18,308 INFO L82 PathProgramCache]: Analyzing trace with hash -955319009, now seen corresponding path program 1 times [2019-12-07 18:20:18,308 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:18,308 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776383537] [2019-12-07 18:20:18,308 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:18,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:18,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:18,363 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776383537] [2019-12-07 18:20:18,363 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:18,363 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:20:18,363 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541360692] [2019-12-07 18:20:18,364 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:20:18,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:18,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:20:18,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:18,364 INFO L87 Difference]: Start difference. First operand 1885 states and 4005 transitions. Second operand 3 states. [2019-12-07 18:20:18,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:18,399 INFO L93 Difference]: Finished difference Result 1885 states and 3977 transitions. [2019-12-07 18:20:18,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:20:18,399 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-12-07 18:20:18,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:18,400 INFO L225 Difference]: With dead ends: 1885 [2019-12-07 18:20:18,401 INFO L226 Difference]: Without dead ends: 1885 [2019-12-07 18:20:18,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:20:18,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1885 states. [2019-12-07 18:20:18,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1885 to 1783. [2019-12-07 18:20:18,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1783 states. [2019-12-07 18:20:18,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1783 states to 1783 states and 3776 transitions. [2019-12-07 18:20:18,415 INFO L78 Accepts]: Start accepts. Automaton has 1783 states and 3776 transitions. Word has length 45 [2019-12-07 18:20:18,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:18,415 INFO L462 AbstractCegarLoop]: Abstraction has 1783 states and 3776 transitions. [2019-12-07 18:20:18,415 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:20:18,415 INFO L276 IsEmpty]: Start isEmpty. Operand 1783 states and 3776 transitions. [2019-12-07 18:20:18,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:20:18,416 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:18,416 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:18,417 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:18,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:18,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1193320725, now seen corresponding path program 1 times [2019-12-07 18:20:18,417 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:18,417 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195637917] [2019-12-07 18:20:18,417 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:18,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:18,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:18,622 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195637917] [2019-12-07 18:20:18,622 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:18,622 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:20:18,622 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434828872] [2019-12-07 18:20:18,622 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 18:20:18,622 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:18,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:20:18,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:20:18,623 INFO L87 Difference]: Start difference. First operand 1783 states and 3776 transitions. Second operand 12 states. [2019-12-07 18:20:18,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:18,973 INFO L93 Difference]: Finished difference Result 2351 states and 4962 transitions. [2019-12-07 18:20:18,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:20:18,973 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 45 [2019-12-07 18:20:18,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:18,974 INFO L225 Difference]: With dead ends: 2351 [2019-12-07 18:20:18,974 INFO L226 Difference]: Without dead ends: 1927 [2019-12-07 18:20:18,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=303, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:20:18,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1927 states. [2019-12-07 18:20:18,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1927 to 1773. [2019-12-07 18:20:18,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1773 states. [2019-12-07 18:20:18,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 3764 transitions. [2019-12-07 18:20:18,988 INFO L78 Accepts]: Start accepts. Automaton has 1773 states and 3764 transitions. Word has length 45 [2019-12-07 18:20:18,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:18,988 INFO L462 AbstractCegarLoop]: Abstraction has 1773 states and 3764 transitions. [2019-12-07 18:20:18,988 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 18:20:18,988 INFO L276 IsEmpty]: Start isEmpty. Operand 1773 states and 3764 transitions. [2019-12-07 18:20:18,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:20:18,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:18,990 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:18,990 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:18,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:18,990 INFO L82 PathProgramCache]: Analyzing trace with hash -1815536888, now seen corresponding path program 2 times [2019-12-07 18:20:18,990 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:18,990 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948385434] [2019-12-07 18:20:18,990 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:19,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:19,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:19,096 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [948385434] [2019-12-07 18:20:19,096 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:19,096 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:20:19,096 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105399479] [2019-12-07 18:20:19,096 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:20:19,096 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:19,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:20:19,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:20:19,097 INFO L87 Difference]: Start difference. First operand 1773 states and 3764 transitions. Second operand 10 states. [2019-12-07 18:20:19,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:19,322 INFO L93 Difference]: Finished difference Result 2379 states and 5069 transitions. [2019-12-07 18:20:19,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:20:19,323 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 45 [2019-12-07 18:20:19,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:19,324 INFO L225 Difference]: With dead ends: 2379 [2019-12-07 18:20:19,324 INFO L226 Difference]: Without dead ends: 2073 [2019-12-07 18:20:19,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=336, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:20:19,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2073 states. [2019-12-07 18:20:19,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2073 to 1902. [2019-12-07 18:20:19,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1902 states. [2019-12-07 18:20:19,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1902 states to 1902 states and 4012 transitions. [2019-12-07 18:20:19,339 INFO L78 Accepts]: Start accepts. Automaton has 1902 states and 4012 transitions. Word has length 45 [2019-12-07 18:20:19,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:19,339 INFO L462 AbstractCegarLoop]: Abstraction has 1902 states and 4012 transitions. [2019-12-07 18:20:19,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:20:19,339 INFO L276 IsEmpty]: Start isEmpty. Operand 1902 states and 4012 transitions. [2019-12-07 18:20:19,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 18:20:19,341 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:19,341 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:19,341 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:19,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:19,341 INFO L82 PathProgramCache]: Analyzing trace with hash 2121919124, now seen corresponding path program 3 times [2019-12-07 18:20:19,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:19,342 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683110553] [2019-12-07 18:20:19,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:19,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:19,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:19,377 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683110553] [2019-12-07 18:20:19,377 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:19,378 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:20:19,378 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090065128] [2019-12-07 18:20:19,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:20:19,378 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:19,378 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:20:19,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:20:19,378 INFO L87 Difference]: Start difference. First operand 1902 states and 4012 transitions. Second operand 5 states. [2019-12-07 18:20:19,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:19,391 INFO L93 Difference]: Finished difference Result 349 states and 614 transitions. [2019-12-07 18:20:19,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:20:19,391 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 18:20:19,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:19,392 INFO L225 Difference]: With dead ends: 349 [2019-12-07 18:20:19,392 INFO L226 Difference]: Without dead ends: 285 [2019-12-07 18:20:19,392 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:20:19,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 285 states. [2019-12-07 18:20:19,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 285 to 220. [2019-12-07 18:20:19,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2019-12-07 18:20:19,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 387 transitions. [2019-12-07 18:20:19,394 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 387 transitions. Word has length 45 [2019-12-07 18:20:19,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:19,394 INFO L462 AbstractCegarLoop]: Abstraction has 220 states and 387 transitions. [2019-12-07 18:20:19,394 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:20:19,394 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 387 transitions. [2019-12-07 18:20:19,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:20:19,395 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:19,395 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:19,395 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:19,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:19,395 INFO L82 PathProgramCache]: Analyzing trace with hash -1590264344, now seen corresponding path program 1 times [2019-12-07 18:20:19,395 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:19,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064046680] [2019-12-07 18:20:19,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:19,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:20:19,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:20:19,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064046680] [2019-12-07 18:20:19,542 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:20:19,542 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:20:19,542 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620345816] [2019-12-07 18:20:19,542 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:20:19,542 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:20:19,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:20:19,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:20:19,543 INFO L87 Difference]: Start difference. First operand 220 states and 387 transitions. Second operand 13 states. [2019-12-07 18:20:19,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:20:19,692 INFO L93 Difference]: Finished difference Result 376 states and 644 transitions. [2019-12-07 18:20:19,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:20:19,692 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2019-12-07 18:20:19,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:20:19,693 INFO L225 Difference]: With dead ends: 376 [2019-12-07 18:20:19,693 INFO L226 Difference]: Without dead ends: 346 [2019-12-07 18:20:19,693 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=300, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:20:19,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-12-07 18:20:19,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 328. [2019-12-07 18:20:19,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-12-07 18:20:19,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 572 transitions. [2019-12-07 18:20:19,696 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 572 transitions. Word has length 56 [2019-12-07 18:20:19,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:20:19,696 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 572 transitions. [2019-12-07 18:20:19,696 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:20:19,696 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 572 transitions. [2019-12-07 18:20:19,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:20:19,697 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:20:19,697 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:20:19,697 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:20:19,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:20:19,697 INFO L82 PathProgramCache]: Analyzing trace with hash -1475134232, now seen corresponding path program 2 times [2019-12-07 18:20:19,697 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:20:19,698 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28837280] [2019-12-07 18:20:19,698 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:20:19,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:20:19,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:20:19,789 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:20:19,789 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:20:19,792 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2498~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2498~0.base_27|) |v_ULTIMATE.start_main_~#t2498~0.offset_20| 0))) (= (store .cse0 |v_ULTIMATE.start_main_~#t2498~0.base_27| 1) |v_#valid_59|) (= 0 v_~y$r_buff1_thd1~0_54) (= (select .cse0 |v_ULTIMATE.start_main_~#t2498~0.base_27|) 0) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2498~0.base_27|) (= |v_ULTIMATE.start_main_~#t2498~0.offset_20| 0) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2498~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, ULTIMATE.start_main_~#t2499~0.offset=|v_ULTIMATE.start_main_~#t2499~0.offset_17|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t2499~0.base=|v_ULTIMATE.start_main_~#t2499~0.base_20|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_~#t2500~0.offset=|v_ULTIMATE.start_main_~#t2500~0.offset_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_~#t2498~0.offset=|v_ULTIMATE.start_main_~#t2498~0.offset_20|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, ULTIMATE.start_main_~#t2500~0.base=|v_ULTIMATE.start_main_~#t2500~0.base_20|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_~#t2498~0.base=|v_ULTIMATE.start_main_~#t2498~0.base_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t2499~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2499~0.base, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t2500~0.offset, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2498~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, ULTIMATE.start_main_~#t2500~0.base, #memory_int, ULTIMATE.start_main_~#t2498~0.base, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:20:19,792 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2499~0.base_9| 1)) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2499~0.base_9|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2499~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2499~0.base_9|)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2499~0.base_9| 4) |v_#length_15|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2499~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2499~0.base_9|) |v_ULTIMATE.start_main_~#t2499~0.offset_9| 1)) |v_#memory_int_13|) (= 0 |v_ULTIMATE.start_main_~#t2499~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2499~0.base=|v_ULTIMATE.start_main_~#t2499~0.base_9|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2499~0.offset=|v_ULTIMATE.start_main_~#t2499~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2499~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t2499~0.offset, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 18:20:19,793 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2500~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2500~0.base_10|) |v_ULTIMATE.start_main_~#t2500~0.offset_9| 2)) |v_#memory_int_11|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2500~0.base_10| 4)) (= 0 |v_ULTIMATE.start_main_~#t2500~0.offset_9|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2500~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2500~0.base_10|)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2500~0.base_10|)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2500~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t2500~0.base=|v_ULTIMATE.start_main_~#t2500~0.base_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2500~0.offset=|v_ULTIMATE.start_main_~#t2500~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2500~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2500~0.offset] because there is no mapped edge [2019-12-07 18:20:19,793 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-24977062 256))) (not (= (mod ~y$w_buff0_used~0_Out-24977062 256) 0)))) 1 0)) (= 1 ~y$w_buff0_used~0_Out-24977062) (= P2Thread1of1ForFork0_~arg.offset_Out-24977062 |P2Thread1of1ForFork0_#in~arg.offset_In-24977062|) (= |P2Thread1of1ForFork0_#in~arg.base_In-24977062| P2Thread1of1ForFork0_~arg.base_Out-24977062) (= ~y$w_buff0_used~0_In-24977062 ~y$w_buff1_used~0_Out-24977062) (= ~y$w_buff0~0_Out-24977062 2) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062)) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062) (= ~y$w_buff1~0_Out-24977062 ~y$w_buff0~0_In-24977062)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-24977062, ~y$w_buff0~0=~y$w_buff0~0_In-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-24977062, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-24977062, ~y$w_buff1~0=~y$w_buff1~0_Out-24977062, ~y$w_buff0~0=~y$w_buff0~0_Out-24977062, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-24977062} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:20:19,793 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:20:19,794 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-2000280432 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2000280432 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| ~y$w_buff0_used~0_In-2000280432) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2000280432|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:20:19,794 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork2_#t~ite4_Out-1032287144| |P1Thread1of1ForFork2_#t~ite3_Out-1032287144|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1032287144 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1032287144 256)))) (or (and (not .cse0) (not .cse1) .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y$w_buff1~0_In-1032287144)) (and .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y~0_In-1032287144) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, ~y~0=~y~0_In-1032287144, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1032287144|, ~y~0=~y~0_In-1032287144, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1032287144|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:20:19,795 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In439139011 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd3~0_In439139011 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In439139011 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In439139011 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| ~y$w_buff1_used~0_In439139011)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out439139011|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:20:19,795 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In10111743 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In10111743 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| ~y$w_buff0_used~0_In10111743) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out10111743|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:20:19,795 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1807078712 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1807078712 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1807078712 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1807078712 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| 0)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| ~y$w_buff1_used~0_In1807078712) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1807078712|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1375098561 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1375098561 256)))) (or (and (= ~y$r_buff0_thd2~0_In1375098561 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1375098561|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1670259436 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1670259436 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1670259436 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1670259436 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|)) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1670259436 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1670259436|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In16129428 256))) (.cse2 (= ~y$r_buff0_thd3~0_Out16129428 ~y$r_buff0_thd3~0_In16129428)) (.cse1 (= (mod ~y$w_buff0_used~0_In16129428 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out16129428 0) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In16129428} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out16129428, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out16129428|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1318651703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1318651703 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1318651703 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In1318651703 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1318651703|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1318651703| ~y$r_buff1_thd3~0_In1318651703) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1318651703|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:20:19,796 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:20:19,797 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-535386570 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-535386570 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite18_Out-535386570| |ULTIMATE.start_main_#t~ite19_Out-535386570|))) (or (and (not .cse0) .cse1 (not .cse2) (= ~y$w_buff1~0_In-535386570 |ULTIMATE.start_main_#t~ite18_Out-535386570|)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-535386570| ~y~0_In-535386570) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-535386570, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-535386570, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-535386570|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-535386570|, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:20:19,797 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1592832274 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1592832274 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1592832274| ~y$w_buff0_used~0_In-1592832274) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1592832274|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1592832274|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:20:19,797 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-97834117 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-97834117 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-97834117 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-97834117 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-97834117| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite21_Out-97834117| ~y$w_buff1_used~0_In-97834117)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-97834117|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:20:19,798 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1041155812 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1041155812| ~y$r_buff0_thd0~0_In1041155812)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out1041155812|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1041155812|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:20:19,798 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-705899353 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-705899353 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-705899353 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-705899353 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-705899353 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-705899353|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:20:19,798 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1030380200 256) 0))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1030380200 256) 0))) (or (and (= (mod ~y$w_buff1_used~0_In-1030380200 256) 0) .cse0) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-1030380200 256) 0)) (= (mod ~y$w_buff0_used~0_In-1030380200 256) 0))) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= ~y$w_buff0~0_In-1030380200 |ULTIMATE.start_main_#t~ite29_Out-1030380200|) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite29_In-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| ~y$w_buff0~0_In-1030380200)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1030380200|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:20:19,799 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-254870859 256) 0))) (or (and (not .cse0) (= ~y$w_buff1~0_In-254870859 |ULTIMATE.start_main_#t~ite33_Out-254870859|) (= |ULTIMATE.start_main_#t~ite32_In-254870859| |ULTIMATE.start_main_#t~ite32_Out-254870859|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-254870859| ~y$w_buff1~0_In-254870859) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-254870859 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-254870859 256) 0)) (and (= 0 (mod ~y$w_buff1_used~0_In-254870859 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-254870859 256)))) (= |ULTIMATE.start_main_#t~ite32_Out-254870859| |ULTIMATE.start_main_#t~ite33_Out-254870859|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-254870859|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 18:20:19,799 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In984766544 256) 0))) (or (and (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite35_Out984766544|) (= |ULTIMATE.start_main_#t~ite36_Out984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In984766544 256)))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In984766544 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In984766544 256) 0) .cse0) (= (mod ~y$w_buff0_used~0_In984766544 256) 0))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite36_Out984766544|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out984766544|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 18:20:19,800 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:20:19,800 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:20:19,800 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:20:19,850 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:20:19 BasicIcfg [2019-12-07 18:20:19,850 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:20:19,850 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:20:19,850 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:20:19,850 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:20:19,850 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:20:10" (3/4) ... [2019-12-07 18:20:19,852 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:20:19,852 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= |v_#memory_int_23| (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2498~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2498~0.base_27|) |v_ULTIMATE.start_main_~#t2498~0.offset_20| 0))) (= (store .cse0 |v_ULTIMATE.start_main_~#t2498~0.base_27| 1) |v_#valid_59|) (= 0 v_~y$r_buff1_thd1~0_54) (= (select .cse0 |v_ULTIMATE.start_main_~#t2498~0.base_27|) 0) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2498~0.base_27|) (= |v_ULTIMATE.start_main_~#t2498~0.offset_20| 0) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2498~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= v_~y$r_buff1_thd0~0_237 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, ULTIMATE.start_main_~#t2499~0.offset=|v_ULTIMATE.start_main_~#t2499~0.offset_17|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t2499~0.base=|v_ULTIMATE.start_main_~#t2499~0.base_20|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_~#t2500~0.offset=|v_ULTIMATE.start_main_~#t2500~0.offset_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_~#t2498~0.offset=|v_ULTIMATE.start_main_~#t2498~0.offset_20|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, ULTIMATE.start_main_~#t2500~0.base=|v_ULTIMATE.start_main_~#t2500~0.base_20|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_~#t2498~0.base=|v_ULTIMATE.start_main_~#t2498~0.base_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t2499~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2499~0.base, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_~#t2500~0.offset, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2498~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, ULTIMATE.start_main_~#t2500~0.base, #memory_int, ULTIMATE.start_main_~#t2498~0.base, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:20:19,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2499~0.base_9| 1)) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2499~0.base_9|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2499~0.base_9|) (not (= 0 |v_ULTIMATE.start_main_~#t2499~0.base_9|)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2499~0.base_9| 4) |v_#length_15|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2499~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2499~0.base_9|) |v_ULTIMATE.start_main_~#t2499~0.offset_9| 1)) |v_#memory_int_13|) (= 0 |v_ULTIMATE.start_main_~#t2499~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2499~0.base=|v_ULTIMATE.start_main_~#t2499~0.base_9|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2499~0.offset=|v_ULTIMATE.start_main_~#t2499~0.offset_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2499~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t2499~0.offset, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 18:20:19,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2500~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2500~0.base_10|) |v_ULTIMATE.start_main_~#t2500~0.offset_9| 2)) |v_#memory_int_11|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t2500~0.base_10| 4)) (= 0 |v_ULTIMATE.start_main_~#t2500~0.offset_9|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2500~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t2500~0.base_10|)) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2500~0.base_10|)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2500~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t2500~0.base=|v_ULTIMATE.start_main_~#t2500~0.base_10|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_13|, ULTIMATE.start_main_~#t2500~0.offset=|v_ULTIMATE.start_main_~#t2500~0.offset_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2500~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2500~0.offset] because there is no mapped edge [2019-12-07 18:20:19,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-24977062 256))) (not (= (mod ~y$w_buff0_used~0_Out-24977062 256) 0)))) 1 0)) (= 1 ~y$w_buff0_used~0_Out-24977062) (= P2Thread1of1ForFork0_~arg.offset_Out-24977062 |P2Thread1of1ForFork0_#in~arg.offset_In-24977062|) (= |P2Thread1of1ForFork0_#in~arg.base_In-24977062| P2Thread1of1ForFork0_~arg.base_Out-24977062) (= ~y$w_buff0_used~0_In-24977062 ~y$w_buff1_used~0_Out-24977062) (= ~y$w_buff0~0_Out-24977062 2) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062)) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062) (= ~y$w_buff1~0_Out-24977062 ~y$w_buff0~0_In-24977062)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-24977062, ~y$w_buff0~0=~y$w_buff0~0_In-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-24977062, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-24977062, ~y$w_buff1~0=~y$w_buff1~0_Out-24977062, ~y$w_buff0~0=~y$w_buff0~0_Out-24977062, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-24977062} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:20:19,853 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:20:19,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-2000280432 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2000280432 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| ~y$w_buff0_used~0_In-2000280432) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2000280432|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:20:19,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork2_#t~ite4_Out-1032287144| |P1Thread1of1ForFork2_#t~ite3_Out-1032287144|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1032287144 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1032287144 256)))) (or (and (not .cse0) (not .cse1) .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y$w_buff1~0_In-1032287144)) (and .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y~0_In-1032287144) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, ~y~0=~y~0_In-1032287144, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1032287144|, ~y~0=~y~0_In-1032287144, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1032287144|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:20:19,854 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In439139011 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd3~0_In439139011 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In439139011 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In439139011 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| ~y$w_buff1_used~0_In439139011)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out439139011|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:20:19,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In10111743 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In10111743 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| ~y$w_buff0_used~0_In10111743) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out10111743|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:20:19,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1807078712 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1807078712 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1807078712 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1807078712 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| 0)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| ~y$w_buff1_used~0_In1807078712) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1807078712|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:20:19,855 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1375098561 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1375098561 256)))) (or (and (= ~y$r_buff0_thd2~0_In1375098561 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1375098561|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1670259436 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1670259436 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1670259436 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1670259436 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|)) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1670259436 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1670259436|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In16129428 256))) (.cse2 (= ~y$r_buff0_thd3~0_Out16129428 ~y$r_buff0_thd3~0_In16129428)) (.cse1 (= (mod ~y$w_buff0_used~0_In16129428 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out16129428 0) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In16129428} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out16129428, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out16129428|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1318651703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1318651703 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1318651703 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In1318651703 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1318651703|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1318651703| ~y$r_buff1_thd3~0_In1318651703) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1318651703|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:20:19,856 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-535386570 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-535386570 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite18_Out-535386570| |ULTIMATE.start_main_#t~ite19_Out-535386570|))) (or (and (not .cse0) .cse1 (not .cse2) (= ~y$w_buff1~0_In-535386570 |ULTIMATE.start_main_#t~ite18_Out-535386570|)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-535386570| ~y~0_In-535386570) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-535386570, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-535386570, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-535386570|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-535386570|, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:20:19,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1592832274 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1592832274 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1592832274| ~y$w_buff0_used~0_In-1592832274) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1592832274|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1592832274|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:20:19,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-97834117 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-97834117 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-97834117 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-97834117 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-97834117| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite21_Out-97834117| ~y$w_buff1_used~0_In-97834117)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-97834117|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:20:19,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1041155812 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1041155812| ~y$r_buff0_thd0~0_In1041155812)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out1041155812|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1041155812|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:20:19,857 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-705899353 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-705899353 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-705899353 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-705899353 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-705899353 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-705899353|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:20:19,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1030380200 256) 0))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1030380200 256) 0))) (or (and (= (mod ~y$w_buff1_used~0_In-1030380200 256) 0) .cse0) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-1030380200 256) 0)) (= (mod ~y$w_buff0_used~0_In-1030380200 256) 0))) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= ~y$w_buff0~0_In-1030380200 |ULTIMATE.start_main_#t~ite29_Out-1030380200|) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite29_In-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| ~y$w_buff0~0_In-1030380200)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1030380200|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:20:19,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-254870859 256) 0))) (or (and (not .cse0) (= ~y$w_buff1~0_In-254870859 |ULTIMATE.start_main_#t~ite33_Out-254870859|) (= |ULTIMATE.start_main_#t~ite32_In-254870859| |ULTIMATE.start_main_#t~ite32_Out-254870859|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-254870859| ~y$w_buff1~0_In-254870859) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-254870859 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-254870859 256) 0)) (and (= 0 (mod ~y$w_buff1_used~0_In-254870859 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-254870859 256)))) (= |ULTIMATE.start_main_#t~ite32_Out-254870859| |ULTIMATE.start_main_#t~ite33_Out-254870859|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-254870859|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 18:20:19,859 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In984766544 256) 0))) (or (and (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite35_Out984766544|) (= |ULTIMATE.start_main_#t~ite36_Out984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In984766544 256)))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In984766544 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In984766544 256) 0) .cse0) (= (mod ~y$w_buff0_used~0_In984766544 256) 0))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite36_Out984766544|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out984766544|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 18:20:19,859 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 18:20:19,860 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:20:19,860 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:20:19,913 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a05f0a5b-44cb-4dc1-b643-353c856f536b/bin/uautomizer/witness.graphml [2019-12-07 18:20:19,914 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:20:19,915 INFO L168 Benchmark]: Toolchain (without parser) took 10791.27 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 493.9 MB). Free memory was 939.3 MB in the beginning and 789.1 MB in the end (delta: 150.2 MB). Peak memory consumption was 644.1 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,915 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 966.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:20:19,915 INFO L168 Benchmark]: CACSL2BoogieTranslator took 447.64 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -135.5 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,915 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.51 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,916 INFO L168 Benchmark]: Boogie Preprocessor took 24.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:20:19,916 INFO L168 Benchmark]: RCFGBuilder took 390.18 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,916 INFO L168 Benchmark]: TraceAbstraction took 9820.56 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 392.2 MB). Free memory was 1.0 GB in the beginning and 815.2 MB in the end (delta: 198.8 MB). Peak memory consumption was 591.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,916 INFO L168 Benchmark]: Witness Printer took 63.74 ms. Allocated memory is still 1.5 GB. Free memory was 815.2 MB in the beginning and 789.1 MB in the end (delta: 26.0 MB). Peak memory consumption was 26.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:20:19,918 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 966.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 447.64 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -135.5 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.51 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 24.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 390.18 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.5 MB). Peak memory consumption was 55.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 9820.56 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 392.2 MB). Free memory was 1.0 GB in the beginning and 815.2 MB in the end (delta: 198.8 MB). Peak memory consumption was 591.0 MB. Max. memory is 11.5 GB. * Witness Printer took 63.74 ms. Allocated memory is still 1.5 GB. Free memory was 815.2 MB in the beginning and 789.1 MB in the end (delta: 26.0 MB). Peak memory consumption was 26.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 161 ProgramPointsBefore, 81 ProgramPointsAfterwards, 192 TransitionsBefore, 86 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 30 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 4050 VarBasedMoverChecksPositive, 194 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 46210 CheckedPairsTotal, 110 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L798] FCALL, FORK 0 pthread_create(&t2498, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L800] FCALL, FORK 0 pthread_create(&t2499, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t2500, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L765] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L766] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L767] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L768] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L769] 3 y$r_buff0_thd3 = (_Bool)1 [L772] 3 z = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L775] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L740] 2 x = 2 [L743] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L775] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L746] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L776] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L746] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L777] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L747] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L748] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L749] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L808] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L808] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L809] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L810] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L811] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L812] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L815] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L816] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L817] 0 y$flush_delayed = weak$$choice2 [L818] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L820] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L821] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L822] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L825] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L826] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 152 locations, 2 error locations. Result: UNSAFE, OverallTime: 9.6s, OverallIterations: 17, TraceHistogramMax: 1, AutomataDifference: 2.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2161 SDtfs, 2128 SDslu, 5964 SDs, 0 SdLazy, 2196 SolverSat, 133 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 135 GetRequests, 21 SyntacticMatches, 8 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=21678occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.5s AutomataMinimizationTime, 16 MinimizatonAttempts, 4628 StatesRemovedByMinimization, 13 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 624 NumberOfCodeBlocks, 624 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 552 ConstructedInterpolants, 0 QuantifiedInterpolants, 132150 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 16 InterpolantComputations, 16 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...