./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe030_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe030_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0fe6e14686a8f189a613e7a8d687dac9171f59aa ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:59:28,959 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:59:28,960 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:59:28,969 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:59:28,969 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:59:28,970 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:59:28,971 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:59:28,972 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:59:28,974 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:59:28,975 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:59:28,976 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:59:28,977 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:59:28,977 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:59:28,978 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:59:28,979 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:59:28,980 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:59:28,981 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:59:28,981 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:59:28,983 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:59:28,985 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:59:28,986 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:59:28,987 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:59:28,988 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:59:28,989 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:59:28,991 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:59:28,991 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:59:28,991 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:59:28,992 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:59:28,992 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:59:28,993 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:59:28,993 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:59:28,994 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:59:28,994 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:59:28,995 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:59:28,995 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:59:28,996 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:59:28,996 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:59:28,996 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:59:28,996 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:59:28,997 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:59:28,998 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:59:28,998 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:59:29,010 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:59:29,010 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:59:29,011 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:59:29,011 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:59:29,011 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:59:29,011 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:59:29,012 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:59:29,013 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:59:29,013 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:59:29,013 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:59:29,013 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:59:29,013 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:59:29,013 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:29,014 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:59:29,014 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:59:29,015 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:59:29,015 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0fe6e14686a8f189a613e7a8d687dac9171f59aa [2019-12-07 18:59:29,123 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:59:29,131 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:59:29,134 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:59:29,136 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:59:29,136 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:59:29,137 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe030_rmo.opt.i [2019-12-07 18:59:29,181 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/data/041045e7a/ebdef337de5b4fc287b2fc6a374af538/FLAG081e048b0 [2019-12-07 18:59:29,614 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:59:29,615 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/sv-benchmarks/c/pthread-wmm/safe030_rmo.opt.i [2019-12-07 18:59:29,626 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/data/041045e7a/ebdef337de5b4fc287b2fc6a374af538/FLAG081e048b0 [2019-12-07 18:59:29,983 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/data/041045e7a/ebdef337de5b4fc287b2fc6a374af538 [2019-12-07 18:59:29,989 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:59:29,991 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:59:29,992 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:29,992 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:59:29,997 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:59:29,997 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:29" (1/1) ... [2019-12-07 18:59:30,000 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@296938c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:29, skipping insertion in model container [2019-12-07 18:59:30,000 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:29" (1/1) ... [2019-12-07 18:59:30,009 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:59:30,049 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:59:30,322 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:30,331 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:59:30,382 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:30,441 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:59:30,442 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30 WrapperNode [2019-12-07 18:59:30,442 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:30,442 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:30,442 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:59:30,443 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:59:30,450 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,467 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,491 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:30,491 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:59:30,491 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:59:30,491 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:59:30,498 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,498 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,501 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,502 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,508 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,511 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,514 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... [2019-12-07 18:59:30,517 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:59:30,517 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:59:30,517 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:59:30,518 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:59:30,518 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:59:30,564 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:59:30,564 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:59:30,564 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:59:30,565 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:59:30,565 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:59:30,565 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:59:30,565 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:59:30,566 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:59:30,905 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:59:30,905 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:59:30,906 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30 BoogieIcfgContainer [2019-12-07 18:59:30,906 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:59:30,907 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:59:30,907 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:59:30,908 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:59:30,909 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:59:29" (1/3) ... [2019-12-07 18:59:30,909 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb955a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:30, skipping insertion in model container [2019-12-07 18:59:30,909 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:30" (2/3) ... [2019-12-07 18:59:30,909 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3cb955a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:30, skipping insertion in model container [2019-12-07 18:59:30,910 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30" (3/3) ... [2019-12-07 18:59:30,911 INFO L109 eAbstractionObserver]: Analyzing ICFG safe030_rmo.opt.i [2019-12-07 18:59:30,917 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:59:30,917 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:59:30,922 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:59:30,922 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:59:30,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,943 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,943 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,943 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,944 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,944 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,944 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,944 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,945 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,946 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,947 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,948 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,949 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,950 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,951 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,952 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,953 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:30,964 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:59:30,976 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:59:30,976 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:59:30,976 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:59:30,977 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:59:30,977 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:59:30,977 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:59:30,977 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:59:30,977 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:59:30,987 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 161 places, 192 transitions [2019-12-07 18:59:30,989 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:59:31,037 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:59:31,037 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:31,045 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:59:31,058 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 161 places, 192 transitions [2019-12-07 18:59:31,084 INFO L134 PetriNetUnfolder]: 41/189 cut-off events. [2019-12-07 18:59:31,085 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:31,088 INFO L76 FinitePrefix]: Finished finitePrefix Result has 199 conditions, 189 events. 41/189 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 462 event pairs. 9/155 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:59:31,097 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 18:59:31,098 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:59:33,886 WARN L192 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 85 DAG size of output: 83 [2019-12-07 18:59:33,966 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46210 [2019-12-07 18:59:33,966 INFO L214 etLargeBlockEncoding]: Total number of compositions: 110 [2019-12-07 18:59:33,968 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 81 places, 86 transitions [2019-12-07 18:59:34,640 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15658 states. [2019-12-07 18:59:34,641 INFO L276 IsEmpty]: Start isEmpty. Operand 15658 states. [2019-12-07 18:59:34,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:59:34,645 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:34,646 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:34,646 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:34,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:34,650 INFO L82 PathProgramCache]: Analyzing trace with hash 430910871, now seen corresponding path program 1 times [2019-12-07 18:59:34,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:34,656 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986991763] [2019-12-07 18:59:34,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:34,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:34,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:34,828 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986991763] [2019-12-07 18:59:34,829 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:34,829 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:59:34,830 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870153576] [2019-12-07 18:59:34,834 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:34,834 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:34,846 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:34,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:34,849 INFO L87 Difference]: Start difference. First operand 15658 states. Second operand 3 states. [2019-12-07 18:59:35,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:35,068 INFO L93 Difference]: Finished difference Result 15586 states and 57554 transitions. [2019-12-07 18:59:35,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:35,069 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:59:35,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:35,183 INFO L225 Difference]: With dead ends: 15586 [2019-12-07 18:59:35,184 INFO L226 Difference]: Without dead ends: 15248 [2019-12-07 18:59:35,184 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:35,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15248 states. [2019-12-07 18:59:35,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15248 to 15248. [2019-12-07 18:59:35,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15248 states. [2019-12-07 18:59:35,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15248 states to 15248 states and 56345 transitions. [2019-12-07 18:59:35,818 INFO L78 Accepts]: Start accepts. Automaton has 15248 states and 56345 transitions. Word has length 7 [2019-12-07 18:59:35,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:35,819 INFO L462 AbstractCegarLoop]: Abstraction has 15248 states and 56345 transitions. [2019-12-07 18:59:35,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:35,820 INFO L276 IsEmpty]: Start isEmpty. Operand 15248 states and 56345 transitions. [2019-12-07 18:59:35,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:59:35,823 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:35,823 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:35,823 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:35,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:35,824 INFO L82 PathProgramCache]: Analyzing trace with hash 1550259791, now seen corresponding path program 1 times [2019-12-07 18:59:35,824 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:35,824 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982336363] [2019-12-07 18:59:35,824 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:35,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:35,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:35,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982336363] [2019-12-07 18:59:35,884 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:35,884 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:35,884 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612533838] [2019-12-07 18:59:35,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:59:35,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:35,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:59:35,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:59:35,886 INFO L87 Difference]: Start difference. First operand 15248 states and 56345 transitions. Second operand 4 states. [2019-12-07 18:59:36,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:36,201 INFO L93 Difference]: Finished difference Result 24364 states and 86703 transitions. [2019-12-07 18:59:36,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:59:36,202 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:59:36,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:36,317 INFO L225 Difference]: With dead ends: 24364 [2019-12-07 18:59:36,317 INFO L226 Difference]: Without dead ends: 24350 [2019-12-07 18:59:36,318 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:59:36,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24350 states. [2019-12-07 18:59:36,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24350 to 21678. [2019-12-07 18:59:36,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21678 states. [2019-12-07 18:59:36,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21678 states to 21678 states and 78082 transitions. [2019-12-07 18:59:36,838 INFO L78 Accepts]: Start accepts. Automaton has 21678 states and 78082 transitions. Word has length 13 [2019-12-07 18:59:36,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:36,838 INFO L462 AbstractCegarLoop]: Abstraction has 21678 states and 78082 transitions. [2019-12-07 18:59:36,838 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:59:36,838 INFO L276 IsEmpty]: Start isEmpty. Operand 21678 states and 78082 transitions. [2019-12-07 18:59:36,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:59:36,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:36,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:36,842 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:36,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:36,842 INFO L82 PathProgramCache]: Analyzing trace with hash -1785022215, now seen corresponding path program 1 times [2019-12-07 18:59:36,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:36,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333735575] [2019-12-07 18:59:36,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:36,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:36,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:36,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333735575] [2019-12-07 18:59:36,904 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:36,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:36,904 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054604958] [2019-12-07 18:59:36,904 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:59:36,904 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:36,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:59:36,905 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:59:36,905 INFO L87 Difference]: Start difference. First operand 21678 states and 78082 transitions. Second operand 4 states. [2019-12-07 18:59:37,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:37,079 INFO L93 Difference]: Finished difference Result 26634 states and 94744 transitions. [2019-12-07 18:59:37,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:59:37,080 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:59:37,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:37,140 INFO L225 Difference]: With dead ends: 26634 [2019-12-07 18:59:37,140 INFO L226 Difference]: Without dead ends: 26634 [2019-12-07 18:59:37,140 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:59:37,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26634 states. [2019-12-07 18:59:37,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26634 to 23780. [2019-12-07 18:59:37,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23780 states. [2019-12-07 18:59:37,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23780 states to 23780 states and 85353 transitions. [2019-12-07 18:59:37,617 INFO L78 Accepts]: Start accepts. Automaton has 23780 states and 85353 transitions. Word has length 13 [2019-12-07 18:59:37,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:37,618 INFO L462 AbstractCegarLoop]: Abstraction has 23780 states and 85353 transitions. [2019-12-07 18:59:37,618 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:59:37,618 INFO L276 IsEmpty]: Start isEmpty. Operand 23780 states and 85353 transitions. [2019-12-07 18:59:37,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:59:37,622 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:37,622 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:37,623 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:37,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:37,623 INFO L82 PathProgramCache]: Analyzing trace with hash -1491137103, now seen corresponding path program 1 times [2019-12-07 18:59:37,623 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:37,623 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809683444] [2019-12-07 18:59:37,623 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:37,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:37,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:37,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809683444] [2019-12-07 18:59:37,670 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:37,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:59:37,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678031435] [2019-12-07 18:59:37,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:59:37,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:37,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:59:37,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:59:37,672 INFO L87 Difference]: Start difference. First operand 23780 states and 85353 transitions. Second operand 5 states. [2019-12-07 18:59:38,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:38,011 INFO L93 Difference]: Finished difference Result 32276 states and 113793 transitions. [2019-12-07 18:59:38,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:59:38,011 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:59:38,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:38,067 INFO L225 Difference]: With dead ends: 32276 [2019-12-07 18:59:38,067 INFO L226 Difference]: Without dead ends: 32262 [2019-12-07 18:59:38,068 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:59:38,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32262 states. [2019-12-07 18:59:38,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32262 to 23678. [2019-12-07 18:59:38,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23678 states. [2019-12-07 18:59:38,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23678 states to 23678 states and 84856 transitions. [2019-12-07 18:59:38,622 INFO L78 Accepts]: Start accepts. Automaton has 23678 states and 84856 transitions. Word has length 19 [2019-12-07 18:59:38,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:38,622 INFO L462 AbstractCegarLoop]: Abstraction has 23678 states and 84856 transitions. [2019-12-07 18:59:38,623 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:59:38,623 INFO L276 IsEmpty]: Start isEmpty. Operand 23678 states and 84856 transitions. [2019-12-07 18:59:38,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:59:38,639 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:38,640 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:38,640 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:38,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:38,640 INFO L82 PathProgramCache]: Analyzing trace with hash -1614044955, now seen corresponding path program 1 times [2019-12-07 18:59:38,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:38,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844478787] [2019-12-07 18:59:38,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:38,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:38,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:38,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844478787] [2019-12-07 18:59:38,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:38,698 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:59:38,698 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473117499] [2019-12-07 18:59:38,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:59:38,699 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:38,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:59:38,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:59:38,699 INFO L87 Difference]: Start difference. First operand 23678 states and 84856 transitions. Second operand 5 states. [2019-12-07 18:59:38,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:38,931 INFO L93 Difference]: Finished difference Result 30866 states and 109434 transitions. [2019-12-07 18:59:38,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:59:38,932 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2019-12-07 18:59:38,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:38,984 INFO L225 Difference]: With dead ends: 30866 [2019-12-07 18:59:38,984 INFO L226 Difference]: Without dead ends: 30850 [2019-12-07 18:59:38,985 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:59:39,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30850 states. [2019-12-07 18:59:39,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30850 to 27838. [2019-12-07 18:59:39,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27838 states. [2019-12-07 18:59:39,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27838 states to 27838 states and 99028 transitions. [2019-12-07 18:59:39,520 INFO L78 Accepts]: Start accepts. Automaton has 27838 states and 99028 transitions. Word has length 27 [2019-12-07 18:59:39,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:39,521 INFO L462 AbstractCegarLoop]: Abstraction has 27838 states and 99028 transitions. [2019-12-07 18:59:39,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:59:39,521 INFO L276 IsEmpty]: Start isEmpty. Operand 27838 states and 99028 transitions. [2019-12-07 18:59:39,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:59:39,545 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:39,545 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:39,545 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:39,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:39,546 INFO L82 PathProgramCache]: Analyzing trace with hash -633448160, now seen corresponding path program 1 times [2019-12-07 18:59:39,546 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:39,546 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748216502] [2019-12-07 18:59:39,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:39,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:39,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:39,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748216502] [2019-12-07 18:59:39,586 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:39,586 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:59:39,586 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435363002] [2019-12-07 18:59:39,586 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:39,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:39,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:39,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:39,586 INFO L87 Difference]: Start difference. First operand 27838 states and 99028 transitions. Second operand 3 states. [2019-12-07 18:59:39,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:39,722 INFO L93 Difference]: Finished difference Result 33728 states and 120449 transitions. [2019-12-07 18:59:39,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:39,723 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 18:59:39,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:39,781 INFO L225 Difference]: With dead ends: 33728 [2019-12-07 18:59:39,781 INFO L226 Difference]: Without dead ends: 33728 [2019-12-07 18:59:39,781 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:39,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33728 states. [2019-12-07 18:59:40,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33728 to 31198. [2019-12-07 18:59:40,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31198 states. [2019-12-07 18:59:40,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31198 states to 31198 states and 111684 transitions. [2019-12-07 18:59:40,314 INFO L78 Accepts]: Start accepts. Automaton has 31198 states and 111684 transitions. Word has length 32 [2019-12-07 18:59:40,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:40,315 INFO L462 AbstractCegarLoop]: Abstraction has 31198 states and 111684 transitions. [2019-12-07 18:59:40,315 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:40,315 INFO L276 IsEmpty]: Start isEmpty. Operand 31198 states and 111684 transitions. [2019-12-07 18:59:40,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:59:40,340 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:40,340 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:40,340 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:40,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:40,340 INFO L82 PathProgramCache]: Analyzing trace with hash 775187136, now seen corresponding path program 1 times [2019-12-07 18:59:40,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:40,341 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585755609] [2019-12-07 18:59:40,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:40,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:40,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:40,367 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585755609] [2019-12-07 18:59:40,367 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:40,368 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:40,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145069585] [2019-12-07 18:59:40,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:40,368 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:40,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:40,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:40,368 INFO L87 Difference]: Start difference. First operand 31198 states and 111684 transitions. Second operand 3 states. [2019-12-07 18:59:40,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:40,474 INFO L93 Difference]: Finished difference Result 17541 states and 54208 transitions. [2019-12-07 18:59:40,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:40,475 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2019-12-07 18:59:40,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:40,494 INFO L225 Difference]: With dead ends: 17541 [2019-12-07 18:59:40,494 INFO L226 Difference]: Without dead ends: 17541 [2019-12-07 18:59:40,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:40,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17541 states. [2019-12-07 18:59:40,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17541 to 17541. [2019-12-07 18:59:40,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17541 states. [2019-12-07 18:59:40,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17541 states to 17541 states and 54208 transitions. [2019-12-07 18:59:40,728 INFO L78 Accepts]: Start accepts. Automaton has 17541 states and 54208 transitions. Word has length 32 [2019-12-07 18:59:40,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:40,728 INFO L462 AbstractCegarLoop]: Abstraction has 17541 states and 54208 transitions. [2019-12-07 18:59:40,729 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:40,729 INFO L276 IsEmpty]: Start isEmpty. Operand 17541 states and 54208 transitions. [2019-12-07 18:59:40,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:59:40,741 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:40,741 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:40,741 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:40,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:40,742 INFO L82 PathProgramCache]: Analyzing trace with hash 1291274326, now seen corresponding path program 1 times [2019-12-07 18:59:40,742 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:40,742 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984465769] [2019-12-07 18:59:40,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:40,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:40,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:40,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984465769] [2019-12-07 18:59:40,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:40,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:40,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397611243] [2019-12-07 18:59:40,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:40,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:40,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:40,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:40,780 INFO L87 Difference]: Start difference. First operand 17541 states and 54208 transitions. Second operand 3 states. [2019-12-07 18:59:40,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:40,847 INFO L93 Difference]: Finished difference Result 17541 states and 54000 transitions. [2019-12-07 18:59:40,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:40,847 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 18:59:40,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:40,867 INFO L225 Difference]: With dead ends: 17541 [2019-12-07 18:59:40,867 INFO L226 Difference]: Without dead ends: 17541 [2019-12-07 18:59:40,867 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:40,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17541 states. [2019-12-07 18:59:41,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17541 to 17541. [2019-12-07 18:59:41,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17541 states. [2019-12-07 18:59:41,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17541 states to 17541 states and 54000 transitions. [2019-12-07 18:59:41,104 INFO L78 Accepts]: Start accepts. Automaton has 17541 states and 54000 transitions. Word has length 33 [2019-12-07 18:59:41,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:41,104 INFO L462 AbstractCegarLoop]: Abstraction has 17541 states and 54000 transitions. [2019-12-07 18:59:41,104 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:41,104 INFO L276 IsEmpty]: Start isEmpty. Operand 17541 states and 54000 transitions. [2019-12-07 18:59:41,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 18:59:41,116 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:41,117 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:41,117 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:41,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:41,117 INFO L82 PathProgramCache]: Analyzing trace with hash -986581286, now seen corresponding path program 1 times [2019-12-07 18:59:41,117 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:41,117 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710612671] [2019-12-07 18:59:41,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:41,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:41,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:41,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710612671] [2019-12-07 18:59:41,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:41,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:59:41,185 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271743508] [2019-12-07 18:59:41,185 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:59:41,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:41,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:59:41,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:59:41,186 INFO L87 Difference]: Start difference. First operand 17541 states and 54000 transitions. Second operand 6 states. [2019-12-07 18:59:41,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:41,397 INFO L93 Difference]: Finished difference Result 39110 states and 121229 transitions. [2019-12-07 18:59:41,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:59:41,397 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2019-12-07 18:59:41,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:41,425 INFO L225 Difference]: With dead ends: 39110 [2019-12-07 18:59:41,425 INFO L226 Difference]: Without dead ends: 24298 [2019-12-07 18:59:41,425 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:59:41,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24298 states. [2019-12-07 18:59:41,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24298 to 21545. [2019-12-07 18:59:41,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21545 states. [2019-12-07 18:59:41,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21545 states to 21545 states and 64972 transitions. [2019-12-07 18:59:41,770 INFO L78 Accepts]: Start accepts. Automaton has 21545 states and 64972 transitions. Word has length 33 [2019-12-07 18:59:41,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:41,771 INFO L462 AbstractCegarLoop]: Abstraction has 21545 states and 64972 transitions. [2019-12-07 18:59:41,771 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:59:41,771 INFO L276 IsEmpty]: Start isEmpty. Operand 21545 states and 64972 transitions. [2019-12-07 18:59:41,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:59:41,782 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:41,782 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:41,782 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:41,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:41,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1833353799, now seen corresponding path program 1 times [2019-12-07 18:59:41,782 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:41,782 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357386273] [2019-12-07 18:59:41,782 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:41,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:41,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:41,837 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357386273] [2019-12-07 18:59:41,837 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:41,837 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:59:41,838 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136292505] [2019-12-07 18:59:41,838 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:59:41,838 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:41,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:59:41,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:59:41,838 INFO L87 Difference]: Start difference. First operand 21545 states and 64972 transitions. Second operand 6 states. [2019-12-07 18:59:42,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:42,187 INFO L93 Difference]: Finished difference Result 25124 states and 75040 transitions. [2019-12-07 18:59:42,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:59:42,188 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 18:59:42,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:42,217 INFO L225 Difference]: With dead ends: 25124 [2019-12-07 18:59:42,217 INFO L226 Difference]: Without dead ends: 24712 [2019-12-07 18:59:42,217 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:59:42,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24712 states. [2019-12-07 18:59:42,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24712 to 19573. [2019-12-07 18:59:42,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19573 states. [2019-12-07 18:59:42,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19573 states to 19573 states and 59529 transitions. [2019-12-07 18:59:42,516 INFO L78 Accepts]: Start accepts. Automaton has 19573 states and 59529 transitions. Word has length 34 [2019-12-07 18:59:42,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:42,516 INFO L462 AbstractCegarLoop]: Abstraction has 19573 states and 59529 transitions. [2019-12-07 18:59:42,516 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:59:42,516 INFO L276 IsEmpty]: Start isEmpty. Operand 19573 states and 59529 transitions. [2019-12-07 18:59:42,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:59:42,525 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:42,525 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:42,525 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:42,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:42,526 INFO L82 PathProgramCache]: Analyzing trace with hash 638623931, now seen corresponding path program 1 times [2019-12-07 18:59:42,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:42,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711970956] [2019-12-07 18:59:42,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:42,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:42,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:42,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711970956] [2019-12-07 18:59:42,666 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:42,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:59:42,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652637412] [2019-12-07 18:59:42,666 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:59:42,666 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:42,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:59:42,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:59:42,667 INFO L87 Difference]: Start difference. First operand 19573 states and 59529 transitions. Second operand 10 states. [2019-12-07 18:59:43,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:43,066 INFO L93 Difference]: Finished difference Result 37283 states and 114653 transitions. [2019-12-07 18:59:43,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:59:43,066 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2019-12-07 18:59:43,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:43,107 INFO L225 Difference]: With dead ends: 37283 [2019-12-07 18:59:43,107 INFO L226 Difference]: Without dead ends: 31719 [2019-12-07 18:59:43,108 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=82, Invalid=338, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:59:43,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31719 states. [2019-12-07 18:59:43,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31719 to 23203. [2019-12-07 18:59:43,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23203 states. [2019-12-07 18:59:43,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23203 states to 23203 states and 70316 transitions. [2019-12-07 18:59:43,500 INFO L78 Accepts]: Start accepts. Automaton has 23203 states and 70316 transitions. Word has length 34 [2019-12-07 18:59:43,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:43,500 INFO L462 AbstractCegarLoop]: Abstraction has 23203 states and 70316 transitions. [2019-12-07 18:59:43,500 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:59:43,500 INFO L276 IsEmpty]: Start isEmpty. Operand 23203 states and 70316 transitions. [2019-12-07 18:59:43,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:59:43,516 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:43,516 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:43,516 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:43,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:43,516 INFO L82 PathProgramCache]: Analyzing trace with hash 1676958407, now seen corresponding path program 2 times [2019-12-07 18:59:43,516 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:43,517 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564721899] [2019-12-07 18:59:43,517 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:43,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:43,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:43,611 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564721899] [2019-12-07 18:59:43,611 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:43,611 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:59:43,611 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816270828] [2019-12-07 18:59:43,612 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:59:43,612 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:43,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:59:43,612 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:59:43,612 INFO L87 Difference]: Start difference. First operand 23203 states and 70316 transitions. Second operand 9 states. [2019-12-07 18:59:43,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:43,925 INFO L93 Difference]: Finished difference Result 44604 states and 138140 transitions. [2019-12-07 18:59:43,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:59:43,925 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2019-12-07 18:59:43,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:44,016 INFO L225 Difference]: With dead ends: 44604 [2019-12-07 18:59:44,016 INFO L226 Difference]: Without dead ends: 39445 [2019-12-07 18:59:44,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=267, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:59:44,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39445 states. [2019-12-07 18:59:44,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39445 to 22895. [2019-12-07 18:59:44,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22895 states. [2019-12-07 18:59:44,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22895 states to 22895 states and 69360 transitions. [2019-12-07 18:59:44,401 INFO L78 Accepts]: Start accepts. Automaton has 22895 states and 69360 transitions. Word has length 34 [2019-12-07 18:59:44,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:44,402 INFO L462 AbstractCegarLoop]: Abstraction has 22895 states and 69360 transitions. [2019-12-07 18:59:44,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:59:44,402 INFO L276 IsEmpty]: Start isEmpty. Operand 22895 states and 69360 transitions. [2019-12-07 18:59:44,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 18:59:44,418 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:44,418 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:44,418 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:44,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:44,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1945525913, now seen corresponding path program 1 times [2019-12-07 18:59:44,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:44,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761653733] [2019-12-07 18:59:44,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:44,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:44,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:44,527 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761653733] [2019-12-07 18:59:44,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:44,528 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:59:44,528 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638420308] [2019-12-07 18:59:44,528 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:59:44,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:44,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:59:44,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:59:44,528 INFO L87 Difference]: Start difference. First operand 22895 states and 69360 transitions. Second operand 9 states. [2019-12-07 18:59:44,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:44,969 INFO L93 Difference]: Finished difference Result 35456 states and 109477 transitions. [2019-12-07 18:59:44,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:59:44,969 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 35 [2019-12-07 18:59:44,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:45,016 INFO L225 Difference]: With dead ends: 35456 [2019-12-07 18:59:45,016 INFO L226 Difference]: Without dead ends: 32690 [2019-12-07 18:59:45,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:59:45,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32690 states. [2019-12-07 18:59:45,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32690 to 22767. [2019-12-07 18:59:45,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22767 states. [2019-12-07 18:59:45,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22767 states to 22767 states and 68883 transitions. [2019-12-07 18:59:45,379 INFO L78 Accepts]: Start accepts. Automaton has 22767 states and 68883 transitions. Word has length 35 [2019-12-07 18:59:45,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:45,379 INFO L462 AbstractCegarLoop]: Abstraction has 22767 states and 68883 transitions. [2019-12-07 18:59:45,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:59:45,379 INFO L276 IsEmpty]: Start isEmpty. Operand 22767 states and 68883 transitions. [2019-12-07 18:59:45,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 18:59:45,394 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:45,394 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:45,394 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:45,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:45,394 INFO L82 PathProgramCache]: Analyzing trace with hash 1810599033, now seen corresponding path program 1 times [2019-12-07 18:59:45,394 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:45,394 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362087520] [2019-12-07 18:59:45,394 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:45,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:45,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:45,510 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362087520] [2019-12-07 18:59:45,510 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:45,511 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:59:45,511 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135597614] [2019-12-07 18:59:45,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:59:45,511 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:45,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:59:45,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:59:45,511 INFO L87 Difference]: Start difference. First operand 22767 states and 68883 transitions. Second operand 8 states. [2019-12-07 18:59:45,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:45,851 INFO L93 Difference]: Finished difference Result 31006 states and 93467 transitions. [2019-12-07 18:59:45,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:59:45,852 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 36 [2019-12-07 18:59:45,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:45,890 INFO L225 Difference]: With dead ends: 31006 [2019-12-07 18:59:45,890 INFO L226 Difference]: Without dead ends: 30862 [2019-12-07 18:59:45,890 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:59:45,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30862 states. [2019-12-07 18:59:46,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30862 to 27537. [2019-12-07 18:59:46,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27537 states. [2019-12-07 18:59:46,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27537 states to 27537 states and 83037 transitions. [2019-12-07 18:59:46,317 INFO L78 Accepts]: Start accepts. Automaton has 27537 states and 83037 transitions. Word has length 36 [2019-12-07 18:59:46,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:46,318 INFO L462 AbstractCegarLoop]: Abstraction has 27537 states and 83037 transitions. [2019-12-07 18:59:46,318 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:59:46,318 INFO L276 IsEmpty]: Start isEmpty. Operand 27537 states and 83037 transitions. [2019-12-07 18:59:46,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 18:59:46,335 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:46,336 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:46,336 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:46,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:46,336 INFO L82 PathProgramCache]: Analyzing trace with hash -2016154181, now seen corresponding path program 2 times [2019-12-07 18:59:46,336 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:46,336 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590567567] [2019-12-07 18:59:46,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:46,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:46,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:46,476 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590567567] [2019-12-07 18:59:46,476 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:46,476 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:59:46,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686262240] [2019-12-07 18:59:46,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:59:46,477 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:46,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:59:46,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:59:46,477 INFO L87 Difference]: Start difference. First operand 27537 states and 83037 transitions. Second operand 10 states. [2019-12-07 18:59:46,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:46,923 INFO L93 Difference]: Finished difference Result 39897 states and 121630 transitions. [2019-12-07 18:59:46,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:59:46,923 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2019-12-07 18:59:46,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:46,962 INFO L225 Difference]: With dead ends: 39897 [2019-12-07 18:59:46,962 INFO L226 Difference]: Without dead ends: 33197 [2019-12-07 18:59:46,962 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:59:47,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33197 states. [2019-12-07 18:59:47,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33197 to 25729. [2019-12-07 18:59:47,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25729 states. [2019-12-07 18:59:47,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25729 states to 25729 states and 77457 transitions. [2019-12-07 18:59:47,361 INFO L78 Accepts]: Start accepts. Automaton has 25729 states and 77457 transitions. Word has length 36 [2019-12-07 18:59:47,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:47,361 INFO L462 AbstractCegarLoop]: Abstraction has 25729 states and 77457 transitions. [2019-12-07 18:59:47,362 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:59:47,362 INFO L276 IsEmpty]: Start isEmpty. Operand 25729 states and 77457 transitions. [2019-12-07 18:59:47,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:47,379 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:47,379 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:47,379 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:47,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:47,379 INFO L82 PathProgramCache]: Analyzing trace with hash 1164744073, now seen corresponding path program 1 times [2019-12-07 18:59:47,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:47,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935458252] [2019-12-07 18:59:47,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:47,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:47,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:47,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935458252] [2019-12-07 18:59:47,406 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:47,406 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:47,406 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787511067] [2019-12-07 18:59:47,406 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:47,407 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:47,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:47,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:47,407 INFO L87 Difference]: Start difference. First operand 25729 states and 77457 transitions. Second operand 3 states. [2019-12-07 18:59:47,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:47,484 INFO L93 Difference]: Finished difference Result 25729 states and 76187 transitions. [2019-12-07 18:59:47,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:47,485 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 37 [2019-12-07 18:59:47,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:47,512 INFO L225 Difference]: With dead ends: 25729 [2019-12-07 18:59:47,512 INFO L226 Difference]: Without dead ends: 25729 [2019-12-07 18:59:47,513 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:47,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25729 states. [2019-12-07 18:59:47,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25729 to 25607. [2019-12-07 18:59:47,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25607 states. [2019-12-07 18:59:47,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25607 states to 25607 states and 75856 transitions. [2019-12-07 18:59:47,846 INFO L78 Accepts]: Start accepts. Automaton has 25607 states and 75856 transitions. Word has length 37 [2019-12-07 18:59:47,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:47,846 INFO L462 AbstractCegarLoop]: Abstraction has 25607 states and 75856 transitions. [2019-12-07 18:59:47,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:47,846 INFO L276 IsEmpty]: Start isEmpty. Operand 25607 states and 75856 transitions. [2019-12-07 18:59:47,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:47,862 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:47,862 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:47,863 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:47,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:47,863 INFO L82 PathProgramCache]: Analyzing trace with hash 871404576, now seen corresponding path program 1 times [2019-12-07 18:59:47,863 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:47,863 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009528560] [2019-12-07 18:59:47,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:47,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:48,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:48,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009528560] [2019-12-07 18:59:48,061 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:48,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:59:48,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146783804] [2019-12-07 18:59:48,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:59:48,062 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:48,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:59:48,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:59:48,062 INFO L87 Difference]: Start difference. First operand 25607 states and 75856 transitions. Second operand 11 states. [2019-12-07 18:59:48,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:48,488 INFO L93 Difference]: Finished difference Result 44486 states and 132527 transitions. [2019-12-07 18:59:48,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:59:48,488 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 18:59:48,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:48,528 INFO L225 Difference]: With dead ends: 44486 [2019-12-07 18:59:48,528 INFO L226 Difference]: Without dead ends: 37388 [2019-12-07 18:59:48,529 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=296, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:59:48,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37388 states. [2019-12-07 18:59:48,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37388 to 25524. [2019-12-07 18:59:48,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25524 states. [2019-12-07 18:59:48,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25524 states to 25524 states and 75507 transitions. [2019-12-07 18:59:48,982 INFO L78 Accepts]: Start accepts. Automaton has 25524 states and 75507 transitions. Word has length 37 [2019-12-07 18:59:48,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:48,982 INFO L462 AbstractCegarLoop]: Abstraction has 25524 states and 75507 transitions. [2019-12-07 18:59:48,982 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:59:48,982 INFO L276 IsEmpty]: Start isEmpty. Operand 25524 states and 75507 transitions. [2019-12-07 18:59:49,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:49,003 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:49,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:49,003 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:49,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:49,003 INFO L82 PathProgramCache]: Analyzing trace with hash -1236357120, now seen corresponding path program 2 times [2019-12-07 18:59:49,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:49,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473932159] [2019-12-07 18:59:49,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:49,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:49,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:49,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473932159] [2019-12-07 18:59:49,077 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:49,077 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:59:49,077 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142293726] [2019-12-07 18:59:49,078 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:59:49,078 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:49,078 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:59:49,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:59:49,078 INFO L87 Difference]: Start difference. First operand 25524 states and 75507 transitions. Second operand 8 states. [2019-12-07 18:59:49,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:49,384 INFO L93 Difference]: Finished difference Result 44961 states and 134240 transitions. [2019-12-07 18:59:49,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:59:49,384 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2019-12-07 18:59:49,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:49,428 INFO L225 Difference]: With dead ends: 44961 [2019-12-07 18:59:49,428 INFO L226 Difference]: Without dead ends: 40510 [2019-12-07 18:59:49,429 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:59:49,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40510 states. [2019-12-07 18:59:49,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40510 to 26701. [2019-12-07 18:59:49,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26701 states. [2019-12-07 18:59:49,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26701 states to 26701 states and 78717 transitions. [2019-12-07 18:59:49,867 INFO L78 Accepts]: Start accepts. Automaton has 26701 states and 78717 transitions. Word has length 37 [2019-12-07 18:59:49,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:49,867 INFO L462 AbstractCegarLoop]: Abstraction has 26701 states and 78717 transitions. [2019-12-07 18:59:49,867 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:59:49,867 INFO L276 IsEmpty]: Start isEmpty. Operand 26701 states and 78717 transitions. [2019-12-07 18:59:49,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:49,884 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:49,884 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:49,884 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:49,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:49,885 INFO L82 PathProgramCache]: Analyzing trace with hash -1210979228, now seen corresponding path program 3 times [2019-12-07 18:59:49,885 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:49,885 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291561535] [2019-12-07 18:59:49,885 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:49,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:49,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:49,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291561535] [2019-12-07 18:59:49,958 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:49,958 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:59:49,958 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042713416] [2019-12-07 18:59:49,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 18:59:49,958 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:49,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:59:49,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:59:49,958 INFO L87 Difference]: Start difference. First operand 26701 states and 78717 transitions. Second operand 9 states. [2019-12-07 18:59:50,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:50,351 INFO L93 Difference]: Finished difference Result 48124 states and 143182 transitions. [2019-12-07 18:59:50,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:59:50,352 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2019-12-07 18:59:50,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:50,399 INFO L225 Difference]: With dead ends: 48124 [2019-12-07 18:59:50,399 INFO L226 Difference]: Without dead ends: 40841 [2019-12-07 18:59:50,399 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=99, Invalid=321, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:59:50,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40841 states. [2019-12-07 18:59:50,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40841 to 26599. [2019-12-07 18:59:50,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26599 states. [2019-12-07 18:59:50,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26599 states to 26599 states and 78244 transitions. [2019-12-07 18:59:50,839 INFO L78 Accepts]: Start accepts. Automaton has 26599 states and 78244 transitions. Word has length 37 [2019-12-07 18:59:50,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:50,840 INFO L462 AbstractCegarLoop]: Abstraction has 26599 states and 78244 transitions. [2019-12-07 18:59:50,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 18:59:50,840 INFO L276 IsEmpty]: Start isEmpty. Operand 26599 states and 78244 transitions. [2019-12-07 18:59:50,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:50,856 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:50,856 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:50,856 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:50,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:50,857 INFO L82 PathProgramCache]: Analyzing trace with hash 393927768, now seen corresponding path program 4 times [2019-12-07 18:59:50,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:50,857 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654206505] [2019-12-07 18:59:50,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:50,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:50,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:50,980 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654206505] [2019-12-07 18:59:50,980 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:50,980 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:59:50,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161425872] [2019-12-07 18:59:50,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:59:50,980 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:50,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:59:50,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:59:50,981 INFO L87 Difference]: Start difference. First operand 26599 states and 78244 transitions. Second operand 10 states. [2019-12-07 18:59:51,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:51,368 INFO L93 Difference]: Finished difference Result 47398 states and 141004 transitions. [2019-12-07 18:59:51,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:59:51,369 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2019-12-07 18:59:51,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:51,417 INFO L225 Difference]: With dead ends: 47398 [2019-12-07 18:59:51,417 INFO L226 Difference]: Without dead ends: 42947 [2019-12-07 18:59:51,418 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=233, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:59:51,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42947 states. [2019-12-07 18:59:51,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42947 to 27184. [2019-12-07 18:59:51,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27184 states. [2019-12-07 18:59:51,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27184 states to 27184 states and 79942 transitions. [2019-12-07 18:59:51,872 INFO L78 Accepts]: Start accepts. Automaton has 27184 states and 79942 transitions. Word has length 37 [2019-12-07 18:59:51,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:51,872 INFO L462 AbstractCegarLoop]: Abstraction has 27184 states and 79942 transitions. [2019-12-07 18:59:51,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:59:51,872 INFO L276 IsEmpty]: Start isEmpty. Operand 27184 states and 79942 transitions. [2019-12-07 18:59:51,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:51,889 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:51,889 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:51,889 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:51,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:51,890 INFO L82 PathProgramCache]: Analyzing trace with hash 419305660, now seen corresponding path program 5 times [2019-12-07 18:59:51,890 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:51,890 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146794467] [2019-12-07 18:59:51,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:51,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:51,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:51,985 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146794467] [2019-12-07 18:59:51,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:51,985 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:59:51,985 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601822635] [2019-12-07 18:59:51,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:59:51,985 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:51,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:59:51,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:59:51,986 INFO L87 Difference]: Start difference. First operand 27184 states and 79942 transitions. Second operand 11 states. [2019-12-07 18:59:52,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:52,592 INFO L93 Difference]: Finished difference Result 49020 states and 145864 transitions. [2019-12-07 18:59:52,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:59:52,593 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2019-12-07 18:59:52,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:52,640 INFO L225 Difference]: With dead ends: 49020 [2019-12-07 18:59:52,640 INFO L226 Difference]: Without dead ends: 41668 [2019-12-07 18:59:52,640 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=142, Invalid=508, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:59:52,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41668 states. [2019-12-07 18:59:53,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41668 to 26583. [2019-12-07 18:59:53,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26583 states. [2019-12-07 18:59:53,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26583 states to 26583 states and 78146 transitions. [2019-12-07 18:59:53,084 INFO L78 Accepts]: Start accepts. Automaton has 26583 states and 78146 transitions. Word has length 37 [2019-12-07 18:59:53,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:53,084 INFO L462 AbstractCegarLoop]: Abstraction has 26583 states and 78146 transitions. [2019-12-07 18:59:53,084 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:59:53,084 INFO L276 IsEmpty]: Start isEmpty. Operand 26583 states and 78146 transitions. [2019-12-07 18:59:53,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:53,101 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:53,101 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:53,102 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:53,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:53,102 INFO L82 PathProgramCache]: Analyzing trace with hash -1415953768, now seen corresponding path program 6 times [2019-12-07 18:59:53,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:53,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085555101] [2019-12-07 18:59:53,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:53,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:53,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:53,272 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085555101] [2019-12-07 18:59:53,272 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:53,272 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:59:53,272 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300296811] [2019-12-07 18:59:53,272 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:59:53,272 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:53,273 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:59:53,273 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:59:53,273 INFO L87 Difference]: Start difference. First operand 26583 states and 78146 transitions. Second operand 14 states. [2019-12-07 18:59:54,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:54,427 INFO L93 Difference]: Finished difference Result 56283 states and 168613 transitions. [2019-12-07 18:59:54,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:59:54,428 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 37 [2019-12-07 18:59:54,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:54,497 INFO L225 Difference]: With dead ends: 56283 [2019-12-07 18:59:54,497 INFO L226 Difference]: Without dead ends: 54431 [2019-12-07 18:59:54,498 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=223, Invalid=1037, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:59:54,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54431 states. [2019-12-07 18:59:55,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54431 to 27455. [2019-12-07 18:59:55,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27455 states. [2019-12-07 18:59:55,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27455 states to 27455 states and 81153 transitions. [2019-12-07 18:59:55,054 INFO L78 Accepts]: Start accepts. Automaton has 27455 states and 81153 transitions. Word has length 37 [2019-12-07 18:59:55,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:55,054 INFO L462 AbstractCegarLoop]: Abstraction has 27455 states and 81153 transitions. [2019-12-07 18:59:55,054 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:59:55,054 INFO L276 IsEmpty]: Start isEmpty. Operand 27455 states and 81153 transitions. [2019-12-07 18:59:55,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 18:59:55,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:55,071 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:55,072 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:55,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:55,072 INFO L82 PathProgramCache]: Analyzing trace with hash -799815126, now seen corresponding path program 7 times [2019-12-07 18:59:55,072 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:55,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82304435] [2019-12-07 18:59:55,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:55,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:55,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:55,212 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82304435] [2019-12-07 18:59:55,212 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:55,212 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:59:55,213 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143536328] [2019-12-07 18:59:55,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:59:55,213 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:55,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:59:55,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:59:55,213 INFO L87 Difference]: Start difference. First operand 27455 states and 81153 transitions. Second operand 14 states. [2019-12-07 18:59:58,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:58,036 INFO L93 Difference]: Finished difference Result 71336 states and 213389 transitions. [2019-12-07 18:59:58,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2019-12-07 18:59:58,037 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 37 [2019-12-07 18:59:58,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:58,131 INFO L225 Difference]: With dead ends: 71336 [2019-12-07 18:59:58,132 INFO L226 Difference]: Without dead ends: 65292 [2019-12-07 18:59:58,134 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2215 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=959, Invalid=4893, Unknown=0, NotChecked=0, Total=5852 [2019-12-07 18:59:58,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65292 states. [2019-12-07 18:59:58,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65292 to 27246. [2019-12-07 18:59:58,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27246 states. [2019-12-07 18:59:58,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27246 states to 27246 states and 80458 transitions. [2019-12-07 18:59:58,859 INFO L78 Accepts]: Start accepts. Automaton has 27246 states and 80458 transitions. Word has length 37 [2019-12-07 18:59:58,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:58,859 INFO L462 AbstractCegarLoop]: Abstraction has 27246 states and 80458 transitions. [2019-12-07 18:59:58,860 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:59:58,860 INFO L276 IsEmpty]: Start isEmpty. Operand 27246 states and 80458 transitions. [2019-12-07 18:59:58,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:59:58,877 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:58,878 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:58,878 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:58,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:58,878 INFO L82 PathProgramCache]: Analyzing trace with hash 800914666, now seen corresponding path program 1 times [2019-12-07 18:59:58,878 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:58,878 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165449757] [2019-12-07 18:59:58,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:58,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:58,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:58,934 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165449757] [2019-12-07 18:59:58,934 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:58,934 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:59:58,934 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678094878] [2019-12-07 18:59:58,934 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:59:58,934 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:58,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:59:58,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:59:58,934 INFO L87 Difference]: Start difference. First operand 27246 states and 80458 transitions. Second operand 6 states. [2019-12-07 18:59:59,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:59,119 INFO L93 Difference]: Finished difference Result 39214 states and 116745 transitions. [2019-12-07 18:59:59,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:59:59,119 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2019-12-07 18:59:59,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:59,133 INFO L225 Difference]: With dead ends: 39214 [2019-12-07 18:59:59,133 INFO L226 Difference]: Without dead ends: 13953 [2019-12-07 18:59:59,133 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:59:59,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13953 states. [2019-12-07 18:59:59,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13953 to 11531. [2019-12-07 18:59:59,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11531 states. [2019-12-07 18:59:59,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11531 states to 11531 states and 33578 transitions. [2019-12-07 18:59:59,291 INFO L78 Accepts]: Start accepts. Automaton has 11531 states and 33578 transitions. Word has length 38 [2019-12-07 18:59:59,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:59,291 INFO L462 AbstractCegarLoop]: Abstraction has 11531 states and 33578 transitions. [2019-12-07 18:59:59,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:59:59,291 INFO L276 IsEmpty]: Start isEmpty. Operand 11531 states and 33578 transitions. [2019-12-07 18:59:59,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 18:59:59,297 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:59,297 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:59,297 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:59,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:59,297 INFO L82 PathProgramCache]: Analyzing trace with hash -1884635564, now seen corresponding path program 1 times [2019-12-07 18:59:59,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:59,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531968906] [2019-12-07 18:59:59,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:59,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:59,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:59,393 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531968906] [2019-12-07 18:59:59,393 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:59,393 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:59:59,393 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951350057] [2019-12-07 18:59:59,393 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:59:59,393 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:59,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:59:59,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:59:59,394 INFO L87 Difference]: Start difference. First operand 11531 states and 33578 transitions. Second operand 11 states. [2019-12-07 18:59:59,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:59,838 INFO L93 Difference]: Finished difference Result 15149 states and 43775 transitions. [2019-12-07 18:59:59,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:59:59,839 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 18:59:59,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:59,861 INFO L225 Difference]: With dead ends: 15149 [2019-12-07 18:59:59,862 INFO L226 Difference]: Without dead ends: 14169 [2019-12-07 18:59:59,862 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=220, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:59:59,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14169 states. [2019-12-07 19:00:00,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14169 to 11584. [2019-12-07 19:00:00,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11584 states. [2019-12-07 19:00:00,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11584 states to 11584 states and 33678 transitions. [2019-12-07 19:00:00,020 INFO L78 Accepts]: Start accepts. Automaton has 11584 states and 33678 transitions. Word has length 38 [2019-12-07 19:00:00,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:00,021 INFO L462 AbstractCegarLoop]: Abstraction has 11584 states and 33678 transitions. [2019-12-07 19:00:00,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:00:00,021 INFO L276 IsEmpty]: Start isEmpty. Operand 11584 states and 33678 transitions. [2019-12-07 19:00:00,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:00,027 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:00,027 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:00,027 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:00,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:00,028 INFO L82 PathProgramCache]: Analyzing trace with hash -1994366254, now seen corresponding path program 2 times [2019-12-07 19:00:00,028 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:00,028 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000888385] [2019-12-07 19:00:00,028 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:00,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:00,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:00,127 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000888385] [2019-12-07 19:00:00,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:00,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:00:00,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309902737] [2019-12-07 19:00:00,128 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:00:00,128 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:00,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:00:00,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:00:00,129 INFO L87 Difference]: Start difference. First operand 11584 states and 33678 transitions. Second operand 11 states. [2019-12-07 19:00:00,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:00,462 INFO L93 Difference]: Finished difference Result 15024 states and 43515 transitions. [2019-12-07 19:00:00,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 19:00:00,463 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 19:00:00,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:00,476 INFO L225 Difference]: With dead ends: 15024 [2019-12-07 19:00:00,477 INFO L226 Difference]: Without dead ends: 14168 [2019-12-07 19:00:00,477 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=46, Invalid=194, Unknown=0, NotChecked=0, Total=240 [2019-12-07 19:00:00,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14168 states. [2019-12-07 19:00:00,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14168 to 11588. [2019-12-07 19:00:00,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11588 states. [2019-12-07 19:00:00,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11588 states to 11588 states and 33679 transitions. [2019-12-07 19:00:00,634 INFO L78 Accepts]: Start accepts. Automaton has 11588 states and 33679 transitions. Word has length 38 [2019-12-07 19:00:00,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:00,634 INFO L462 AbstractCegarLoop]: Abstraction has 11588 states and 33679 transitions. [2019-12-07 19:00:00,634 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:00:00,634 INFO L276 IsEmpty]: Start isEmpty. Operand 11588 states and 33679 transitions. [2019-12-07 19:00:00,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:00,640 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:00,640 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:00,640 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:00,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:00,641 INFO L82 PathProgramCache]: Analyzing trace with hash -364081366, now seen corresponding path program 3 times [2019-12-07 19:00:00,641 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:00,641 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558766432] [2019-12-07 19:00:00,641 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:00,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:00,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:00,751 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558766432] [2019-12-07 19:00:00,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:00,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 19:00:00,752 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337217926] [2019-12-07 19:00:00,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 19:00:00,752 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:00,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 19:00:00,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 19:00:00,752 INFO L87 Difference]: Start difference. First operand 11588 states and 33679 transitions. Second operand 12 states. [2019-12-07 19:00:01,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:01,431 INFO L93 Difference]: Finished difference Result 23603 states and 68416 transitions. [2019-12-07 19:00:01,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 19:00:01,432 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 19:00:01,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:01,446 INFO L225 Difference]: With dead ends: 23603 [2019-12-07 19:00:01,447 INFO L226 Difference]: Without dead ends: 15532 [2019-12-07 19:00:01,447 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 316 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=219, Invalid=1113, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 19:00:01,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15532 states. [2019-12-07 19:00:01,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15532 to 10695. [2019-12-07 19:00:01,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10695 states. [2019-12-07 19:00:01,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10695 states to 10695 states and 31138 transitions. [2019-12-07 19:00:01,607 INFO L78 Accepts]: Start accepts. Automaton has 10695 states and 31138 transitions. Word has length 38 [2019-12-07 19:00:01,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:01,607 INFO L462 AbstractCegarLoop]: Abstraction has 10695 states and 31138 transitions. [2019-12-07 19:00:01,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 19:00:01,607 INFO L276 IsEmpty]: Start isEmpty. Operand 10695 states and 31138 transitions. [2019-12-07 19:00:01,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:01,613 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:01,613 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:01,613 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:01,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:01,613 INFO L82 PathProgramCache]: Analyzing trace with hash 122973388, now seen corresponding path program 4 times [2019-12-07 19:00:01,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:01,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335916412] [2019-12-07 19:00:01,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:01,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:01,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:01,791 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335916412] [2019-12-07 19:00:01,791 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:01,791 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 19:00:01,791 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006644056] [2019-12-07 19:00:01,792 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 19:00:01,792 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:01,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 19:00:01,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=170, Unknown=0, NotChecked=0, Total=210 [2019-12-07 19:00:01,792 INFO L87 Difference]: Start difference. First operand 10695 states and 31138 transitions. Second operand 15 states. [2019-12-07 19:00:03,105 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 35 [2019-12-07 19:00:04,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:04,605 INFO L93 Difference]: Finished difference Result 20740 states and 59500 transitions. [2019-12-07 19:00:04,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 19:00:04,607 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 38 [2019-12-07 19:00:04,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:04,640 INFO L225 Difference]: With dead ends: 20740 [2019-12-07 19:00:04,640 INFO L226 Difference]: Without dead ends: 19723 [2019-12-07 19:00:04,641 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 455 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=347, Invalid=1459, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 19:00:04,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19723 states. [2019-12-07 19:00:04,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19723 to 10816. [2019-12-07 19:00:04,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10816 states. [2019-12-07 19:00:04,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10816 states to 10816 states and 31364 transitions. [2019-12-07 19:00:04,835 INFO L78 Accepts]: Start accepts. Automaton has 10816 states and 31364 transitions. Word has length 38 [2019-12-07 19:00:04,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:04,835 INFO L462 AbstractCegarLoop]: Abstraction has 10816 states and 31364 transitions. [2019-12-07 19:00:04,835 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 19:00:04,835 INFO L276 IsEmpty]: Start isEmpty. Operand 10816 states and 31364 transitions. [2019-12-07 19:00:04,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:04,842 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:04,842 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:04,842 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:04,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:04,842 INFO L82 PathProgramCache]: Analyzing trace with hash 739112030, now seen corresponding path program 5 times [2019-12-07 19:00:04,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:04,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657289433] [2019-12-07 19:00:04,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:04,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:04,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:04,959 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657289433] [2019-12-07 19:00:04,959 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:04,959 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:00:04,959 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889722251] [2019-12-07 19:00:04,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:00:04,959 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:04,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:00:04,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:00:04,960 INFO L87 Difference]: Start difference. First operand 10816 states and 31364 transitions. Second operand 11 states. [2019-12-07 19:00:05,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:05,277 INFO L93 Difference]: Finished difference Result 13590 states and 38882 transitions. [2019-12-07 19:00:05,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 19:00:05,277 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 19:00:05,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:05,288 INFO L225 Difference]: With dead ends: 13590 [2019-12-07 19:00:05,289 INFO L226 Difference]: Without dead ends: 12400 [2019-12-07 19:00:05,289 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=218, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:00:05,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12400 states. [2019-12-07 19:00:05,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12400 to 10633. [2019-12-07 19:00:05,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10633 states. [2019-12-07 19:00:05,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10633 states to 10633 states and 30937 transitions. [2019-12-07 19:00:05,443 INFO L78 Accepts]: Start accepts. Automaton has 10633 states and 30937 transitions. Word has length 38 [2019-12-07 19:00:05,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:05,444 INFO L462 AbstractCegarLoop]: Abstraction has 10633 states and 30937 transitions. [2019-12-07 19:00:05,444 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:00:05,444 INFO L276 IsEmpty]: Start isEmpty. Operand 10633 states and 30937 transitions. [2019-12-07 19:00:05,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:05,449 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:05,449 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:05,450 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:05,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:05,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1027193848, now seen corresponding path program 6 times [2019-12-07 19:00:05,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:05,450 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332805051] [2019-12-07 19:00:05,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:05,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:05,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:05,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332805051] [2019-12-07 19:00:05,627 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:05,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 19:00:05,628 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551674518] [2019-12-07 19:00:05,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 19:00:05,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:05,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 19:00:05,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 19:00:05,628 INFO L87 Difference]: Start difference. First operand 10633 states and 30937 transitions. Second operand 12 states. [2019-12-07 19:00:08,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,272 INFO L93 Difference]: Finished difference Result 17712 states and 51990 transitions. [2019-12-07 19:00:08,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 19:00:08,273 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2019-12-07 19:00:08,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,298 INFO L225 Difference]: With dead ends: 17712 [2019-12-07 19:00:08,298 INFO L226 Difference]: Without dead ends: 14356 [2019-12-07 19:00:08,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 138 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=149, Invalid=663, Unknown=0, NotChecked=0, Total=812 [2019-12-07 19:00:08,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14356 states. [2019-12-07 19:00:08,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14356 to 10494. [2019-12-07 19:00:08,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10494 states. [2019-12-07 19:00:08,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10494 states to 10494 states and 30369 transitions. [2019-12-07 19:00:08,456 INFO L78 Accepts]: Start accepts. Automaton has 10494 states and 30369 transitions. Word has length 38 [2019-12-07 19:00:08,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:08,456 INFO L462 AbstractCegarLoop]: Abstraction has 10494 states and 30369 transitions. [2019-12-07 19:00:08,456 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 19:00:08,456 INFO L276 IsEmpty]: Start isEmpty. Operand 10494 states and 30369 transitions. [2019-12-07 19:00:08,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:08,462 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:08,462 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:08,462 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:08,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:08,463 INFO L82 PathProgramCache]: Analyzing trace with hash 169364536, now seen corresponding path program 7 times [2019-12-07 19:00:08,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:08,463 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213544873] [2019-12-07 19:00:08,463 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:08,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:08,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:08,574 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213544873] [2019-12-07 19:00:08,574 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:08,574 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:00:08,574 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696274930] [2019-12-07 19:00:08,574 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:00:08,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:08,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:00:08,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:00:08,575 INFO L87 Difference]: Start difference. First operand 10494 states and 30369 transitions. Second operand 11 states. [2019-12-07 19:00:08,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,936 INFO L93 Difference]: Finished difference Result 12729 states and 36666 transitions. [2019-12-07 19:00:08,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 19:00:08,937 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2019-12-07 19:00:08,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,948 INFO L225 Difference]: With dead ends: 12729 [2019-12-07 19:00:08,948 INFO L226 Difference]: Without dead ends: 11708 [2019-12-07 19:00:08,948 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=273, Unknown=0, NotChecked=0, Total=342 [2019-12-07 19:00:08,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11708 states. [2019-12-07 19:00:09,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11708 to 9957. [2019-12-07 19:00:09,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9957 states. [2019-12-07 19:00:09,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9957 states to 9957 states and 29149 transitions. [2019-12-07 19:00:09,086 INFO L78 Accepts]: Start accepts. Automaton has 9957 states and 29149 transitions. Word has length 38 [2019-12-07 19:00:09,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,086 INFO L462 AbstractCegarLoop]: Abstraction has 9957 states and 29149 transitions. [2019-12-07 19:00:09,087 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:00:09,087 INFO L276 IsEmpty]: Start isEmpty. Operand 9957 states and 29149 transitions. [2019-12-07 19:00:09,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:09,092 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,092 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,092 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,092 INFO L82 PathProgramCache]: Analyzing trace with hash -1499297712, now seen corresponding path program 2 times [2019-12-07 19:00:09,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911285205] [2019-12-07 19:00:09,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,175 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911285205] [2019-12-07 19:00:09,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,176 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 19:00:09,176 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506410381] [2019-12-07 19:00:09,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 19:00:09,176 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 19:00:09,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 19:00:09,176 INFO L87 Difference]: Start difference. First operand 9957 states and 29149 transitions. Second operand 10 states. [2019-12-07 19:00:09,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,568 INFO L93 Difference]: Finished difference Result 17645 states and 51962 transitions. [2019-12-07 19:00:09,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 19:00:09,569 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 38 [2019-12-07 19:00:09,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,582 INFO L225 Difference]: With dead ends: 17645 [2019-12-07 19:00:09,582 INFO L226 Difference]: Without dead ends: 14037 [2019-12-07 19:00:09,582 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:00:09,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14037 states. [2019-12-07 19:00:09,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14037 to 10021. [2019-12-07 19:00:09,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10021 states. [2019-12-07 19:00:09,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10021 states to 10021 states and 29325 transitions. [2019-12-07 19:00:09,729 INFO L78 Accepts]: Start accepts. Automaton has 10021 states and 29325 transitions. Word has length 38 [2019-12-07 19:00:09,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,729 INFO L462 AbstractCegarLoop]: Abstraction has 10021 states and 29325 transitions. [2019-12-07 19:00:09,729 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 19:00:09,729 INFO L276 IsEmpty]: Start isEmpty. Operand 10021 states and 29325 transitions. [2019-12-07 19:00:09,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 19:00:09,735 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,735 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,735 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,735 INFO L82 PathProgramCache]: Analyzing trace with hash 2089288892, now seen corresponding path program 3 times [2019-12-07 19:00:09,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,736 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872340688] [2019-12-07 19:00:09,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,755 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872340688] [2019-12-07 19:00:09,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,755 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:09,755 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850028197] [2019-12-07 19:00:09,755 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:09,756 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:09,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:09,756 INFO L87 Difference]: Start difference. First operand 10021 states and 29325 transitions. Second operand 4 states. [2019-12-07 19:00:09,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,765 INFO L93 Difference]: Finished difference Result 1375 states and 2960 transitions. [2019-12-07 19:00:09,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 19:00:09,766 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2019-12-07 19:00:09,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,767 INFO L225 Difference]: With dead ends: 1375 [2019-12-07 19:00:09,767 INFO L226 Difference]: Without dead ends: 1364 [2019-12-07 19:00:09,767 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:09,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1364 states. [2019-12-07 19:00:09,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1364 to 1352. [2019-12-07 19:00:09,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1352 states. [2019-12-07 19:00:09,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1352 states to 1352 states and 2917 transitions. [2019-12-07 19:00:09,777 INFO L78 Accepts]: Start accepts. Automaton has 1352 states and 2917 transitions. Word has length 38 [2019-12-07 19:00:09,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,777 INFO L462 AbstractCegarLoop]: Abstraction has 1352 states and 2917 transitions. [2019-12-07 19:00:09,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:09,777 INFO L276 IsEmpty]: Start isEmpty. Operand 1352 states and 2917 transitions. [2019-12-07 19:00:09,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 19:00:09,778 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,778 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,778 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1815536888, now seen corresponding path program 1 times [2019-12-07 19:00:09,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022011578] [2019-12-07 19:00:09,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:10,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:10,038 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022011578] [2019-12-07 19:00:10,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:10,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 19:00:10,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665407657] [2019-12-07 19:00:10,038 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 19:00:10,038 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:10,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 19:00:10,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=260, Unknown=0, NotChecked=0, Total=306 [2019-12-07 19:00:10,039 INFO L87 Difference]: Start difference. First operand 1352 states and 2917 transitions. Second operand 18 states. [2019-12-07 19:00:10,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:10,937 INFO L93 Difference]: Finished difference Result 2131 states and 4574 transitions. [2019-12-07 19:00:10,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 19:00:10,938 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 45 [2019-12-07 19:00:10,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:10,939 INFO L225 Difference]: With dead ends: 2131 [2019-12-07 19:00:10,939 INFO L226 Difference]: Without dead ends: 1744 [2019-12-07 19:00:10,939 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=750, Unknown=0, NotChecked=0, Total=870 [2019-12-07 19:00:10,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1744 states. [2019-12-07 19:00:10,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1744 to 1401. [2019-12-07 19:00:10,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1401 states. [2019-12-07 19:00:10,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1401 states to 1401 states and 3013 transitions. [2019-12-07 19:00:10,950 INFO L78 Accepts]: Start accepts. Automaton has 1401 states and 3013 transitions. Word has length 45 [2019-12-07 19:00:10,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:10,950 INFO L462 AbstractCegarLoop]: Abstraction has 1401 states and 3013 transitions. [2019-12-07 19:00:10,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 19:00:10,950 INFO L276 IsEmpty]: Start isEmpty. Operand 1401 states and 3013 transitions. [2019-12-07 19:00:10,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 19:00:10,951 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:10,951 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:10,951 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:10,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:10,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1466667480, now seen corresponding path program 2 times [2019-12-07 19:00:10,952 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:10,952 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970134144] [2019-12-07 19:00:10,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:10,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970134144] [2019-12-07 19:00:11,027 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,027 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 19:00:11,027 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014748678] [2019-12-07 19:00:11,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 19:00:11,027 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 19:00:11,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 19:00:11,027 INFO L87 Difference]: Start difference. First operand 1401 states and 3013 transitions. Second operand 10 states. [2019-12-07 19:00:11,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,239 INFO L93 Difference]: Finished difference Result 2031 states and 4371 transitions. [2019-12-07 19:00:11,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 19:00:11,239 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 45 [2019-12-07 19:00:11,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,240 INFO L225 Difference]: With dead ends: 2031 [2019-12-07 19:00:11,240 INFO L226 Difference]: Without dead ends: 1633 [2019-12-07 19:00:11,240 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:00:11,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1633 states. [2019-12-07 19:00:11,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1633 to 1385. [2019-12-07 19:00:11,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1385 states. [2019-12-07 19:00:11,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 1385 states and 2982 transitions. [2019-12-07 19:00:11,251 INFO L78 Accepts]: Start accepts. Automaton has 1385 states and 2982 transitions. Word has length 45 [2019-12-07 19:00:11,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,251 INFO L462 AbstractCegarLoop]: Abstraction has 1385 states and 2982 transitions. [2019-12-07 19:00:11,251 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 19:00:11,251 INFO L276 IsEmpty]: Start isEmpty. Operand 1385 states and 2982 transitions. [2019-12-07 19:00:11,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 19:00:11,251 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,252 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,252 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,252 INFO L82 PathProgramCache]: Analyzing trace with hash 2121919124, now seen corresponding path program 3 times [2019-12-07 19:00:11,252 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,252 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660971841] [2019-12-07 19:00:11,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,278 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660971841] [2019-12-07 19:00:11,278 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,278 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:00:11,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331753091] [2019-12-07 19:00:11,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:11,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:11,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:11,279 INFO L87 Difference]: Start difference. First operand 1385 states and 2982 transitions. Second operand 5 states. [2019-12-07 19:00:11,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,290 INFO L93 Difference]: Finished difference Result 251 states and 445 transitions. [2019-12-07 19:00:11,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:11,290 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 45 [2019-12-07 19:00:11,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,290 INFO L225 Difference]: With dead ends: 251 [2019-12-07 19:00:11,290 INFO L226 Difference]: Without dead ends: 251 [2019-12-07 19:00:11,290 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:11,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2019-12-07 19:00:11,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 219. [2019-12-07 19:00:11,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2019-12-07 19:00:11,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 385 transitions. [2019-12-07 19:00:11,292 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 385 transitions. Word has length 45 [2019-12-07 19:00:11,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,292 INFO L462 AbstractCegarLoop]: Abstraction has 219 states and 385 transitions. [2019-12-07 19:00:11,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:11,292 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 385 transitions. [2019-12-07 19:00:11,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 19:00:11,293 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,293 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,293 INFO L82 PathProgramCache]: Analyzing trace with hash -1590264344, now seen corresponding path program 1 times [2019-12-07 19:00:11,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598723260] [2019-12-07 19:00:11,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598723260] [2019-12-07 19:00:11,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 19:00:11,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130619599] [2019-12-07 19:00:11,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 19:00:11,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 19:00:11,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-12-07 19:00:11,448 INFO L87 Difference]: Start difference. First operand 219 states and 385 transitions. Second operand 14 states. [2019-12-07 19:00:11,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,746 INFO L93 Difference]: Finished difference Result 389 states and 667 transitions. [2019-12-07 19:00:11,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 19:00:11,747 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 56 [2019-12-07 19:00:11,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,747 INFO L225 Difference]: With dead ends: 389 [2019-12-07 19:00:11,747 INFO L226 Difference]: Without dead ends: 259 [2019-12-07 19:00:11,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=106, Invalid=494, Unknown=0, NotChecked=0, Total=600 [2019-12-07 19:00:11,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2019-12-07 19:00:11,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 227. [2019-12-07 19:00:11,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2019-12-07 19:00:11,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 395 transitions. [2019-12-07 19:00:11,749 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 395 transitions. Word has length 56 [2019-12-07 19:00:11,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,749 INFO L462 AbstractCegarLoop]: Abstraction has 227 states and 395 transitions. [2019-12-07 19:00:11,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 19:00:11,749 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 395 transitions. [2019-12-07 19:00:11,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 19:00:11,750 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,750 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,750 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1710889504, now seen corresponding path program 2 times [2019-12-07 19:00:11,750 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,750 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595709269] [2019-12-07 19:00:11,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,843 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595709269] [2019-12-07 19:00:11,844 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,844 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 19:00:11,844 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324023417] [2019-12-07 19:00:11,844 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 19:00:11,844 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 19:00:11,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 19:00:11,844 INFO L87 Difference]: Start difference. First operand 227 states and 395 transitions. Second operand 12 states. [2019-12-07 19:00:11,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,977 INFO L93 Difference]: Finished difference Result 317 states and 527 transitions. [2019-12-07 19:00:11,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 19:00:11,977 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 56 [2019-12-07 19:00:11,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,977 INFO L225 Difference]: With dead ends: 317 [2019-12-07 19:00:11,977 INFO L226 Difference]: Without dead ends: 203 [2019-12-07 19:00:11,978 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-12-07 19:00:11,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2019-12-07 19:00:11,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 203. [2019-12-07 19:00:11,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2019-12-07 19:00:11,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 349 transitions. [2019-12-07 19:00:11,979 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 349 transitions. Word has length 56 [2019-12-07 19:00:11,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,980 INFO L462 AbstractCegarLoop]: Abstraction has 203 states and 349 transitions. [2019-12-07 19:00:11,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 19:00:11,980 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 349 transitions. [2019-12-07 19:00:11,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 19:00:11,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,980 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,980 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,980 INFO L82 PathProgramCache]: Analyzing trace with hash -1475134232, now seen corresponding path program 3 times [2019-12-07 19:00:11,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007291288] [2019-12-07 19:00:11,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:00:12,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:00:12,047 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 19:00:12,047 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 19:00:12,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2504~0.base_27|) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2504~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2504~0.base_27|)) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2504~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2504~0.base_27|) |v_ULTIMATE.start_main_~#t2504~0.offset_20| 0)) |v_#memory_int_23|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= |v_#valid_59| (store .cse0 |v_ULTIMATE.start_main_~#t2504~0.base_27| 1)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= 0 |v_ULTIMATE.start_main_~#t2504~0.offset_20|) (= v_~y$r_buff1_thd0~0_237 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_~#t2504~0.base=|v_ULTIMATE.start_main_~#t2504~0.base_27|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2504~0.offset=|v_ULTIMATE.start_main_~#t2504~0.offset_20|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ULTIMATE.start_main_~#t2505~0.offset=|v_ULTIMATE.start_main_~#t2505~0.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_~#t2506~0.offset=|v_ULTIMATE.start_main_~#t2506~0.offset_16|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2506~0.base=|v_ULTIMATE.start_main_~#t2506~0.base_20|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ULTIMATE.start_main_~#t2505~0.base=|v_ULTIMATE.start_main_~#t2505~0.base_20|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2504~0.base, ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2504~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t2505~0.offset, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t2506~0.offset, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2506~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t2505~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 19:00:12,050 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2505~0.base_9| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2505~0.base_9|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2505~0.base_9|)) (not (= 0 |v_ULTIMATE.start_main_~#t2505~0.base_9|)) (= (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2505~0.base_9| 1) |v_#valid_33|) (= |v_ULTIMATE.start_main_~#t2505~0.offset_9| 0) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2505~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2505~0.base_9|) |v_ULTIMATE.start_main_~#t2505~0.offset_9| 1)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, ULTIMATE.start_main_~#t2505~0.offset=|v_ULTIMATE.start_main_~#t2505~0.offset_9|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2505~0.base=|v_ULTIMATE.start_main_~#t2505~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2505~0.offset, #length, ULTIMATE.start_main_~#t2505~0.base] because there is no mapped edge [2019-12-07 19:00:12,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= |v_ULTIMATE.start_main_~#t2506~0.offset_9| 0) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2506~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2506~0.base_10|) |v_ULTIMATE.start_main_~#t2506~0.offset_9| 2)) |v_#memory_int_11|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2506~0.base_10| 1)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2506~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2506~0.base_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2506~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t2506~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t2506~0.offset=|v_ULTIMATE.start_main_~#t2506~0.offset_9|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t2506~0.base=|v_ULTIMATE.start_main_~#t2506~0.base_10|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2506~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t2506~0.base, #length] because there is no mapped edge [2019-12-07 19:00:12,051 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-24977062 256))) (not (= (mod ~y$w_buff0_used~0_Out-24977062 256) 0)))) 1 0)) (= 1 ~y$w_buff0_used~0_Out-24977062) (= P2Thread1of1ForFork0_~arg.offset_Out-24977062 |P2Thread1of1ForFork0_#in~arg.offset_In-24977062|) (= |P2Thread1of1ForFork0_#in~arg.base_In-24977062| P2Thread1of1ForFork0_~arg.base_Out-24977062) (= ~y$w_buff0_used~0_In-24977062 ~y$w_buff1_used~0_Out-24977062) (= ~y$w_buff0~0_Out-24977062 2) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062)) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062) (= ~y$w_buff1~0_Out-24977062 ~y$w_buff0~0_In-24977062)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-24977062, ~y$w_buff0~0=~y$w_buff0~0_In-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-24977062, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-24977062, ~y$w_buff1~0=~y$w_buff1~0_Out-24977062, ~y$w_buff0~0=~y$w_buff0~0_Out-24977062, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-24977062} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 19:00:12,052 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 19:00:12,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-2000280432 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2000280432 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| ~y$w_buff0_used~0_In-2000280432) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2000280432|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 19:00:12,053 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork2_#t~ite4_Out-1032287144| |P1Thread1of1ForFork2_#t~ite3_Out-1032287144|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1032287144 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1032287144 256)))) (or (and (not .cse0) (not .cse1) .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y$w_buff1~0_In-1032287144)) (and .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y~0_In-1032287144) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, ~y~0=~y~0_In-1032287144, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1032287144|, ~y~0=~y~0_In-1032287144, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1032287144|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 19:00:12,054 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In439139011 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd3~0_In439139011 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In439139011 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In439139011 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| ~y$w_buff1_used~0_In439139011)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out439139011|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 19:00:12,054 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In10111743 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In10111743 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| ~y$w_buff0_used~0_In10111743) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out10111743|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 19:00:12,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1807078712 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1807078712 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1807078712 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1807078712 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| 0)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| ~y$w_buff1_used~0_In1807078712) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1807078712|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 19:00:12,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1375098561 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1375098561 256)))) (or (and (= ~y$r_buff0_thd2~0_In1375098561 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1375098561|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 19:00:12,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1670259436 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1670259436 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1670259436 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1670259436 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|)) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1670259436 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1670259436|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 19:00:12,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 19:00:12,055 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In16129428 256))) (.cse2 (= ~y$r_buff0_thd3~0_Out16129428 ~y$r_buff0_thd3~0_In16129428)) (.cse1 (= (mod ~y$w_buff0_used~0_In16129428 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out16129428 0) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In16129428} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out16129428, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out16129428|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 19:00:12,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1318651703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1318651703 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1318651703 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In1318651703 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1318651703|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1318651703| ~y$r_buff1_thd3~0_In1318651703) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1318651703|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 19:00:12,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 19:00:12,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:00:12,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-535386570 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-535386570 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite18_Out-535386570| |ULTIMATE.start_main_#t~ite19_Out-535386570|))) (or (and (not .cse0) .cse1 (not .cse2) (= ~y$w_buff1~0_In-535386570 |ULTIMATE.start_main_#t~ite18_Out-535386570|)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-535386570| ~y~0_In-535386570) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-535386570, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-535386570, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-535386570|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-535386570|, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 19:00:12,056 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1592832274 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1592832274 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1592832274| ~y$w_buff0_used~0_In-1592832274) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1592832274|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1592832274|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 19:00:12,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-97834117 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-97834117 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-97834117 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-97834117 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-97834117| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite21_Out-97834117| ~y$w_buff1_used~0_In-97834117)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-97834117|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 19:00:12,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1041155812 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1041155812| ~y$r_buff0_thd0~0_In1041155812)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out1041155812|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1041155812|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 19:00:12,057 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-705899353 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-705899353 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-705899353 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-705899353 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-705899353 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-705899353|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 19:00:12,058 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1030380200 256) 0))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1030380200 256) 0))) (or (and (= (mod ~y$w_buff1_used~0_In-1030380200 256) 0) .cse0) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-1030380200 256) 0)) (= (mod ~y$w_buff0_used~0_In-1030380200 256) 0))) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= ~y$w_buff0~0_In-1030380200 |ULTIMATE.start_main_#t~ite29_Out-1030380200|) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite29_In-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| ~y$w_buff0~0_In-1030380200)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1030380200|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 19:00:12,058 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-254870859 256) 0))) (or (and (not .cse0) (= ~y$w_buff1~0_In-254870859 |ULTIMATE.start_main_#t~ite33_Out-254870859|) (= |ULTIMATE.start_main_#t~ite32_In-254870859| |ULTIMATE.start_main_#t~ite32_Out-254870859|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-254870859| ~y$w_buff1~0_In-254870859) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-254870859 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-254870859 256) 0)) (and (= 0 (mod ~y$w_buff1_used~0_In-254870859 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-254870859 256)))) (= |ULTIMATE.start_main_#t~ite32_Out-254870859| |ULTIMATE.start_main_#t~ite33_Out-254870859|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-254870859|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 19:00:12,058 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In984766544 256) 0))) (or (and (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite35_Out984766544|) (= |ULTIMATE.start_main_#t~ite36_Out984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In984766544 256)))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In984766544 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In984766544 256) 0) .cse0) (= (mod ~y$w_buff0_used~0_In984766544 256) 0))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite36_Out984766544|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out984766544|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 19:00:12,059 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 19:00:12,059 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:00:12,059 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 19:00:12,109 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 07:00:12 BasicIcfg [2019-12-07 19:00:12,109 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 19:00:12,109 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 19:00:12,109 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 19:00:12,109 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 19:00:12,110 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:30" (3/4) ... [2019-12-07 19:00:12,111 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 19:00:12,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] ULTIMATE.startENTRY-->L798: Formula: (let ((.cse0 (store |v_#valid_61| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~y$r_buff1_thd1~0_54) (= 0 v_~y$r_buff1_thd3~0_115) (= 0 v_~y$r_buff1_thd2~0_106) (= v_~weak$$choice2~0_112 0) (= v_~y$r_buff0_thd1~0_53 0) (= v_~y$r_buff0_thd0~0_348 0) (= v_~y$w_buff0_used~0_737 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t2504~0.base_27|) (= v_~y$w_buff1~0_230 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff0_thd3~0_169) (= 0 v_~y$w_buff0~0_338) (< 0 |v_#StackHeapBarrier_18|) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t2504~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2504~0.base_27|)) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2504~0.base_27| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t2504~0.base_27|) |v_ULTIMATE.start_main_~#t2504~0.offset_20| 0)) |v_#memory_int_23|) (= v_~y$mem_tmp~0_19 0) (= v_~z~0_90 0) (= v_~x~0_77 0) (= v_~y$w_buff1_used~0_407 0) (= v_~main$tmp_guard0~0_21 0) (= |v_#valid_59| (store .cse0 |v_ULTIMATE.start_main_~#t2504~0.base_27| 1)) (= |v_#NULL.offset_5| 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~__unbuffered_cnt~0_90) (= 0 |v_ULTIMATE.start_main_~#t2504~0.offset_20|) (= v_~y$r_buff1_thd0~0_237 0) (= 0 v_~y$flush_delayed~0_38) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= 0 |v_#NULL.base_5|) (= 0 v_~weak$$choice0~0_12))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_61|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_~#t2504~0.base=|v_ULTIMATE.start_main_~#t2504~0.base_27|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_34|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_39|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_62|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_71|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_115, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_53, ~y$flush_delayed~0=v_~y$flush_delayed~0_38, #length=|v_#length_25|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_33|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_118|, ULTIMATE.start_main_~#t2504~0.offset=|v_ULTIMATE.start_main_~#t2504~0.offset_20|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_45|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_34|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_37|, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_40|, ~y$w_buff1~0=v_~y$w_buff1~0_230, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_9|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_21|, ULTIMATE.start_main_~#t2505~0.offset=|v_ULTIMATE.start_main_~#t2505~0.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_237, ~x~0=v_~x~0_77, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_737, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_45|, ULTIMATE.start_main_~#t2506~0.offset=|v_ULTIMATE.start_main_~#t2506~0.offset_16|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_37|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_43|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_24|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_62|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_54, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ~y$w_buff0~0=v_~y$w_buff0~0_338, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_169, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_37|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_206|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_43|, ULTIMATE.start_main_~#t2506~0.base=|v_ULTIMATE.start_main_~#t2506~0.base_20|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_21, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_114|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_106, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_42|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_348, #valid=|v_#valid_59|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_90, ~weak$$choice2~0=v_~weak$$choice2~0_112, ULTIMATE.start_main_~#t2505~0.base=|v_ULTIMATE.start_main_~#t2505~0.base_20|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2504~0.base, ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t2504~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t2505~0.offset, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t2506~0.offset, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2506~0.base, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t2505~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 19:00:12,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [707] [707] L798-1-->L800: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2505~0.base_9| 4)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2505~0.base_9|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2505~0.base_9|)) (not (= 0 |v_ULTIMATE.start_main_~#t2505~0.base_9|)) (= (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2505~0.base_9| 1) |v_#valid_33|) (= |v_ULTIMATE.start_main_~#t2505~0.offset_9| 0) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2505~0.base_9| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2505~0.base_9|) |v_ULTIMATE.start_main_~#t2505~0.offset_9| 1)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, ULTIMATE.start_main_~#t2505~0.offset=|v_ULTIMATE.start_main_~#t2505~0.offset_9|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2505~0.base=|v_ULTIMATE.start_main_~#t2505~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2505~0.offset, #length, ULTIMATE.start_main_~#t2505~0.base] because there is no mapped edge [2019-12-07 19:00:12,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L800-1-->L802: Formula: (and (= |v_ULTIMATE.start_main_~#t2506~0.offset_9| 0) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2506~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2506~0.base_10|) |v_ULTIMATE.start_main_~#t2506~0.offset_9| 2)) |v_#memory_int_11|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t2506~0.base_10| 1)) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2506~0.base_10| 4) |v_#length_13|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t2506~0.base_10|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t2506~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t2506~0.base_10| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t2506~0.offset=|v_ULTIMATE.start_main_~#t2506~0.offset_9|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t2506~0.base=|v_ULTIMATE.start_main_~#t2506~0.base_10|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2506~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t2506~0.base, #length] because there is no mapped edge [2019-12-07 19:00:12,113 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] P2ENTRY-->L4-3: Formula: (and (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| (ite (not (and (not (= 0 (mod ~y$w_buff1_used~0_Out-24977062 256))) (not (= (mod ~y$w_buff0_used~0_Out-24977062 256) 0)))) 1 0)) (= 1 ~y$w_buff0_used~0_Out-24977062) (= P2Thread1of1ForFork0_~arg.offset_Out-24977062 |P2Thread1of1ForFork0_#in~arg.offset_In-24977062|) (= |P2Thread1of1ForFork0_#in~arg.base_In-24977062| P2Thread1of1ForFork0_~arg.base_Out-24977062) (= ~y$w_buff0_used~0_In-24977062 ~y$w_buff1_used~0_Out-24977062) (= ~y$w_buff0~0_Out-24977062 2) (not (= 0 P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062)) (= |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062| P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062) (= ~y$w_buff1~0_Out-24977062 ~y$w_buff0~0_In-24977062)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-24977062, ~y$w_buff0~0=~y$w_buff0~0_In-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|} OutVars{P2Thread1of1ForFork0_~arg.base=P2Thread1of1ForFork0_~arg.base_Out-24977062, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_Out-24977062|, P2Thread1of1ForFork0_#in~arg.offset=|P2Thread1of1ForFork0_#in~arg.offset_In-24977062|, ~y$w_buff0_used~0=~y$w_buff0_used~0_Out-24977062, ~y$w_buff1~0=~y$w_buff1~0_Out-24977062, ~y$w_buff0~0=~y$w_buff0~0_Out-24977062, P2Thread1of1ForFork0_~arg.offset=P2Thread1of1ForFork0_~arg.offset_Out-24977062, P2Thread1of1ForFork0_#in~arg.base=|P2Thread1of1ForFork0_#in~arg.base_In-24977062|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=P2Thread1of1ForFork0___VERIFIER_assert_~expression_Out-24977062, ~y$w_buff1_used~0=~y$w_buff1_used~0_Out-24977062} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 19:00:12,113 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_60 1) (= (+ v_~__unbuffered_cnt~0_57 1) v_~__unbuffered_cnt~0_56) (= |v_P0Thread1of1ForFork1_#in~arg.base_17| v_P0Thread1of1ForFork1_~arg.base_15) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= v_P0Thread1of1ForFork1_~arg.offset_15 |v_P0Thread1of1ForFork1_#in~arg.offset_17|) (= v_~z~0_51 2) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_57, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_17|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_15, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, ~z~0=v_~z~0_51, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_17|, ~x~0=v_~x~0_60, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_15} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 19:00:12,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L776-->L776-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In-2000280432 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2000280432 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| ~y$w_buff0_used~0_In-2000280432) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-2000280432| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2000280432, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-2000280432|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2000280432} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 19:00:12,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L746-2-->L746-5: Formula: (let ((.cse2 (= |P1Thread1of1ForFork2_#t~ite4_Out-1032287144| |P1Thread1of1ForFork2_#t~ite3_Out-1032287144|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1032287144 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-1032287144 256)))) (or (and (not .cse0) (not .cse1) .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y$w_buff1~0_In-1032287144)) (and .cse2 (= |P1Thread1of1ForFork2_#t~ite3_Out-1032287144| ~y~0_In-1032287144) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, ~y~0=~y~0_In-1032287144, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1032287144, ~y$w_buff1~0=~y$w_buff1~0_In-1032287144, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1032287144|, ~y~0=~y~0_In-1032287144, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1032287144|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1032287144} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 19:00:12,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L777-->L777-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In439139011 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd3~0_In439139011 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In439139011 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In439139011 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| ~y$w_buff1_used~0_In439139011)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out439139011| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In439139011, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439139011, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out439139011|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In439139011, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439139011} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 19:00:12,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In10111743 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In10111743 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| 0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out10111743| ~y$w_buff0_used~0_In10111743) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In10111743, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In10111743, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out10111743|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 19:00:12,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [672] [672] L748-->L748-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1807078712 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1807078712 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1807078712 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1807078712 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| 0)) (and (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out1807078712| ~y$w_buff1_used~0_In1807078712) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1807078712, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1807078712, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1807078712, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1807078712|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1807078712} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 19:00:12,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1375098561 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1375098561 256)))) (or (and (= ~y$r_buff0_thd2~0_In1375098561 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1375098561|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1375098561, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1375098561, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1375098561|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 19:00:12,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L750-->L750-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1670259436 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1670259436 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1670259436 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1670259436 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|)) (and (or .cse1 .cse0) (= ~y$r_buff1_thd2~0_In1670259436 |P1Thread1of1ForFork2_#t~ite8_Out1670259436|) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1670259436, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1670259436, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1670259436|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1670259436, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1670259436} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 19:00:12,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L750-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_34| v_~y$r_buff1_thd2~0_71) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_71, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_33|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L778-->L779: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In16129428 256))) (.cse2 (= ~y$r_buff0_thd3~0_Out16129428 ~y$r_buff0_thd3~0_In16129428)) (.cse1 (= (mod ~y$w_buff0_used~0_In16129428 256) 0))) (or (and (= ~y$r_buff0_thd3~0_Out16129428 0) (not .cse0) (not .cse1)) (and .cse2 .cse0) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In16129428} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In16129428, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out16129428, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out16129428|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L779-->L779-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1318651703 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In1318651703 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1318651703 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In1318651703 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1318651703|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out1318651703| ~y$r_buff1_thd3~0_In1318651703) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1318651703|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1318651703, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1318651703, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1318651703, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1318651703} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L779-2-->P2EXIT: Formula: (and (= v_~__unbuffered_cnt~0_68 (+ v_~__unbuffered_cnt~0_69 1)) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_32| v_~y$r_buff1_thd3~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_69} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_31|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_66, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L802-1-->L808: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L808-2-->L808-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-535386570 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-535386570 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite18_Out-535386570| |ULTIMATE.start_main_#t~ite19_Out-535386570|))) (or (and (not .cse0) .cse1 (not .cse2) (= ~y$w_buff1~0_In-535386570 |ULTIMATE.start_main_#t~ite18_Out-535386570|)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-535386570| ~y~0_In-535386570) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-535386570, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-535386570, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-535386570|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-535386570|, ~y~0=~y~0_In-535386570, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-535386570, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-535386570} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 19:00:12,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-->L809-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1592832274 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1592832274 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1592832274| ~y$w_buff0_used~0_In-1592832274) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1592832274|) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1592832274, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1592832274, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1592832274|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 19:00:12,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L810-->L810-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-97834117 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-97834117 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-97834117 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd0~0_In-97834117 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-97834117| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite21_Out-97834117| ~y$w_buff1_used~0_In-97834117)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-97834117, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-97834117, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-97834117|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-97834117, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-97834117} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 19:00:12,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1041155812 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1041155812 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1041155812| ~y$r_buff0_thd0~0_In1041155812)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out1041155812|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1041155812, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1041155812, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1041155812|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 19:00:12,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L812-->L812-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-705899353 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-705899353 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-705899353 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-705899353 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-705899353 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-705899353|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-705899353, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-705899353, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-705899353, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-705899353|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-705899353} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 19:00:12,118 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L820-->L820-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1030380200 256) 0))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1030380200 256) 0))) (or (and (= (mod ~y$w_buff1_used~0_In-1030380200 256) 0) .cse0) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-1030380200 256) 0)) (= (mod ~y$w_buff0_used~0_In-1030380200 256) 0))) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= ~y$w_buff0~0_In-1030380200 |ULTIMATE.start_main_#t~ite29_Out-1030380200|) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite29_In-1030380200| |ULTIMATE.start_main_#t~ite29_Out-1030380200|) (= |ULTIMATE.start_main_#t~ite30_Out-1030380200| ~y$w_buff0~0_In-1030380200)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1030380200|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1030380200, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1030380200|, ~y$w_buff0~0=~y$w_buff0~0_In-1030380200, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1030380200, ~weak$$choice2~0=~weak$$choice2~0_In-1030380200, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1030380200, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1030380200} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 19:00:12,118 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L821-->L821-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-254870859 256) 0))) (or (and (not .cse0) (= ~y$w_buff1~0_In-254870859 |ULTIMATE.start_main_#t~ite33_Out-254870859|) (= |ULTIMATE.start_main_#t~ite32_In-254870859| |ULTIMATE.start_main_#t~ite32_Out-254870859|)) (and .cse0 (= |ULTIMATE.start_main_#t~ite32_Out-254870859| ~y$w_buff1~0_In-254870859) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-254870859 256)))) (or (and .cse1 (= (mod ~y$r_buff1_thd0~0_In-254870859 256) 0)) (and (= 0 (mod ~y$w_buff1_used~0_In-254870859 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In-254870859 256)))) (= |ULTIMATE.start_main_#t~ite32_Out-254870859| |ULTIMATE.start_main_#t~ite33_Out-254870859|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-254870859, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-254870859, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-254870859, ~weak$$choice2~0=~weak$$choice2~0_In-254870859, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-254870859|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-254870859, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out-254870859|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-254870859} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-12-07 19:00:12,119 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In984766544 256) 0))) (or (and (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite35_Out984766544|) (= |ULTIMATE.start_main_#t~ite36_Out984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In984766544 256)))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In984766544 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In984766544 256) 0) .cse0) (= (mod ~y$w_buff0_used~0_In984766544 256) 0))) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In984766544| |ULTIMATE.start_main_#t~ite35_Out984766544|) (= ~y$w_buff0_used~0_In984766544 |ULTIMATE.start_main_#t~ite36_Out984766544|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In984766544, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In984766544, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out984766544|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out984766544|, ~weak$$choice2~0=~weak$$choice2~0_In984766544, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In984766544, ~y$w_buff1_used~0=~y$w_buff1_used~0_In984766544} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-12-07 19:00:12,119 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L824-->L825-8: Formula: (and (= v_~y$r_buff1_thd0~0_226 |v_ULTIMATE.start_main_#t~ite45_60|) (not (= 0 (mod v_~weak$$choice2~0_105 256))) (= |v_ULTIMATE.start_main_#t~ite43_49| |v_ULTIMATE.start_main_#t~ite43_48|) (= |v_ULTIMATE.start_main_#t~ite44_49| |v_ULTIMATE.start_main_#t~ite44_48|) (= v_~y$r_buff0_thd0~0_339 v_~y$r_buff0_thd0~0_338)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_339, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_49|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_49|} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_35|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_338, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ~weak$$choice2~0=v_~weak$$choice2~0_105, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_226, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_19|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_48|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 19:00:12,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] L827-->L830-1: Formula: (and (= (mod v_~main$tmp_guard1~0_21 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_~y~0_89 v_~y$mem_tmp~0_11) (= 0 v_~y$flush_delayed~0_23) (not (= (mod v_~y$flush_delayed~0_24 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_23, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_23|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_21, ~y~0=v_~y~0_89, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:00:12,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [703] [703] L830-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 19:00:12,169 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_1c35f7e4-5638-4824-a506-03ee135e3f73/bin/uautomizer/witness.graphml [2019-12-07 19:00:12,170 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 19:00:12,171 INFO L168 Benchmark]: Toolchain (without parser) took 42181.08 ms. Allocated memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: 2.5 GB). Free memory was 939.3 MB in the beginning and 1.4 GB in the end (delta: -503.6 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,171 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:00:12,171 INFO L168 Benchmark]: CACSL2BoogieTranslator took 449.95 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -125.2 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,171 INFO L168 Benchmark]: Boogie Procedure Inliner took 48.41 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,172 INFO L168 Benchmark]: Boogie Preprocessor took 26.26 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:00:12,172 INFO L168 Benchmark]: RCFGBuilder took 388.66 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.1 MB). Peak memory consumption was 54.1 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,172 INFO L168 Benchmark]: TraceAbstraction took 41202.44 ms. Allocated memory was 1.1 GB in the beginning and 3.5 GB in the end (delta: 2.4 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -454.5 MB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,172 INFO L168 Benchmark]: Witness Printer took 60.41 ms. Allocated memory is still 3.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 16.6 MB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:12,174 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 449.95 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -125.2 MB). Peak memory consumption was 23.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 48.41 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.26 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 388.66 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 54.1 MB). Peak memory consumption was 54.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 41202.44 ms. Allocated memory was 1.1 GB in the beginning and 3.5 GB in the end (delta: 2.4 GB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -454.5 MB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. * Witness Printer took 60.41 ms. Allocated memory is still 3.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 16.6 MB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 161 ProgramPointsBefore, 81 ProgramPointsAfterwards, 192 TransitionsBefore, 86 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 30 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 4050 VarBasedMoverChecksPositive, 194 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 46210 CheckedPairsTotal, 110 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L798] FCALL, FORK 0 pthread_create(&t2504, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L800] FCALL, FORK 0 pthread_create(&t2505, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t2506, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L765] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L766] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L767] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L768] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L769] 3 y$r_buff0_thd3 = (_Bool)1 [L772] 3 z = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L775] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L740] 2 x = 2 [L743] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L775] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L746] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L776] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L746] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L777] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L747] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L748] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L749] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L808] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L808] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L809] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L810] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L811] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L812] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L815] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L816] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L817] 0 y$flush_delayed = weak$$choice2 [L818] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L819] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L820] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L821] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L822] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L825] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L826] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 152 locations, 2 error locations. Result: UNSAFE, OverallTime: 41.0s, OverallIterations: 39, TraceHistogramMax: 1, AutomataDifference: 21.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7247 SDtfs, 10266 SDslu, 35419 SDs, 0 SdLazy, 15512 SolverSat, 758 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 660 GetRequests, 50 SyntacticMatches, 18 SemanticMatches, 592 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4411 ImplicationChecksByTransitivity, 7.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=31198occurred in iteration=6, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.6s AutomataMinimizationTime, 38 MinimizatonAttempts, 242627 StatesRemovedByMinimization, 34 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 3.1s InterpolantComputationTime, 1397 NumberOfCodeBlocks, 1397 NumberOfCodeBlocksAsserted, 39 NumberOfCheckSat, 1303 ConstructedInterpolants, 0 QuantifiedInterpolants, 301838 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 38 InterpolantComputations, 38 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...