./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b4d1a2938d6ae8a9b01acdb4953c59ea95e54f7d ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:30:37,474 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:30:37,475 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:30:37,483 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:30:37,484 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:30:37,484 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:30:37,485 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:30:37,487 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:30:37,488 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:30:37,489 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:30:37,490 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:30:37,491 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:30:37,491 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:30:37,492 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:30:37,493 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:30:37,494 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:30:37,495 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:30:37,496 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:30:37,497 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:30:37,499 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:30:37,500 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:30:37,501 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:30:37,502 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:30:37,503 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:30:37,505 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:30:37,505 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:30:37,505 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:30:37,506 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:30:37,506 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:30:37,507 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:30:37,507 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:30:37,508 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:30:37,508 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:30:37,509 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:30:37,510 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:30:37,510 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:30:37,510 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:30:37,510 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:30:37,511 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:30:37,511 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:30:37,512 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:30:37,513 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 14:30:37,524 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:30:37,524 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:30:37,525 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 14:30:37,525 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 14:30:37,525 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 14:30:37,525 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:30:37,526 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:30:37,527 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:30:37,527 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:30:37,527 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:30:37,527 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:30:37,527 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:30:37,527 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:30:37,528 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:30:37,528 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:30:37,529 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:30:37,529 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b4d1a2938d6ae8a9b01acdb4953c59ea95e54f7d [2019-12-07 14:30:37,638 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:30:37,649 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:30:37,651 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:30:37,653 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:30:37,653 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:30:37,654 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i [2019-12-07 14:30:37,697 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/data/74398a5fb/c5fdf9c260454b1cab5ab07c6ba2ade0/FLAG5d26ed693 [2019-12-07 14:30:38,071 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:30:38,072 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/sv-benchmarks/c/pthread-wmm/safe031_power.opt.i [2019-12-07 14:30:38,082 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/data/74398a5fb/c5fdf9c260454b1cab5ab07c6ba2ade0/FLAG5d26ed693 [2019-12-07 14:30:38,091 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/data/74398a5fb/c5fdf9c260454b1cab5ab07c6ba2ade0 [2019-12-07 14:30:38,093 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:30:38,094 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:30:38,094 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:30:38,094 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:30:38,096 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:30:38,097 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,099 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5bd1e142 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38, skipping insertion in model container [2019-12-07 14:30:38,099 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,104 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:30:38,134 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:30:38,375 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:30:38,383 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:30:38,426 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:30:38,473 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:30:38,473 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38 WrapperNode [2019-12-07 14:30:38,473 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:30:38,474 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:30:38,474 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:30:38,474 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:30:38,480 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,492 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,517 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:30:38,517 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:30:38,517 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:30:38,517 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:30:38,524 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,524 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,527 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,527 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,534 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,536 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,539 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... [2019-12-07 14:30:38,542 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:30:38,542 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:30:38,543 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:30:38,543 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:30:38,543 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 14:30:38,587 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 14:30:38,587 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 14:30:38,587 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 14:30:38,588 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 14:30:38,588 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 14:30:38,588 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:30:38,588 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:30:38,589 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 14:30:38,943 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:30:38,943 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 14:30:38,944 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:30:38 BoogieIcfgContainer [2019-12-07 14:30:38,944 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:30:38,945 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:30:38,945 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:30:38,947 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:30:38,947 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:30:38" (1/3) ... [2019-12-07 14:30:38,947 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@62397131 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:30:38, skipping insertion in model container [2019-12-07 14:30:38,948 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:30:38" (2/3) ... [2019-12-07 14:30:38,948 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@62397131 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:30:38, skipping insertion in model container [2019-12-07 14:30:38,948 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:30:38" (3/3) ... [2019-12-07 14:30:38,949 INFO L109 eAbstractionObserver]: Analyzing ICFG safe031_power.opt.i [2019-12-07 14:30:38,955 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 14:30:38,955 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:30:38,959 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 14:30:38,960 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,983 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,984 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,984 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,984 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,984 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,984 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,985 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,986 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,987 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,987 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,987 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,987 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,987 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,988 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,988 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,988 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,988 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,988 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,989 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,989 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,989 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,990 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,991 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,991 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,991 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,991 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,992 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,993 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,994 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:38,995 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:30:39,005 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 14:30:39,018 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:30:39,018 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:30:39,018 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:30:39,018 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:30:39,019 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:30:39,019 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:30:39,019 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:30:39,019 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:30:39,031 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-12-07 14:30:39,032 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-12-07 14:30:39,093 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-12-07 14:30:39,093 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:30:39,103 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 14:30:39,113 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-12-07 14:30:39,146 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-12-07 14:30:39,146 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:30:39,151 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 14:30:39,161 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 14:30:39,162 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 14:30:41,829 WARN L192 SmtUtils]: Spent 132.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 14:30:41,909 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48124 [2019-12-07 14:30:41,909 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 14:30:41,912 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 94 transitions [2019-12-07 14:30:42,590 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15710 states. [2019-12-07 14:30:42,592 INFO L276 IsEmpty]: Start isEmpty. Operand 15710 states. [2019-12-07 14:30:42,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 14:30:42,596 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:42,597 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:42,597 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:42,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:42,601 INFO L82 PathProgramCache]: Analyzing trace with hash 2126234855, now seen corresponding path program 1 times [2019-12-07 14:30:42,607 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:42,607 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153985612] [2019-12-07 14:30:42,607 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:42,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:42,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:42,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153985612] [2019-12-07 14:30:42,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:42,755 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 14:30:42,755 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034662149] [2019-12-07 14:30:42,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:30:42,758 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:42,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:30:42,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:42,769 INFO L87 Difference]: Start difference. First operand 15710 states. Second operand 3 states. [2019-12-07 14:30:43,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:43,012 INFO L93 Difference]: Finished difference Result 15638 states and 59348 transitions. [2019-12-07 14:30:43,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:30:43,013 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 14:30:43,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:43,132 INFO L225 Difference]: With dead ends: 15638 [2019-12-07 14:30:43,132 INFO L226 Difference]: Without dead ends: 15326 [2019-12-07 14:30:43,133 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:43,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15326 states. [2019-12-07 14:30:43,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15326 to 15326. [2019-12-07 14:30:43,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15326 states. [2019-12-07 14:30:43,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15326 states to 15326 states and 58230 transitions. [2019-12-07 14:30:43,673 INFO L78 Accepts]: Start accepts. Automaton has 15326 states and 58230 transitions. Word has length 7 [2019-12-07 14:30:43,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:43,674 INFO L462 AbstractCegarLoop]: Abstraction has 15326 states and 58230 transitions. [2019-12-07 14:30:43,674 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:30:43,674 INFO L276 IsEmpty]: Start isEmpty. Operand 15326 states and 58230 transitions. [2019-12-07 14:30:43,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:30:43,677 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:43,677 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:43,677 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:43,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:43,677 INFO L82 PathProgramCache]: Analyzing trace with hash -380072381, now seen corresponding path program 1 times [2019-12-07 14:30:43,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:43,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605364975] [2019-12-07 14:30:43,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:43,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:43,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:43,736 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605364975] [2019-12-07 14:30:43,736 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:43,736 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:30:43,736 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029463427] [2019-12-07 14:30:43,737 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:30:43,737 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:43,738 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:30:43,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:30:43,738 INFO L87 Difference]: Start difference. First operand 15326 states and 58230 transitions. Second operand 4 states. [2019-12-07 14:30:44,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:44,039 INFO L93 Difference]: Finished difference Result 24490 states and 89350 transitions. [2019-12-07 14:30:44,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:30:44,040 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:30:44,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:44,098 INFO L225 Difference]: With dead ends: 24490 [2019-12-07 14:30:44,098 INFO L226 Difference]: Without dead ends: 24476 [2019-12-07 14:30:44,099 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:44,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24476 states. [2019-12-07 14:30:44,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24476 to 22206. [2019-12-07 14:30:44,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22206 states. [2019-12-07 14:30:44,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22206 states to 22206 states and 82052 transitions. [2019-12-07 14:30:44,661 INFO L78 Accepts]: Start accepts. Automaton has 22206 states and 82052 transitions. Word has length 13 [2019-12-07 14:30:44,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:44,661 INFO L462 AbstractCegarLoop]: Abstraction has 22206 states and 82052 transitions. [2019-12-07 14:30:44,661 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:30:44,661 INFO L276 IsEmpty]: Start isEmpty. Operand 22206 states and 82052 transitions. [2019-12-07 14:30:44,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:30:44,664 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:44,664 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:44,664 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:44,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:44,665 INFO L82 PathProgramCache]: Analyzing trace with hash 691839138, now seen corresponding path program 1 times [2019-12-07 14:30:44,665 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:44,665 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554074421] [2019-12-07 14:30:44,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:44,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:44,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:44,713 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554074421] [2019-12-07 14:30:44,713 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:44,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:30:44,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635726732] [2019-12-07 14:30:44,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:30:44,714 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:44,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:30:44,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:30:44,714 INFO L87 Difference]: Start difference. First operand 22206 states and 82052 transitions. Second operand 4 states. [2019-12-07 14:30:44,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:44,904 INFO L93 Difference]: Finished difference Result 27876 states and 102039 transitions. [2019-12-07 14:30:44,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:30:44,904 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:30:44,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:45,043 INFO L225 Difference]: With dead ends: 27876 [2019-12-07 14:30:45,043 INFO L226 Difference]: Without dead ends: 27876 [2019-12-07 14:30:45,043 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:45,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27876 states. [2019-12-07 14:30:45,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27876 to 24582. [2019-12-07 14:30:45,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24582 states. [2019-12-07 14:30:45,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24582 states to 24582 states and 90664 transitions. [2019-12-07 14:30:45,501 INFO L78 Accepts]: Start accepts. Automaton has 24582 states and 90664 transitions. Word has length 13 [2019-12-07 14:30:45,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:45,501 INFO L462 AbstractCegarLoop]: Abstraction has 24582 states and 90664 transitions. [2019-12-07 14:30:45,501 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:30:45,502 INFO L276 IsEmpty]: Start isEmpty. Operand 24582 states and 90664 transitions. [2019-12-07 14:30:45,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 14:30:45,506 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:45,506 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:45,507 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:45,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:45,507 INFO L82 PathProgramCache]: Analyzing trace with hash -165939970, now seen corresponding path program 1 times [2019-12-07 14:30:45,507 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:45,507 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453739110] [2019-12-07 14:30:45,507 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:45,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:45,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:45,582 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453739110] [2019-12-07 14:30:45,582 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:45,582 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:30:45,582 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293321059] [2019-12-07 14:30:45,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:30:45,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:45,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:30:45,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:45,583 INFO L87 Difference]: Start difference. First operand 24582 states and 90664 transitions. Second operand 5 states. [2019-12-07 14:30:45,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:45,928 INFO L93 Difference]: Finished difference Result 33300 states and 120391 transitions. [2019-12-07 14:30:45,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:30:45,929 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 14:30:45,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:46,079 INFO L225 Difference]: With dead ends: 33300 [2019-12-07 14:30:46,079 INFO L226 Difference]: Without dead ends: 33286 [2019-12-07 14:30:46,080 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:30:46,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33286 states. [2019-12-07 14:30:46,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33286 to 24486. [2019-12-07 14:30:46,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24486 states. [2019-12-07 14:30:46,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24486 states to 24486 states and 90098 transitions. [2019-12-07 14:30:46,568 INFO L78 Accepts]: Start accepts. Automaton has 24486 states and 90098 transitions. Word has length 19 [2019-12-07 14:30:46,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:46,568 INFO L462 AbstractCegarLoop]: Abstraction has 24486 states and 90098 transitions. [2019-12-07 14:30:46,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:30:46,568 INFO L276 IsEmpty]: Start isEmpty. Operand 24486 states and 90098 transitions. [2019-12-07 14:30:46,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 14:30:46,585 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:46,585 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:46,585 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:46,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:46,586 INFO L82 PathProgramCache]: Analyzing trace with hash -1278693284, now seen corresponding path program 1 times [2019-12-07 14:30:46,586 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:46,586 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554496718] [2019-12-07 14:30:46,586 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:46,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:46,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:46,616 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554496718] [2019-12-07 14:30:46,616 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:46,616 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:30:46,616 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210914572] [2019-12-07 14:30:46,616 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:30:46,616 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:46,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:30:46,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:46,617 INFO L87 Difference]: Start difference. First operand 24486 states and 90098 transitions. Second operand 3 states. [2019-12-07 14:30:46,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:46,738 INFO L93 Difference]: Finished difference Result 29936 states and 108805 transitions. [2019-12-07 14:30:46,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:30:46,738 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 14:30:46,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:46,792 INFO L225 Difference]: With dead ends: 29936 [2019-12-07 14:30:46,792 INFO L226 Difference]: Without dead ends: 29936 [2019-12-07 14:30:46,793 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:47,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29936 states. [2019-12-07 14:30:47,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29936 to 26410. [2019-12-07 14:30:47,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26410 states. [2019-12-07 14:30:47,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26410 states to 26410 states and 96908 transitions. [2019-12-07 14:30:47,332 INFO L78 Accepts]: Start accepts. Automaton has 26410 states and 96908 transitions. Word has length 27 [2019-12-07 14:30:47,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:47,333 INFO L462 AbstractCegarLoop]: Abstraction has 26410 states and 96908 transitions. [2019-12-07 14:30:47,333 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:30:47,333 INFO L276 IsEmpty]: Start isEmpty. Operand 26410 states and 96908 transitions. [2019-12-07 14:30:47,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 14:30:47,345 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:47,345 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:47,345 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:47,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:47,346 INFO L82 PathProgramCache]: Analyzing trace with hash -1374888423, now seen corresponding path program 1 times [2019-12-07 14:30:47,346 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:47,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710731343] [2019-12-07 14:30:47,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:47,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:47,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:47,378 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710731343] [2019-12-07 14:30:47,378 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:47,378 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:30:47,378 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683813517] [2019-12-07 14:30:47,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:30:47,379 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:47,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:30:47,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:47,379 INFO L87 Difference]: Start difference. First operand 26410 states and 96908 transitions. Second operand 3 states. [2019-12-07 14:30:47,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:47,437 INFO L93 Difference]: Finished difference Result 15137 states and 48090 transitions. [2019-12-07 14:30:47,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:30:47,438 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 14:30:47,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:47,458 INFO L225 Difference]: With dead ends: 15137 [2019-12-07 14:30:47,458 INFO L226 Difference]: Without dead ends: 15137 [2019-12-07 14:30:47,458 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:47,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15137 states. [2019-12-07 14:30:47,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15137 to 15137. [2019-12-07 14:30:47,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15137 states. [2019-12-07 14:30:47,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15137 states to 15137 states and 48090 transitions. [2019-12-07 14:30:47,683 INFO L78 Accepts]: Start accepts. Automaton has 15137 states and 48090 transitions. Word has length 27 [2019-12-07 14:30:47,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:47,683 INFO L462 AbstractCegarLoop]: Abstraction has 15137 states and 48090 transitions. [2019-12-07 14:30:47,683 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:30:47,684 INFO L276 IsEmpty]: Start isEmpty. Operand 15137 states and 48090 transitions. [2019-12-07 14:30:47,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 14:30:47,690 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:47,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:47,690 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:47,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:47,690 INFO L82 PathProgramCache]: Analyzing trace with hash 783683513, now seen corresponding path program 1 times [2019-12-07 14:30:47,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:47,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439030989] [2019-12-07 14:30:47,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:47,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:47,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:47,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439030989] [2019-12-07 14:30:47,728 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:47,728 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:30:47,728 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461420422] [2019-12-07 14:30:47,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:30:47,728 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:47,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:30:47,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:30:47,729 INFO L87 Difference]: Start difference. First operand 15137 states and 48090 transitions. Second operand 4 states. [2019-12-07 14:30:47,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:47,744 INFO L93 Difference]: Finished difference Result 2291 states and 5311 transitions. [2019-12-07 14:30:47,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:30:47,745 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-12-07 14:30:47,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:47,747 INFO L225 Difference]: With dead ends: 2291 [2019-12-07 14:30:47,747 INFO L226 Difference]: Without dead ends: 2291 [2019-12-07 14:30:47,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:30:47,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2291 states. [2019-12-07 14:30:47,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2291 to 2291. [2019-12-07 14:30:47,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2291 states. [2019-12-07 14:30:47,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2291 states to 2291 states and 5311 transitions. [2019-12-07 14:30:47,767 INFO L78 Accepts]: Start accepts. Automaton has 2291 states and 5311 transitions. Word has length 28 [2019-12-07 14:30:47,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:47,768 INFO L462 AbstractCegarLoop]: Abstraction has 2291 states and 5311 transitions. [2019-12-07 14:30:47,768 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:30:47,768 INFO L276 IsEmpty]: Start isEmpty. Operand 2291 states and 5311 transitions. [2019-12-07 14:30:47,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 14:30:47,770 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:47,770 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:47,770 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:47,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:47,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1644769556, now seen corresponding path program 1 times [2019-12-07 14:30:47,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:47,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022570853] [2019-12-07 14:30:47,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:47,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:47,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:47,819 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022570853] [2019-12-07 14:30:47,819 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:47,819 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:30:47,819 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509438983] [2019-12-07 14:30:47,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:30:47,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:47,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:30:47,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:47,820 INFO L87 Difference]: Start difference. First operand 2291 states and 5311 transitions. Second operand 5 states. [2019-12-07 14:30:47,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:47,835 INFO L93 Difference]: Finished difference Result 653 states and 1502 transitions. [2019-12-07 14:30:47,836 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:30:47,836 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-12-07 14:30:47,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:47,836 INFO L225 Difference]: With dead ends: 653 [2019-12-07 14:30:47,836 INFO L226 Difference]: Without dead ends: 653 [2019-12-07 14:30:47,837 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:47,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 653 states. [2019-12-07 14:30:47,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 653 to 597. [2019-12-07 14:30:47,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-12-07 14:30:47,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1370 transitions. [2019-12-07 14:30:47,842 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1370 transitions. Word has length 40 [2019-12-07 14:30:47,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:47,842 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1370 transitions. [2019-12-07 14:30:47,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:30:47,842 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1370 transitions. [2019-12-07 14:30:47,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 14:30:47,844 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:47,844 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:47,844 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:47,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:47,844 INFO L82 PathProgramCache]: Analyzing trace with hash -922835002, now seen corresponding path program 1 times [2019-12-07 14:30:47,844 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:47,844 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060813808] [2019-12-07 14:30:47,844 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:47,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:47,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:47,915 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060813808] [2019-12-07 14:30:47,915 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:47,915 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:30:47,915 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57502678] [2019-12-07 14:30:47,916 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:30:47,916 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:47,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:30:47,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:30:47,916 INFO L87 Difference]: Start difference. First operand 597 states and 1370 transitions. Second operand 6 states. [2019-12-07 14:30:48,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,114 INFO L93 Difference]: Finished difference Result 950 states and 2192 transitions. [2019-12-07 14:30:48,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 14:30:48,114 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-12-07 14:30:48,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,115 INFO L225 Difference]: With dead ends: 950 [2019-12-07 14:30:48,115 INFO L226 Difference]: Without dead ends: 950 [2019-12-07 14:30:48,116 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:30:48,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 950 states. [2019-12-07 14:30:48,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 950 to 852. [2019-12-07 14:30:48,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 852 states. [2019-12-07 14:30:48,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 852 states to 852 states and 1967 transitions. [2019-12-07 14:30:48,123 INFO L78 Accepts]: Start accepts. Automaton has 852 states and 1967 transitions. Word has length 55 [2019-12-07 14:30:48,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,123 INFO L462 AbstractCegarLoop]: Abstraction has 852 states and 1967 transitions. [2019-12-07 14:30:48,123 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:30:48,123 INFO L276 IsEmpty]: Start isEmpty. Operand 852 states and 1967 transitions. [2019-12-07 14:30:48,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 14:30:48,124 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,125 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,125 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,125 INFO L82 PathProgramCache]: Analyzing trace with hash -256459022, now seen corresponding path program 2 times [2019-12-07 14:30:48,125 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,125 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633350564] [2019-12-07 14:30:48,125 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:48,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:48,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633350564] [2019-12-07 14:30:48,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:48,190 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:30:48,190 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315277541] [2019-12-07 14:30:48,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:30:48,190 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:48,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:30:48,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:30:48,191 INFO L87 Difference]: Start difference. First operand 852 states and 1967 transitions. Second operand 6 states. [2019-12-07 14:30:48,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,419 INFO L93 Difference]: Finished difference Result 1292 states and 2987 transitions. [2019-12-07 14:30:48,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:30:48,419 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-12-07 14:30:48,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,421 INFO L225 Difference]: With dead ends: 1292 [2019-12-07 14:30:48,421 INFO L226 Difference]: Without dead ends: 1292 [2019-12-07 14:30:48,421 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:30:48,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1292 states. [2019-12-07 14:30:48,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1292 to 934. [2019-12-07 14:30:48,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2019-12-07 14:30:48,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 2174 transitions. [2019-12-07 14:30:48,430 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 2174 transitions. Word has length 55 [2019-12-07 14:30:48,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,431 INFO L462 AbstractCegarLoop]: Abstraction has 934 states and 2174 transitions. [2019-12-07 14:30:48,431 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:30:48,431 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 2174 transitions. [2019-12-07 14:30:48,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 14:30:48,432 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,432 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,432 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,432 INFO L82 PathProgramCache]: Analyzing trace with hash -198491454, now seen corresponding path program 3 times [2019-12-07 14:30:48,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,433 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148632027] [2019-12-07 14:30:48,433 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:48,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:48,472 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148632027] [2019-12-07 14:30:48,472 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:48,473 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:30:48,473 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341481522] [2019-12-07 14:30:48,473 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:30:48,473 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:48,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:30:48,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:48,474 INFO L87 Difference]: Start difference. First operand 934 states and 2174 transitions. Second operand 3 states. [2019-12-07 14:30:48,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,503 INFO L93 Difference]: Finished difference Result 934 states and 2173 transitions. [2019-12-07 14:30:48,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:30:48,503 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-12-07 14:30:48,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,505 INFO L225 Difference]: With dead ends: 934 [2019-12-07 14:30:48,505 INFO L226 Difference]: Without dead ends: 934 [2019-12-07 14:30:48,505 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:48,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 934 states. [2019-12-07 14:30:48,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 934 to 645. [2019-12-07 14:30:48,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 645 states. [2019-12-07 14:30:48,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 645 states and 1497 transitions. [2019-12-07 14:30:48,514 INFO L78 Accepts]: Start accepts. Automaton has 645 states and 1497 transitions. Word has length 55 [2019-12-07 14:30:48,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,514 INFO L462 AbstractCegarLoop]: Abstraction has 645 states and 1497 transitions. [2019-12-07 14:30:48,515 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:30:48,515 INFO L276 IsEmpty]: Start isEmpty. Operand 645 states and 1497 transitions. [2019-12-07 14:30:48,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 14:30:48,516 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,516 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,516 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,516 INFO L82 PathProgramCache]: Analyzing trace with hash 1438906431, now seen corresponding path program 1 times [2019-12-07 14:30:48,517 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,517 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767968432] [2019-12-07 14:30:48,517 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:48,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:48,581 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767968432] [2019-12-07 14:30:48,581 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:48,581 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:30:48,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144029213] [2019-12-07 14:30:48,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:30:48,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:48,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:30:48,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:30:48,582 INFO L87 Difference]: Start difference. First operand 645 states and 1497 transitions. Second operand 5 states. [2019-12-07 14:30:48,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,616 INFO L93 Difference]: Finished difference Result 933 states and 2016 transitions. [2019-12-07 14:30:48,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:30:48,616 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 14:30:48,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,617 INFO L225 Difference]: With dead ends: 933 [2019-12-07 14:30:48,617 INFO L226 Difference]: Without dead ends: 580 [2019-12-07 14:30:48,617 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:30:48,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states. [2019-12-07 14:30:48,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 580. [2019-12-07 14:30:48,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 580 states. [2019-12-07 14:30:48,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 580 states to 580 states and 1308 transitions. [2019-12-07 14:30:48,622 INFO L78 Accepts]: Start accepts. Automaton has 580 states and 1308 transitions. Word has length 56 [2019-12-07 14:30:48,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,622 INFO L462 AbstractCegarLoop]: Abstraction has 580 states and 1308 transitions. [2019-12-07 14:30:48,622 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:30:48,622 INFO L276 IsEmpty]: Start isEmpty. Operand 580 states and 1308 transitions. [2019-12-07 14:30:48,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 14:30:48,623 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,623 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,623 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,624 INFO L82 PathProgramCache]: Analyzing trace with hash 89701865, now seen corresponding path program 2 times [2019-12-07 14:30:48,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622570887] [2019-12-07 14:30:48,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:48,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:48,656 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622570887] [2019-12-07 14:30:48,656 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:48,656 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:30:48,656 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147014341] [2019-12-07 14:30:48,656 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:30:48,656 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:48,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:30:48,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:48,657 INFO L87 Difference]: Start difference. First operand 580 states and 1308 transitions. Second operand 3 states. [2019-12-07 14:30:48,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,665 INFO L93 Difference]: Finished difference Result 571 states and 1252 transitions. [2019-12-07 14:30:48,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:30:48,665 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-12-07 14:30:48,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,666 INFO L225 Difference]: With dead ends: 571 [2019-12-07 14:30:48,666 INFO L226 Difference]: Without dead ends: 571 [2019-12-07 14:30:48,666 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:30:48,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2019-12-07 14:30:48,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 535. [2019-12-07 14:30:48,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 535 states. [2019-12-07 14:30:48,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 535 states to 535 states and 1166 transitions. [2019-12-07 14:30:48,670 INFO L78 Accepts]: Start accepts. Automaton has 535 states and 1166 transitions. Word has length 56 [2019-12-07 14:30:48,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,670 INFO L462 AbstractCegarLoop]: Abstraction has 535 states and 1166 transitions. [2019-12-07 14:30:48,670 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:30:48,670 INFO L276 IsEmpty]: Start isEmpty. Operand 535 states and 1166 transitions. [2019-12-07 14:30:48,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:48,671 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,671 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,671 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,672 INFO L82 PathProgramCache]: Analyzing trace with hash 574299964, now seen corresponding path program 1 times [2019-12-07 14:30:48,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184842230] [2019-12-07 14:30:48,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:48,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:48,763 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184842230] [2019-12-07 14:30:48,763 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:48,763 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:30:48,763 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406186938] [2019-12-07 14:30:48,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:30:48,763 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:48,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:30:48,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:30:48,764 INFO L87 Difference]: Start difference. First operand 535 states and 1166 transitions. Second operand 7 states. [2019-12-07 14:30:48,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:48,848 INFO L93 Difference]: Finished difference Result 788 states and 1679 transitions. [2019-12-07 14:30:48,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 14:30:48,848 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-12-07 14:30:48,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:48,849 INFO L225 Difference]: With dead ends: 788 [2019-12-07 14:30:48,849 INFO L226 Difference]: Without dead ends: 233 [2019-12-07 14:30:48,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:30:48,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2019-12-07 14:30:48,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 209. [2019-12-07 14:30:48,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2019-12-07 14:30:48,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 365 transitions. [2019-12-07 14:30:48,852 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 365 transitions. Word has length 57 [2019-12-07 14:30:48,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:48,853 INFO L462 AbstractCegarLoop]: Abstraction has 209 states and 365 transitions. [2019-12-07 14:30:48,853 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:30:48,853 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 365 transitions. [2019-12-07 14:30:48,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:48,853 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:48,853 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:48,854 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:48,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:48,854 INFO L82 PathProgramCache]: Analyzing trace with hash -431408076, now seen corresponding path program 2 times [2019-12-07 14:30:48,854 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:48,854 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585243243] [2019-12-07 14:30:48,854 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:48,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:49,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:49,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585243243] [2019-12-07 14:30:49,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:49,387 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 14:30:49,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557010000] [2019-12-07 14:30:49,387 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 14:30:49,388 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:49,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 14:30:49,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2019-12-07 14:30:49,388 INFO L87 Difference]: Start difference. First operand 209 states and 365 transitions. Second operand 21 states. [2019-12-07 14:30:50,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:50,192 INFO L93 Difference]: Finished difference Result 615 states and 1058 transitions. [2019-12-07 14:30:50,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 14:30:50,192 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 57 [2019-12-07 14:30:50,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:50,192 INFO L225 Difference]: With dead ends: 615 [2019-12-07 14:30:50,193 INFO L226 Difference]: Without dead ends: 582 [2019-12-07 14:30:50,193 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 295 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=225, Invalid=1107, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 14:30:50,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2019-12-07 14:30:50,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 272. [2019-12-07 14:30:50,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-12-07 14:30:50,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 470 transitions. [2019-12-07 14:30:50,196 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 470 transitions. Word has length 57 [2019-12-07 14:30:50,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:50,196 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 470 transitions. [2019-12-07 14:30:50,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 14:30:50,196 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 470 transitions. [2019-12-07 14:30:50,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:50,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:50,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:50,197 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:50,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:50,197 INFO L82 PathProgramCache]: Analyzing trace with hash -550616912, now seen corresponding path program 3 times [2019-12-07 14:30:50,197 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:50,197 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249387590] [2019-12-07 14:30:50,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:50,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:50,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:50,452 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249387590] [2019-12-07 14:30:50,452 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:50,452 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 14:30:50,452 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984656403] [2019-12-07 14:30:50,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 14:30:50,453 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:50,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 14:30:50,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=193, Unknown=0, NotChecked=0, Total=240 [2019-12-07 14:30:50,453 INFO L87 Difference]: Start difference. First operand 272 states and 470 transitions. Second operand 16 states. [2019-12-07 14:30:50,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:50,976 INFO L93 Difference]: Finished difference Result 491 states and 835 transitions. [2019-12-07 14:30:50,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 14:30:50,976 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 57 [2019-12-07 14:30:50,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:50,977 INFO L225 Difference]: With dead ends: 491 [2019-12-07 14:30:50,977 INFO L226 Difference]: Without dead ends: 458 [2019-12-07 14:30:50,977 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=137, Invalid=619, Unknown=0, NotChecked=0, Total=756 [2019-12-07 14:30:50,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states. [2019-12-07 14:30:50,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 302. [2019-12-07 14:30:50,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2019-12-07 14:30:50,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 529 transitions. [2019-12-07 14:30:50,980 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 529 transitions. Word has length 57 [2019-12-07 14:30:50,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:50,980 INFO L462 AbstractCegarLoop]: Abstraction has 302 states and 529 transitions. [2019-12-07 14:30:50,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 14:30:50,981 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 529 transitions. [2019-12-07 14:30:50,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:50,981 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:50,981 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:50,981 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:50,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:50,981 INFO L82 PathProgramCache]: Analyzing trace with hash 83087540, now seen corresponding path program 4 times [2019-12-07 14:30:50,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:50,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497661691] [2019-12-07 14:30:50,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:50,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:51,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:51,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497661691] [2019-12-07 14:30:51,184 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:51,184 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 14:30:51,184 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630176007] [2019-12-07 14:30:51,184 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 14:30:51,185 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:51,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 14:30:51,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:30:51,185 INFO L87 Difference]: Start difference. First operand 302 states and 529 transitions. Second operand 14 states. [2019-12-07 14:30:51,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:51,548 INFO L93 Difference]: Finished difference Result 449 states and 765 transitions. [2019-12-07 14:30:51,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 14:30:51,548 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-12-07 14:30:51,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:51,549 INFO L225 Difference]: With dead ends: 449 [2019-12-07 14:30:51,549 INFO L226 Difference]: Without dead ends: 414 [2019-12-07 14:30:51,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=107, Invalid=493, Unknown=0, NotChecked=0, Total=600 [2019-12-07 14:30:51,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states. [2019-12-07 14:30:51,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 305. [2019-12-07 14:30:51,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 305 states. [2019-12-07 14:30:51,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305 states to 305 states and 529 transitions. [2019-12-07 14:30:51,553 INFO L78 Accepts]: Start accepts. Automaton has 305 states and 529 transitions. Word has length 57 [2019-12-07 14:30:51,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:51,553 INFO L462 AbstractCegarLoop]: Abstraction has 305 states and 529 transitions. [2019-12-07 14:30:51,553 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 14:30:51,553 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 529 transitions. [2019-12-07 14:30:51,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:51,554 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:51,554 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:51,554 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:51,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:51,554 INFO L82 PathProgramCache]: Analyzing trace with hash 42803636, now seen corresponding path program 5 times [2019-12-07 14:30:51,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:51,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922457423] [2019-12-07 14:30:51,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:51,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:51,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:51,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922457423] [2019-12-07 14:30:51,754 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:51,754 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 14:30:51,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219128278] [2019-12-07 14:30:51,755 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 14:30:51,755 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:51,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 14:30:51,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:30:51,755 INFO L87 Difference]: Start difference. First operand 305 states and 529 transitions. Second operand 14 states. [2019-12-07 14:30:52,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:52,113 INFO L93 Difference]: Finished difference Result 426 states and 715 transitions. [2019-12-07 14:30:52,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 14:30:52,113 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-12-07 14:30:52,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:52,114 INFO L225 Difference]: With dead ends: 426 [2019-12-07 14:30:52,114 INFO L226 Difference]: Without dead ends: 391 [2019-12-07 14:30:52,114 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=503, Unknown=0, NotChecked=0, Total=600 [2019-12-07 14:30:52,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2019-12-07 14:30:52,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 309. [2019-12-07 14:30:52,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 309 states. [2019-12-07 14:30:52,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 536 transitions. [2019-12-07 14:30:52,117 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 536 transitions. Word has length 57 [2019-12-07 14:30:52,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:52,117 INFO L462 AbstractCegarLoop]: Abstraction has 309 states and 536 transitions. [2019-12-07 14:30:52,117 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 14:30:52,117 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 536 transitions. [2019-12-07 14:30:52,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:52,118 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:52,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:52,118 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:52,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:52,118 INFO L82 PathProgramCache]: Analyzing trace with hash -1239613688, now seen corresponding path program 6 times [2019-12-07 14:30:52,118 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:52,118 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172955231] [2019-12-07 14:30:52,118 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:52,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:30:52,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:30:52,247 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172955231] [2019-12-07 14:30:52,247 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:30:52,247 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:30:52,247 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038358297] [2019-12-07 14:30:52,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:30:52,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:30:52,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:30:52,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:30:52,248 INFO L87 Difference]: Start difference. First operand 309 states and 536 transitions. Second operand 12 states. [2019-12-07 14:30:52,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:30:52,479 INFO L93 Difference]: Finished difference Result 414 states and 694 transitions. [2019-12-07 14:30:52,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 14:30:52,479 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2019-12-07 14:30:52,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:30:52,480 INFO L225 Difference]: With dead ends: 414 [2019-12-07 14:30:52,480 INFO L226 Difference]: Without dead ends: 379 [2019-12-07 14:30:52,480 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=342, Unknown=0, NotChecked=0, Total=420 [2019-12-07 14:30:52,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2019-12-07 14:30:52,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 317. [2019-12-07 14:30:52,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-12-07 14:30:52,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 550 transitions. [2019-12-07 14:30:52,483 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 550 transitions. Word has length 57 [2019-12-07 14:30:52,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:30:52,483 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 550 transitions. [2019-12-07 14:30:52,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:30:52,483 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 550 transitions. [2019-12-07 14:30:52,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 14:30:52,483 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:30:52,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:30:52,484 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:30:52,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:30:52,484 INFO L82 PathProgramCache]: Analyzing trace with hash -97225810, now seen corresponding path program 7 times [2019-12-07 14:30:52,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:30:52,484 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490130022] [2019-12-07 14:30:52,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:30:52,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:30:52,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:30:52,541 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 14:30:52,541 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:30:52,543 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22| 1)) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= (select .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22|) 0) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2516~0.base_22|) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= 0 |v_ULTIMATE.start_main_~#t2516~0.offset_17|) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22|) |v_ULTIMATE.start_main_~#t2516~0.offset_17| 0)) |v_#memory_int_19|) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2516~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_~#t2516~0.base=|v_ULTIMATE.start_main_~#t2516~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_15|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t2516~0.offset=|v_ULTIMATE.start_main_~#t2516~0.offset_17|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_18|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_19|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_15|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t2516~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2517~0.offset, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t2516~0.offset, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2518~0.base, ULTIMATE.start_main_~#t2517~0.base, ULTIMATE.start_main_~#t2518~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:30:52,544 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2517~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2517~0.base_11|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11|) |v_ULTIMATE.start_main_~#t2517~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2517~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t2517~0.base_11| 0)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2517~0.offset, ULTIMATE.start_main_~#t2517~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 14:30:52,544 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2518~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10|) |v_ULTIMATE.start_main_~#t2518~0.offset_10| 2)) |v_#memory_int_13|) (not (= 0 |v_ULTIMATE.start_main_~#t2518~0.base_10|)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10| 1)) (= 0 |v_ULTIMATE.start_main_~#t2518~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2518~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2518~0.base] because there is no mapped edge [2019-12-07 14:30:52,544 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:30:52,545 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 14:30:52,545 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1355249050 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1355249050 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1355249050 |P2Thread1of1ForFork0_#t~ite11_Out1355249050|)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out1355249050| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1355249050, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1355249050} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1355249050, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1355249050|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1355249050} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 14:30:52,546 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-295519737 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-295519737 256) 0)) (.cse1 (= |P1Thread1of1ForFork2_#t~ite4_Out-295519737| |P1Thread1of1ForFork2_#t~ite3_Out-295519737|))) (or (and (not .cse0) (= ~y$w_buff1~0_In-295519737 |P1Thread1of1ForFork2_#t~ite3_Out-295519737|) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= ~y~0_In-295519737 |P1Thread1of1ForFork2_#t~ite3_Out-295519737|) .cse1))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-295519737, ~y$w_buff1~0=~y$w_buff1~0_In-295519737, ~y~0=~y~0_In-295519737, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-295519737} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-295519737, ~y$w_buff1~0=~y$w_buff1~0_In-295519737, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-295519737|, ~y~0=~y~0_In-295519737, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-295519737|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-295519737} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:30:52,546 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In238760992 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In238760992 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite5_Out238760992| ~y$w_buff0_used~0_In238760992) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out238760992| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In238760992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In238760992} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In238760992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In238760992, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out238760992|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:30:52,547 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-790703078 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-790703078 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-790703078 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-790703078 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-790703078|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-790703078 |P2Thread1of1ForFork0_#t~ite12_Out-790703078|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-790703078, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-790703078, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-790703078, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-790703078} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-790703078, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-790703078, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-790703078|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-790703078, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-790703078} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 14:30:52,547 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In382979464 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In382979464 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In382979464 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In382979464 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out382979464|)) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out382979464| ~y$w_buff1_used~0_In382979464)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In382979464, ~y$w_buff0_used~0=~y$w_buff0_used~0_In382979464, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In382979464, ~y$w_buff1_used~0=~y$w_buff1_used~0_In382979464} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In382979464, ~y$w_buff0_used~0=~y$w_buff0_used~0_In382979464, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In382979464, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out382979464|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In382979464} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:30:52,547 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1846937123 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1846937123 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff0_thd2~0_In-1846937123 |P1Thread1of1ForFork2_#t~ite7_Out-1846937123|)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-1846937123|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1846937123, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1846937123} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1846937123, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1846937123, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1846937123|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:30:52,547 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In-1290212418 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-1290212418 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1290212418 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1290212418 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-1290212418|)) (and (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-1290212418 |P1Thread1of1ForFork2_#t~ite8_Out-1290212418|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1290212418, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1290212418, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1290212418, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1290212418} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1290212418, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1290212418, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-1290212418|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1290212418, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1290212418} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:30:52,547 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 14:30:52,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= ~y$r_buff0_thd3~0_Out-781701001 ~y$r_buff0_thd3~0_In-781701001)) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-781701001 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-781701001 256) 0))) (or (and .cse0 .cse1) (and .cse1 .cse2) (and (not .cse2) (= ~y$r_buff0_thd3~0_Out-781701001 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-781701001, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-781701001} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-781701001, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-781701001, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-781701001|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 14:30:52,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-1231143379 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1231143379 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In-1231143379 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1231143379 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd3~0_In-1231143379 |P2Thread1of1ForFork0_#t~ite14_Out-1231143379|)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out-1231143379| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1231143379, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1231143379, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1231143379, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1231143379} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1231143379|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1231143379, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1231143379, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1231143379, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1231143379} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 14:30:52,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 14:30:52,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 14:30:52,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In1844935308 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In1844935308 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite18_Out1844935308| |ULTIMATE.start_main_#t~ite19_Out1844935308|))) (or (and .cse0 (not .cse1) (= ~y$w_buff1~0_In1844935308 |ULTIMATE.start_main_#t~ite18_Out1844935308|) (not .cse2)) (and (or .cse2 .cse1) .cse0 (= |ULTIMATE.start_main_#t~ite18_Out1844935308| ~y~0_In1844935308)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1844935308, ~y~0=~y~0_In1844935308, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1844935308, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1844935308} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1844935308, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1844935308|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out1844935308|, ~y~0=~y~0_In1844935308, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1844935308, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1844935308} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:30:52,549 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1757608102 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-1757608102 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1757608102| ~y$w_buff0_used~0_In-1757608102) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-1757608102| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1757608102, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1757608102} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1757608102, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1757608102, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1757608102|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:30:52,549 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1628320572 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-1628320572 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In-1628320572 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-1628320572 256) 0))) (or (and (= ~y$w_buff1_used~0_In-1628320572 |ULTIMATE.start_main_#t~ite21_Out-1628320572|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |ULTIMATE.start_main_#t~ite21_Out-1628320572|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1628320572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1628320572, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1628320572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1628320572} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1628320572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1628320572, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1628320572|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1628320572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1628320572} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:30:52,549 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1513771628 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1513771628 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1513771628| ~y$r_buff0_thd0~0_In1513771628)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite22_Out1513771628| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1513771628, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1513771628} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1513771628, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1513771628, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1513771628|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:30:52,549 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In1678852574 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1678852574 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1678852574 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1678852574 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In1678852574 |ULTIMATE.start_main_#t~ite23_Out1678852574|) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite23_Out1678852574| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1678852574, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1678852574, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1678852574, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1678852574} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1678852574, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1678852574, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1678852574, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1678852574|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1678852574} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:30:52,551 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1991186277 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_Out-1991186277| |ULTIMATE.start_main_#t~ite38_Out-1991186277|) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1991186277 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In-1991186277 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-1991186277 256) 0) (and (= (mod ~y$r_buff1_thd0~0_In-1991186277 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite38_Out-1991186277| ~y$w_buff1_used~0_In-1991186277)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out-1991186277| ~y$w_buff1_used~0_In-1991186277) (= |ULTIMATE.start_main_#t~ite38_In-1991186277| |ULTIMATE.start_main_#t~ite38_Out-1991186277|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1991186277, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1991186277, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1991186277|, ~weak$$choice2~0=~weak$$choice2~0_In-1991186277, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1991186277, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991186277} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1991186277, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1991186277|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1991186277, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1991186277|, ~weak$$choice2~0=~weak$$choice2~0_In-1991186277, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1991186277, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991186277} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 14:30:52,552 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:30:52,552 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:30:52,552 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:30:52,604 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:30:52 BasicIcfg [2019-12-07 14:30:52,604 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:30:52,605 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:30:52,605 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:30:52,605 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:30:52,605 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:30:38" (3/4) ... [2019-12-07 14:30:52,607 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:30:52,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22| 1)) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= (select .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22|) 0) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2516~0.base_22|) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= 0 |v_ULTIMATE.start_main_~#t2516~0.offset_17|) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22|) |v_ULTIMATE.start_main_~#t2516~0.offset_17| 0)) |v_#memory_int_19|) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2516~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_~#t2516~0.base=|v_ULTIMATE.start_main_~#t2516~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_15|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t2516~0.offset=|v_ULTIMATE.start_main_~#t2516~0.offset_17|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_18|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_19|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_15|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t2516~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2517~0.offset, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t2516~0.offset, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2518~0.base, ULTIMATE.start_main_~#t2517~0.base, ULTIMATE.start_main_~#t2518~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:30:52,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2517~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2517~0.base_11|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11|) |v_ULTIMATE.start_main_~#t2517~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2517~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t2517~0.base_11| 0)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2517~0.offset, ULTIMATE.start_main_~#t2517~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-12-07 14:30:52,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2518~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10|) |v_ULTIMATE.start_main_~#t2518~0.offset_10| 2)) |v_#memory_int_13|) (not (= 0 |v_ULTIMATE.start_main_~#t2518~0.base_10|)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10| 1)) (= 0 |v_ULTIMATE.start_main_~#t2518~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2518~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2518~0.base] because there is no mapped edge [2019-12-07 14:30:52,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 14:30:52,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 14:30:52,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1355249050 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1355249050 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1355249050 |P2Thread1of1ForFork0_#t~ite11_Out1355249050|)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out1355249050| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1355249050, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1355249050} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1355249050, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1355249050|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1355249050} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 14:30:52,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-295519737 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-295519737 256) 0)) (.cse1 (= |P1Thread1of1ForFork2_#t~ite4_Out-295519737| |P1Thread1of1ForFork2_#t~ite3_Out-295519737|))) (or (and (not .cse0) (= ~y$w_buff1~0_In-295519737 |P1Thread1of1ForFork2_#t~ite3_Out-295519737|) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= ~y~0_In-295519737 |P1Thread1of1ForFork2_#t~ite3_Out-295519737|) .cse1))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-295519737, ~y$w_buff1~0=~y$w_buff1~0_In-295519737, ~y~0=~y~0_In-295519737, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-295519737} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-295519737, ~y$w_buff1~0=~y$w_buff1~0_In-295519737, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-295519737|, ~y~0=~y~0_In-295519737, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-295519737|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-295519737} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In238760992 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In238760992 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite5_Out238760992| ~y$w_buff0_used~0_In238760992) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out238760992| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In238760992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In238760992} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In238760992, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In238760992, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out238760992|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-790703078 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-790703078 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-790703078 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-790703078 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out-790703078|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-790703078 |P2Thread1of1ForFork0_#t~ite12_Out-790703078|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-790703078, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-790703078, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-790703078, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-790703078} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-790703078, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-790703078, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-790703078|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-790703078, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-790703078} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In382979464 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In382979464 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In382979464 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In382979464 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out382979464|)) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite6_Out382979464| ~y$w_buff1_used~0_In382979464)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In382979464, ~y$w_buff0_used~0=~y$w_buff0_used~0_In382979464, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In382979464, ~y$w_buff1_used~0=~y$w_buff1_used~0_In382979464} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In382979464, ~y$w_buff0_used~0=~y$w_buff0_used~0_In382979464, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In382979464, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out382979464|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In382979464} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1846937123 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1846937123 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff0_thd2~0_In-1846937123 |P1Thread1of1ForFork2_#t~ite7_Out-1846937123|)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-1846937123|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1846937123, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1846937123} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1846937123, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1846937123, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1846937123|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In-1290212418 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-1290212418 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In-1290212418 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1290212418 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-1290212418|)) (and (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-1290212418 |P1Thread1of1ForFork2_#t~ite8_Out-1290212418|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1290212418, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1290212418, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1290212418, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1290212418} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1290212418, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1290212418, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-1290212418|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1290212418, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1290212418} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 14:30:52,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 14:30:52,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= ~y$r_buff0_thd3~0_Out-781701001 ~y$r_buff0_thd3~0_In-781701001)) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-781701001 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-781701001 256) 0))) (or (and .cse0 .cse1) (and .cse1 .cse2) (and (not .cse2) (= ~y$r_buff0_thd3~0_Out-781701001 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-781701001, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-781701001} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-781701001, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-781701001, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-781701001|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 14:30:52,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-1231143379 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1231143379 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd3~0_In-1231143379 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In-1231143379 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd3~0_In-1231143379 |P2Thread1of1ForFork0_#t~ite14_Out-1231143379|)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out-1231143379| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1231143379, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1231143379, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1231143379, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1231143379} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-1231143379|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1231143379, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1231143379, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1231143379, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1231143379} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 14:30:52,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 14:30:52,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 14:30:52,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In1844935308 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In1844935308 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite18_Out1844935308| |ULTIMATE.start_main_#t~ite19_Out1844935308|))) (or (and .cse0 (not .cse1) (= ~y$w_buff1~0_In1844935308 |ULTIMATE.start_main_#t~ite18_Out1844935308|) (not .cse2)) (and (or .cse2 .cse1) .cse0 (= |ULTIMATE.start_main_#t~ite18_Out1844935308| ~y~0_In1844935308)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1844935308, ~y~0=~y~0_In1844935308, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1844935308, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1844935308} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1844935308, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1844935308|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out1844935308|, ~y~0=~y~0_In1844935308, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1844935308, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1844935308} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 14:30:52,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1757608102 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-1757608102 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1757608102| ~y$w_buff0_used~0_In-1757608102) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-1757608102| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1757608102, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1757608102} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1757608102, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1757608102, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1757608102|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 14:30:52,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1628320572 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-1628320572 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In-1628320572 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In-1628320572 256) 0))) (or (and (= ~y$w_buff1_used~0_In-1628320572 |ULTIMATE.start_main_#t~ite21_Out-1628320572|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= 0 |ULTIMATE.start_main_#t~ite21_Out-1628320572|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1628320572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1628320572, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1628320572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1628320572} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1628320572, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1628320572, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1628320572|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1628320572, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1628320572} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 14:30:52,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1513771628 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1513771628 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out1513771628| ~y$r_buff0_thd0~0_In1513771628)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite22_Out1513771628| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1513771628, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1513771628} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1513771628, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1513771628, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1513771628|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 14:30:52,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In1678852574 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In1678852574 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1678852574 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1678852574 256) 0))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In1678852574 |ULTIMATE.start_main_#t~ite23_Out1678852574|) (or .cse2 .cse3)) (and (= |ULTIMATE.start_main_#t~ite23_Out1678852574| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1678852574, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1678852574, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1678852574, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1678852574} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1678852574, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1678852574, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1678852574, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1678852574|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1678852574} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 14:30:52,614 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1991186277 256)))) (or (and (= |ULTIMATE.start_main_#t~ite39_Out-1991186277| |ULTIMATE.start_main_#t~ite38_Out-1991186277|) .cse0 (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1991186277 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In-1991186277 256)) .cse1) (= (mod ~y$w_buff0_used~0_In-1991186277 256) 0) (and (= (mod ~y$r_buff1_thd0~0_In-1991186277 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite38_Out-1991186277| ~y$w_buff1_used~0_In-1991186277)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out-1991186277| ~y$w_buff1_used~0_In-1991186277) (= |ULTIMATE.start_main_#t~ite38_In-1991186277| |ULTIMATE.start_main_#t~ite38_Out-1991186277|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1991186277, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1991186277, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1991186277|, ~weak$$choice2~0=~weak$$choice2~0_In-1991186277, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1991186277, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991186277} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1991186277, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1991186277|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1991186277, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1991186277|, ~weak$$choice2~0=~weak$$choice2~0_In-1991186277, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1991186277, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991186277} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 14:30:52,614 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 14:30:52,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:30:52,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:30:52,667 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_81ffdc2f-e8c3-40cd-a06f-bfa6c131b265/bin/uautomizer/witness.graphml [2019-12-07 14:30:52,667 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:30:52,668 INFO L168 Benchmark]: Toolchain (without parser) took 14574.89 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 955.8 MB). Free memory was 939.9 MB in the beginning and 1.4 GB in the end (delta: -429.9 MB). Peak memory consumption was 525.9 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,669 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:30:52,669 INFO L168 Benchmark]: CACSL2BoogieTranslator took 379.27 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.8 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -130.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,669 INFO L168 Benchmark]: Boogie Procedure Inliner took 42.98 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,669 INFO L168 Benchmark]: Boogie Preprocessor took 25.42 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:30:52,670 INFO L168 Benchmark]: RCFGBuilder took 401.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,670 INFO L168 Benchmark]: TraceAbstraction took 13659.52 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 853.0 MB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -386.0 MB). Peak memory consumption was 467.0 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,670 INFO L168 Benchmark]: Witness Printer took 62.69 ms. Allocated memory is still 2.0 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 26.1 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. [2019-12-07 14:30:52,671 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 379.27 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.8 MB). Free memory was 939.9 MB in the beginning and 1.1 GB in the end (delta: -130.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 42.98 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.42 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 401.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 13659.52 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 853.0 MB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -386.0 MB). Peak memory consumption was 467.0 MB. Max. memory is 11.5 GB. * Witness Printer took 62.69 ms. Allocated memory is still 2.0 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 26.1 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.8s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 94 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 24 ChoiceCompositions, 4225 VarBasedMoverChecksPositive, 199 VarBasedMoverChecksNegative, 61 SemBasedMoverChecksPositive, 194 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 48124 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L802] FCALL, FORK 0 pthread_create(&t2516, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t2517, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L806] FCALL, FORK 0 pthread_create(&t2518, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L770] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L771] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L772] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L773] 3 y$r_buff0_thd3 = (_Bool)1 [L776] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L779] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L744] 2 x = 1 [L747] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L779] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L750] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L780] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L750] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L751] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L752] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L753] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L781] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L812] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L812] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L813] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L814] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L815] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L816] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L819] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L820] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L821] 0 y$flush_delayed = weak$$choice2 [L822] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L824] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L824] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L825] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L826] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L826] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L827] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L829] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L829] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L830] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 13.5s, OverallIterations: 20, TraceHistogramMax: 1, AutomataDifference: 4.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2022 SDtfs, 2260 SDslu, 5766 SDs, 0 SdLazy, 4368 SolverSat, 231 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 225 GetRequests, 29 SyntacticMatches, 17 SemanticMatches, 179 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 1.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=26410occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 2.8s AutomataMinimizationTime, 19 MinimizatonAttempts, 19470 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 850 NumberOfCodeBlocks, 850 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 774 ConstructedInterpolants, 0 QuantifiedInterpolants, 173381 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 19 InterpolantComputations, 19 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...