./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/safe031_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/safe031_rmo.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2b02757bf4ae4f54cb849d3632e927e001c40b7b ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:04:35,483 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:04:35,484 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:04:35,492 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:04:35,492 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:04:35,493 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:04:35,494 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:04:35,495 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:04:35,496 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:04:35,497 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:04:35,497 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:04:35,498 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:04:35,498 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:04:35,499 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:04:35,500 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:04:35,501 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:04:35,501 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:04:35,502 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:04:35,503 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:04:35,505 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:04:35,506 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:04:35,506 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:04:35,507 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:04:35,507 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:04:35,509 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:04:35,509 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:04:35,510 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:04:35,510 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:04:35,510 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:04:35,511 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:04:35,511 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:04:35,511 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:04:35,512 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:04:35,512 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:04:35,513 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:04:35,513 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:04:35,513 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:04:35,514 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:04:35,514 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:04:35,514 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:04:35,515 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:04:35,515 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:04:35,525 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:04:35,525 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:04:35,525 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:04:35,526 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:04:35,526 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:04:35,526 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:04:35,526 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:04:35,526 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:04:35,526 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:04:35,527 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:04:35,528 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:04:35,528 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:04:35,528 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:04:35,528 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:04:35,528 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:04:35,528 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:04:35,528 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:04:35,529 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b02757bf4ae4f54cb849d3632e927e001c40b7b [2019-12-07 18:04:35,626 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:04:35,633 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:04:35,635 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:04:35,636 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:04:35,636 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:04:35,637 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/safe031_rmo.opt.i [2019-12-07 18:04:35,672 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/data/7af997d85/ec42f3984d2247ee9249b63d9e52b958/FLAG397c515a8 [2019-12-07 18:04:36,113 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:04:36,113 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/sv-benchmarks/c/pthread-wmm/safe031_rmo.opt.i [2019-12-07 18:04:36,124 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/data/7af997d85/ec42f3984d2247ee9249b63d9e52b958/FLAG397c515a8 [2019-12-07 18:04:36,134 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/data/7af997d85/ec42f3984d2247ee9249b63d9e52b958 [2019-12-07 18:04:36,136 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:04:36,137 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:04:36,137 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:04:36,137 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:04:36,140 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:04:36,141 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,143 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551fb3cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36, skipping insertion in model container [2019-12-07 18:04:36,143 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,150 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:04:36,180 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:04:36,424 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:04:36,431 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:04:36,472 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:04:36,518 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:04:36,519 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36 WrapperNode [2019-12-07 18:04:36,519 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:04:36,519 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:04:36,520 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:04:36,520 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:04:36,526 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,539 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,564 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:04:36,565 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:04:36,565 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:04:36,565 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:04:36,572 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,572 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,575 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,575 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,582 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,585 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,587 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... [2019-12-07 18:04:36,590 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:04:36,591 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:04:36,591 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:04:36,591 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:04:36,591 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:04:36,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:04:36,638 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:04:36,638 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:04:36,638 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:04:36,638 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:04:36,639 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:04:36,639 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:04:36,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:04:36,640 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:04:36,998 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:04:36,998 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:04:36,999 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:04:36 BoogieIcfgContainer [2019-12-07 18:04:36,999 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:04:37,000 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:04:37,000 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:04:37,002 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:04:37,002 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:04:36" (1/3) ... [2019-12-07 18:04:37,002 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6fea7730 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:04:37, skipping insertion in model container [2019-12-07 18:04:37,002 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:04:36" (2/3) ... [2019-12-07 18:04:37,003 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6fea7730 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:04:37, skipping insertion in model container [2019-12-07 18:04:37,003 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:04:36" (3/3) ... [2019-12-07 18:04:37,004 INFO L109 eAbstractionObserver]: Analyzing ICFG safe031_rmo.opt.i [2019-12-07 18:04:37,010 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:04:37,010 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:04:37,015 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:04:37,015 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,037 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,040 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,041 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,041 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,041 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,041 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,041 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,046 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:04:37,056 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:04:37,069 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:04:37,069 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:04:37,069 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:04:37,069 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:04:37,069 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:04:37,069 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:04:37,069 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:04:37,070 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:04:37,080 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-12-07 18:04:37,081 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-12-07 18:04:37,131 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-12-07 18:04:37,131 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:04:37,139 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:04:37,151 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-12-07 18:04:37,175 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-12-07 18:04:37,175 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:04:37,179 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-12-07 18:04:37,188 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-12-07 18:04:37,189 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:04:39,885 WARN L192 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-12-07 18:04:39,964 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48124 [2019-12-07 18:04:39,964 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 18:04:39,967 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 94 transitions [2019-12-07 18:04:40,694 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15710 states. [2019-12-07 18:04:40,695 INFO L276 IsEmpty]: Start isEmpty. Operand 15710 states. [2019-12-07 18:04:40,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 18:04:40,700 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:40,700 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:40,700 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:40,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:40,704 INFO L82 PathProgramCache]: Analyzing trace with hash 2126234855, now seen corresponding path program 1 times [2019-12-07 18:04:40,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:40,710 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177207610] [2019-12-07 18:04:40,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:40,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:40,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:40,862 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177207610] [2019-12-07 18:04:40,862 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:40,862 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:04:40,863 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107304892] [2019-12-07 18:04:40,866 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:04:40,866 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:40,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:04:40,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:40,877 INFO L87 Difference]: Start difference. First operand 15710 states. Second operand 3 states. [2019-12-07 18:04:41,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:41,097 INFO L93 Difference]: Finished difference Result 15638 states and 59348 transitions. [2019-12-07 18:04:41,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:04:41,098 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 18:04:41,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:41,216 INFO L225 Difference]: With dead ends: 15638 [2019-12-07 18:04:41,216 INFO L226 Difference]: Without dead ends: 15326 [2019-12-07 18:04:41,217 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:41,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15326 states. [2019-12-07 18:04:41,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15326 to 15326. [2019-12-07 18:04:41,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15326 states. [2019-12-07 18:04:41,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15326 states to 15326 states and 58230 transitions. [2019-12-07 18:04:41,738 INFO L78 Accepts]: Start accepts. Automaton has 15326 states and 58230 transitions. Word has length 7 [2019-12-07 18:04:41,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:41,739 INFO L462 AbstractCegarLoop]: Abstraction has 15326 states and 58230 transitions. [2019-12-07 18:04:41,739 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:04:41,739 INFO L276 IsEmpty]: Start isEmpty. Operand 15326 states and 58230 transitions. [2019-12-07 18:04:41,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:04:41,742 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:41,742 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:41,743 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:41,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:41,743 INFO L82 PathProgramCache]: Analyzing trace with hash -380072381, now seen corresponding path program 1 times [2019-12-07 18:04:41,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:41,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549142996] [2019-12-07 18:04:41,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:41,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:41,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:41,829 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549142996] [2019-12-07 18:04:41,829 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:41,829 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:04:41,830 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548994118] [2019-12-07 18:04:41,831 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:04:41,831 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:41,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:04:41,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:04:41,831 INFO L87 Difference]: Start difference. First operand 15326 states and 58230 transitions. Second operand 4 states. [2019-12-07 18:04:42,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:42,122 INFO L93 Difference]: Finished difference Result 24490 states and 89350 transitions. [2019-12-07 18:04:42,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:04:42,122 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:04:42,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:42,226 INFO L225 Difference]: With dead ends: 24490 [2019-12-07 18:04:42,226 INFO L226 Difference]: Without dead ends: 24476 [2019-12-07 18:04:42,227 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:42,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24476 states. [2019-12-07 18:04:42,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24476 to 22206. [2019-12-07 18:04:42,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22206 states. [2019-12-07 18:04:42,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22206 states to 22206 states and 82052 transitions. [2019-12-07 18:04:42,766 INFO L78 Accepts]: Start accepts. Automaton has 22206 states and 82052 transitions. Word has length 13 [2019-12-07 18:04:42,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:42,766 INFO L462 AbstractCegarLoop]: Abstraction has 22206 states and 82052 transitions. [2019-12-07 18:04:42,766 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:04:42,766 INFO L276 IsEmpty]: Start isEmpty. Operand 22206 states and 82052 transitions. [2019-12-07 18:04:42,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:04:42,769 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:42,769 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:42,769 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:42,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:42,769 INFO L82 PathProgramCache]: Analyzing trace with hash 691839138, now seen corresponding path program 1 times [2019-12-07 18:04:42,769 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:42,769 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113825280] [2019-12-07 18:04:42,770 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:42,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:42,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:42,823 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113825280] [2019-12-07 18:04:42,824 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:42,824 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:04:42,824 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044487135] [2019-12-07 18:04:42,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:04:42,824 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:42,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:04:42,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:04:42,825 INFO L87 Difference]: Start difference. First operand 22206 states and 82052 transitions. Second operand 4 states. [2019-12-07 18:04:43,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:43,009 INFO L93 Difference]: Finished difference Result 27876 states and 102039 transitions. [2019-12-07 18:04:43,009 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:04:43,009 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:04:43,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:43,160 INFO L225 Difference]: With dead ends: 27876 [2019-12-07 18:04:43,160 INFO L226 Difference]: Without dead ends: 27876 [2019-12-07 18:04:43,160 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:43,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27876 states. [2019-12-07 18:04:43,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27876 to 24582. [2019-12-07 18:04:43,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24582 states. [2019-12-07 18:04:43,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24582 states to 24582 states and 90664 transitions. [2019-12-07 18:04:43,607 INFO L78 Accepts]: Start accepts. Automaton has 24582 states and 90664 transitions. Word has length 13 [2019-12-07 18:04:43,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:43,607 INFO L462 AbstractCegarLoop]: Abstraction has 24582 states and 90664 transitions. [2019-12-07 18:04:43,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:04:43,608 INFO L276 IsEmpty]: Start isEmpty. Operand 24582 states and 90664 transitions. [2019-12-07 18:04:43,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:04:43,612 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:43,612 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:43,612 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:43,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:43,612 INFO L82 PathProgramCache]: Analyzing trace with hash -165939970, now seen corresponding path program 1 times [2019-12-07 18:04:43,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:43,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670232571] [2019-12-07 18:04:43,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:43,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:43,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:43,652 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670232571] [2019-12-07 18:04:43,652 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:43,652 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:04:43,652 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770468539] [2019-12-07 18:04:43,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:04:43,652 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:43,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:04:43,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:43,653 INFO L87 Difference]: Start difference. First operand 24582 states and 90664 transitions. Second operand 3 states. [2019-12-07 18:04:43,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:43,694 INFO L93 Difference]: Finished difference Result 13890 states and 44399 transitions. [2019-12-07 18:04:43,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:04:43,695 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 18:04:43,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:43,713 INFO L225 Difference]: With dead ends: 13890 [2019-12-07 18:04:43,713 INFO L226 Difference]: Without dead ends: 13890 [2019-12-07 18:04:43,713 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:43,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13890 states. [2019-12-07 18:04:43,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13890 to 13890. [2019-12-07 18:04:43,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13890 states. [2019-12-07 18:04:44,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13890 states to 13890 states and 44399 transitions. [2019-12-07 18:04:44,042 INFO L78 Accepts]: Start accepts. Automaton has 13890 states and 44399 transitions. Word has length 19 [2019-12-07 18:04:44,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:44,043 INFO L462 AbstractCegarLoop]: Abstraction has 13890 states and 44399 transitions. [2019-12-07 18:04:44,043 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:04:44,043 INFO L276 IsEmpty]: Start isEmpty. Operand 13890 states and 44399 transitions. [2019-12-07 18:04:44,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 18:04:44,045 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:44,045 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:44,045 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:44,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:44,045 INFO L82 PathProgramCache]: Analyzing trace with hash 1902167710, now seen corresponding path program 1 times [2019-12-07 18:04:44,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:44,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624380292] [2019-12-07 18:04:44,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:44,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:44,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:44,083 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624380292] [2019-12-07 18:04:44,083 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:44,083 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:04:44,083 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127423836] [2019-12-07 18:04:44,084 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:04:44,084 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:44,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:04:44,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:04:44,084 INFO L87 Difference]: Start difference. First operand 13890 states and 44399 transitions. Second operand 4 states. [2019-12-07 18:04:44,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:44,099 INFO L93 Difference]: Finished difference Result 1935 states and 4569 transitions. [2019-12-07 18:04:44,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:04:44,099 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20 [2019-12-07 18:04:44,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:44,101 INFO L225 Difference]: With dead ends: 1935 [2019-12-07 18:04:44,101 INFO L226 Difference]: Without dead ends: 1935 [2019-12-07 18:04:44,101 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:04:44,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1935 states. [2019-12-07 18:04:44,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1935 to 1935. [2019-12-07 18:04:44,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1935 states. [2019-12-07 18:04:44,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1935 states to 1935 states and 4569 transitions. [2019-12-07 18:04:44,120 INFO L78 Accepts]: Start accepts. Automaton has 1935 states and 4569 transitions. Word has length 20 [2019-12-07 18:04:44,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:44,120 INFO L462 AbstractCegarLoop]: Abstraction has 1935 states and 4569 transitions. [2019-12-07 18:04:44,120 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:04:44,120 INFO L276 IsEmpty]: Start isEmpty. Operand 1935 states and 4569 transitions. [2019-12-07 18:04:44,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 18:04:44,122 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:44,122 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:44,122 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:44,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:44,122 INFO L82 PathProgramCache]: Analyzing trace with hash 968226525, now seen corresponding path program 1 times [2019-12-07 18:04:44,122 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:44,123 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783645470] [2019-12-07 18:04:44,123 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:44,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:44,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:44,302 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783645470] [2019-12-07 18:04:44,302 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:44,303 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:04:44,303 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4918250] [2019-12-07 18:04:44,303 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:04:44,303 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:44,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:04:44,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:04:44,303 INFO L87 Difference]: Start difference. First operand 1935 states and 4569 transitions. Second operand 7 states. [2019-12-07 18:04:44,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:44,653 INFO L93 Difference]: Finished difference Result 2383 states and 5481 transitions. [2019-12-07 18:04:44,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:04:44,653 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2019-12-07 18:04:44,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:44,656 INFO L225 Difference]: With dead ends: 2383 [2019-12-07 18:04:44,656 INFO L226 Difference]: Without dead ends: 2383 [2019-12-07 18:04:44,657 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:04:44,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2383 states. [2019-12-07 18:04:44,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2383 to 2164. [2019-12-07 18:04:44,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2164 states. [2019-12-07 18:04:44,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2164 states to 2164 states and 5049 transitions. [2019-12-07 18:04:44,679 INFO L78 Accepts]: Start accepts. Automaton has 2164 states and 5049 transitions. Word has length 26 [2019-12-07 18:04:44,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:44,679 INFO L462 AbstractCegarLoop]: Abstraction has 2164 states and 5049 transitions. [2019-12-07 18:04:44,679 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:04:44,679 INFO L276 IsEmpty]: Start isEmpty. Operand 2164 states and 5049 transitions. [2019-12-07 18:04:44,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 18:04:44,681 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:44,681 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:44,682 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:44,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:44,682 INFO L82 PathProgramCache]: Analyzing trace with hash 1740964695, now seen corresponding path program 1 times [2019-12-07 18:04:44,682 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:44,682 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150673451] [2019-12-07 18:04:44,682 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:44,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:44,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:44,717 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150673451] [2019-12-07 18:04:44,717 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:44,717 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:04:44,718 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698943417] [2019-12-07 18:04:44,718 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:04:44,718 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:44,718 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:04:44,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:44,718 INFO L87 Difference]: Start difference. First operand 2164 states and 5049 transitions. Second operand 3 states. [2019-12-07 18:04:44,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:44,752 INFO L93 Difference]: Finished difference Result 2506 states and 5736 transitions. [2019-12-07 18:04:44,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:04:44,752 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 18:04:44,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:44,754 INFO L225 Difference]: With dead ends: 2506 [2019-12-07 18:04:44,754 INFO L226 Difference]: Without dead ends: 2506 [2019-12-07 18:04:44,754 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:44,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2506 states. [2019-12-07 18:04:44,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2506 to 2291. [2019-12-07 18:04:44,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2291 states. [2019-12-07 18:04:44,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2291 states to 2291 states and 5311 transitions. [2019-12-07 18:04:44,774 INFO L78 Accepts]: Start accepts. Automaton has 2291 states and 5311 transitions. Word has length 40 [2019-12-07 18:04:44,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:44,774 INFO L462 AbstractCegarLoop]: Abstraction has 2291 states and 5311 transitions. [2019-12-07 18:04:44,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:04:44,774 INFO L276 IsEmpty]: Start isEmpty. Operand 2291 states and 5311 transitions. [2019-12-07 18:04:44,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 18:04:44,776 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:44,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:44,776 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:44,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:44,777 INFO L82 PathProgramCache]: Analyzing trace with hash 1644769556, now seen corresponding path program 1 times [2019-12-07 18:04:44,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:44,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716674273] [2019-12-07 18:04:44,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:44,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:44,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:44,937 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716674273] [2019-12-07 18:04:44,937 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:44,937 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:04:44,937 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128535898] [2019-12-07 18:04:44,937 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 18:04:44,937 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:44,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:04:44,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:04:44,938 INFO L87 Difference]: Start difference. First operand 2291 states and 5311 transitions. Second operand 8 states. [2019-12-07 18:04:45,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:45,219 INFO L93 Difference]: Finished difference Result 2641 states and 5989 transitions. [2019-12-07 18:04:45,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:04:45,219 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2019-12-07 18:04:45,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:45,221 INFO L225 Difference]: With dead ends: 2641 [2019-12-07 18:04:45,221 INFO L226 Difference]: Without dead ends: 2640 [2019-12-07 18:04:45,222 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:04:45,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2640 states. [2019-12-07 18:04:45,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2640 to 2314. [2019-12-07 18:04:45,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2314 states. [2019-12-07 18:04:45,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2314 states to 2314 states and 5358 transitions. [2019-12-07 18:04:45,241 INFO L78 Accepts]: Start accepts. Automaton has 2314 states and 5358 transitions. Word has length 40 [2019-12-07 18:04:45,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:45,242 INFO L462 AbstractCegarLoop]: Abstraction has 2314 states and 5358 transitions. [2019-12-07 18:04:45,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 18:04:45,242 INFO L276 IsEmpty]: Start isEmpty. Operand 2314 states and 5358 transitions. [2019-12-07 18:04:45,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 18:04:45,244 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:45,244 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:45,244 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:45,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:45,244 INFO L82 PathProgramCache]: Analyzing trace with hash 1745362377, now seen corresponding path program 1 times [2019-12-07 18:04:45,244 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:45,245 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941561257] [2019-12-07 18:04:45,245 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:45,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:45,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:45,284 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941561257] [2019-12-07 18:04:45,284 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:45,284 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:04:45,284 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451443574] [2019-12-07 18:04:45,285 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:04:45,285 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:45,285 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:04:45,285 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:45,285 INFO L87 Difference]: Start difference. First operand 2314 states and 5358 transitions. Second operand 5 states. [2019-12-07 18:04:45,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:45,303 INFO L93 Difference]: Finished difference Result 653 states and 1502 transitions. [2019-12-07 18:04:45,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:04:45,303 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-12-07 18:04:45,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:45,304 INFO L225 Difference]: With dead ends: 653 [2019-12-07 18:04:45,304 INFO L226 Difference]: Without dead ends: 653 [2019-12-07 18:04:45,304 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:45,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 653 states. [2019-12-07 18:04:45,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 653 to 597. [2019-12-07 18:04:45,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-12-07 18:04:45,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1370 transitions. [2019-12-07 18:04:45,310 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1370 transitions. Word has length 40 [2019-12-07 18:04:45,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:45,310 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1370 transitions. [2019-12-07 18:04:45,310 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:04:45,310 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1370 transitions. [2019-12-07 18:04:45,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-12-07 18:04:45,311 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:45,311 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:45,311 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:45,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:45,311 INFO L82 PathProgramCache]: Analyzing trace with hash -922835002, now seen corresponding path program 1 times [2019-12-07 18:04:45,312 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:45,312 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696685560] [2019-12-07 18:04:45,312 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:45,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:45,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:45,360 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696685560] [2019-12-07 18:04:45,361 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:45,361 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:04:45,361 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027989557] [2019-12-07 18:04:45,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:04:45,361 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:45,361 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:04:45,361 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:45,361 INFO L87 Difference]: Start difference. First operand 597 states and 1370 transitions. Second operand 3 states. [2019-12-07 18:04:45,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:45,371 INFO L93 Difference]: Finished difference Result 597 states and 1346 transitions. [2019-12-07 18:04:45,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:04:45,372 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-12-07 18:04:45,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:45,372 INFO L225 Difference]: With dead ends: 597 [2019-12-07 18:04:45,372 INFO L226 Difference]: Without dead ends: 597 [2019-12-07 18:04:45,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:45,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 597 states. [2019-12-07 18:04:45,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 597 to 597. [2019-12-07 18:04:45,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-12-07 18:04:45,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1346 transitions. [2019-12-07 18:04:45,378 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1346 transitions. Word has length 55 [2019-12-07 18:04:45,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:45,378 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1346 transitions. [2019-12-07 18:04:45,378 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:04:45,378 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1346 transitions. [2019-12-07 18:04:45,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:04:45,379 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:45,379 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:45,379 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:45,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:45,379 INFO L82 PathProgramCache]: Analyzing trace with hash -1916501781, now seen corresponding path program 1 times [2019-12-07 18:04:45,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:45,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219169380] [2019-12-07 18:04:45,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:45,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:45,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:45,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219169380] [2019-12-07 18:04:45,432 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:45,432 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:04:45,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122735304] [2019-12-07 18:04:45,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:04:45,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:45,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:04:45,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:45,433 INFO L87 Difference]: Start difference. First operand 597 states and 1346 transitions. Second operand 5 states. [2019-12-07 18:04:45,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:45,561 INFO L93 Difference]: Finished difference Result 868 states and 1969 transitions. [2019-12-07 18:04:45,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:04:45,561 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-12-07 18:04:45,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:45,562 INFO L225 Difference]: With dead ends: 868 [2019-12-07 18:04:45,562 INFO L226 Difference]: Without dead ends: 868 [2019-12-07 18:04:45,562 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:04:45,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 868 states. [2019-12-07 18:04:45,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 868 to 766. [2019-12-07 18:04:45,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2019-12-07 18:04:45,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 1736 transitions. [2019-12-07 18:04:45,569 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 1736 transitions. Word has length 56 [2019-12-07 18:04:45,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:45,569 INFO L462 AbstractCegarLoop]: Abstraction has 766 states and 1736 transitions. [2019-12-07 18:04:45,569 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:04:45,569 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 1736 transitions. [2019-12-07 18:04:45,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:04:45,570 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:45,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:45,571 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:45,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:45,571 INFO L82 PathProgramCache]: Analyzing trace with hash 510672277, now seen corresponding path program 2 times [2019-12-07 18:04:45,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:45,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100247929] [2019-12-07 18:04:45,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:45,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:45,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:45,725 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100247929] [2019-12-07 18:04:45,725 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:45,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:04:45,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997017911] [2019-12-07 18:04:45,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:04:45,725 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:45,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:04:45,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:04:45,726 INFO L87 Difference]: Start difference. First operand 766 states and 1736 transitions. Second operand 7 states. [2019-12-07 18:04:45,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:45,847 INFO L93 Difference]: Finished difference Result 939 states and 2124 transitions. [2019-12-07 18:04:45,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:04:45,848 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 56 [2019-12-07 18:04:45,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:45,849 INFO L225 Difference]: With dead ends: 939 [2019-12-07 18:04:45,849 INFO L226 Difference]: Without dead ends: 939 [2019-12-07 18:04:45,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:04:45,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 939 states. [2019-12-07 18:04:45,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 939 to 780. [2019-12-07 18:04:45,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 780 states. [2019-12-07 18:04:45,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 1769 transitions. [2019-12-07 18:04:45,859 INFO L78 Accepts]: Start accepts. Automaton has 780 states and 1769 transitions. Word has length 56 [2019-12-07 18:04:45,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:45,859 INFO L462 AbstractCegarLoop]: Abstraction has 780 states and 1769 transitions. [2019-12-07 18:04:45,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:04:45,859 INFO L276 IsEmpty]: Start isEmpty. Operand 780 states and 1769 transitions. [2019-12-07 18:04:45,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:04:45,860 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:45,860 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:45,860 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:45,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:45,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1314270907, now seen corresponding path program 3 times [2019-12-07 18:04:45,861 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:45,861 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975161900] [2019-12-07 18:04:45,861 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:45,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:46,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:46,105 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975161900] [2019-12-07 18:04:46,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:46,106 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 18:04:46,106 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814157604] [2019-12-07 18:04:46,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:04:46,106 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:46,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:04:46,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:04:46,106 INFO L87 Difference]: Start difference. First operand 780 states and 1769 transitions. Second operand 11 states. [2019-12-07 18:04:46,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:46,514 INFO L93 Difference]: Finished difference Result 1151 states and 2566 transitions. [2019-12-07 18:04:46,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:04:46,515 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 56 [2019-12-07 18:04:46,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:46,516 INFO L225 Difference]: With dead ends: 1151 [2019-12-07 18:04:46,516 INFO L226 Difference]: Without dead ends: 1151 [2019-12-07 18:04:46,516 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:04:46,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1151 states. [2019-12-07 18:04:46,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1151 to 752. [2019-12-07 18:04:46,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 752 states. [2019-12-07 18:04:46,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752 states to 752 states and 1683 transitions. [2019-12-07 18:04:46,523 INFO L78 Accepts]: Start accepts. Automaton has 752 states and 1683 transitions. Word has length 56 [2019-12-07 18:04:46,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:46,523 INFO L462 AbstractCegarLoop]: Abstraction has 752 states and 1683 transitions. [2019-12-07 18:04:46,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:04:46,523 INFO L276 IsEmpty]: Start isEmpty. Operand 752 states and 1683 transitions. [2019-12-07 18:04:46,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-12-07 18:04:46,524 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:46,524 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:46,525 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:46,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:46,525 INFO L82 PathProgramCache]: Analyzing trace with hash 69556479, now seen corresponding path program 4 times [2019-12-07 18:04:46,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:46,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120665210] [2019-12-07 18:04:46,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:46,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:46,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:46,572 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120665210] [2019-12-07 18:04:46,573 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:46,573 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:04:46,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182493009] [2019-12-07 18:04:46,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:04:46,573 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:46,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:04:46,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:46,574 INFO L87 Difference]: Start difference. First operand 752 states and 1683 transitions. Second operand 3 states. [2019-12-07 18:04:46,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:46,603 INFO L93 Difference]: Finished difference Result 752 states and 1682 transitions. [2019-12-07 18:04:46,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:04:46,603 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-12-07 18:04:46,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:46,604 INFO L225 Difference]: With dead ends: 752 [2019-12-07 18:04:46,604 INFO L226 Difference]: Without dead ends: 752 [2019-12-07 18:04:46,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:04:46,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 752 states. [2019-12-07 18:04:46,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 752 to 607. [2019-12-07 18:04:46,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 607 states. [2019-12-07 18:04:46,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 1354 transitions. [2019-12-07 18:04:46,610 INFO L78 Accepts]: Start accepts. Automaton has 607 states and 1354 transitions. Word has length 56 [2019-12-07 18:04:46,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:46,610 INFO L462 AbstractCegarLoop]: Abstraction has 607 states and 1354 transitions. [2019-12-07 18:04:46,610 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:04:46,610 INFO L276 IsEmpty]: Start isEmpty. Operand 607 states and 1354 transitions. [2019-12-07 18:04:46,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 18:04:46,611 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:46,611 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:46,611 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:46,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:46,611 INFO L82 PathProgramCache]: Analyzing trace with hash 700007354, now seen corresponding path program 1 times [2019-12-07 18:04:46,611 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:46,611 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977636681] [2019-12-07 18:04:46,611 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:46,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:46,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:46,684 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977636681] [2019-12-07 18:04:46,684 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:46,684 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:04:46,684 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614658399] [2019-12-07 18:04:46,684 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:04:46,685 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:46,685 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:04:46,685 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:04:46,685 INFO L87 Difference]: Start difference. First operand 607 states and 1354 transitions. Second operand 5 states. [2019-12-07 18:04:46,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:46,721 INFO L93 Difference]: Finished difference Result 875 states and 1810 transitions. [2019-12-07 18:04:46,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:04:46,721 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2019-12-07 18:04:46,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:46,722 INFO L225 Difference]: With dead ends: 875 [2019-12-07 18:04:46,722 INFO L226 Difference]: Without dead ends: 541 [2019-12-07 18:04:46,722 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:04:46,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2019-12-07 18:04:46,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 541. [2019-12-07 18:04:46,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 541 states. [2019-12-07 18:04:46,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541 states to 541 states and 1163 transitions. [2019-12-07 18:04:46,727 INFO L78 Accepts]: Start accepts. Automaton has 541 states and 1163 transitions. Word has length 57 [2019-12-07 18:04:46,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:46,727 INFO L462 AbstractCegarLoop]: Abstraction has 541 states and 1163 transitions. [2019-12-07 18:04:46,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:04:46,727 INFO L276 IsEmpty]: Start isEmpty. Operand 541 states and 1163 transitions. [2019-12-07 18:04:46,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 18:04:46,728 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:46,728 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:46,728 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:46,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:46,728 INFO L82 PathProgramCache]: Analyzing trace with hash 574299964, now seen corresponding path program 2 times [2019-12-07 18:04:46,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:46,729 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984801347] [2019-12-07 18:04:46,729 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:46,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:46,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:46,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984801347] [2019-12-07 18:04:46,885 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:46,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:04:46,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710921293] [2019-12-07 18:04:46,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:04:46,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:46,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:04:46,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:04:46,885 INFO L87 Difference]: Start difference. First operand 541 states and 1163 transitions. Second operand 13 states. [2019-12-07 18:04:47,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:47,321 INFO L93 Difference]: Finished difference Result 1197 states and 2419 transitions. [2019-12-07 18:04:47,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:04:47,322 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-12-07 18:04:47,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:47,322 INFO L225 Difference]: With dead ends: 1197 [2019-12-07 18:04:47,322 INFO L226 Difference]: Without dead ends: 219 [2019-12-07 18:04:47,322 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=200, Invalid=502, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:04:47,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2019-12-07 18:04:47,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 195. [2019-12-07 18:04:47,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2019-12-07 18:04:47,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 324 transitions. [2019-12-07 18:04:47,324 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 324 transitions. Word has length 57 [2019-12-07 18:04:47,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:47,325 INFO L462 AbstractCegarLoop]: Abstraction has 195 states and 324 transitions. [2019-12-07 18:04:47,325 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:04:47,325 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 324 transitions. [2019-12-07 18:04:47,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 18:04:47,325 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:47,325 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:47,325 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:47,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:47,325 INFO L82 PathProgramCache]: Analyzing trace with hash -431408076, now seen corresponding path program 3 times [2019-12-07 18:04:47,326 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:47,326 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132615054] [2019-12-07 18:04:47,326 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:47,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:04:47,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:04:47,459 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132615054] [2019-12-07 18:04:47,459 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:04:47,459 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:04:47,459 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029821571] [2019-12-07 18:04:47,459 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:04:47,459 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:04:47,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:04:47,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:04:47,460 INFO L87 Difference]: Start difference. First operand 195 states and 324 transitions. Second operand 13 states. [2019-12-07 18:04:47,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:04:47,619 INFO L93 Difference]: Finished difference Result 346 states and 571 transitions. [2019-12-07 18:04:47,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:04:47,620 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-12-07 18:04:47,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:04:47,620 INFO L225 Difference]: With dead ends: 346 [2019-12-07 18:04:47,620 INFO L226 Difference]: Without dead ends: 313 [2019-12-07 18:04:47,620 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=70, Invalid=272, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:04:47,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2019-12-07 18:04:47,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 303. [2019-12-07 18:04:47,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-12-07 18:04:47,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 509 transitions. [2019-12-07 18:04:47,623 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 509 transitions. Word has length 57 [2019-12-07 18:04:47,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:04:47,623 INFO L462 AbstractCegarLoop]: Abstraction has 303 states and 509 transitions. [2019-12-07 18:04:47,623 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:04:47,623 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 509 transitions. [2019-12-07 18:04:47,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 18:04:47,623 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:04:47,623 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:04:47,624 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:04:47,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:04:47,624 INFO L82 PathProgramCache]: Analyzing trace with hash -97225810, now seen corresponding path program 4 times [2019-12-07 18:04:47,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:04:47,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395196291] [2019-12-07 18:04:47,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:04:47,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:04:47,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:04:47,702 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:04:47,702 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:04:47,705 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= (select .cse0 |v_ULTIMATE.start_main_~#t2528~0.base_22|) 0) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t2528~0.base_22| 1) |v_#valid_53|) (= 0 v_~y$w_buff0~0_215) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2528~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2528~0.base_22|) |v_ULTIMATE.start_main_~#t2528~0.offset_17| 0)) |v_#memory_int_19|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2528~0.base_22| 4)) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2528~0.base_22|) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard0~0_26 0) (= |v_ULTIMATE.start_main_~#t2528~0.offset_17| 0) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_~#t2530~0.base=|v_ULTIMATE.start_main_~#t2530~0.base_18|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t2529~0.offset=|v_ULTIMATE.start_main_~#t2529~0.offset_15|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ULTIMATE.start_main_~#t2529~0.base=|v_ULTIMATE.start_main_~#t2529~0.base_19|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_~#t2528~0.base=|v_ULTIMATE.start_main_~#t2528~0.base_22|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ULTIMATE.start_main_~#t2530~0.offset=|v_ULTIMATE.start_main_~#t2530~0.offset_15|, ULTIMATE.start_main_~#t2528~0.offset=|v_ULTIMATE.start_main_~#t2528~0.offset_17|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t2530~0.base, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t2529~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t2529~0.base, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2528~0.base, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t2530~0.offset, ULTIMATE.start_main_~#t2528~0.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:04:47,705 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= |v_ULTIMATE.start_main_~#t2529~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2529~0.base_11|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2529~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t2529~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2529~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2529~0.base_11|) |v_ULTIMATE.start_main_~#t2529~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2529~0.base_11| 4)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2529~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2529~0.base=|v_ULTIMATE.start_main_~#t2529~0.base_11|, ULTIMATE.start_main_~#t2529~0.offset=|v_ULTIMATE.start_main_~#t2529~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2529~0.base, ULTIMATE.start_main_~#t2529~0.offset] because there is no mapped edge [2019-12-07 18:04:47,706 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2530~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2530~0.base_10|) |v_ULTIMATE.start_main_~#t2530~0.offset_10| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2530~0.base_10|) (not (= |v_ULTIMATE.start_main_~#t2530~0.base_10| 0)) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2530~0.base_10|)) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2530~0.base_10| 1)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2530~0.base_10| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t2530~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2530~0.base=|v_ULTIMATE.start_main_~#t2530~0.base_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2530~0.offset=|v_ULTIMATE.start_main_~#t2530~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2530~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2530~0.offset] because there is no mapped edge [2019-12-07 18:04:47,706 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:04:47,706 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:04:47,707 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In1995149116 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1995149116 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out1995149116|) (not .cse1)) (and (= ~y$w_buff0_used~0_In1995149116 |P2Thread1of1ForFork0_#t~ite11_Out1995149116|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1995149116} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1995149116|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1995149116} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:04:47,707 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1792641108 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-1792641108 256))) (.cse0 (= |P1Thread1of1ForFork2_#t~ite4_Out-1792641108| |P1Thread1of1ForFork2_#t~ite3_Out-1792641108|))) (or (and (= ~y~0_In-1792641108 |P1Thread1of1ForFork2_#t~ite3_Out-1792641108|) .cse0 (or .cse1 .cse2)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out-1792641108| ~y$w_buff1~0_In-1792641108) (not .cse2) (not .cse1) .cse0))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1792641108, ~y$w_buff1~0=~y$w_buff1~0_In-1792641108, ~y~0=~y~0_In-1792641108, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1792641108, ~y$w_buff1~0=~y$w_buff1~0_In-1792641108, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1792641108|, ~y~0=~y~0_In-1792641108, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1792641108|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:04:47,708 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1095433696 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1095433696 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1095433696 |P1Thread1of1ForFork2_#t~ite5_Out1095433696|)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out1095433696| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1095433696, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1095433696} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1095433696, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1095433696, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out1095433696|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:04:47,708 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-290604012 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-290604012 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-290604012 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-290604012 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-290604012| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out-290604012| ~y$w_buff1_used~0_In-290604012) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-290604012, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-290604012, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-290604012, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-290604012} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-290604012, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-290604012, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-290604012|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-290604012, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-290604012} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:04:47,708 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In2121108650 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In2121108650 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In2121108650 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In2121108650 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out2121108650|)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In2121108650 |P1Thread1of1ForFork2_#t~ite6_Out2121108650|) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2121108650, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2121108650, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2121108650, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2121108650} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2121108650, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2121108650, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2121108650, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out2121108650|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2121108650} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In283203836 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In283203836 256) 0))) (or (and (= ~y$r_buff0_thd2~0_In283203836 |P1Thread1of1ForFork2_#t~ite7_Out283203836|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out283203836|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In283203836, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In283203836} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In283203836, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In283203836, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out283203836|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In-1987365611 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-1987365611 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1987365611 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1987365611 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-1987365611|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-1987365611 |P1Thread1of1ForFork2_#t~ite8_Out-1987365611|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1987365611, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1987365611, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-1987365611|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In-1237046549 ~y$r_buff0_thd3~0_Out-1237046549)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1237046549 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-1237046549 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= ~y$r_buff0_thd3~0_Out-1237046549 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1237046549} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1237046549, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1237046549|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-2124989506 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-2124989506 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In-2124989506 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-2124989506 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out-2124989506| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd3~0_In-2124989506 |P2Thread1of1ForFork0_#t~ite14_Out-2124989506|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2124989506, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2124989506, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2124989506, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2124989506} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-2124989506|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2124989506, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2124989506, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2124989506, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2124989506} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:04:47,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:04:47,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:04:47,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In440452248 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In440452248 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite19_Out440452248| |ULTIMATE.start_main_#t~ite18_Out440452248|))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite18_Out440452248| ~y~0_In440452248) .cse2) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite18_Out440452248| ~y$w_buff1~0_In440452248) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In440452248, ~y~0=~y~0_In440452248, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In440452248, ~y$w_buff1_used~0=~y$w_buff1_used~0_In440452248} OutVars{~y$w_buff1~0=~y$w_buff1~0_In440452248, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out440452248|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out440452248|, ~y~0=~y~0_In440452248, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In440452248, ~y$w_buff1_used~0=~y$w_buff1_used~0_In440452248} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:04:47,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In659112573 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In659112573 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out659112573| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out659112573| ~y$w_buff0_used~0_In659112573)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In659112573} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In659112573, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out659112573|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:04:47,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In682276810 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In682276810 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In682276810 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In682276810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out682276810|)) (and (or .cse3 .cse2) (or .cse1 .cse0) (= ~y$w_buff1_used~0_In682276810 |ULTIMATE.start_main_#t~ite21_Out682276810|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In682276810, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In682276810, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In682276810, ~y$w_buff1_used~0=~y$w_buff1_used~0_In682276810} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In682276810, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In682276810, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out682276810|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In682276810, ~y$w_buff1_used~0=~y$w_buff1_used~0_In682276810} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:04:47,711 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1350341585 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1350341585 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-1350341585| 0)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd0~0_In-1350341585 |ULTIMATE.start_main_#t~ite22_Out-1350341585|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1350341585|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:04:47,711 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In899278187 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In899278187 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In899278187 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In899278187 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite23_Out899278187|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite23_Out899278187| ~y$r_buff1_thd0~0_In899278187) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In899278187, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In899278187, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In899278187, ~y$w_buff1_used~0=~y$w_buff1_used~0_In899278187} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In899278187, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In899278187, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In899278187, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out899278187|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In899278187} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:04:47,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1030726194 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out1030726194| ~y$w_buff1_used~0_In1030726194) (= |ULTIMATE.start_main_#t~ite38_In1030726194| |ULTIMATE.start_main_#t~ite38_Out1030726194|)) (and (= |ULTIMATE.start_main_#t~ite38_Out1030726194| ~y$w_buff1_used~0_In1030726194) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1030726194 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In1030726194 256) 0)) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1030726194 256))) (= (mod ~y$w_buff0_used~0_In1030726194 256) 0))) .cse0 (= |ULTIMATE.start_main_#t~ite38_Out1030726194| |ULTIMATE.start_main_#t~ite39_Out1030726194|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1030726194, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1030726194, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1030726194|, ~weak$$choice2~0=~weak$$choice2~0_In1030726194, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1030726194, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1030726194} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1030726194, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1030726194|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1030726194, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1030726194|, ~weak$$choice2~0=~weak$$choice2~0_In1030726194, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1030726194, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1030726194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 18:04:47,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:04:47,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:04:47,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:04:47,763 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:04:47 BasicIcfg [2019-12-07 18:04:47,763 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:04:47,763 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:04:47,763 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:04:47,764 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:04:47,764 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:04:36" (3/4) ... [2019-12-07 18:04:47,765 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:04:47,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= (select .cse0 |v_ULTIMATE.start_main_~#t2528~0.base_22|) 0) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t2528~0.base_22| 1) |v_#valid_53|) (= 0 v_~y$w_buff0~0_215) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2528~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2528~0.base_22|) |v_ULTIMATE.start_main_~#t2528~0.offset_17| 0)) |v_#memory_int_19|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t2528~0.base_22| 4)) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2528~0.base_22|) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard0~0_26 0) (= |v_ULTIMATE.start_main_~#t2528~0.offset_17| 0) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_~#t2530~0.base=|v_ULTIMATE.start_main_~#t2530~0.base_18|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t2529~0.offset=|v_ULTIMATE.start_main_~#t2529~0.offset_15|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ULTIMATE.start_main_~#t2529~0.base=|v_ULTIMATE.start_main_~#t2529~0.base_19|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_~#t2528~0.base=|v_ULTIMATE.start_main_~#t2528~0.base_22|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ULTIMATE.start_main_~#t2530~0.offset=|v_ULTIMATE.start_main_~#t2530~0.offset_15|, ULTIMATE.start_main_~#t2528~0.offset=|v_ULTIMATE.start_main_~#t2528~0.offset_17|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t2530~0.base, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t2529~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_~#t2529~0.base, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t2528~0.base, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t2530~0.offset, ULTIMATE.start_main_~#t2528~0.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:04:47,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= |v_ULTIMATE.start_main_~#t2529~0.offset_10| 0) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2529~0.base_11|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2529~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t2529~0.base_11| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2529~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2529~0.base_11|) |v_ULTIMATE.start_main_~#t2529~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2529~0.base_11| 4)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2529~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2529~0.base=|v_ULTIMATE.start_main_~#t2529~0.base_11|, ULTIMATE.start_main_~#t2529~0.offset=|v_ULTIMATE.start_main_~#t2529~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2529~0.base, ULTIMATE.start_main_~#t2529~0.offset] because there is no mapped edge [2019-12-07 18:04:47,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2530~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2530~0.base_10|) |v_ULTIMATE.start_main_~#t2530~0.offset_10| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2530~0.base_10|) (not (= |v_ULTIMATE.start_main_~#t2530~0.base_10| 0)) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2530~0.base_10|)) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2530~0.base_10| 1)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t2530~0.base_10| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t2530~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2530~0.base=|v_ULTIMATE.start_main_~#t2530~0.base_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2530~0.offset=|v_ULTIMATE.start_main_~#t2530~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2530~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2530~0.offset] because there is no mapped edge [2019-12-07 18:04:47,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 18:04:47,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-12-07 18:04:47,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In1995149116 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1995149116 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite11_Out1995149116|) (not .cse1)) (and (= ~y$w_buff0_used~0_In1995149116 |P2Thread1of1ForFork0_#t~ite11_Out1995149116|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1995149116} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1995149116, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out1995149116|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1995149116} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 18:04:47,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1792641108 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In-1792641108 256))) (.cse0 (= |P1Thread1of1ForFork2_#t~ite4_Out-1792641108| |P1Thread1of1ForFork2_#t~ite3_Out-1792641108|))) (or (and (= ~y~0_In-1792641108 |P1Thread1of1ForFork2_#t~ite3_Out-1792641108|) .cse0 (or .cse1 .cse2)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out-1792641108| ~y$w_buff1~0_In-1792641108) (not .cse2) (not .cse1) .cse0))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1792641108, ~y$w_buff1~0=~y$w_buff1~0_In-1792641108, ~y~0=~y~0_In-1792641108, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1792641108, ~y$w_buff1~0=~y$w_buff1~0_In-1792641108, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1792641108|, ~y~0=~y~0_In-1792641108, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1792641108|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1792641108} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-12-07 18:04:47,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1095433696 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1095433696 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1095433696 |P1Thread1of1ForFork2_#t~ite5_Out1095433696|)) (and (= |P1Thread1of1ForFork2_#t~ite5_Out1095433696| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1095433696, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1095433696} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1095433696, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1095433696, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out1095433696|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-12-07 18:04:47,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In-290604012 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-290604012 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-290604012 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In-290604012 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-290604012| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out-290604012| ~y$w_buff1_used~0_In-290604012) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-290604012, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-290604012, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-290604012, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-290604012} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-290604012, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-290604012, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-290604012|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-290604012, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-290604012} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 18:04:47,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In2121108650 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In2121108650 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In2121108650 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In2121108650 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite6_Out2121108650|)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In2121108650 |P1Thread1of1ForFork2_#t~ite6_Out2121108650|) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2121108650, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2121108650, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2121108650, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2121108650} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2121108650, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2121108650, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2121108650, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out2121108650|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2121108650} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-12-07 18:04:47,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In283203836 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In283203836 256) 0))) (or (and (= ~y$r_buff0_thd2~0_In283203836 |P1Thread1of1ForFork2_#t~ite7_Out283203836|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out283203836|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In283203836, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In283203836} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In283203836, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In283203836, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out283203836|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-12-07 18:04:47,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In-1987365611 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd2~0_In-1987365611 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-1987365611 256))) (.cse3 (= (mod ~y$w_buff0_used~0_In-1987365611 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-1987365611|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In-1987365611 |P1Thread1of1ForFork2_#t~ite8_Out-1987365611|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1987365611, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1987365611, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1987365611, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-1987365611|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1987365611, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1987365611} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-12-07 18:04:47,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:04:47,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_In-1237046549 ~y$r_buff0_thd3~0_Out-1237046549)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1237046549 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In-1237046549 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (not .cse2) (= ~y$r_buff0_thd3~0_Out-1237046549 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1237046549} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1237046549, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1237046549, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1237046549|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 18:04:47,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-2124989506 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-2124989506 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In-2124989506 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In-2124989506 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite14_Out-2124989506| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd3~0_In-2124989506 |P2Thread1of1ForFork0_#t~ite14_Out-2124989506|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2124989506, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2124989506, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2124989506, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2124989506} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-2124989506|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2124989506, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2124989506, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2124989506, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2124989506} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 18:04:47,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:04:47,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:04:47,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In440452248 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In440452248 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite19_Out440452248| |ULTIMATE.start_main_#t~ite18_Out440452248|))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite18_Out440452248| ~y~0_In440452248) .cse2) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite18_Out440452248| ~y$w_buff1~0_In440452248) (not .cse0) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In440452248, ~y~0=~y~0_In440452248, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In440452248, ~y$w_buff1_used~0=~y$w_buff1_used~0_In440452248} OutVars{~y$w_buff1~0=~y$w_buff1~0_In440452248, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out440452248|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out440452248|, ~y~0=~y~0_In440452248, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In440452248, ~y$w_buff1_used~0=~y$w_buff1_used~0_In440452248} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-12-07 18:04:47,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In659112573 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In659112573 256)))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out659112573| 0) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out659112573| ~y$w_buff0_used~0_In659112573)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In659112573} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In659112573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In659112573, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out659112573|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-12-07 18:04:47,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In682276810 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In682276810 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In682276810 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In682276810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out682276810|)) (and (or .cse3 .cse2) (or .cse1 .cse0) (= ~y$w_buff1_used~0_In682276810 |ULTIMATE.start_main_#t~ite21_Out682276810|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In682276810, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In682276810, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In682276810, ~y$w_buff1_used~0=~y$w_buff1_used~0_In682276810} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In682276810, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In682276810, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out682276810|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In682276810, ~y$w_buff1_used~0=~y$w_buff1_used~0_In682276810} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-12-07 18:04:47,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1350341585 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1350341585 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-1350341585| 0)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd0~0_In-1350341585 |ULTIMATE.start_main_#t~ite22_Out-1350341585|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1350341585, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1350341585, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1350341585|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-12-07 18:04:47,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In899278187 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In899278187 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In899278187 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In899278187 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite23_Out899278187|)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite23_Out899278187| ~y$r_buff1_thd0~0_In899278187) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In899278187, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In899278187, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In899278187, ~y$w_buff1_used~0=~y$w_buff1_used~0_In899278187} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In899278187, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In899278187, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In899278187, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out899278187|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In899278187} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-12-07 18:04:47,773 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1030726194 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite39_Out1030726194| ~y$w_buff1_used~0_In1030726194) (= |ULTIMATE.start_main_#t~ite38_In1030726194| |ULTIMATE.start_main_#t~ite38_Out1030726194|)) (and (= |ULTIMATE.start_main_#t~ite38_Out1030726194| ~y$w_buff1_used~0_In1030726194) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1030726194 256) 0))) (or (and .cse1 (= (mod ~y$w_buff1_used~0_In1030726194 256) 0)) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1030726194 256))) (= (mod ~y$w_buff0_used~0_In1030726194 256) 0))) .cse0 (= |ULTIMATE.start_main_#t~ite38_Out1030726194| |ULTIMATE.start_main_#t~ite39_Out1030726194|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1030726194, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1030726194, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1030726194|, ~weak$$choice2~0=~weak$$choice2~0_In1030726194, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1030726194, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1030726194} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1030726194, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1030726194|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1030726194, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1030726194|, ~weak$$choice2~0=~weak$$choice2~0_In1030726194, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1030726194, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1030726194} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 18:04:47,773 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 18:04:47,774 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:04:47,774 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:04:47,830 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_cac709bb-7881-48bb-8f8d-43e68c380020/bin/uautomizer/witness.graphml [2019-12-07 18:04:47,830 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:04:47,832 INFO L168 Benchmark]: Toolchain (without parser) took 11695.07 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 733.5 MB). Free memory was 938.1 MB in the beginning and 1.0 GB in the end (delta: -108.2 MB). Peak memory consumption was 625.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,832 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:04:47,832 INFO L168 Benchmark]: CACSL2BoogieTranslator took 382.01 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 104.3 MB). Free memory was 938.1 MB in the beginning and 1.1 GB in the end (delta: -133.9 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,833 INFO L168 Benchmark]: Boogie Procedure Inliner took 45.15 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,833 INFO L168 Benchmark]: Boogie Preprocessor took 25.72 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:04:47,833 INFO L168 Benchmark]: RCFGBuilder took 408.45 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,833 INFO L168 Benchmark]: TraceAbstraction took 10763.43 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 629.1 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -57.3 MB). Peak memory consumption was 571.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,834 INFO L168 Benchmark]: Witness Printer took 67.13 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 20.3 MB). Peak memory consumption was 20.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:04:47,835 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 382.01 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 104.3 MB). Free memory was 938.1 MB in the beginning and 1.1 GB in the end (delta: -133.9 MB). Peak memory consumption was 18.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 45.15 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.72 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 408.45 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 10763.43 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 629.1 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -57.3 MB). Peak memory consumption was 571.8 MB. Max. memory is 11.5 GB. * Witness Printer took 67.13 ms. Allocated memory is still 1.8 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 20.3 MB). Peak memory consumption was 20.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.8s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 94 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 24 ChoiceCompositions, 4225 VarBasedMoverChecksPositive, 199 VarBasedMoverChecksNegative, 61 SemBasedMoverChecksPositive, 194 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 48124 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L802] FCALL, FORK 0 pthread_create(&t2528, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t2529, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L806] FCALL, FORK 0 pthread_create(&t2530, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L770] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L771] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L772] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L773] 3 y$r_buff0_thd3 = (_Bool)1 [L776] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L779] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L744] 2 x = 1 [L747] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L779] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L750] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L780] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L750] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L751] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L752] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L753] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L781] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L812] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L812] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L813] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L814] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L815] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L816] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L819] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L820] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L821] 0 y$flush_delayed = weak$$choice2 [L822] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L824] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L824] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L825] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L826] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L826] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L827] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L829] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L829] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L830] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 10.6s, OverallIterations: 18, TraceHistogramMax: 1, AutomataDifference: 3.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1995 SDtfs, 1962 SDslu, 5107 SDs, 0 SdLazy, 2729 SolverSat, 140 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 144 GetRequests, 16 SyntacticMatches, 19 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 241 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=24582occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.9s AutomataMinimizationTime, 17 MinimizatonAttempts, 7219 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 725 NumberOfCodeBlocks, 725 NumberOfCodeBlocksAsserted, 18 NumberOfCheckSat, 651 ConstructedInterpolants, 0 QuantifiedInterpolants, 145875 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 17 InterpolantComputations, 17 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...