./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:00:49,099 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:00:49,101 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:00:49,108 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:00:49,108 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:00:49,109 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:00:49,110 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:00:49,112 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:00:49,113 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:00:49,114 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:00:49,115 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:00:49,116 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:00:49,116 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:00:49,117 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:00:49,118 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:00:49,119 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:00:49,120 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:00:49,121 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:00:49,123 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:00:49,125 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:00:49,126 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:00:49,127 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:00:49,128 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:00:49,129 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:00:49,131 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:00:49,131 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:00:49,131 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:00:49,132 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:00:49,132 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:00:49,133 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:00:49,133 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:00:49,134 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:00:49,134 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:00:49,134 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:00:49,135 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:00:49,136 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:00:49,136 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:00:49,136 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:00:49,136 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:00:49,137 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:00:49,138 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:00:49,138 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 12:00:49,149 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:00:49,149 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:00:49,150 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 12:00:49,150 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 12:00:49,150 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 12:00:49,151 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 12:00:49,151 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 12:00:49,152 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 12:00:49,152 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:00:49,153 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:00:49,153 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-12-07 12:00:49,267 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:00:49,274 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:00:49,277 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:00:49,277 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:00:49,278 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:00:49,278 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-12-07 12:00:49,315 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/data/adb7fa329/7822e01e30cd4157ac547e40105c3363/FLAG898f3e75b [2019-12-07 12:00:49,827 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:00:49,827 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-12-07 12:00:49,833 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/data/adb7fa329/7822e01e30cd4157ac547e40105c3363/FLAG898f3e75b [2019-12-07 12:00:50,314 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/data/adb7fa329/7822e01e30cd4157ac547e40105c3363 [2019-12-07 12:00:50,316 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:00:50,317 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:00:50,318 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:00:50,318 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:00:50,320 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:00:50,320 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,322 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@174ba895 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50, skipping insertion in model container [2019-12-07 12:00:50,322 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,327 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:00:50,348 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:00:50,507 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:00:50,511 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:00:50,538 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:00:50,551 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:00:50,551 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50 WrapperNode [2019-12-07 12:00:50,552 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:00:50,552 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:00:50,552 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:00:50,552 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:00:50,557 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,563 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,589 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:00:50,589 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:00:50,589 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:00:50,589 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:00:50,595 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,595 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,598 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,598 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,606 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,615 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,617 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... [2019-12-07 12:00:50,621 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:00:50,621 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:00:50,621 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:00:50,621 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:00:50,621 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 12:00:50,660 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:00:50,660 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:00:51,118 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:00:51,118 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-12-07 12:00:51,119 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:00:51 BoogieIcfgContainer [2019-12-07 12:00:51,119 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:00:51,120 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 12:00:51,120 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 12:00:51,122 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 12:00:51,122 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 12:00:50" (1/3) ... [2019-12-07 12:00:51,123 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4eea028d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:00:51, skipping insertion in model container [2019-12-07 12:00:51,123 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:00:50" (2/3) ... [2019-12-07 12:00:51,123 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4eea028d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 12:00:51, skipping insertion in model container [2019-12-07 12:00:51,123 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:00:51" (3/3) ... [2019-12-07 12:00:51,124 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-12-07 12:00:51,131 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 12:00:51,136 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 12:00:51,143 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-12-07 12:00:51,164 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 12:00:51,164 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 12:00:51,164 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 12:00:51,164 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:00:51,164 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:00:51,164 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 12:00:51,164 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:00:51,164 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 12:00:51,180 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-12-07 12:00:51,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,186 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,190 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-12-07 12:00:51,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225292546] [2019-12-07 12:00:51,196 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,300 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225292546] [2019-12-07 12:00:51,301 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,301 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:51,302 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147210093] [2019-12-07 12:00:51,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,306 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,316 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-12-07 12:00:51,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,371 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-12-07 12:00:51,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,373 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,385 INFO L225 Difference]: With dead ends: 547 [2019-12-07 12:00:51,385 INFO L226 Difference]: Without dead ends: 272 [2019-12-07 12:00:51,388 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-12-07 12:00:51,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-12-07 12:00:51,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-12-07 12:00:51,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-12-07 12:00:51,427 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-12-07 12:00:51,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,428 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-12-07 12:00:51,428 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,428 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-12-07 12:00:51,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,430 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,430 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,431 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,431 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-12-07 12:00:51,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108350047] [2019-12-07 12:00:51,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,464 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108350047] [2019-12-07 12:00:51,465 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,465 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,465 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72915555] [2019-12-07 12:00:51,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,466 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,467 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-12-07 12:00:51,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,522 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-12-07 12:00:51,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,522 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,525 INFO L225 Difference]: With dead ends: 730 [2019-12-07 12:00:51,525 INFO L226 Difference]: Without dead ends: 466 [2019-12-07 12:00:51,526 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-12-07 12:00:51,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-12-07 12:00:51,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-12-07 12:00:51,548 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-12-07 12:00:51,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,548 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-12-07 12:00:51,548 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,548 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-12-07 12:00:51,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,549 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,549 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,550 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,550 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-12-07 12:00:51,550 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,550 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080865851] [2019-12-07 12:00:51,550 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,578 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080865851] [2019-12-07 12:00:51,578 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,578 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,578 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664584315] [2019-12-07 12:00:51,578 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,579 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,579 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-12-07 12:00:51,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,603 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-12-07 12:00:51,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,603 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,605 INFO L225 Difference]: With dead ends: 919 [2019-12-07 12:00:51,606 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:51,606 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:51,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:51,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-12-07 12:00:51,620 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-12-07 12:00:51,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,620 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-12-07 12:00:51,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,620 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-12-07 12:00:51,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,621 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,621 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,622 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,622 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-12-07 12:00:51,622 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,622 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983675139] [2019-12-07 12:00:51,622 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983675139] [2019-12-07 12:00:51,645 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,645 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,645 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565788413] [2019-12-07 12:00:51,645 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,646 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,646 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-12-07 12:00:51,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,667 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-12-07 12:00:51,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,667 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,669 INFO L225 Difference]: With dead ends: 918 [2019-12-07 12:00:51,669 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:51,670 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:51,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:51,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-12-07 12:00:51,685 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-12-07 12:00:51,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,686 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-12-07 12:00:51,686 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,686 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-12-07 12:00:51,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,687 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,687 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,687 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-12-07 12:00:51,687 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,687 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500158772] [2019-12-07 12:00:51,688 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500158772] [2019-12-07 12:00:51,712 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,712 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,712 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429482406] [2019-12-07 12:00:51,712 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,713 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-12-07 12:00:51,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,738 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-12-07 12:00:51,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,741 INFO L225 Difference]: With dead ends: 917 [2019-12-07 12:00:51,741 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:51,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:51,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:51,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-12-07 12:00:51,757 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-12-07 12:00:51,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,758 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-12-07 12:00:51,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,758 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-12-07 12:00:51,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,758 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,759 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,759 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,759 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-12-07 12:00:51,759 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,759 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086647917] [2019-12-07 12:00:51,759 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,781 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086647917] [2019-12-07 12:00:51,782 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,782 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,782 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347971510] [2019-12-07 12:00:51,782 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,782 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,783 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,783 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-12-07 12:00:51,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,832 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-12-07 12:00:51,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,833 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,836 INFO L225 Difference]: With dead ends: 916 [2019-12-07 12:00:51,836 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:51,837 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:51,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:51,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-12-07 12:00:51,859 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-12-07 12:00:51,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,859 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-12-07 12:00:51,859 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,859 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-12-07 12:00:51,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,860 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,860 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,860 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-12-07 12:00:51,861 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,861 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867991397] [2019-12-07 12:00:51,861 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:51,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:51,888 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867991397] [2019-12-07 12:00:51,888 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:51,888 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:51,888 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250872155] [2019-12-07 12:00:51,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:51,889 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:51,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:51,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,889 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-12-07 12:00:51,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:51,937 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-12-07 12:00:51,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:51,937 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:51,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:51,940 INFO L225 Difference]: With dead ends: 914 [2019-12-07 12:00:51,940 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:51,942 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:51,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:51,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:51,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:51,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-12-07 12:00:51,971 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-12-07 12:00:51,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:51,971 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-12-07 12:00:51,971 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:51,971 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-12-07 12:00:51,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:51,972 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:51,972 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:51,972 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:51,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:51,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-12-07 12:00:51,973 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:51,973 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098187316] [2019-12-07 12:00:51,973 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:51,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098187316] [2019-12-07 12:00:52,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:52,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969178579] [2019-12-07 12:00:52,011 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,011 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-12-07 12:00:52,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,046 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-12-07 12:00:52,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,047 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:52,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,050 INFO L225 Difference]: With dead ends: 915 [2019-12-07 12:00:52,050 INFO L226 Difference]: Without dead ends: 464 [2019-12-07 12:00:52,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-12-07 12:00:52,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-12-07 12:00:52,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-12-07 12:00:52,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-12-07 12:00:52,070 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-12-07 12:00:52,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:52,070 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-12-07 12:00:52,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:52,070 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-12-07 12:00:52,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 12:00:52,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:52,071 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:52,071 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:52,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:52,071 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-12-07 12:00:52,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:52,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783568053] [2019-12-07 12:00:52,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:52,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783568053] [2019-12-07 12:00:52,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:52,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634647945] [2019-12-07 12:00:52,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,098 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,099 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-12-07 12:00:52,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,154 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-12-07 12:00:52,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,154 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-12-07 12:00:52,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,159 INFO L225 Difference]: With dead ends: 1299 [2019-12-07 12:00:52,159 INFO L226 Difference]: Without dead ends: 884 [2019-12-07 12:00:52,160 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-12-07 12:00:52,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-12-07 12:00:52,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-12-07 12:00:52,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-12-07 12:00:52,189 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-12-07 12:00:52,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:52,189 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-12-07 12:00:52,189 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:52,189 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-12-07 12:00:52,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-12-07 12:00:52,190 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:52,190 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:52,190 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:52,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:52,190 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-12-07 12:00:52,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:52,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799550712] [2019-12-07 12:00:52,191 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:52,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,212 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799550712] [2019-12-07 12:00:52,212 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,212 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:52,212 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571013935] [2019-12-07 12:00:52,212 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,213 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,213 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-12-07 12:00:52,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,288 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-12-07 12:00:52,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,288 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-12-07 12:00:52,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,296 INFO L225 Difference]: With dead ends: 2234 [2019-12-07 12:00:52,296 INFO L226 Difference]: Without dead ends: 1494 [2019-12-07 12:00:52,298 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-12-07 12:00:52,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-12-07 12:00:52,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-12-07 12:00:52,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-12-07 12:00:52,356 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-12-07 12:00:52,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:52,356 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-12-07 12:00:52,356 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:52,356 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-12-07 12:00:52,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-12-07 12:00:52,357 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:52,357 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:52,357 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:52,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:52,358 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-12-07 12:00:52,358 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:52,358 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249839771] [2019-12-07 12:00:52,358 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:52,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,380 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249839771] [2019-12-07 12:00:52,380 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,380 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:52,380 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558586694] [2019-12-07 12:00:52,380 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,380 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,380 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,381 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-12-07 12:00:52,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,462 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-12-07 12:00:52,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,463 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-12-07 12:00:52,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,472 INFO L225 Difference]: With dead ends: 3972 [2019-12-07 12:00:52,472 INFO L226 Difference]: Without dead ends: 2642 [2019-12-07 12:00:52,474 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-12-07 12:00:52,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-12-07 12:00:52,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-12-07 12:00:52,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-12-07 12:00:52,542 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-12-07 12:00:52,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:52,542 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-12-07 12:00:52,542 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:52,542 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-12-07 12:00:52,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-12-07 12:00:52,543 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:52,543 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:52,543 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:52,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:52,543 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-12-07 12:00:52,543 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:52,543 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769140124] [2019-12-07 12:00:52,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:52,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769140124] [2019-12-07 12:00:52,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:52,555 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668343070] [2019-12-07 12:00:52,556 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,556 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,556 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-12-07 12:00:52,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,633 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-12-07 12:00:52,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,634 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-12-07 12:00:52,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,646 INFO L225 Difference]: With dead ends: 4968 [2019-12-07 12:00:52,646 INFO L226 Difference]: Without dead ends: 2474 [2019-12-07 12:00:52,650 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-12-07 12:00:52,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-12-07 12:00:52,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-12-07 12:00:52,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-12-07 12:00:52,723 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-12-07 12:00:52,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:52,724 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-12-07 12:00:52,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:52,724 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-12-07 12:00:52,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 12:00:52,724 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:52,724 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:52,724 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:52,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:52,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-12-07 12:00:52,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:52,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831525533] [2019-12-07 12:00:52,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:52,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:52,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:52,749 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831525533] [2019-12-07 12:00:52,749 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:52,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:52,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280533313] [2019-12-07 12:00:52,750 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:52,750 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:52,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:52,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,750 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-12-07 12:00:52,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:52,899 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-12-07 12:00:52,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:52,899 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-12-07 12:00:52,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:52,917 INFO L225 Difference]: With dead ends: 7190 [2019-12-07 12:00:52,917 INFO L226 Difference]: Without dead ends: 4786 [2019-12-07 12:00:52,920 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:52,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-12-07 12:00:53,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-12-07 12:00:53,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-12-07 12:00:53,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-12-07 12:00:53,050 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-12-07 12:00:53,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:53,050 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-12-07 12:00:53,050 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:53,050 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-12-07 12:00:53,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-12-07 12:00:53,052 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:53,052 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:53,052 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:53,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:53,052 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-12-07 12:00:53,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:53,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289506951] [2019-12-07 12:00:53,053 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:53,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:53,080 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:53,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289506951] [2019-12-07 12:00:53,081 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:53,081 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:53,081 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262520560] [2019-12-07 12:00:53,082 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:53,082 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:53,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:53,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:53,082 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-12-07 12:00:53,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:53,345 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-12-07 12:00:53,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:53,345 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-12-07 12:00:53,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:53,379 INFO L225 Difference]: With dead ends: 14046 [2019-12-07 12:00:53,379 INFO L226 Difference]: Without dead ends: 9384 [2019-12-07 12:00:53,385 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:53,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-12-07 12:00:53,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-12-07 12:00:53,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-12-07 12:00:53,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-12-07 12:00:53,611 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-12-07 12:00:53,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:53,612 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-12-07 12:00:53,612 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:53,612 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-12-07 12:00:53,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 12:00:53,616 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:53,616 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:53,616 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:53,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:53,617 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-12-07 12:00:53,617 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:53,617 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709924786] [2019-12-07 12:00:53,617 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:53,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:53,669 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-12-07 12:00:53,669 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709924786] [2019-12-07 12:00:53,670 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:53,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:53,670 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662235745] [2019-12-07 12:00:53,670 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:53,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:53,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:53,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:53,670 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-12-07 12:00:53,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:53,990 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-12-07 12:00:53,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:53,990 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-12-07 12:00:53,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:54,023 INFO L225 Difference]: With dead ends: 22768 [2019-12-07 12:00:54,024 INFO L226 Difference]: Without dead ends: 13486 [2019-12-07 12:00:54,037 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:54,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-12-07 12:00:54,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-12-07 12:00:54,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-12-07 12:00:54,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-12-07 12:00:54,419 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-12-07 12:00:54,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:54,419 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-12-07 12:00:54,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:54,419 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-12-07 12:00:54,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 12:00:54,425 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:54,425 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:54,425 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:54,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:54,426 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-12-07 12:00:54,426 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:54,426 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722940452] [2019-12-07 12:00:54,426 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:54,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:54,459 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-12-07 12:00:54,459 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722940452] [2019-12-07 12:00:54,460 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:54,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:00:54,460 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345796378] [2019-12-07 12:00:54,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:54,460 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:54,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:54,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:54,461 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-12-07 12:00:54,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:54,849 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-12-07 12:00:54,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:54,849 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-12-07 12:00:54,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:54,882 INFO L225 Difference]: With dead ends: 32624 [2019-12-07 12:00:54,882 INFO L226 Difference]: Without dead ends: 19278 [2019-12-07 12:00:54,892 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:54,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-12-07 12:00:55,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-12-07 12:00:55,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-12-07 12:00:55,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-12-07 12:00:55,270 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-12-07 12:00:55,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:55,270 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-12-07 12:00:55,270 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:55,270 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-12-07 12:00:55,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 12:00:55,279 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:55,279 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:55,279 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:55,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:55,279 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-12-07 12:00:55,280 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:55,280 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628873376] [2019-12-07 12:00:55,280 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:55,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:55,330 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 12:00:55,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628873376] [2019-12-07 12:00:55,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:55,331 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:00:55,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025090090] [2019-12-07 12:00:55,332 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:00:55,332 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:55,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:00:55,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:00:55,332 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-12-07 12:00:56,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:56,024 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-12-07 12:00:56,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:00:56,024 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-12-07 12:00:56,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:56,049 INFO L225 Difference]: With dead ends: 47102 [2019-12-07 12:00:56,049 INFO L226 Difference]: Without dead ends: 28012 [2019-12-07 12:00:56,064 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:00:56,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-12-07 12:00:56,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-12-07 12:00:56,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-12-07 12:00:56,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-12-07 12:00:56,568 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-12-07 12:00:56,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:56,568 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-12-07 12:00:56,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:00:56,568 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-12-07 12:00:56,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 12:00:56,574 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:56,575 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:56,575 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:56,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:56,575 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-12-07 12:00:56,575 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:56,575 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217531711] [2019-12-07 12:00:56,575 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:56,604 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 12:00:56,604 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217531711] [2019-12-07 12:00:56,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:56,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:00:56,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26523333] [2019-12-07 12:00:56,605 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:00:56,605 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:56,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:00:56,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:00:56,605 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-12-07 12:00:57,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:57,355 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-12-07 12:00:57,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:00:57,356 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-12-07 12:00:57,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:57,375 INFO L225 Difference]: With dead ends: 45442 [2019-12-07 12:00:57,375 INFO L226 Difference]: Without dead ends: 26232 [2019-12-07 12:00:57,385 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:00:57,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-12-07 12:00:57,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-12-07 12:00:57,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-12-07 12:00:57,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-12-07 12:00:57,896 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-12-07 12:00:57,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:57,896 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-12-07 12:00:57,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:00:57,896 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-12-07 12:00:57,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 12:00:57,901 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:57,902 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:57,902 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:57,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:57,902 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-12-07 12:00:57,902 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:57,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452413443] [2019-12-07 12:00:57,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:57,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:57,925 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:00:57,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452413443] [2019-12-07 12:00:57,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:57,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:00:57,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063678789] [2019-12-07 12:00:57,926 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:00:57,926 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:57,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:00:57,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:57,927 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-12-07 12:00:58,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:58,419 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-12-07 12:00:58,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:00:58,420 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-12-07 12:00:58,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:58,432 INFO L225 Difference]: With dead ends: 29198 [2019-12-07 12:00:58,432 INFO L226 Difference]: Without dead ends: 19420 [2019-12-07 12:00:58,439 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:00:58,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-12-07 12:00:58,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-12-07 12:00:58,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-12-07 12:00:58,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-12-07 12:00:58,936 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-12-07 12:00:58,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:00:58,936 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-12-07 12:00:58,936 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:00:58,936 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-12-07 12:00:58,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-12-07 12:00:58,942 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:00:58,942 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:00:58,942 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:00:58,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:00:58,942 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-12-07 12:00:58,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:00:58,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187073738] [2019-12-07 12:00:58,943 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:00:58,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:00:58,972 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 12:00:58,972 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187073738] [2019-12-07 12:00:58,972 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:00:58,972 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:00:58,972 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145489133] [2019-12-07 12:00:58,973 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:00:58,973 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:00:58,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:00:58,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:00:58,973 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-12-07 12:00:59,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:00:59,725 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-12-07 12:00:59,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:00:59,726 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-12-07 12:00:59,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:00:59,738 INFO L225 Difference]: With dead ends: 37116 [2019-12-07 12:00:59,738 INFO L226 Difference]: Without dead ends: 17840 [2019-12-07 12:00:59,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:00:59,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-12-07 12:01:00,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-12-07 12:01:00,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-12-07 12:01:00,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-12-07 12:01:00,146 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-12-07 12:01:00,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:00,146 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-12-07 12:01:00,146 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:01:00,146 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-12-07 12:01:00,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-07 12:01:00,150 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:00,150 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:00,150 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:00,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:00,151 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-12-07 12:01:00,151 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:00,151 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319954189] [2019-12-07 12:01:00,151 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:00,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:00,172 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:01:00,172 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319954189] [2019-12-07 12:01:00,172 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:00,172 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:01:00,172 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008167430] [2019-12-07 12:01:00,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:01:00,173 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:00,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:01:00,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:00,173 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-12-07 12:01:00,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:00,514 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-12-07 12:01:00,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:01:00,514 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-12-07 12:01:00,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:00,521 INFO L225 Difference]: With dead ends: 21196 [2019-12-07 12:01:00,521 INFO L226 Difference]: Without dead ends: 11030 [2019-12-07 12:01:00,529 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:00,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-12-07 12:01:00,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-12-07 12:01:00,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-12-07 12:01:00,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-12-07 12:01:00,872 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-12-07 12:01:00,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:00,872 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-12-07 12:01:00,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:01:00,872 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-12-07 12:01:00,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-12-07 12:01:00,877 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:00,877 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:00,877 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:00,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:00,877 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-12-07 12:01:00,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:00,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484810551] [2019-12-07 12:01:00,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:00,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:00,908 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:01:00,908 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484810551] [2019-12-07 12:01:00,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:00,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:01:00,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991737813] [2019-12-07 12:01:00,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:01:00,909 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:00,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:01:00,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:00,909 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-12-07 12:01:01,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:01,228 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-12-07 12:01:01,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:01:01,228 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-12-07 12:01:01,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:01,235 INFO L225 Difference]: With dead ends: 20200 [2019-12-07 12:01:01,235 INFO L226 Difference]: Without dead ends: 11030 [2019-12-07 12:01:01,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:01,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-12-07 12:01:01,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-12-07 12:01:01,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-12-07 12:01:01,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-12-07 12:01:01,558 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-12-07 12:01:01,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:01,558 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-12-07 12:01:01,558 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:01:01,558 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-12-07 12:01:01,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-12-07 12:01:01,563 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:01,563 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:01,563 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:01,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:01,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-12-07 12:01:01,563 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:01,564 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139086790] [2019-12-07 12:01:01,564 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:01,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:01,598 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 12:01:01,598 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139086790] [2019-12-07 12:01:01,598 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:01,598 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:01:01,598 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725961886] [2019-12-07 12:01:01,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 12:01:01,599 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:01,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:01:01,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:01:01,599 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-12-07 12:01:02,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:02,550 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-12-07 12:01:02,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:01:02,550 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-12-07 12:01:02,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:02,565 INFO L225 Difference]: With dead ends: 35306 [2019-12-07 12:01:02,565 INFO L226 Difference]: Without dead ends: 24343 [2019-12-07 12:01:02,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:01:02,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-12-07 12:01:03,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-12-07 12:01:03,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-12-07 12:01:03,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-12-07 12:01:03,019 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-12-07 12:01:03,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:03,019 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-12-07 12:01:03,019 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 12:01:03,020 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-12-07 12:01:03,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-12-07 12:01:03,024 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:03,024 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:03,025 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:03,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:03,025 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-12-07 12:01:03,025 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:03,025 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942529553] [2019-12-07 12:01:03,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:03,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:03,063 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:01:03,063 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942529553] [2019-12-07 12:01:03,063 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:03,063 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:01:03,063 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764142050] [2019-12-07 12:01:03,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:01:03,063 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:03,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:01:03,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:03,064 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-12-07 12:01:03,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:03,479 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-12-07 12:01:03,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:01:03,479 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-12-07 12:01:03,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:03,487 INFO L225 Difference]: With dead ends: 19722 [2019-12-07 12:01:03,487 INFO L226 Difference]: Without dead ends: 11442 [2019-12-07 12:01:03,492 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:03,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-12-07 12:01:03,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-12-07 12:01:03,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-12-07 12:01:03,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-12-07 12:01:03,907 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-12-07 12:01:03,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:03,907 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-12-07 12:01:03,907 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:01:03,907 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-12-07 12:01:03,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 12:01:03,912 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:03,912 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:03,912 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:03,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:03,912 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-12-07 12:01:03,912 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:03,913 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108579400] [2019-12-07 12:01:03,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:03,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:03,946 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 12:01:03,946 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108579400] [2019-12-07 12:01:03,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:03,947 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:01:03,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789661327] [2019-12-07 12:01:03,947 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:01:03,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:03,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:01:03,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:03,947 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-12-07 12:01:04,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:04,400 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-12-07 12:01:04,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:01:04,400 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 12:01:04,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:04,405 INFO L225 Difference]: With dead ends: 22664 [2019-12-07 12:01:04,405 INFO L226 Difference]: Without dead ends: 6788 [2019-12-07 12:01:04,410 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:04,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-12-07 12:01:04,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-12-07 12:01:04,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-12-07 12:01:04,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-12-07 12:01:04,653 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-12-07 12:01:04,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:04,653 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-12-07 12:01:04,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:01:04,653 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-12-07 12:01:04,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-12-07 12:01:04,657 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:04,657 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:04,658 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:04,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:04,658 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-12-07 12:01:04,658 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:04,658 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078331126] [2019-12-07 12:01:04,658 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:04,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:01:04,691 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:01:04,691 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078331126] [2019-12-07 12:01:04,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:01:04,692 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:01:04,692 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530143948] [2019-12-07 12:01:04,692 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 12:01:04,692 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:01:04,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:01:04,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:04,692 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-12-07 12:01:04,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:01:04,945 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-12-07 12:01:04,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:01:04,946 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-12-07 12:01:04,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 12:01:04,950 INFO L225 Difference]: With dead ends: 11554 [2019-12-07 12:01:04,950 INFO L226 Difference]: Without dead ends: 6580 [2019-12-07 12:01:04,952 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:01:04,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-12-07 12:01:05,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-12-07 12:01:05,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-12-07 12:01:05,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-12-07 12:01:05,199 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-12-07 12:01:05,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 12:01:05,199 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-12-07 12:01:05,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 12:01:05,200 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-12-07 12:01:05,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-12-07 12:01:05,204 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 12:01:05,204 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:01:05,204 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 12:01:05,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:01:05,204 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-12-07 12:01:05,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:01:05,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229272529] [2019-12-07 12:01:05,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:01:05,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:01:05,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:01:05,273 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:01:05,273 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 12:01:05,375 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 12:01:05 BoogieIcfgContainer [2019-12-07 12:01:05,375 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 12:01:05,375 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:01:05,375 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:01:05,376 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:01:05,376 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:00:51" (3/4) ... [2019-12-07 12:01:05,377 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 12:01:05,461 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_6af3554d-0177-4382-b0f8-cac8d3345f8f/bin/uautomizer/witness.graphml [2019-12-07 12:01:05,462 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:01:05,463 INFO L168 Benchmark]: Toolchain (without parser) took 15145.61 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 945.1 MB in the beginning and 1.8 GB in the end (delta: -849.4 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,463 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 961.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:01:05,464 INFO L168 Benchmark]: CACSL2BoogieTranslator took 234.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 945.1 MB in the beginning and 1.1 GB in the end (delta: -156.6 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,464 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.09 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:01:05,464 INFO L168 Benchmark]: Boogie Preprocessor took 31.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,464 INFO L168 Benchmark]: RCFGBuilder took 498.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 70.2 MB). Peak memory consumption was 70.2 MB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,465 INFO L168 Benchmark]: TraceAbstraction took 14254.93 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: -784.8 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,465 INFO L168 Benchmark]: Witness Printer took 86.45 ms. Allocated memory is still 3.2 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 15.4 MB). Peak memory consumption was 15.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:01:05,466 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 961.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 234.10 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 112.2 MB). Free memory was 945.1 MB in the beginning and 1.1 GB in the end (delta: -156.6 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.09 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 31.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 498.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 70.2 MB). Peak memory consumption was 70.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 14254.93 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: -784.8 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 86.45 ms. Allocated memory is still 3.2 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 15.4 MB). Peak memory consumption was 15.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 14.1s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 7.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.4s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.4s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...