./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:56:29,924 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:56:29,925 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:56:29,935 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:56:29,935 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:56:29,936 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:56:29,937 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:56:29,938 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:56:29,940 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:56:29,940 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:56:29,941 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:56:29,942 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:56:29,942 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:56:29,942 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:56:29,943 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:56:29,944 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:56:29,945 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:56:29,946 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:56:29,947 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:56:29,948 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:56:29,950 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:56:29,951 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:56:29,952 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:56:29,952 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:56:29,954 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:56:29,954 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:56:29,954 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:56:29,955 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:56:29,955 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:56:29,956 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:56:29,956 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:56:29,957 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:56:29,957 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:56:29,958 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:56:29,959 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:56:29,959 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:56:29,959 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:56:29,960 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:56:29,960 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:56:29,961 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:56:29,961 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:56:29,962 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:56:29,971 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:56:29,972 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:56:29,972 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:56:29,972 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:56:29,972 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:56:29,973 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:56:29,973 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:56:29,974 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:56:29,974 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:56:29,974 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:56:29,975 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2019-12-07 17:56:30,078 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:56:30,086 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:56:30,088 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:56:30,089 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:56:30,089 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:56:30,089 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-12-07 17:56:30,127 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/data/92c399e6f/7f8f669fd98d459897ed2230617139c1/FLAG432e8cf65 [2019-12-07 17:56:30,555 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:56:30,556 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-12-07 17:56:30,563 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/data/92c399e6f/7f8f669fd98d459897ed2230617139c1/FLAG432e8cf65 [2019-12-07 17:56:30,571 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/data/92c399e6f/7f8f669fd98d459897ed2230617139c1 [2019-12-07 17:56:30,573 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:56:30,574 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:56:30,574 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:56:30,574 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:56:30,576 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:56:30,577 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,579 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e3d67c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30, skipping insertion in model container [2019-12-07 17:56:30,579 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,584 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:56:30,613 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:56:30,777 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:56:30,781 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:56:30,812 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:56:30,825 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:56:30,826 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30 WrapperNode [2019-12-07 17:56:30,826 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:56:30,826 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:56:30,826 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:56:30,827 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:56:30,832 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,837 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,867 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:56:30,867 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:56:30,867 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:56:30,867 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:56:30,874 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,874 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,878 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,878 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,888 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,898 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,901 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... [2019-12-07 17:56:30,905 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:56:30,905 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:56:30,905 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:56:30,905 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:56:30,906 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:56:30,956 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:56:30,957 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:56:31,499 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:56:31,499 INFO L287 CfgBuilder]: Removed 148 assume(true) statements. [2019-12-07 17:56:31,500 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:56:31 BoogieIcfgContainer [2019-12-07 17:56:31,500 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:56:31,501 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:56:31,501 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:56:31,504 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:56:31,504 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:56:30" (1/3) ... [2019-12-07 17:56:31,505 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c204a3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:56:31, skipping insertion in model container [2019-12-07 17:56:31,505 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:56:30" (2/3) ... [2019-12-07 17:56:31,505 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c204a3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:56:31, skipping insertion in model container [2019-12-07 17:56:31,505 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:56:31" (3/3) ... [2019-12-07 17:56:31,506 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2019-12-07 17:56:31,515 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:56:31,521 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 17:56:31,531 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-12-07 17:56:31,550 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:56:31,550 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:56:31,550 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:56:31,550 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:56:31,550 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:56:31,550 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:56:31,551 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:56:31,551 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:56:31,566 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states. [2019-12-07 17:56:31,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:31,573 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:31,574 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:31,574 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:31,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:31,578 INFO L82 PathProgramCache]: Analyzing trace with hash -1653942868, now seen corresponding path program 1 times [2019-12-07 17:56:31,584 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:31,584 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211122330] [2019-12-07 17:56:31,584 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:31,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:31,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:31,708 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211122330] [2019-12-07 17:56:31,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:31,709 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:31,710 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863336437] [2019-12-07 17:56:31,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:31,715 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:31,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:31,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:31,725 INFO L87 Difference]: Start difference. First operand 374 states. Second operand 3 states. [2019-12-07 17:56:31,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:31,777 INFO L93 Difference]: Finished difference Result 743 states and 1159 transitions. [2019-12-07 17:56:31,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:31,779 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:31,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:31,792 INFO L225 Difference]: With dead ends: 743 [2019-12-07 17:56:31,792 INFO L226 Difference]: Without dead ends: 370 [2019-12-07 17:56:31,796 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:31,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2019-12-07 17:56:31,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 370. [2019-12-07 17:56:31,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2019-12-07 17:56:31,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 561 transitions. [2019-12-07 17:56:31,847 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 561 transitions. Word has length 73 [2019-12-07 17:56:31,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:31,848 INFO L462 AbstractCegarLoop]: Abstraction has 370 states and 561 transitions. [2019-12-07 17:56:31,848 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:31,848 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 561 transitions. [2019-12-07 17:56:31,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:31,850 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:31,850 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:31,850 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:31,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:31,851 INFO L82 PathProgramCache]: Analyzing trace with hash -1161316694, now seen corresponding path program 1 times [2019-12-07 17:56:31,851 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:31,851 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122588850] [2019-12-07 17:56:31,851 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:31,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:31,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:31,889 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122588850] [2019-12-07 17:56:31,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:31,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:31,889 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793644989] [2019-12-07 17:56:31,891 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:31,891 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:31,891 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:31,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:31,892 INFO L87 Difference]: Start difference. First operand 370 states and 561 transitions. Second operand 3 states. [2019-12-07 17:56:31,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:31,948 INFO L93 Difference]: Finished difference Result 1004 states and 1519 transitions. [2019-12-07 17:56:31,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:31,949 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:31,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:31,952 INFO L225 Difference]: With dead ends: 1004 [2019-12-07 17:56:31,952 INFO L226 Difference]: Without dead ends: 643 [2019-12-07 17:56:31,954 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:31,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 643 states. [2019-12-07 17:56:31,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 643 to 641. [2019-12-07 17:56:31,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:31,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 961 transitions. [2019-12-07 17:56:31,983 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 961 transitions. Word has length 73 [2019-12-07 17:56:31,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:31,983 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 961 transitions. [2019-12-07 17:56:31,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:31,983 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 961 transitions. [2019-12-07 17:56:31,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:31,984 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:31,985 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:31,985 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:31,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:31,985 INFO L82 PathProgramCache]: Analyzing trace with hash 1509510378, now seen corresponding path program 1 times [2019-12-07 17:56:31,985 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:31,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681608580] [2019-12-07 17:56:31,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:31,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,019 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681608580] [2019-12-07 17:56:32,019 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,020 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,020 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643299996] [2019-12-07 17:56:32,020 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,020 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,021 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,021 INFO L87 Difference]: Start difference. First operand 641 states and 961 transitions. Second operand 3 states. [2019-12-07 17:56:32,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,055 INFO L93 Difference]: Finished difference Result 1272 states and 1907 transitions. [2019-12-07 17:56:32,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,056 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,060 INFO L225 Difference]: With dead ends: 1272 [2019-12-07 17:56:32,060 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,061 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 953 transitions. [2019-12-07 17:56:32,087 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 953 transitions. Word has length 73 [2019-12-07 17:56:32,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,088 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 953 transitions. [2019-12-07 17:56:32,088 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,088 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 953 transitions. [2019-12-07 17:56:32,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,089 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,090 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,090 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,090 INFO L82 PathProgramCache]: Analyzing trace with hash 1595666090, now seen corresponding path program 1 times [2019-12-07 17:56:32,090 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718864717] [2019-12-07 17:56:32,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,129 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718864717] [2019-12-07 17:56:32,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,130 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616357781] [2019-12-07 17:56:32,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,130 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,131 INFO L87 Difference]: Start difference. First operand 641 states and 953 transitions. Second operand 3 states. [2019-12-07 17:56:32,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,161 INFO L93 Difference]: Finished difference Result 1271 states and 1890 transitions. [2019-12-07 17:56:32,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,162 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,166 INFO L225 Difference]: With dead ends: 1271 [2019-12-07 17:56:32,166 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,168 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 945 transitions. [2019-12-07 17:56:32,195 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 945 transitions. Word has length 73 [2019-12-07 17:56:32,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,196 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 945 transitions. [2019-12-07 17:56:32,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,196 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 945 transitions. [2019-12-07 17:56:32,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,197 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,198 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,198 INFO L82 PathProgramCache]: Analyzing trace with hash 1178269484, now seen corresponding path program 1 times [2019-12-07 17:56:32,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459650807] [2019-12-07 17:56:32,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,229 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459650807] [2019-12-07 17:56:32,229 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,229 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370348039] [2019-12-07 17:56:32,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,230 INFO L87 Difference]: Start difference. First operand 641 states and 945 transitions. Second operand 3 states. [2019-12-07 17:56:32,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,257 INFO L93 Difference]: Finished difference Result 1270 states and 1873 transitions. [2019-12-07 17:56:32,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,258 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,260 INFO L225 Difference]: With dead ends: 1270 [2019-12-07 17:56:32,261 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,262 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 937 transitions. [2019-12-07 17:56:32,292 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 937 transitions. Word has length 73 [2019-12-07 17:56:32,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,292 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 937 transitions. [2019-12-07 17:56:32,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,292 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 937 transitions. [2019-12-07 17:56:32,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,293 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,293 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,293 INFO L82 PathProgramCache]: Analyzing trace with hash 52103404, now seen corresponding path program 1 times [2019-12-07 17:56:32,294 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,294 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589272575] [2019-12-07 17:56:32,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,317 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589272575] [2019-12-07 17:56:32,317 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,317 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,317 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894661848] [2019-12-07 17:56:32,317 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,317 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,318 INFO L87 Difference]: Start difference. First operand 641 states and 937 transitions. Second operand 3 states. [2019-12-07 17:56:32,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,353 INFO L93 Difference]: Finished difference Result 1268 states and 1854 transitions. [2019-12-07 17:56:32,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,353 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,356 INFO L225 Difference]: With dead ends: 1268 [2019-12-07 17:56:32,356 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,357 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 919 transitions. [2019-12-07 17:56:32,374 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 919 transitions. Word has length 73 [2019-12-07 17:56:32,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,375 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 919 transitions. [2019-12-07 17:56:32,375 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,375 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 919 transitions. [2019-12-07 17:56:32,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,375 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,375 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,375 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,376 INFO L82 PathProgramCache]: Analyzing trace with hash 2144832493, now seen corresponding path program 1 times [2019-12-07 17:56:32,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876835616] [2019-12-07 17:56:32,376 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,403 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876835616] [2019-12-07 17:56:32,403 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,403 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,403 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768706472] [2019-12-07 17:56:32,404 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,404 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,404 INFO L87 Difference]: Start difference. First operand 641 states and 919 transitions. Second operand 3 states. [2019-12-07 17:56:32,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,442 INFO L93 Difference]: Finished difference Result 1267 states and 1817 transitions. [2019-12-07 17:56:32,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,442 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,445 INFO L225 Difference]: With dead ends: 1267 [2019-12-07 17:56:32,445 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 901 transitions. [2019-12-07 17:56:32,463 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 901 transitions. Word has length 73 [2019-12-07 17:56:32,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,464 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 901 transitions. [2019-12-07 17:56:32,464 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,464 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 901 transitions. [2019-12-07 17:56:32,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,464 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,464 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,464 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,465 INFO L82 PathProgramCache]: Analyzing trace with hash 1887883821, now seen corresponding path program 1 times [2019-12-07 17:56:32,465 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,465 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083528065] [2019-12-07 17:56:32,465 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,485 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083528065] [2019-12-07 17:56:32,485 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,485 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,485 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64434335] [2019-12-07 17:56:32,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,486 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,486 INFO L87 Difference]: Start difference. First operand 641 states and 901 transitions. Second operand 3 states. [2019-12-07 17:56:32,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,524 INFO L93 Difference]: Finished difference Result 1266 states and 1780 transitions. [2019-12-07 17:56:32,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,525 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,528 INFO L225 Difference]: With dead ends: 1266 [2019-12-07 17:56:32,528 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,530 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 883 transitions. [2019-12-07 17:56:32,551 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 883 transitions. Word has length 73 [2019-12-07 17:56:32,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,551 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 883 transitions. [2019-12-07 17:56:32,551 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,551 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 883 transitions. [2019-12-07 17:56:32,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,551 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,552 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,552 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1757929134, now seen corresponding path program 1 times [2019-12-07 17:56:32,552 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,552 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868602902] [2019-12-07 17:56:32,552 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868602902] [2019-12-07 17:56:32,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643946690] [2019-12-07 17:56:32,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,572 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,572 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,572 INFO L87 Difference]: Start difference. First operand 641 states and 883 transitions. Second operand 3 states. [2019-12-07 17:56:32,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,613 INFO L93 Difference]: Finished difference Result 1265 states and 1743 transitions. [2019-12-07 17:56:32,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,614 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,617 INFO L225 Difference]: With dead ends: 1265 [2019-12-07 17:56:32,618 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,619 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 865 transitions. [2019-12-07 17:56:32,645 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 865 transitions. Word has length 73 [2019-12-07 17:56:32,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,645 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 865 transitions. [2019-12-07 17:56:32,645 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,646 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 865 transitions. [2019-12-07 17:56:32,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,646 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,646 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,647 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1024701678, now seen corresponding path program 1 times [2019-12-07 17:56:32,647 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,647 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065938679] [2019-12-07 17:56:32,647 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065938679] [2019-12-07 17:56:32,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,674 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:32,674 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841926046] [2019-12-07 17:56:32,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,675 INFO L87 Difference]: Start difference. First operand 641 states and 865 transitions. Second operand 3 states. [2019-12-07 17:56:32,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,697 INFO L93 Difference]: Finished difference Result 1269 states and 1712 transitions. [2019-12-07 17:56:32,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,698 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,700 INFO L225 Difference]: With dead ends: 1269 [2019-12-07 17:56:32,700 INFO L226 Difference]: Without dead ends: 641 [2019-12-07 17:56:32,701 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2019-12-07 17:56:32,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2019-12-07 17:56:32,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2019-12-07 17:56:32,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 857 transitions. [2019-12-07 17:56:32,718 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 857 transitions. Word has length 73 [2019-12-07 17:56:32,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,719 INFO L462 AbstractCegarLoop]: Abstraction has 641 states and 857 transitions. [2019-12-07 17:56:32,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,719 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 857 transitions. [2019-12-07 17:56:32,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:56:32,719 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,719 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,719 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1243556396, now seen corresponding path program 1 times [2019-12-07 17:56:32,720 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,720 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121528559] [2019-12-07 17:56:32,720 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,744 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121528559] [2019-12-07 17:56:32,745 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,745 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:32,745 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415843727] [2019-12-07 17:56:32,745 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,745 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,746 INFO L87 Difference]: Start difference. First operand 641 states and 857 transitions. Second operand 3 states. [2019-12-07 17:56:32,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,804 INFO L93 Difference]: Finished difference Result 1812 states and 2410 transitions. [2019-12-07 17:56:32,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,804 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2019-12-07 17:56:32,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,809 INFO L225 Difference]: With dead ends: 1812 [2019-12-07 17:56:32,809 INFO L226 Difference]: Without dead ends: 1232 [2019-12-07 17:56:32,810 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1232 states. [2019-12-07 17:56:32,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1232 to 1168. [2019-12-07 17:56:32,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2019-12-07 17:56:32,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1539 transitions. [2019-12-07 17:56:32,842 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1539 transitions. Word has length 73 [2019-12-07 17:56:32,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:32,842 INFO L462 AbstractCegarLoop]: Abstraction has 1168 states and 1539 transitions. [2019-12-07 17:56:32,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:32,842 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1539 transitions. [2019-12-07 17:56:32,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-12-07 17:56:32,843 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:32,843 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:32,843 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:32,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:32,843 INFO L82 PathProgramCache]: Analyzing trace with hash -546581241, now seen corresponding path program 1 times [2019-12-07 17:56:32,843 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:32,843 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200462724] [2019-12-07 17:56:32,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:32,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:32,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:32,875 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200462724] [2019-12-07 17:56:32,875 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:32,875 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:32,875 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929578425] [2019-12-07 17:56:32,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:32,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:32,876 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:32,876 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,876 INFO L87 Difference]: Start difference. First operand 1168 states and 1539 transitions. Second operand 3 states. [2019-12-07 17:56:32,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:32,962 INFO L93 Difference]: Finished difference Result 3182 states and 4193 transitions. [2019-12-07 17:56:32,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:32,963 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-12-07 17:56:32,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:32,970 INFO L225 Difference]: With dead ends: 3182 [2019-12-07 17:56:32,970 INFO L226 Difference]: Without dead ends: 2132 [2019-12-07 17:56:32,972 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:32,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2132 states. [2019-12-07 17:56:33,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2132 to 2034. [2019-12-07 17:56:33,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2034 states. [2019-12-07 17:56:33,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2034 states to 2034 states and 2664 transitions. [2019-12-07 17:56:33,030 INFO L78 Accepts]: Start accepts. Automaton has 2034 states and 2664 transitions. Word has length 74 [2019-12-07 17:56:33,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:33,031 INFO L462 AbstractCegarLoop]: Abstraction has 2034 states and 2664 transitions. [2019-12-07 17:56:33,031 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:33,031 INFO L276 IsEmpty]: Start isEmpty. Operand 2034 states and 2664 transitions. [2019-12-07 17:56:33,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 17:56:33,031 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:33,032 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:33,032 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:33,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:33,032 INFO L82 PathProgramCache]: Analyzing trace with hash 1027993841, now seen corresponding path program 1 times [2019-12-07 17:56:33,032 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:33,032 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896448513] [2019-12-07 17:56:33,032 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:33,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:33,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:33,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896448513] [2019-12-07 17:56:33,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:33,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:33,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036618421] [2019-12-07 17:56:33,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:33,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:33,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:33,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,053 INFO L87 Difference]: Start difference. First operand 2034 states and 2664 transitions. Second operand 3 states. [2019-12-07 17:56:33,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:33,188 INFO L93 Difference]: Finished difference Result 5772 states and 7544 transitions. [2019-12-07 17:56:33,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:33,188 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-12-07 17:56:33,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:33,202 INFO L225 Difference]: With dead ends: 5772 [2019-12-07 17:56:33,202 INFO L226 Difference]: Without dead ends: 3856 [2019-12-07 17:56:33,204 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3856 states. [2019-12-07 17:56:33,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3856 to 3718. [2019-12-07 17:56:33,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3718 states. [2019-12-07 17:56:33,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3718 states to 3718 states and 4834 transitions. [2019-12-07 17:56:33,300 INFO L78 Accepts]: Start accepts. Automaton has 3718 states and 4834 transitions. Word has length 75 [2019-12-07 17:56:33,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:33,300 INFO L462 AbstractCegarLoop]: Abstraction has 3718 states and 4834 transitions. [2019-12-07 17:56:33,300 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:33,300 INFO L276 IsEmpty]: Start isEmpty. Operand 3718 states and 4834 transitions. [2019-12-07 17:56:33,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-12-07 17:56:33,301 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:33,301 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:33,301 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:33,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:33,301 INFO L82 PathProgramCache]: Analyzing trace with hash -934868943, now seen corresponding path program 1 times [2019-12-07 17:56:33,302 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:33,302 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456519910] [2019-12-07 17:56:33,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:33,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:33,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:33,312 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456519910] [2019-12-07 17:56:33,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:33,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:33,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841551417] [2019-12-07 17:56:33,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:33,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:33,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:33,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,313 INFO L87 Difference]: Start difference. First operand 3718 states and 4834 transitions. Second operand 3 states. [2019-12-07 17:56:33,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:33,420 INFO L93 Difference]: Finished difference Result 7254 states and 9443 transitions. [2019-12-07 17:56:33,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:33,421 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2019-12-07 17:56:33,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:33,434 INFO L225 Difference]: With dead ends: 7254 [2019-12-07 17:56:33,434 INFO L226 Difference]: Without dead ends: 3608 [2019-12-07 17:56:33,438 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3608 states. [2019-12-07 17:56:33,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3608 to 3608. [2019-12-07 17:56:33,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3608 states. [2019-12-07 17:56:33,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3608 states to 3608 states and 4698 transitions. [2019-12-07 17:56:33,537 INFO L78 Accepts]: Start accepts. Automaton has 3608 states and 4698 transitions. Word has length 75 [2019-12-07 17:56:33,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:33,537 INFO L462 AbstractCegarLoop]: Abstraction has 3608 states and 4698 transitions. [2019-12-07 17:56:33,537 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:33,537 INFO L276 IsEmpty]: Start isEmpty. Operand 3608 states and 4698 transitions. [2019-12-07 17:56:33,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-12-07 17:56:33,538 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:33,538 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:33,538 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:33,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:33,539 INFO L82 PathProgramCache]: Analyzing trace with hash -607730891, now seen corresponding path program 1 times [2019-12-07 17:56:33,539 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:33,539 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573272747] [2019-12-07 17:56:33,539 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:33,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:33,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:33,560 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573272747] [2019-12-07 17:56:33,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:33,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:33,560 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401000583] [2019-12-07 17:56:33,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:33,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:33,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:33,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,561 INFO L87 Difference]: Start difference. First operand 3608 states and 4698 transitions. Second operand 3 states. [2019-12-07 17:56:33,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:33,740 INFO L93 Difference]: Finished difference Result 10194 states and 13246 transitions. [2019-12-07 17:56:33,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:33,740 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-12-07 17:56:33,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:33,762 INFO L225 Difference]: With dead ends: 10194 [2019-12-07 17:56:33,762 INFO L226 Difference]: Without dead ends: 6704 [2019-12-07 17:56:33,766 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6704 states. [2019-12-07 17:56:33,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6704 to 6542. [2019-12-07 17:56:33,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6542 states. [2019-12-07 17:56:33,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6542 states to 6542 states and 8460 transitions. [2019-12-07 17:56:33,950 INFO L78 Accepts]: Start accepts. Automaton has 6542 states and 8460 transitions. Word has length 76 [2019-12-07 17:56:33,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:33,950 INFO L462 AbstractCegarLoop]: Abstraction has 6542 states and 8460 transitions. [2019-12-07 17:56:33,950 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:33,950 INFO L276 IsEmpty]: Start isEmpty. Operand 6542 states and 8460 transitions. [2019-12-07 17:56:33,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2019-12-07 17:56:33,952 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:33,952 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:33,952 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:33,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:33,952 INFO L82 PathProgramCache]: Analyzing trace with hash 906360113, now seen corresponding path program 1 times [2019-12-07 17:56:33,952 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:33,953 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762199243] [2019-12-07 17:56:33,953 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:33,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:33,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:33,968 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762199243] [2019-12-07 17:56:33,968 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:33,968 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:33,968 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649093160] [2019-12-07 17:56:33,969 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:33,969 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:33,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:33,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:33,969 INFO L87 Difference]: Start difference. First operand 6542 states and 8460 transitions. Second operand 3 states. [2019-12-07 17:56:34,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:34,123 INFO L93 Difference]: Finished difference Result 12890 states and 16683 transitions. [2019-12-07 17:56:34,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:34,124 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2019-12-07 17:56:34,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:34,144 INFO L225 Difference]: With dead ends: 12890 [2019-12-07 17:56:34,144 INFO L226 Difference]: Without dead ends: 6434 [2019-12-07 17:56:34,149 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:34,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6434 states. [2019-12-07 17:56:34,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6434 to 6434. [2019-12-07 17:56:34,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6434 states. [2019-12-07 17:56:34,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6434 states to 6434 states and 8328 transitions. [2019-12-07 17:56:34,303 INFO L78 Accepts]: Start accepts. Automaton has 6434 states and 8328 transitions. Word has length 76 [2019-12-07 17:56:34,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:34,303 INFO L462 AbstractCegarLoop]: Abstraction has 6434 states and 8328 transitions. [2019-12-07 17:56:34,303 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:34,303 INFO L276 IsEmpty]: Start isEmpty. Operand 6434 states and 8328 transitions. [2019-12-07 17:56:34,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-12-07 17:56:34,304 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:34,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:34,304 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:34,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:34,304 INFO L82 PathProgramCache]: Analyzing trace with hash 675279555, now seen corresponding path program 1 times [2019-12-07 17:56:34,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:34,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542718809] [2019-12-07 17:56:34,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:34,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:34,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:34,327 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542718809] [2019-12-07 17:56:34,327 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:34,327 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:34,327 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617809962] [2019-12-07 17:56:34,327 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:34,328 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:34,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:34,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:34,328 INFO L87 Difference]: Start difference. First operand 6434 states and 8328 transitions. Second operand 3 states. [2019-12-07 17:56:34,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:34,681 INFO L93 Difference]: Finished difference Result 18946 states and 24537 transitions. [2019-12-07 17:56:34,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:34,681 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2019-12-07 17:56:34,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:34,697 INFO L225 Difference]: With dead ends: 18946 [2019-12-07 17:56:34,697 INFO L226 Difference]: Without dead ends: 12602 [2019-12-07 17:56:34,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:34,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12602 states. [2019-12-07 17:56:34,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12602 to 12538. [2019-12-07 17:56:34,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12538 states. [2019-12-07 17:56:34,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12538 states to 12538 states and 16110 transitions. [2019-12-07 17:56:34,980 INFO L78 Accepts]: Start accepts. Automaton has 12538 states and 16110 transitions. Word has length 77 [2019-12-07 17:56:34,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:34,980 INFO L462 AbstractCegarLoop]: Abstraction has 12538 states and 16110 transitions. [2019-12-07 17:56:34,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:34,980 INFO L276 IsEmpty]: Start isEmpty. Operand 12538 states and 16110 transitions. [2019-12-07 17:56:34,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-07 17:56:34,983 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:34,983 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:34,983 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:34,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:34,984 INFO L82 PathProgramCache]: Analyzing trace with hash -1687722621, now seen corresponding path program 1 times [2019-12-07 17:56:34,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:34,984 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837761689] [2019-12-07 17:56:34,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:34,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:35,006 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:35,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837761689] [2019-12-07 17:56:35,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:35,007 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:35,007 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872352792] [2019-12-07 17:56:35,007 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:35,007 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:35,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:35,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:35,008 INFO L87 Difference]: Start difference. First operand 12538 states and 16110 transitions. Second operand 3 states. [2019-12-07 17:56:35,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:35,524 INFO L93 Difference]: Finished difference Result 37260 states and 47825 transitions. [2019-12-07 17:56:35,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:35,525 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 96 [2019-12-07 17:56:35,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:35,562 INFO L225 Difference]: With dead ends: 37260 [2019-12-07 17:56:35,562 INFO L226 Difference]: Without dead ends: 24838 [2019-12-07 17:56:35,575 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:35,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24838 states. [2019-12-07 17:56:36,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24838 to 24838. [2019-12-07 17:56:36,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24838 states. [2019-12-07 17:56:36,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24838 states to 24838 states and 31776 transitions. [2019-12-07 17:56:36,224 INFO L78 Accepts]: Start accepts. Automaton has 24838 states and 31776 transitions. Word has length 96 [2019-12-07 17:56:36,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:36,224 INFO L462 AbstractCegarLoop]: Abstraction has 24838 states and 31776 transitions. [2019-12-07 17:56:36,224 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:36,224 INFO L276 IsEmpty]: Start isEmpty. Operand 24838 states and 31776 transitions. [2019-12-07 17:56:36,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 17:56:36,236 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:36,236 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:36,236 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:36,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:36,236 INFO L82 PathProgramCache]: Analyzing trace with hash 393922111, now seen corresponding path program 1 times [2019-12-07 17:56:36,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:36,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286760243] [2019-12-07 17:56:36,237 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:36,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:36,270 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-12-07 17:56:36,270 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286760243] [2019-12-07 17:56:36,270 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:36,270 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:36,270 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722244225] [2019-12-07 17:56:36,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:36,271 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:36,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:36,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:36,271 INFO L87 Difference]: Start difference. First operand 24838 states and 31776 transitions. Second operand 3 states. [2019-12-07 17:56:36,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:36,981 INFO L93 Difference]: Finished difference Result 60602 states and 77478 transitions. [2019-12-07 17:56:36,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:36,982 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-12-07 17:56:36,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:37,023 INFO L225 Difference]: With dead ends: 60602 [2019-12-07 17:56:37,023 INFO L226 Difference]: Without dead ends: 35876 [2019-12-07 17:56:37,041 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:37,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35876 states. [2019-12-07 17:56:37,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35876 to 35746. [2019-12-07 17:56:37,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35746 states. [2019-12-07 17:56:37,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35746 states to 35746 states and 45448 transitions. [2019-12-07 17:56:37,888 INFO L78 Accepts]: Start accepts. Automaton has 35746 states and 45448 transitions. Word has length 131 [2019-12-07 17:56:37,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:37,889 INFO L462 AbstractCegarLoop]: Abstraction has 35746 states and 45448 transitions. [2019-12-07 17:56:37,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:37,889 INFO L276 IsEmpty]: Start isEmpty. Operand 35746 states and 45448 transitions. [2019-12-07 17:56:37,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 17:56:37,900 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:37,900 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:37,900 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:37,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:37,901 INFO L82 PathProgramCache]: Analyzing trace with hash 760471151, now seen corresponding path program 1 times [2019-12-07 17:56:37,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:37,901 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810107613] [2019-12-07 17:56:37,901 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:37,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:37,933 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-12-07 17:56:37,934 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810107613] [2019-12-07 17:56:37,934 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:37,934 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:37,934 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614191308] [2019-12-07 17:56:37,934 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:37,934 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:37,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:37,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:37,935 INFO L87 Difference]: Start difference. First operand 35746 states and 45448 transitions. Second operand 3 states. [2019-12-07 17:56:38,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:38,993 INFO L93 Difference]: Finished difference Result 87290 states and 110962 transitions. [2019-12-07 17:56:38,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:38,994 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-12-07 17:56:38,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:39,040 INFO L225 Difference]: With dead ends: 87290 [2019-12-07 17:56:39,040 INFO L226 Difference]: Without dead ends: 51680 [2019-12-07 17:56:39,060 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:39,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51680 states. [2019-12-07 17:56:40,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51680 to 51486. [2019-12-07 17:56:40,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51486 states. [2019-12-07 17:56:40,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51486 states to 51486 states and 65112 transitions. [2019-12-07 17:56:40,327 INFO L78 Accepts]: Start accepts. Automaton has 51486 states and 65112 transitions. Word has length 131 [2019-12-07 17:56:40,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:40,327 INFO L462 AbstractCegarLoop]: Abstraction has 51486 states and 65112 transitions. [2019-12-07 17:56:40,327 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:40,327 INFO L276 IsEmpty]: Start isEmpty. Operand 51486 states and 65112 transitions. [2019-12-07 17:56:40,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 17:56:40,345 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:40,345 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:40,345 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:40,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:40,346 INFO L82 PathProgramCache]: Analyzing trace with hash -776225517, now seen corresponding path program 1 times [2019-12-07 17:56:40,346 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:40,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484584754] [2019-12-07 17:56:40,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:40,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:40,377 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-12-07 17:56:40,377 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484584754] [2019-12-07 17:56:40,377 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:40,377 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:56:40,377 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425383880] [2019-12-07 17:56:40,377 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:40,378 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:40,378 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:40,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:40,378 INFO L87 Difference]: Start difference. First operand 51486 states and 65112 transitions. Second operand 3 states. [2019-12-07 17:56:41,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:41,887 INFO L93 Difference]: Finished difference Result 125690 states and 158770 transitions. [2019-12-07 17:56:41,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:41,888 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-12-07 17:56:41,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:41,949 INFO L225 Difference]: With dead ends: 125690 [2019-12-07 17:56:41,949 INFO L226 Difference]: Without dead ends: 74288 [2019-12-07 17:56:41,976 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:42,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74288 states. [2019-12-07 17:56:43,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74288 to 73998. [2019-12-07 17:56:43,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73998 states. [2019-12-07 17:56:43,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73998 states to 73998 states and 92936 transitions. [2019-12-07 17:56:43,791 INFO L78 Accepts]: Start accepts. Automaton has 73998 states and 92936 transitions. Word has length 131 [2019-12-07 17:56:43,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:43,791 INFO L462 AbstractCegarLoop]: Abstraction has 73998 states and 92936 transitions. [2019-12-07 17:56:43,791 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:43,791 INFO L276 IsEmpty]: Start isEmpty. Operand 73998 states and 92936 transitions. [2019-12-07 17:56:43,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 17:56:43,814 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:43,815 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:43,815 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:43,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:43,815 INFO L82 PathProgramCache]: Analyzing trace with hash 216677618, now seen corresponding path program 1 times [2019-12-07 17:56:43,815 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:43,815 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379016385] [2019-12-07 17:56:43,815 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:43,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:43,854 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 17:56:43,855 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379016385] [2019-12-07 17:56:43,855 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:43,855 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:56:43,855 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167560613] [2019-12-07 17:56:43,855 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:56:43,856 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:43,856 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:56:43,856 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:56:43,856 INFO L87 Difference]: Start difference. First operand 73998 states and 92936 transitions. Second operand 5 states. [2019-12-07 17:56:46,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:46,290 INFO L93 Difference]: Finished difference Result 179776 states and 227199 transitions. [2019-12-07 17:56:46,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:56:46,291 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 131 [2019-12-07 17:56:46,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:46,394 INFO L225 Difference]: With dead ends: 179776 [2019-12-07 17:56:46,394 INFO L226 Difference]: Without dead ends: 105878 [2019-12-07 17:56:46,434 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:56:46,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105878 states. [2019-12-07 17:56:48,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105878 to 74430. [2019-12-07 17:56:48,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74430 states. [2019-12-07 17:56:48,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74430 states to 74430 states and 92212 transitions. [2019-12-07 17:56:48,753 INFO L78 Accepts]: Start accepts. Automaton has 74430 states and 92212 transitions. Word has length 131 [2019-12-07 17:56:48,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:48,754 INFO L462 AbstractCegarLoop]: Abstraction has 74430 states and 92212 transitions. [2019-12-07 17:56:48,754 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:56:48,754 INFO L276 IsEmpty]: Start isEmpty. Operand 74430 states and 92212 transitions. [2019-12-07 17:56:48,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2019-12-07 17:56:48,770 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:48,771 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:48,771 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:48,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:48,771 INFO L82 PathProgramCache]: Analyzing trace with hash -1889102986, now seen corresponding path program 1 times [2019-12-07 17:56:48,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:48,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484763593] [2019-12-07 17:56:48,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:48,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:48,805 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:56:48,805 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484763593] [2019-12-07 17:56:48,805 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:48,805 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:56:48,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876129464] [2019-12-07 17:56:48,806 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:56:48,806 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:48,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:56:48,806 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:48,806 INFO L87 Difference]: Start difference. First operand 74430 states and 92212 transitions. Second operand 3 states. [2019-12-07 17:56:51,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:51,130 INFO L93 Difference]: Finished difference Result 112028 states and 139157 transitions. [2019-12-07 17:56:51,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:56:51,131 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2019-12-07 17:56:51,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:51,201 INFO L225 Difference]: With dead ends: 112028 [2019-12-07 17:56:51,201 INFO L226 Difference]: Without dead ends: 74430 [2019-12-07 17:56:51,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:56:51,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74430 states. [2019-12-07 17:56:53,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74430 to 74216. [2019-12-07 17:56:53,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74216 states. [2019-12-07 17:56:53,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74216 states to 74216 states and 91134 transitions. [2019-12-07 17:56:53,169 INFO L78 Accepts]: Start accepts. Automaton has 74216 states and 91134 transitions. Word has length 131 [2019-12-07 17:56:53,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:53,170 INFO L462 AbstractCegarLoop]: Abstraction has 74216 states and 91134 transitions. [2019-12-07 17:56:53,170 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:56:53,170 INFO L276 IsEmpty]: Start isEmpty. Operand 74216 states and 91134 transitions. [2019-12-07 17:56:53,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 17:56:53,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:53,186 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:53,186 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:53,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:53,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1177275041, now seen corresponding path program 1 times [2019-12-07 17:56:53,186 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:53,186 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536005038] [2019-12-07 17:56:53,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:53,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:53,238 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-12-07 17:56:53,238 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536005038] [2019-12-07 17:56:53,239 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:53,239 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:56:53,239 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108905581] [2019-12-07 17:56:53,239 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:56:53,239 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:53,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:56:53,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:56:53,239 INFO L87 Difference]: Start difference. First operand 74216 states and 91134 transitions. Second operand 5 states. [2019-12-07 17:56:56,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:56:56,425 INFO L93 Difference]: Finished difference Result 172884 states and 213543 transitions. [2019-12-07 17:56:56,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:56:56,425 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-12-07 17:56:56,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:56:56,521 INFO L225 Difference]: With dead ends: 172884 [2019-12-07 17:56:56,521 INFO L226 Difference]: Without dead ends: 98792 [2019-12-07 17:56:56,564 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:56:56,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98792 states. [2019-12-07 17:56:59,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98792 to 74504. [2019-12-07 17:56:59,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74504 states. [2019-12-07 17:56:59,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74504 states to 74504 states and 90218 transitions. [2019-12-07 17:56:59,169 INFO L78 Accepts]: Start accepts. Automaton has 74504 states and 90218 transitions. Word has length 132 [2019-12-07 17:56:59,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:56:59,169 INFO L462 AbstractCegarLoop]: Abstraction has 74504 states and 90218 transitions. [2019-12-07 17:56:59,169 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:56:59,169 INFO L276 IsEmpty]: Start isEmpty. Operand 74504 states and 90218 transitions. [2019-12-07 17:56:59,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 17:56:59,185 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:56:59,185 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:56:59,185 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:56:59,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:56:59,185 INFO L82 PathProgramCache]: Analyzing trace with hash -1238601315, now seen corresponding path program 1 times [2019-12-07 17:56:59,185 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:56:59,185 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851018187] [2019-12-07 17:56:59,186 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:56:59,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:56:59,237 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-12-07 17:56:59,237 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851018187] [2019-12-07 17:56:59,237 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:56:59,237 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:56:59,238 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650405691] [2019-12-07 17:56:59,238 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:56:59,238 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:56:59,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:56:59,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:56:59,238 INFO L87 Difference]: Start difference. First operand 74504 states and 90218 transitions. Second operand 5 states. [2019-12-07 17:57:02,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:02,982 INFO L93 Difference]: Finished difference Result 176172 states and 214583 transitions. [2019-12-07 17:57:02,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:57:02,983 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-12-07 17:57:02,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:03,081 INFO L225 Difference]: With dead ends: 176172 [2019-12-07 17:57:03,082 INFO L226 Difference]: Without dead ends: 101816 [2019-12-07 17:57:03,120 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:57:03,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101816 states. [2019-12-07 17:57:06,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101816 to 74792. [2019-12-07 17:57:06,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74792 states. [2019-12-07 17:57:06,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74792 states to 74792 states and 89302 transitions. [2019-12-07 17:57:06,179 INFO L78 Accepts]: Start accepts. Automaton has 74792 states and 89302 transitions. Word has length 132 [2019-12-07 17:57:06,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:06,179 INFO L462 AbstractCegarLoop]: Abstraction has 74792 states and 89302 transitions. [2019-12-07 17:57:06,179 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:57:06,179 INFO L276 IsEmpty]: Start isEmpty. Operand 74792 states and 89302 transitions. [2019-12-07 17:57:06,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 17:57:06,194 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:06,194 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:06,195 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:06,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:06,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1048246887, now seen corresponding path program 1 times [2019-12-07 17:57:06,195 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:06,195 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94033265] [2019-12-07 17:57:06,195 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:06,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:06,238 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2019-12-07 17:57:06,239 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94033265] [2019-12-07 17:57:06,239 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:06,239 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:57:06,239 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400473399] [2019-12-07 17:57:06,239 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:57:06,239 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:06,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:57:06,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:57:06,240 INFO L87 Difference]: Start difference. First operand 74792 states and 89302 transitions. Second operand 5 states. [2019-12-07 17:57:09,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:09,954 INFO L93 Difference]: Finished difference Result 144386 states and 173411 transitions. [2019-12-07 17:57:09,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:57:09,954 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 132 [2019-12-07 17:57:09,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:10,020 INFO L225 Difference]: With dead ends: 144386 [2019-12-07 17:57:10,020 INFO L226 Difference]: Without dead ends: 69686 [2019-12-07 17:57:10,053 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:57:10,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69686 states. [2019-12-07 17:57:12,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69686 to 50828. [2019-12-07 17:57:12,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50828 states. [2019-12-07 17:57:12,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50828 states to 50828 states and 59968 transitions. [2019-12-07 17:57:12,432 INFO L78 Accepts]: Start accepts. Automaton has 50828 states and 59968 transitions. Word has length 132 [2019-12-07 17:57:12,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:12,432 INFO L462 AbstractCegarLoop]: Abstraction has 50828 states and 59968 transitions. [2019-12-07 17:57:12,432 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:57:12,432 INFO L276 IsEmpty]: Start isEmpty. Operand 50828 states and 59968 transitions. [2019-12-07 17:57:12,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 17:57:12,441 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:12,441 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:12,441 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:12,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:12,442 INFO L82 PathProgramCache]: Analyzing trace with hash -307341713, now seen corresponding path program 1 times [2019-12-07 17:57:12,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:12,442 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156616434] [2019-12-07 17:57:12,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:12,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:12,465 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:12,465 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156616434] [2019-12-07 17:57:12,466 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:12,466 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:12,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551618858] [2019-12-07 17:57:12,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:12,466 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:12,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:12,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:12,466 INFO L87 Difference]: Start difference. First operand 50828 states and 59968 transitions. Second operand 3 states. [2019-12-07 17:57:14,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:14,285 INFO L93 Difference]: Finished difference Result 81694 states and 96668 transitions. [2019-12-07 17:57:14,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:14,286 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-12-07 17:57:14,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:14,320 INFO L225 Difference]: With dead ends: 81694 [2019-12-07 17:57:14,320 INFO L226 Difference]: Without dead ends: 42420 [2019-12-07 17:57:14,342 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:14,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42420 states. [2019-12-07 17:57:16,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42420 to 42416. [2019-12-07 17:57:16,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42416 states. [2019-12-07 17:57:16,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42416 states to 42416 states and 50000 transitions. [2019-12-07 17:57:16,772 INFO L78 Accepts]: Start accepts. Automaton has 42416 states and 50000 transitions. Word has length 134 [2019-12-07 17:57:16,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:16,773 INFO L462 AbstractCegarLoop]: Abstraction has 42416 states and 50000 transitions. [2019-12-07 17:57:16,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:16,773 INFO L276 IsEmpty]: Start isEmpty. Operand 42416 states and 50000 transitions. [2019-12-07 17:57:16,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2019-12-07 17:57:16,783 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:16,783 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:16,783 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:16,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:16,783 INFO L82 PathProgramCache]: Analyzing trace with hash -451521753, now seen corresponding path program 1 times [2019-12-07 17:57:16,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:16,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632092693] [2019-12-07 17:57:16,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:16,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:16,822 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:16,823 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632092693] [2019-12-07 17:57:16,823 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:16,823 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:16,823 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862760078] [2019-12-07 17:57:16,823 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:16,823 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:16,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:16,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:16,823 INFO L87 Difference]: Start difference. First operand 42416 states and 50000 transitions. Second operand 3 states. [2019-12-07 17:57:18,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:18,292 INFO L93 Difference]: Finished difference Result 69170 states and 81824 transitions. [2019-12-07 17:57:18,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:18,292 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 173 [2019-12-07 17:57:18,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:18,322 INFO L225 Difference]: With dead ends: 69170 [2019-12-07 17:57:18,322 INFO L226 Difference]: Without dead ends: 33872 [2019-12-07 17:57:18,347 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:18,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-12-07 17:57:19,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-12-07 17:57:19,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-12-07 17:57:19,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39884 transitions. [2019-12-07 17:57:19,883 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39884 transitions. Word has length 173 [2019-12-07 17:57:19,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:19,883 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39884 transitions. [2019-12-07 17:57:19,883 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:19,884 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39884 transitions. [2019-12-07 17:57:19,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2019-12-07 17:57:19,893 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:19,893 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:19,893 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:19,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:19,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1942944609, now seen corresponding path program 1 times [2019-12-07 17:57:19,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:19,894 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062720750] [2019-12-07 17:57:19,894 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:19,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:19,929 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:19,929 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062720750] [2019-12-07 17:57:19,929 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:19,929 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:19,929 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221243351] [2019-12-07 17:57:19,930 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:19,930 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:19,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:19,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:19,930 INFO L87 Difference]: Start difference. First operand 33868 states and 39884 transitions. Second operand 3 states. [2019-12-07 17:57:21,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:21,419 INFO L93 Difference]: Finished difference Result 63390 states and 74832 transitions. [2019-12-07 17:57:21,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:21,420 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 212 [2019-12-07 17:57:21,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:21,448 INFO L225 Difference]: With dead ends: 63390 [2019-12-07 17:57:21,448 INFO L226 Difference]: Without dead ends: 33872 [2019-12-07 17:57:21,466 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:21,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33872 states. [2019-12-07 17:57:22,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33872 to 33868. [2019-12-07 17:57:22,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33868 states. [2019-12-07 17:57:22,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33868 states to 33868 states and 39684 transitions. [2019-12-07 17:57:22,969 INFO L78 Accepts]: Start accepts. Automaton has 33868 states and 39684 transitions. Word has length 212 [2019-12-07 17:57:22,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:22,969 INFO L462 AbstractCegarLoop]: Abstraction has 33868 states and 39684 transitions. [2019-12-07 17:57:22,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:22,970 INFO L276 IsEmpty]: Start isEmpty. Operand 33868 states and 39684 transitions. [2019-12-07 17:57:22,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-12-07 17:57:22,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:22,980 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:22,980 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:22,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:22,981 INFO L82 PathProgramCache]: Analyzing trace with hash -980083650, now seen corresponding path program 1 times [2019-12-07 17:57:22,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:22,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089365817] [2019-12-07 17:57:22,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:22,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:23,051 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 17:57:23,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089365817] [2019-12-07 17:57:23,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:23,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:57:23,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308966866] [2019-12-07 17:57:23,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:57:23,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:23,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:57:23,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:57:23,053 INFO L87 Difference]: Start difference. First operand 33868 states and 39684 transitions. Second operand 5 states. [2019-12-07 17:57:26,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:26,456 INFO L93 Difference]: Finished difference Result 107663 states and 125750 transitions. [2019-12-07 17:57:26,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:57:26,457 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 248 [2019-12-07 17:57:26,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:26,518 INFO L225 Difference]: With dead ends: 107663 [2019-12-07 17:57:26,518 INFO L226 Difference]: Without dead ends: 73872 [2019-12-07 17:57:26,545 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:57:26,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73872 states. [2019-12-07 17:57:28,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73872 to 34876. [2019-12-07 17:57:28,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-12-07 17:57:28,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 40450 transitions. [2019-12-07 17:57:28,553 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 40450 transitions. Word has length 248 [2019-12-07 17:57:28,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:28,553 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 40450 transitions. [2019-12-07 17:57:28,553 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:57:28,553 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 40450 transitions. [2019-12-07 17:57:28,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2019-12-07 17:57:28,563 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:28,564 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:28,564 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:28,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:28,564 INFO L82 PathProgramCache]: Analyzing trace with hash -1127279802, now seen corresponding path program 1 times [2019-12-07 17:57:28,564 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:28,564 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410853570] [2019-12-07 17:57:28,564 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:28,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:28,612 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:28,612 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410853570] [2019-12-07 17:57:28,613 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:28,613 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:28,613 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1261981934] [2019-12-07 17:57:28,613 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:28,613 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:28,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:28,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:28,613 INFO L87 Difference]: Start difference. First operand 34876 states and 40450 transitions. Second operand 3 states. [2019-12-07 17:57:30,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:30,432 INFO L93 Difference]: Finished difference Result 62462 states and 72623 transitions. [2019-12-07 17:57:30,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:30,433 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 248 [2019-12-07 17:57:30,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:30,460 INFO L225 Difference]: With dead ends: 62462 [2019-12-07 17:57:30,460 INFO L226 Difference]: Without dead ends: 34940 [2019-12-07 17:57:30,476 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:30,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-12-07 17:57:32,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-12-07 17:57:32,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-12-07 17:57:32,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39858 transitions. [2019-12-07 17:57:32,418 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39858 transitions. Word has length 248 [2019-12-07 17:57:32,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:32,418 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39858 transitions. [2019-12-07 17:57:32,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:32,419 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39858 transitions. [2019-12-07 17:57:32,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2019-12-07 17:57:32,429 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:32,429 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:32,429 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:32,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:32,429 INFO L82 PathProgramCache]: Analyzing trace with hash -301505065, now seen corresponding path program 1 times [2019-12-07 17:57:32,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:32,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173817484] [2019-12-07 17:57:32,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:32,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:32,472 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:32,473 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173817484] [2019-12-07 17:57:32,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:32,473 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:32,473 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489288991] [2019-12-07 17:57:32,473 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:32,473 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:32,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:32,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:32,474 INFO L87 Difference]: Start difference. First operand 34876 states and 39858 transitions. Second operand 3 states. [2019-12-07 17:57:34,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:34,365 INFO L93 Difference]: Finished difference Result 59234 states and 67843 transitions. [2019-12-07 17:57:34,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:34,366 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 251 [2019-12-07 17:57:34,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:34,391 INFO L225 Difference]: With dead ends: 59234 [2019-12-07 17:57:34,391 INFO L226 Difference]: Without dead ends: 34940 [2019-12-07 17:57:34,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:34,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34940 states. [2019-12-07 17:57:36,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34940 to 34876. [2019-12-07 17:57:36,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2019-12-07 17:57:36,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39354 transitions. [2019-12-07 17:57:36,305 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39354 transitions. Word has length 251 [2019-12-07 17:57:36,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:36,306 INFO L462 AbstractCegarLoop]: Abstraction has 34876 states and 39354 transitions. [2019-12-07 17:57:36,306 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:36,306 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39354 transitions. [2019-12-07 17:57:36,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2019-12-07 17:57:36,316 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:36,316 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:36,317 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:36,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:36,317 INFO L82 PathProgramCache]: Analyzing trace with hash 391416485, now seen corresponding path program 1 times [2019-12-07 17:57:36,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:36,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448068585] [2019-12-07 17:57:36,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:36,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:36,374 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 17:57:36,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448068585] [2019-12-07 17:57:36,374 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:36,374 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:36,374 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65797523] [2019-12-07 17:57:36,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:36,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:36,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:36,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:36,375 INFO L87 Difference]: Start difference. First operand 34876 states and 39354 transitions. Second operand 3 states. [2019-12-07 17:57:37,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:37,925 INFO L93 Difference]: Finished difference Result 62718 states and 70361 transitions. [2019-12-07 17:57:37,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:37,925 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 254 [2019-12-07 17:57:37,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:37,938 INFO L225 Difference]: With dead ends: 62718 [2019-12-07 17:57:37,938 INFO L226 Difference]: Without dead ends: 16774 [2019-12-07 17:57:37,956 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:37,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16774 states. [2019-12-07 17:57:38,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16774 to 16254. [2019-12-07 17:57:38,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-12-07 17:57:38,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17772 transitions. [2019-12-07 17:57:38,889 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17772 transitions. Word has length 254 [2019-12-07 17:57:38,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:38,890 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17772 transitions. [2019-12-07 17:57:38,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:38,890 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17772 transitions. [2019-12-07 17:57:38,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 258 [2019-12-07 17:57:38,898 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:38,898 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:38,898 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:38,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:38,898 INFO L82 PathProgramCache]: Analyzing trace with hash -1392087481, now seen corresponding path program 1 times [2019-12-07 17:57:38,899 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:38,899 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308581200] [2019-12-07 17:57:38,899 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:38,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:57:38,950 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:57:38,951 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308581200] [2019-12-07 17:57:38,951 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:57:38,951 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:57:38,951 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654950164] [2019-12-07 17:57:38,951 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:57:38,951 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:57:38,951 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:57:38,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:38,952 INFO L87 Difference]: Start difference. First operand 16254 states and 17772 transitions. Second operand 3 states. [2019-12-07 17:57:39,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:57:39,841 INFO L93 Difference]: Finished difference Result 28760 states and 31491 transitions. [2019-12-07 17:57:39,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:57:39,841 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 257 [2019-12-07 17:57:39,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:57:39,852 INFO L225 Difference]: With dead ends: 28760 [2019-12-07 17:57:39,853 INFO L226 Difference]: Without dead ends: 16254 [2019-12-07 17:57:39,860 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:57:39,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16254 states. [2019-12-07 17:57:40,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16254 to 16254. [2019-12-07 17:57:40,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2019-12-07 17:57:40,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17606 transitions. [2019-12-07 17:57:40,762 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17606 transitions. Word has length 257 [2019-12-07 17:57:40,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:57:40,762 INFO L462 AbstractCegarLoop]: Abstraction has 16254 states and 17606 transitions. [2019-12-07 17:57:40,762 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:57:40,762 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17606 transitions. [2019-12-07 17:57:40,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2019-12-07 17:57:40,770 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:57:40,770 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:57:40,770 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:57:40,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:57:40,770 INFO L82 PathProgramCache]: Analyzing trace with hash 1978087514, now seen corresponding path program 1 times [2019-12-07 17:57:40,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:57:40,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136387425] [2019-12-07 17:57:40,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:57:40,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:57:40,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:57:40,877 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:57:40,877 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:57:41,023 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:57:41 BoogieIcfgContainer [2019-12-07 17:57:41,023 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:57:41,023 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:57:41,023 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:57:41,024 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:57:41,024 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:56:31" (3/4) ... [2019-12-07 17:57:41,025 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:57:41,137 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_55ea7f94-4007-4fce-b812-a0b285804952/bin/uautomizer/witness.graphml [2019-12-07 17:57:41,137 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:57:41,139 INFO L168 Benchmark]: Toolchain (without parser) took 70564.64 ms. Allocated memory was 1.0 GB in the beginning and 5.8 GB in the end (delta: 4.7 GB). Free memory was 944.7 MB in the beginning and 2.1 GB in the end (delta: -1.2 GB). Peak memory consumption was 3.6 GB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,139 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:57:41,140 INFO L168 Benchmark]: CACSL2BoogieTranslator took 251.87 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -146.5 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,140 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,140 INFO L168 Benchmark]: Boogie Preprocessor took 38.10 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,141 INFO L168 Benchmark]: RCFGBuilder took 595.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 986.9 MB in the end (delta: 93.6 MB). Peak memory consumption was 93.6 MB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,141 INFO L168 Benchmark]: TraceAbstraction took 69521.90 ms. Allocated memory was 1.1 GB in the beginning and 5.8 GB in the end (delta: 4.6 GB). Free memory was 986.9 MB in the beginning and 2.1 GB in the end (delta: -1.2 GB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,142 INFO L168 Benchmark]: Witness Printer took 113.81 ms. Allocated memory is still 5.8 GB. Free memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 24.9 MB). Peak memory consumption was 24.9 MB. Max. memory is 11.5 GB. [2019-12-07 17:57:41,143 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 251.87 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -146.5 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 40.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.10 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 595.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 986.9 MB in the end (delta: 93.6 MB). Peak memory consumption was 93.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 69521.90 ms. Allocated memory was 1.1 GB in the beginning and 5.8 GB in the end (delta: 4.6 GB). Free memory was 986.9 MB in the beginning and 2.1 GB in the end (delta: -1.2 GB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. * Witness Printer took 113.81 ms. Allocated memory is still 5.8 GB. Free memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 24.9 MB). Peak memory consumption was 24.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L331] COND TRUE m_i == 1 [L332] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L492] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L497] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L502] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L545] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L550] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L555] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L769] kernel_st = 1 [L397] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] t4_pc = 1 [L209] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L401] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L63] E_1 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] m_pc = 1 [L71] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L109] E_2 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L144] E_3 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L179] E_4 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L181] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 374 locations, 1 error locations. Result: UNSAFE, OverallTime: 69.3s, OverallIterations: 35, TraceHistogramMax: 2, AutomataDifference: 36.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 19229 SDtfs, 17991 SDslu, 12915 SDs, 0 SdLazy, 695 SolverSat, 359 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 113 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=74792occurred in iteration=25, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 31.1s AutomataMinimizationTime, 34 MinimizatonAttempts, 142630 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.5s InterpolantComputationTime, 4440 NumberOfCodeBlocks, 4440 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 4146 ConstructedInterpolants, 0 QuantifiedInterpolants, 888600 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 34 InterpolantComputations, 34 PerfectInterpolantSequences, 352/352 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...