./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 11:18:40,383 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 11:18:40,385 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 11:18:40,392 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 11:18:40,392 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 11:18:40,393 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 11:18:40,394 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 11:18:40,395 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 11:18:40,397 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 11:18:40,397 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 11:18:40,398 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 11:18:40,399 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 11:18:40,399 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 11:18:40,400 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 11:18:40,400 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 11:18:40,401 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 11:18:40,402 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 11:18:40,402 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 11:18:40,404 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 11:18:40,405 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 11:18:40,406 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 11:18:40,407 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 11:18:40,408 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 11:18:40,408 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 11:18:40,410 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 11:18:40,410 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 11:18:40,410 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 11:18:40,411 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 11:18:40,411 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 11:18:40,411 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 11:18:40,412 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 11:18:40,412 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 11:18:40,412 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 11:18:40,413 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 11:18:40,413 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 11:18:40,414 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 11:18:40,414 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 11:18:40,414 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 11:18:40,414 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 11:18:40,415 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 11:18:40,415 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 11:18:40,416 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 11:18:40,425 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 11:18:40,425 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 11:18:40,426 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 11:18:40,426 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 11:18:40,427 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 11:18:40,427 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 11:18:40,428 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 11:18:40,428 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:18:40,429 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 11:18:40,429 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 11:18:40,430 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 11:18:40,430 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 11:18:40,430 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 11:18:40,430 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 11:18:40,430 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a [2019-12-07 11:18:40,528 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 11:18:40,535 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 11:18:40,538 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 11:18:40,539 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 11:18:40,539 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 11:18:40,539 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2019-12-07 11:18:40,576 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/data/e36b00bfb/ebea6b4837a0497da4fa1a293806ea4e/FLAG83897c096 [2019-12-07 11:18:40,950 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 11:18:40,950 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/sv-benchmarks/c/systemc/transmitter.05.cil.c [2019-12-07 11:18:40,958 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/data/e36b00bfb/ebea6b4837a0497da4fa1a293806ea4e/FLAG83897c096 [2019-12-07 11:18:40,967 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/data/e36b00bfb/ebea6b4837a0497da4fa1a293806ea4e [2019-12-07 11:18:40,969 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 11:18:40,970 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 11:18:40,970 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 11:18:40,970 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 11:18:40,973 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 11:18:40,973 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:18:40" (1/1) ... [2019-12-07 11:18:40,975 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e3d67c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:40, skipping insertion in model container [2019-12-07 11:18:40,975 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:18:40" (1/1) ... [2019-12-07 11:18:40,981 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 11:18:41,012 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 11:18:41,199 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:18:41,203 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 11:18:41,236 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:18:41,249 INFO L208 MainTranslator]: Completed translation [2019-12-07 11:18:41,249 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41 WrapperNode [2019-12-07 11:18:41,250 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 11:18:41,250 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 11:18:41,250 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 11:18:41,250 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 11:18:41,255 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,262 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,297 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 11:18:41,297 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 11:18:41,297 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 11:18:41,297 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 11:18:41,304 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,304 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,307 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,307 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,319 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,331 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,333 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... [2019-12-07 11:18:41,337 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 11:18:41,338 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 11:18:41,338 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 11:18:41,338 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 11:18:41,339 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:18:41,380 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 11:18:41,380 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 11:18:42,025 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 11:18:42,025 INFO L287 CfgBuilder]: Removed 181 assume(true) statements. [2019-12-07 11:18:42,026 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:18:42 BoogieIcfgContainer [2019-12-07 11:18:42,026 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 11:18:42,027 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 11:18:42,027 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 11:18:42,029 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 11:18:42,029 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 11:18:40" (1/3) ... [2019-12-07 11:18:42,029 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2c03c5a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:18:42, skipping insertion in model container [2019-12-07 11:18:42,030 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:18:41" (2/3) ... [2019-12-07 11:18:42,030 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2c03c5a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:18:42, skipping insertion in model container [2019-12-07 11:18:42,030 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:18:42" (3/3) ... [2019-12-07 11:18:42,031 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.05.cil.c [2019-12-07 11:18:42,037 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 11:18:42,042 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 11:18:42,050 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-12-07 11:18:42,068 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 11:18:42,069 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 11:18:42,069 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 11:18:42,069 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 11:18:42,069 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 11:18:42,069 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 11:18:42,069 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 11:18:42,069 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 11:18:42,086 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states. [2019-12-07 11:18:42,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,093 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,094 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,094 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,098 INFO L82 PathProgramCache]: Analyzing trace with hash 1912114834, now seen corresponding path program 1 times [2019-12-07 11:18:42,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451239212] [2019-12-07 11:18:42,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451239212] [2019-12-07 11:18:42,225 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,225 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:42,226 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837609921] [2019-12-07 11:18:42,229 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,229 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,239 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2019-12-07 11:18:42,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,293 INFO L93 Difference]: Finished difference Result 967 states and 1501 transitions. [2019-12-07 11:18:42,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,294 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,305 INFO L225 Difference]: With dead ends: 967 [2019-12-07 11:18:42,305 INFO L226 Difference]: Without dead ends: 482 [2019-12-07 11:18:42,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states. [2019-12-07 11:18:42,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 482. [2019-12-07 11:18:42,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 482 states. [2019-12-07 11:18:42,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 482 states and 730 transitions. [2019-12-07 11:18:42,355 INFO L78 Accepts]: Start accepts. Automaton has 482 states and 730 transitions. Word has length 85 [2019-12-07 11:18:42,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,356 INFO L462 AbstractCegarLoop]: Abstraction has 482 states and 730 transitions. [2019-12-07 11:18:42,356 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,356 INFO L276 IsEmpty]: Start isEmpty. Operand 482 states and 730 transitions. [2019-12-07 11:18:42,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,358 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,358 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,359 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,359 INFO L82 PathProgramCache]: Analyzing trace with hash -1325014384, now seen corresponding path program 1 times [2019-12-07 11:18:42,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046767042] [2019-12-07 11:18:42,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,405 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046767042] [2019-12-07 11:18:42,405 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,405 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:42,406 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576704949] [2019-12-07 11:18:42,407 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,407 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,407 INFO L87 Difference]: Start difference. First operand 482 states and 730 transitions. Second operand 3 states. [2019-12-07 11:18:42,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,483 INFO L93 Difference]: Finished difference Result 1320 states and 1994 transitions. [2019-12-07 11:18:42,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,484 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,489 INFO L225 Difference]: With dead ends: 1320 [2019-12-07 11:18:42,490 INFO L226 Difference]: Without dead ends: 848 [2019-12-07 11:18:42,491 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 848 states. [2019-12-07 11:18:42,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 848 to 846. [2019-12-07 11:18:42,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:42,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1268 transitions. [2019-12-07 11:18:42,530 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1268 transitions. Word has length 85 [2019-12-07 11:18:42,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,530 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1268 transitions. [2019-12-07 11:18:42,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,530 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1268 transitions. [2019-12-07 11:18:42,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,532 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,533 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,533 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,533 INFO L82 PathProgramCache]: Analyzing trace with hash -1311229201, now seen corresponding path program 1 times [2019-12-07 11:18:42,534 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,534 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418394024] [2019-12-07 11:18:42,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,583 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418394024] [2019-12-07 11:18:42,583 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,583 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:42,584 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415675589] [2019-12-07 11:18:42,584 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,585 INFO L87 Difference]: Start difference. First operand 846 states and 1268 transitions. Second operand 3 states. [2019-12-07 11:18:42,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,627 INFO L93 Difference]: Finished difference Result 1681 states and 2519 transitions. [2019-12-07 11:18:42,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,633 INFO L225 Difference]: With dead ends: 1681 [2019-12-07 11:18:42,633 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:42,635 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:42,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:42,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:42,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1260 transitions. [2019-12-07 11:18:42,669 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1260 transitions. Word has length 85 [2019-12-07 11:18:42,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,669 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1260 transitions. [2019-12-07 11:18:42,669 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,670 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1260 transitions. [2019-12-07 11:18:42,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,671 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,671 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,672 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,672 INFO L82 PathProgramCache]: Analyzing trace with hash -86597841, now seen corresponding path program 1 times [2019-12-07 11:18:42,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,673 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741921501] [2019-12-07 11:18:42,673 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,715 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741921501] [2019-12-07 11:18:42,715 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,715 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:42,716 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066625574] [2019-12-07 11:18:42,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,716 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,717 INFO L87 Difference]: Start difference. First operand 846 states and 1260 transitions. Second operand 3 states. [2019-12-07 11:18:42,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,758 INFO L93 Difference]: Finished difference Result 1680 states and 2502 transitions. [2019-12-07 11:18:42,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,758 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,762 INFO L225 Difference]: With dead ends: 1680 [2019-12-07 11:18:42,762 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:42,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:42,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:42,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:42,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1252 transitions. [2019-12-07 11:18:42,783 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1252 transitions. Word has length 85 [2019-12-07 11:18:42,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,783 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1252 transitions. [2019-12-07 11:18:42,784 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,784 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1252 transitions. [2019-12-07 11:18:42,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,784 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,784 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,785 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1571114257, now seen corresponding path program 1 times [2019-12-07 11:18:42,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848901150] [2019-12-07 11:18:42,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,812 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848901150] [2019-12-07 11:18:42,812 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,812 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:42,812 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822502284] [2019-12-07 11:18:42,812 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,813 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,813 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,813 INFO L87 Difference]: Start difference. First operand 846 states and 1252 transitions. Second operand 3 states. [2019-12-07 11:18:42,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,840 INFO L93 Difference]: Finished difference Result 1678 states and 2483 transitions. [2019-12-07 11:18:42,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,840 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,844 INFO L225 Difference]: With dead ends: 1678 [2019-12-07 11:18:42,844 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:42,845 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:42,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:42,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:42,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1244 transitions. [2019-12-07 11:18:42,865 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1244 transitions. Word has length 85 [2019-12-07 11:18:42,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,865 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1244 transitions. [2019-12-07 11:18:42,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,866 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1244 transitions. [2019-12-07 11:18:42,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,866 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,866 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,866 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1353664849, now seen corresponding path program 1 times [2019-12-07 11:18:42,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,867 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840147179] [2019-12-07 11:18:42,867 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:42,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840147179] [2019-12-07 11:18:42,895 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:42,895 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:42,895 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167014373] [2019-12-07 11:18:42,896 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:42,896 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:42,896 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:42,896 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,896 INFO L87 Difference]: Start difference. First operand 846 states and 1244 transitions. Second operand 3 states. [2019-12-07 11:18:42,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:42,931 INFO L93 Difference]: Finished difference Result 1677 states and 2466 transitions. [2019-12-07 11:18:42,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:42,931 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:42,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:42,936 INFO L225 Difference]: With dead ends: 1677 [2019-12-07 11:18:42,936 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:42,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:42,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:42,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:42,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:42,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1236 transitions. [2019-12-07 11:18:42,967 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1236 transitions. Word has length 85 [2019-12-07 11:18:42,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:42,967 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1236 transitions. [2019-12-07 11:18:42,967 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:42,967 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1236 transitions. [2019-12-07 11:18:42,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:42,968 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:42,968 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:42,968 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:42,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:42,969 INFO L82 PathProgramCache]: Analyzing trace with hash 1839938287, now seen corresponding path program 1 times [2019-12-07 11:18:42,969 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:42,969 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481957639] [2019-12-07 11:18:42,969 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:42,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:42,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,000 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481957639] [2019-12-07 11:18:43,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,000 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462919189] [2019-12-07 11:18:43,000 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,000 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,001 INFO L87 Difference]: Start difference. First operand 846 states and 1236 transitions. Second operand 3 states. [2019-12-07 11:18:43,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,045 INFO L93 Difference]: Finished difference Result 1676 states and 2449 transitions. [2019-12-07 11:18:43,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,045 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,050 INFO L225 Difference]: With dead ends: 1676 [2019-12-07 11:18:43,050 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1216 transitions. [2019-12-07 11:18:43,082 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1216 transitions. Word has length 85 [2019-12-07 11:18:43,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,082 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1216 transitions. [2019-12-07 11:18:43,083 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,083 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1216 transitions. [2019-12-07 11:18:43,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,083 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,084 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,084 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,084 INFO L82 PathProgramCache]: Analyzing trace with hash -1688218612, now seen corresponding path program 1 times [2019-12-07 11:18:43,084 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,084 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364477780] [2019-12-07 11:18:43,084 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,110 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364477780] [2019-12-07 11:18:43,110 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,110 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,110 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868144931] [2019-12-07 11:18:43,111 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,111 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,111 INFO L87 Difference]: Start difference. First operand 846 states and 1216 transitions. Second operand 3 states. [2019-12-07 11:18:43,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,155 INFO L93 Difference]: Finished difference Result 1675 states and 2408 transitions. [2019-12-07 11:18:43,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,155 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,158 INFO L225 Difference]: With dead ends: 1675 [2019-12-07 11:18:43,158 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,160 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1196 transitions. [2019-12-07 11:18:43,181 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1196 transitions. Word has length 85 [2019-12-07 11:18:43,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,182 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1196 transitions. [2019-12-07 11:18:43,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,182 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1196 transitions. [2019-12-07 11:18:43,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,182 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,183 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,183 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,183 INFO L82 PathProgramCache]: Analyzing trace with hash -1961990068, now seen corresponding path program 1 times [2019-12-07 11:18:43,183 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,183 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835545123] [2019-12-07 11:18:43,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835545123] [2019-12-07 11:18:43,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,200 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,200 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546131573] [2019-12-07 11:18:43,200 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,201 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,201 INFO L87 Difference]: Start difference. First operand 846 states and 1196 transitions. Second operand 3 states. [2019-12-07 11:18:43,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,243 INFO L93 Difference]: Finished difference Result 1674 states and 2367 transitions. [2019-12-07 11:18:43,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,243 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,246 INFO L225 Difference]: With dead ends: 1674 [2019-12-07 11:18:43,247 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,248 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1176 transitions. [2019-12-07 11:18:43,271 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1176 transitions. Word has length 85 [2019-12-07 11:18:43,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,271 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1176 transitions. [2019-12-07 11:18:43,271 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,272 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1176 transitions. [2019-12-07 11:18:43,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,272 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,273 INFO L82 PathProgramCache]: Analyzing trace with hash -1893352853, now seen corresponding path program 1 times [2019-12-07 11:18:43,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633149941] [2019-12-07 11:18:43,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,289 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633149941] [2019-12-07 11:18:43,289 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,289 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,289 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330165939] [2019-12-07 11:18:43,289 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,290 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,290 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,290 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,290 INFO L87 Difference]: Start difference. First operand 846 states and 1176 transitions. Second operand 3 states. [2019-12-07 11:18:43,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,341 INFO L93 Difference]: Finished difference Result 1673 states and 2326 transitions. [2019-12-07 11:18:43,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,341 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,344 INFO L225 Difference]: With dead ends: 1673 [2019-12-07 11:18:43,345 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,346 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1156 transitions. [2019-12-07 11:18:43,369 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1156 transitions. Word has length 85 [2019-12-07 11:18:43,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,369 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1156 transitions. [2019-12-07 11:18:43,369 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,369 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1156 transitions. [2019-12-07 11:18:43,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,370 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,370 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,370 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,370 INFO L82 PathProgramCache]: Analyzing trace with hash 367812267, now seen corresponding path program 1 times [2019-12-07 11:18:43,370 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,370 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132180562] [2019-12-07 11:18:43,370 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,386 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132180562] [2019-12-07 11:18:43,386 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,386 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,386 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882859916] [2019-12-07 11:18:43,387 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,387 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,387 INFO L87 Difference]: Start difference. First operand 846 states and 1156 transitions. Second operand 3 states. [2019-12-07 11:18:43,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,434 INFO L93 Difference]: Finished difference Result 1672 states and 2285 transitions. [2019-12-07 11:18:43,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,435 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,439 INFO L225 Difference]: With dead ends: 1672 [2019-12-07 11:18:43,439 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,441 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1136 transitions. [2019-12-07 11:18:43,474 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1136 transitions. Word has length 85 [2019-12-07 11:18:43,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,474 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1136 transitions. [2019-12-07 11:18:43,474 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,474 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1136 transitions. [2019-12-07 11:18:43,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,474 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,475 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,475 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,475 INFO L82 PathProgramCache]: Analyzing trace with hash 613218122, now seen corresponding path program 1 times [2019-12-07 11:18:43,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,475 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230987405] [2019-12-07 11:18:43,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230987405] [2019-12-07 11:18:43,503 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,503 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:43,503 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373378044] [2019-12-07 11:18:43,503 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,503 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,504 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,504 INFO L87 Difference]: Start difference. First operand 846 states and 1136 transitions. Second operand 3 states. [2019-12-07 11:18:43,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,539 INFO L93 Difference]: Finished difference Result 1679 states and 2253 transitions. [2019-12-07 11:18:43,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,539 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,542 INFO L225 Difference]: With dead ends: 1679 [2019-12-07 11:18:43,542 INFO L226 Difference]: Without dead ends: 846 [2019-12-07 11:18:43,544 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2019-12-07 11:18:43,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 846. [2019-12-07 11:18:43,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 846 states. [2019-12-07 11:18:43,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 846 states to 846 states and 1128 transitions. [2019-12-07 11:18:43,568 INFO L78 Accepts]: Start accepts. Automaton has 846 states and 1128 transitions. Word has length 85 [2019-12-07 11:18:43,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,568 INFO L462 AbstractCegarLoop]: Abstraction has 846 states and 1128 transitions. [2019-12-07 11:18:43,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,568 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1128 transitions. [2019-12-07 11:18:43,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:18:43,569 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,569 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,569 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,569 INFO L82 PathProgramCache]: Analyzing trace with hash 675257736, now seen corresponding path program 1 times [2019-12-07 11:18:43,569 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,570 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225172177] [2019-12-07 11:18:43,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,592 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225172177] [2019-12-07 11:18:43,592 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,592 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:43,592 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243353625] [2019-12-07 11:18:43,592 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,593 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,593 INFO L87 Difference]: Start difference. First operand 846 states and 1128 transitions. Second operand 3 states. [2019-12-07 11:18:43,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,663 INFO L93 Difference]: Finished difference Result 2409 states and 3196 transitions. [2019-12-07 11:18:43,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,663 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:18:43,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,669 INFO L225 Difference]: With dead ends: 2409 [2019-12-07 11:18:43,669 INFO L226 Difference]: Without dead ends: 1636 [2019-12-07 11:18:43,671 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1636 states. [2019-12-07 11:18:43,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1636 to 1558. [2019-12-07 11:18:43,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1558 states. [2019-12-07 11:18:43,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 1558 states and 2051 transitions. [2019-12-07 11:18:43,716 INFO L78 Accepts]: Start accepts. Automaton has 1558 states and 2051 transitions. Word has length 85 [2019-12-07 11:18:43,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,716 INFO L462 AbstractCegarLoop]: Abstraction has 1558 states and 2051 transitions. [2019-12-07 11:18:43,716 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,716 INFO L276 IsEmpty]: Start isEmpty. Operand 1558 states and 2051 transitions. [2019-12-07 11:18:43,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-12-07 11:18:43,717 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,717 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,717 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1992098123, now seen corresponding path program 1 times [2019-12-07 11:18:43,718 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,718 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554796857] [2019-12-07 11:18:43,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,740 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554796857] [2019-12-07 11:18:43,740 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,740 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:43,740 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065161071] [2019-12-07 11:18:43,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,740 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,741 INFO L87 Difference]: Start difference. First operand 1558 states and 2051 transitions. Second operand 3 states. [2019-12-07 11:18:43,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:43,843 INFO L93 Difference]: Finished difference Result 4298 states and 5657 transitions. [2019-12-07 11:18:43,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:43,844 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-12-07 11:18:43,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:43,854 INFO L225 Difference]: With dead ends: 4298 [2019-12-07 11:18:43,854 INFO L226 Difference]: Without dead ends: 2882 [2019-12-07 11:18:43,857 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2882 states. [2019-12-07 11:18:43,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2882 to 2756. [2019-12-07 11:18:43,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2756 states. [2019-12-07 11:18:43,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2756 states to 2756 states and 3610 transitions. [2019-12-07 11:18:43,957 INFO L78 Accepts]: Start accepts. Automaton has 2756 states and 3610 transitions. Word has length 86 [2019-12-07 11:18:43,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:43,957 INFO L462 AbstractCegarLoop]: Abstraction has 2756 states and 3610 transitions. [2019-12-07 11:18:43,957 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:43,957 INFO L276 IsEmpty]: Start isEmpty. Operand 2756 states and 3610 transitions. [2019-12-07 11:18:43,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-12-07 11:18:43,958 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:43,958 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:43,958 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:43,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:43,958 INFO L82 PathProgramCache]: Analyzing trace with hash -1848388678, now seen corresponding path program 1 times [2019-12-07 11:18:43,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:43,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519397118] [2019-12-07 11:18:43,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:43,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:43,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:43,985 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519397118] [2019-12-07 11:18:43,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:43,985 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:43,985 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524472355] [2019-12-07 11:18:43,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:43,986 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:43,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:43,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:43,986 INFO L87 Difference]: Start difference. First operand 2756 states and 3610 transitions. Second operand 3 states. [2019-12-07 11:18:44,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:44,138 INFO L93 Difference]: Finished difference Result 7908 states and 10340 transitions. [2019-12-07 11:18:44,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:44,139 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-12-07 11:18:44,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:44,157 INFO L225 Difference]: With dead ends: 7908 [2019-12-07 11:18:44,157 INFO L226 Difference]: Without dead ends: 5294 [2019-12-07 11:18:44,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:44,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5294 states. [2019-12-07 11:18:44,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5294 to 5100. [2019-12-07 11:18:44,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5100 states. [2019-12-07 11:18:44,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5100 states to 5100 states and 6642 transitions. [2019-12-07 11:18:44,296 INFO L78 Accepts]: Start accepts. Automaton has 5100 states and 6642 transitions. Word has length 87 [2019-12-07 11:18:44,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:44,296 INFO L462 AbstractCegarLoop]: Abstraction has 5100 states and 6642 transitions. [2019-12-07 11:18:44,296 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:44,296 INFO L276 IsEmpty]: Start isEmpty. Operand 5100 states and 6642 transitions. [2019-12-07 11:18:44,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-12-07 11:18:44,297 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:44,297 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:44,297 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:44,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:44,298 INFO L82 PathProgramCache]: Analyzing trace with hash -281630728, now seen corresponding path program 1 times [2019-12-07 11:18:44,298 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:44,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353846923] [2019-12-07 11:18:44,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:44,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:44,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:44,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353846923] [2019-12-07 11:18:44,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:44,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:44,310 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684097912] [2019-12-07 11:18:44,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:44,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:44,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:44,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:44,311 INFO L87 Difference]: Start difference. First operand 5100 states and 6642 transitions. Second operand 3 states. [2019-12-07 11:18:44,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:44,439 INFO L93 Difference]: Finished difference Result 9988 states and 13021 transitions. [2019-12-07 11:18:44,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:44,439 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-12-07 11:18:44,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:44,456 INFO L225 Difference]: With dead ends: 9988 [2019-12-07 11:18:44,456 INFO L226 Difference]: Without dead ends: 4966 [2019-12-07 11:18:44,461 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:44,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4966 states. [2019-12-07 11:18:44,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4966 to 4966. [2019-12-07 11:18:44,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4966 states. [2019-12-07 11:18:44,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4966 states to 4966 states and 6476 transitions. [2019-12-07 11:18:44,587 INFO L78 Accepts]: Start accepts. Automaton has 4966 states and 6476 transitions. Word has length 87 [2019-12-07 11:18:44,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:44,588 INFO L462 AbstractCegarLoop]: Abstraction has 4966 states and 6476 transitions. [2019-12-07 11:18:44,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:44,588 INFO L276 IsEmpty]: Start isEmpty. Operand 4966 states and 6476 transitions. [2019-12-07 11:18:44,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-12-07 11:18:44,589 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:44,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:44,589 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:44,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:44,589 INFO L82 PathProgramCache]: Analyzing trace with hash 1875736048, now seen corresponding path program 1 times [2019-12-07 11:18:44,589 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:44,589 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103104554] [2019-12-07 11:18:44,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:44,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:44,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:44,612 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103104554] [2019-12-07 11:18:44,612 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:44,612 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:44,612 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991461439] [2019-12-07 11:18:44,612 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:44,613 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:44,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:44,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:44,613 INFO L87 Difference]: Start difference. First operand 4966 states and 6476 transitions. Second operand 3 states. [2019-12-07 11:18:44,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:44,861 INFO L93 Difference]: Finished difference Result 14238 states and 18538 transitions. [2019-12-07 11:18:44,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:44,862 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-12-07 11:18:44,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:44,885 INFO L225 Difference]: With dead ends: 14238 [2019-12-07 11:18:44,885 INFO L226 Difference]: Without dead ends: 9414 [2019-12-07 11:18:44,892 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:44,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9414 states. [2019-12-07 11:18:45,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9414 to 9140. [2019-12-07 11:18:45,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9140 states. [2019-12-07 11:18:45,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9140 states to 9140 states and 11860 transitions. [2019-12-07 11:18:45,149 INFO L78 Accepts]: Start accepts. Automaton has 9140 states and 11860 transitions. Word has length 88 [2019-12-07 11:18:45,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:45,149 INFO L462 AbstractCegarLoop]: Abstraction has 9140 states and 11860 transitions. [2019-12-07 11:18:45,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:45,150 INFO L276 IsEmpty]: Start isEmpty. Operand 9140 states and 11860 transitions. [2019-12-07 11:18:45,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-12-07 11:18:45,151 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:45,151 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:45,151 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:45,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:45,152 INFO L82 PathProgramCache]: Analyzing trace with hash 41013040, now seen corresponding path program 1 times [2019-12-07 11:18:45,152 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:45,152 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846955603] [2019-12-07 11:18:45,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:45,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:45,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:45,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846955603] [2019-12-07 11:18:45,165 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:45,165 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:45,165 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110678829] [2019-12-07 11:18:45,165 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:45,165 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:45,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:45,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:45,166 INFO L87 Difference]: Start difference. First operand 9140 states and 11860 transitions. Second operand 3 states. [2019-12-07 11:18:45,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:45,338 INFO L93 Difference]: Finished difference Result 18056 states and 23445 transitions. [2019-12-07 11:18:45,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:45,338 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-12-07 11:18:45,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:45,350 INFO L225 Difference]: With dead ends: 18056 [2019-12-07 11:18:45,350 INFO L226 Difference]: Without dead ends: 9008 [2019-12-07 11:18:45,359 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:45,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9008 states. [2019-12-07 11:18:45,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9008 to 9008. [2019-12-07 11:18:45,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9008 states. [2019-12-07 11:18:45,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9008 states to 9008 states and 11698 transitions. [2019-12-07 11:18:45,580 INFO L78 Accepts]: Start accepts. Automaton has 9008 states and 11698 transitions. Word has length 88 [2019-12-07 11:18:45,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:45,580 INFO L462 AbstractCegarLoop]: Abstraction has 9008 states and 11698 transitions. [2019-12-07 11:18:45,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:45,580 INFO L276 IsEmpty]: Start isEmpty. Operand 9008 states and 11698 transitions. [2019-12-07 11:18:45,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-12-07 11:18:45,581 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:45,581 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:45,582 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:45,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:45,582 INFO L82 PathProgramCache]: Analyzing trace with hash -465206145, now seen corresponding path program 1 times [2019-12-07 11:18:45,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:45,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85599473] [2019-12-07 11:18:45,582 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:45,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:45,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:45,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85599473] [2019-12-07 11:18:45,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:45,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:45,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566154037] [2019-12-07 11:18:45,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:45,603 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:45,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:45,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:45,604 INFO L87 Difference]: Start difference. First operand 9008 states and 11698 transitions. Second operand 3 states. [2019-12-07 11:18:45,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:45,944 INFO L93 Difference]: Finished difference Result 25648 states and 33248 transitions. [2019-12-07 11:18:45,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:45,944 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-12-07 11:18:45,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:45,965 INFO L225 Difference]: With dead ends: 25648 [2019-12-07 11:18:45,965 INFO L226 Difference]: Without dead ends: 16782 [2019-12-07 11:18:45,976 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:45,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16782 states. [2019-12-07 11:18:46,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16782 to 16460. [2019-12-07 11:18:46,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16460 states. [2019-12-07 11:18:46,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16460 states to 16460 states and 21266 transitions. [2019-12-07 11:18:46,400 INFO L78 Accepts]: Start accepts. Automaton has 16460 states and 21266 transitions. Word has length 89 [2019-12-07 11:18:46,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:46,401 INFO L462 AbstractCegarLoop]: Abstraction has 16460 states and 21266 transitions. [2019-12-07 11:18:46,401 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:46,401 INFO L276 IsEmpty]: Start isEmpty. Operand 16460 states and 21266 transitions. [2019-12-07 11:18:46,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-12-07 11:18:46,403 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:46,403 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:46,403 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:46,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:46,403 INFO L82 PathProgramCache]: Analyzing trace with hash -270255493, now seen corresponding path program 1 times [2019-12-07 11:18:46,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:46,404 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101815434] [2019-12-07 11:18:46,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:46,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:46,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:46,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101815434] [2019-12-07 11:18:46,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:46,421 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:46,421 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664265378] [2019-12-07 11:18:46,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:46,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:46,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:46,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:46,422 INFO L87 Difference]: Start difference. First operand 16460 states and 21266 transitions. Second operand 3 states. [2019-12-07 11:18:46,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:46,788 INFO L93 Difference]: Finished difference Result 32684 states and 42245 transitions. [2019-12-07 11:18:46,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:46,788 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-12-07 11:18:46,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:46,802 INFO L225 Difference]: With dead ends: 32684 [2019-12-07 11:18:46,802 INFO L226 Difference]: Without dead ends: 16330 [2019-12-07 11:18:46,813 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:46,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16330 states. [2019-12-07 11:18:47,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16330 to 16330. [2019-12-07 11:18:47,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16330 states. [2019-12-07 11:18:47,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16330 states to 16330 states and 21108 transitions. [2019-12-07 11:18:47,174 INFO L78 Accepts]: Start accepts. Automaton has 16330 states and 21108 transitions. Word has length 89 [2019-12-07 11:18:47,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:47,174 INFO L462 AbstractCegarLoop]: Abstraction has 16330 states and 21108 transitions. [2019-12-07 11:18:47,174 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:47,174 INFO L276 IsEmpty]: Start isEmpty. Operand 16330 states and 21108 transitions. [2019-12-07 11:18:47,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2019-12-07 11:18:47,175 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:47,176 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:47,176 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:47,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:47,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1860831531, now seen corresponding path program 1 times [2019-12-07 11:18:47,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:47,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006738905] [2019-12-07 11:18:47,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:47,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:47,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:47,202 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006738905] [2019-12-07 11:18:47,202 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:47,202 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:47,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763038003] [2019-12-07 11:18:47,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:47,203 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:47,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:47,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:47,203 INFO L87 Difference]: Start difference. First operand 16330 states and 21108 transitions. Second operand 3 states. [2019-12-07 11:18:47,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:47,927 INFO L93 Difference]: Finished difference Result 48414 states and 62601 transitions. [2019-12-07 11:18:47,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:47,928 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 90 [2019-12-07 11:18:47,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:47,954 INFO L225 Difference]: With dead ends: 48414 [2019-12-07 11:18:47,954 INFO L226 Difference]: Without dead ends: 32194 [2019-12-07 11:18:47,966 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:47,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32194 states. [2019-12-07 11:18:48,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32194 to 32066. [2019-12-07 11:18:48,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32066 states. [2019-12-07 11:18:48,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32066 states to 32066 states and 41178 transitions. [2019-12-07 11:18:48,727 INFO L78 Accepts]: Start accepts. Automaton has 32066 states and 41178 transitions. Word has length 90 [2019-12-07 11:18:48,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:48,727 INFO L462 AbstractCegarLoop]: Abstraction has 32066 states and 41178 transitions. [2019-12-07 11:18:48,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:48,727 INFO L276 IsEmpty]: Start isEmpty. Operand 32066 states and 41178 transitions. [2019-12-07 11:18:48,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-12-07 11:18:48,733 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:48,733 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:48,733 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:48,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:48,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1352583657, now seen corresponding path program 1 times [2019-12-07 11:18:48,733 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:48,733 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708242681] [2019-12-07 11:18:48,733 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:48,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:48,757 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:18:48,757 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708242681] [2019-12-07 11:18:48,757 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:48,757 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:18:48,757 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424428893] [2019-12-07 11:18:48,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:48,758 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:48,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:48,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:48,758 INFO L87 Difference]: Start difference. First operand 32066 states and 41178 transitions. Second operand 3 states. [2019-12-07 11:18:50,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:50,144 INFO L93 Difference]: Finished difference Result 95594 states and 122647 transitions. [2019-12-07 11:18:50,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:50,144 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 111 [2019-12-07 11:18:50,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:50,201 INFO L225 Difference]: With dead ends: 95594 [2019-12-07 11:18:50,202 INFO L226 Difference]: Without dead ends: 63668 [2019-12-07 11:18:50,224 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:50,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63668 states. [2019-12-07 11:18:51,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63668 to 63668. [2019-12-07 11:18:51,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63668 states. [2019-12-07 11:18:51,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63668 states to 63668 states and 81494 transitions. [2019-12-07 11:18:51,785 INFO L78 Accepts]: Start accepts. Automaton has 63668 states and 81494 transitions. Word has length 111 [2019-12-07 11:18:51,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:51,786 INFO L462 AbstractCegarLoop]: Abstraction has 63668 states and 81494 transitions. [2019-12-07 11:18:51,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:51,786 INFO L276 IsEmpty]: Start isEmpty. Operand 63668 states and 81494 transitions. [2019-12-07 11:18:51,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:18:51,813 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:51,813 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:51,813 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:51,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:51,814 INFO L82 PathProgramCache]: Analyzing trace with hash 734407375, now seen corresponding path program 1 times [2019-12-07 11:18:51,814 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:51,814 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568688273] [2019-12-07 11:18:51,814 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:51,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:51,863 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-12-07 11:18:51,863 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568688273] [2019-12-07 11:18:51,863 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:51,863 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:51,863 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797563488] [2019-12-07 11:18:51,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:51,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:51,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:51,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:51,864 INFO L87 Difference]: Start difference. First operand 63668 states and 81494 transitions. Second operand 3 states. [2019-12-07 11:18:53,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:53,894 INFO L93 Difference]: Finished difference Result 155852 states and 199384 transitions. [2019-12-07 11:18:53,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:53,895 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 152 [2019-12-07 11:18:53,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:53,973 INFO L225 Difference]: With dead ends: 155852 [2019-12-07 11:18:53,973 INFO L226 Difference]: Without dead ends: 92306 [2019-12-07 11:18:54,004 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:54,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92306 states. [2019-12-07 11:18:56,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92306 to 92048. [2019-12-07 11:18:56,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92048 states. [2019-12-07 11:18:56,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92048 states to 92048 states and 117198 transitions. [2019-12-07 11:18:56,363 INFO L78 Accepts]: Start accepts. Automaton has 92048 states and 117198 transitions. Word has length 152 [2019-12-07 11:18:56,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:18:56,363 INFO L462 AbstractCegarLoop]: Abstraction has 92048 states and 117198 transitions. [2019-12-07 11:18:56,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:18:56,363 INFO L276 IsEmpty]: Start isEmpty. Operand 92048 states and 117198 transitions. [2019-12-07 11:18:56,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:18:56,398 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:18:56,399 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:18:56,399 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:18:56,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:18:56,399 INFO L82 PathProgramCache]: Analyzing trace with hash -1781759337, now seen corresponding path program 1 times [2019-12-07 11:18:56,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:18:56,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842259875] [2019-12-07 11:18:56,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:18:56,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:18:56,447 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-12-07 11:18:56,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842259875] [2019-12-07 11:18:56,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:18:56,448 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:18:56,448 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742720834] [2019-12-07 11:18:56,448 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:18:56,449 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:18:56,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:18:56,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:56,449 INFO L87 Difference]: Start difference. First operand 92048 states and 117198 transitions. Second operand 3 states. [2019-12-07 11:18:59,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:18:59,346 INFO L93 Difference]: Finished difference Result 225404 states and 286908 transitions. [2019-12-07 11:18:59,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:18:59,347 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 152 [2019-12-07 11:18:59,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:18:59,469 INFO L225 Difference]: With dead ends: 225404 [2019-12-07 11:18:59,469 INFO L226 Difference]: Without dead ends: 133502 [2019-12-07 11:18:59,522 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:18:59,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133502 states. [2019-12-07 11:19:03,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133502 to 133116. [2019-12-07 11:19:03,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133116 states. [2019-12-07 11:19:03,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133116 states to 133116 states and 168662 transitions. [2019-12-07 11:19:03,976 INFO L78 Accepts]: Start accepts. Automaton has 133116 states and 168662 transitions. Word has length 152 [2019-12-07 11:19:03,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:19:03,977 INFO L462 AbstractCegarLoop]: Abstraction has 133116 states and 168662 transitions. [2019-12-07 11:19:03,977 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:19:03,977 INFO L276 IsEmpty]: Start isEmpty. Operand 133116 states and 168662 transitions. [2019-12-07 11:19:04,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:19:04,012 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:19:04,012 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:19:04,012 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:19:04,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:19:04,012 INFO L82 PathProgramCache]: Analyzing trace with hash 66864795, now seen corresponding path program 1 times [2019-12-07 11:19:04,012 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:19:04,012 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635618994] [2019-12-07 11:19:04,013 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:19:04,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:19:04,057 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2019-12-07 11:19:04,057 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635618994] [2019-12-07 11:19:04,057 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:19:04,057 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:19:04,057 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490698192] [2019-12-07 11:19:04,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:19:04,057 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:19:04,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:19:04,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:19:04,058 INFO L87 Difference]: Start difference. First operand 133116 states and 168662 transitions. Second operand 3 states. [2019-12-07 11:19:08,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:19:08,476 INFO L93 Difference]: Finished difference Result 325972 states and 412968 transitions. [2019-12-07 11:19:08,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:19:08,477 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 152 [2019-12-07 11:19:08,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:19:08,659 INFO L225 Difference]: With dead ends: 325972 [2019-12-07 11:19:08,659 INFO L226 Difference]: Without dead ends: 193026 [2019-12-07 11:19:08,733 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:19:08,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193026 states. [2019-12-07 11:19:13,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193026 to 192448. [2019-12-07 11:19:13,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192448 states. [2019-12-07 11:19:13,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192448 states to 192448 states and 242726 transitions. [2019-12-07 11:19:13,783 INFO L78 Accepts]: Start accepts. Automaton has 192448 states and 242726 transitions. Word has length 152 [2019-12-07 11:19:13,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:19:13,783 INFO L462 AbstractCegarLoop]: Abstraction has 192448 states and 242726 transitions. [2019-12-07 11:19:13,783 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:19:13,783 INFO L276 IsEmpty]: Start isEmpty. Operand 192448 states and 242726 transitions. [2019-12-07 11:19:13,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:19:13,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:19:13,842 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:19:13,842 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:19:13,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:19:13,842 INFO L82 PathProgramCache]: Analyzing trace with hash -1013280947, now seen corresponding path program 1 times [2019-12-07 11:19:13,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:19:13,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393838666] [2019-12-07 11:19:13,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:19:13,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:19:13,874 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-12-07 11:19:13,874 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393838666] [2019-12-07 11:19:13,874 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:19:13,874 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:19:13,874 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235201429] [2019-12-07 11:19:13,874 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:19:13,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:19:13,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:19:13,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:19:13,875 INFO L87 Difference]: Start difference. First operand 192448 states and 242726 transitions. Second operand 3 states. [2019-12-07 11:19:21,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:19:21,465 INFO L93 Difference]: Finished difference Result 470804 states and 593244 transitions. [2019-12-07 11:19:21,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:19:21,466 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 152 [2019-12-07 11:19:21,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:19:21,734 INFO L225 Difference]: With dead ends: 470804 [2019-12-07 11:19:21,734 INFO L226 Difference]: Without dead ends: 278450 [2019-12-07 11:19:21,821 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:19:22,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278450 states. [2019-12-07 11:19:28,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278450 to 277584. [2019-12-07 11:19:28,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277584 states. [2019-12-07 11:19:28,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277584 states to 277584 states and 348030 transitions. [2019-12-07 11:19:28,862 INFO L78 Accepts]: Start accepts. Automaton has 277584 states and 348030 transitions. Word has length 152 [2019-12-07 11:19:28,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:19:28,863 INFO L462 AbstractCegarLoop]: Abstraction has 277584 states and 348030 transitions. [2019-12-07 11:19:28,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:19:28,863 INFO L276 IsEmpty]: Start isEmpty. Operand 277584 states and 348030 transitions. [2019-12-07 11:19:28,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:19:28,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:19:28,927 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:19:28,927 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:19:28,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:19:28,928 INFO L82 PathProgramCache]: Analyzing trace with hash 371466903, now seen corresponding path program 1 times [2019-12-07 11:19:28,928 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:19:28,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412152921] [2019-12-07 11:19:28,928 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:19:28,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:19:28,970 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 11:19:28,971 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412152921] [2019-12-07 11:19:28,971 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:19:28,971 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:19:28,971 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443975488] [2019-12-07 11:19:28,971 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:19:28,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:19:28,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:19:28,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:19:28,971 INFO L87 Difference]: Start difference. First operand 277584 states and 348030 transitions. Second operand 5 states. [2019-12-07 11:19:43,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:19:43,643 INFO L93 Difference]: Finished difference Result 877260 states and 1093999 transitions. [2019-12-07 11:19:43,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:19:43,644 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 152 [2019-12-07 11:19:43,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:19:44,245 INFO L225 Difference]: With dead ends: 877260 [2019-12-07 11:19:44,245 INFO L226 Difference]: Without dead ends: 599844 [2019-12-07 11:19:44,399 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:19:44,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 599844 states. [2019-12-07 11:19:57,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 599844 to 285036. [2019-12-07 11:19:57,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285036 states. [2019-12-07 11:19:57,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285036 states to 285036 states and 353642 transitions. [2019-12-07 11:19:57,940 INFO L78 Accepts]: Start accepts. Automaton has 285036 states and 353642 transitions. Word has length 152 [2019-12-07 11:19:57,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:19:57,940 INFO L462 AbstractCegarLoop]: Abstraction has 285036 states and 353642 transitions. [2019-12-07 11:19:57,940 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:19:57,940 INFO L276 IsEmpty]: Start isEmpty. Operand 285036 states and 353642 transitions. [2019-12-07 11:19:58,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:19:58,004 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:19:58,004 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:19:58,004 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:19:58,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:19:58,005 INFO L82 PathProgramCache]: Analyzing trace with hash -416127077, now seen corresponding path program 1 times [2019-12-07 11:19:58,005 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:19:58,005 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601284686] [2019-12-07 11:19:58,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:19:58,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:19:58,064 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 11:19:58,064 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601284686] [2019-12-07 11:19:58,064 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:19:58,064 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:19:58,065 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691973160] [2019-12-07 11:19:58,065 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:19:58,065 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:19:58,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:19:58,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:19:58,065 INFO L87 Difference]: Start difference. First operand 285036 states and 353642 transitions. Second operand 5 states. [2019-12-07 11:20:10,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:20:10,822 INFO L93 Difference]: Finished difference Result 676654 states and 843889 transitions. [2019-12-07 11:20:10,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:20:10,823 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 152 [2019-12-07 11:20:10,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:20:11,227 INFO L225 Difference]: With dead ends: 676654 [2019-12-07 11:20:11,227 INFO L226 Difference]: Without dead ends: 391800 [2019-12-07 11:20:11,353 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:20:11,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391800 states. [2019-12-07 11:20:22,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391800 to 285900. [2019-12-07 11:20:22,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285900 states. [2019-12-07 11:20:22,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285900 states to 285900 states and 350470 transitions. [2019-12-07 11:20:22,425 INFO L78 Accepts]: Start accepts. Automaton has 285900 states and 350470 transitions. Word has length 152 [2019-12-07 11:20:22,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:20:22,425 INFO L462 AbstractCegarLoop]: Abstraction has 285900 states and 350470 transitions. [2019-12-07 11:20:22,425 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:20:22,425 INFO L276 IsEmpty]: Start isEmpty. Operand 285900 states and 350470 transitions. [2019-12-07 11:20:22,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2019-12-07 11:20:22,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:20:22,488 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:20:22,488 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:20:22,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:20:22,488 INFO L82 PathProgramCache]: Analyzing trace with hash 40007839, now seen corresponding path program 1 times [2019-12-07 11:20:22,488 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:20:22,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567361089] [2019-12-07 11:20:22,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:20:22,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:20:22,525 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:20:22,525 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567361089] [2019-12-07 11:20:22,525 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:20:22,525 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:20:22,525 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443853960] [2019-12-07 11:20:22,526 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:20:22,526 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:20:22,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:20:22,526 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:20:22,526 INFO L87 Difference]: Start difference. First operand 285900 states and 350470 transitions. Second operand 3 states. [2019-12-07 11:20:32,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:20:32,335 INFO L93 Difference]: Finished difference Result 430292 states and 528647 transitions. [2019-12-07 11:20:32,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:20:32,335 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 152 [2019-12-07 11:20:32,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:20:32,622 INFO L225 Difference]: With dead ends: 430292 [2019-12-07 11:20:32,623 INFO L226 Difference]: Without dead ends: 285900 [2019-12-07 11:20:32,704 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:20:32,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 285900 states. [2019-12-07 11:20:45,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 285900 to 285254. [2019-12-07 11:20:45,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285254 states. [2019-12-07 11:20:45,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285254 states to 285254 states and 347016 transitions. [2019-12-07 11:20:45,820 INFO L78 Accepts]: Start accepts. Automaton has 285254 states and 347016 transitions. Word has length 152 [2019-12-07 11:20:45,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:20:45,820 INFO L462 AbstractCegarLoop]: Abstraction has 285254 states and 347016 transitions. [2019-12-07 11:20:45,820 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:20:45,821 INFO L276 IsEmpty]: Start isEmpty. Operand 285254 states and 347016 transitions. [2019-12-07 11:20:45,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2019-12-07 11:20:45,882 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:20:45,883 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:20:45,883 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:20:45,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:20:45,883 INFO L82 PathProgramCache]: Analyzing trace with hash -226089385, now seen corresponding path program 1 times [2019-12-07 11:20:45,883 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:20:45,883 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175453908] [2019-12-07 11:20:45,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:20:45,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:20:45,944 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-12-07 11:20:45,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175453908] [2019-12-07 11:20:45,945 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:20:45,945 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:20:45,945 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555273413] [2019-12-07 11:20:45,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:20:45,946 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:20:45,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:20:45,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:20:45,946 INFO L87 Difference]: Start difference. First operand 285254 states and 347016 transitions. Second operand 5 states. [2019-12-07 11:21:02,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:21:02,126 INFO L93 Difference]: Finished difference Result 685202 states and 838953 transitions. [2019-12-07 11:21:02,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:21:02,127 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 153 [2019-12-07 11:21:02,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:21:02,560 INFO L225 Difference]: With dead ends: 685202 [2019-12-07 11:21:02,560 INFO L226 Difference]: Without dead ends: 400058 [2019-12-07 11:21:02,698 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:21:02,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400058 states. [2019-12-07 11:21:15,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400058 to 286550. [2019-12-07 11:21:15,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286550 states. [2019-12-07 11:21:15,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286550 states to 286550 states and 344420 transitions. [2019-12-07 11:21:15,929 INFO L78 Accepts]: Start accepts. Automaton has 286550 states and 344420 transitions. Word has length 153 [2019-12-07 11:21:15,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:21:15,929 INFO L462 AbstractCegarLoop]: Abstraction has 286550 states and 344420 transitions. [2019-12-07 11:21:15,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:21:15,929 INFO L276 IsEmpty]: Start isEmpty. Operand 286550 states and 344420 transitions. [2019-12-07 11:21:15,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2019-12-07 11:21:15,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:21:15,991 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:21:15,991 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:21:15,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:21:15,991 INFO L82 PathProgramCache]: Analyzing trace with hash 2018469013, now seen corresponding path program 1 times [2019-12-07 11:21:15,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:21:15,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744888919] [2019-12-07 11:21:15,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:21:16,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:21:16,047 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-12-07 11:21:16,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744888919] [2019-12-07 11:21:16,047 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:21:16,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:21:16,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397243034] [2019-12-07 11:21:16,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:21:16,048 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:21:16,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:21:16,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:21:16,048 INFO L87 Difference]: Start difference. First operand 286550 states and 344420 transitions. Second operand 5 states. [2019-12-07 11:21:33,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:21:33,722 INFO L93 Difference]: Finished difference Result 670414 states and 810865 transitions. [2019-12-07 11:21:33,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:21:33,723 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 153 [2019-12-07 11:21:33,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:21:34,146 INFO L225 Difference]: With dead ends: 670414 [2019-12-07 11:21:34,146 INFO L226 Difference]: Without dead ends: 384022 [2019-12-07 11:21:34,271 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:21:34,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384022 states. [2019-12-07 11:21:52,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384022 to 287414. [2019-12-07 11:21:52,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287414 states. [2019-12-07 11:21:52,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287414 states to 287414 states and 341248 transitions. [2019-12-07 11:21:52,378 INFO L78 Accepts]: Start accepts. Automaton has 287414 states and 341248 transitions. Word has length 153 [2019-12-07 11:21:52,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:21:52,378 INFO L462 AbstractCegarLoop]: Abstraction has 287414 states and 341248 transitions. [2019-12-07 11:21:52,378 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:21:52,378 INFO L276 IsEmpty]: Start isEmpty. Operand 287414 states and 341248 transitions. [2019-12-07 11:21:52,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2019-12-07 11:21:52,439 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:21:52,440 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:21:52,440 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:21:52,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:21:52,440 INFO L82 PathProgramCache]: Analyzing trace with hash -90249455, now seen corresponding path program 1 times [2019-12-07 11:21:52,440 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:21:52,440 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123322256] [2019-12-07 11:21:52,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:21:52,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:21:52,495 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-12-07 11:21:52,495 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123322256] [2019-12-07 11:21:52,495 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:21:52,495 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:21:52,495 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239860570] [2019-12-07 11:21:52,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:21:52,496 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:21:52,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:21:52,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:21:52,496 INFO L87 Difference]: Start difference. First operand 287414 states and 341248 transitions. Second operand 5 states. [2019-12-07 11:22:10,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:22:10,027 INFO L93 Difference]: Finished difference Result 557010 states and 664761 transitions. [2019-12-07 11:22:10,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:22:10,028 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 153 [2019-12-07 11:22:10,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:22:10,298 INFO L225 Difference]: With dead ends: 557010 [2019-12-07 11:22:10,298 INFO L226 Difference]: Without dead ends: 269706 [2019-12-07 11:22:10,411 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:22:10,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269706 states. [2019-12-07 11:22:21,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269706 to 194908. [2019-12-07 11:22:21,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194908 states. [2019-12-07 11:22:21,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194908 states to 194908 states and 228974 transitions. [2019-12-07 11:22:21,461 INFO L78 Accepts]: Start accepts. Automaton has 194908 states and 228974 transitions. Word has length 153 [2019-12-07 11:22:21,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:22:21,461 INFO L462 AbstractCegarLoop]: Abstraction has 194908 states and 228974 transitions. [2019-12-07 11:22:21,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:22:21,461 INFO L276 IsEmpty]: Start isEmpty. Operand 194908 states and 228974 transitions. [2019-12-07 11:22:21,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-12-07 11:22:21,505 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:22:21,505 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:22:21,505 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:22:21,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:22:21,505 INFO L82 PathProgramCache]: Analyzing trace with hash -1391161611, now seen corresponding path program 1 times [2019-12-07 11:22:21,505 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:22:21,506 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907574013] [2019-12-07 11:22:21,506 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:22:21,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:22:21,539 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:22:21,539 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907574013] [2019-12-07 11:22:21,540 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:22:21,540 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:22:21,540 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26014694] [2019-12-07 11:22:21,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:22:21,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:22:21,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:22:21,540 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:22:21,541 INFO L87 Difference]: Start difference. First operand 194908 states and 228974 transitions. Second operand 3 states. [2019-12-07 11:22:30,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:22:30,357 INFO L93 Difference]: Finished difference Result 313016 states and 368590 transitions. [2019-12-07 11:22:30,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:22:30,357 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 155 [2019-12-07 11:22:30,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:22:30,522 INFO L225 Difference]: With dead ends: 313016 [2019-12-07 11:22:30,522 INFO L226 Difference]: Without dead ends: 162514 [2019-12-07 11:22:30,588 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:22:30,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162514 states. [2019-12-07 11:22:39,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162514 to 162510. [2019-12-07 11:22:39,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162510 states. [2019-12-07 11:22:39,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162510 states to 162510 states and 190822 transitions. [2019-12-07 11:22:39,633 INFO L78 Accepts]: Start accepts. Automaton has 162510 states and 190822 transitions. Word has length 155 [2019-12-07 11:22:39,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:22:39,633 INFO L462 AbstractCegarLoop]: Abstraction has 162510 states and 190822 transitions. [2019-12-07 11:22:39,633 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:22:39,633 INFO L276 IsEmpty]: Start isEmpty. Operand 162510 states and 190822 transitions. [2019-12-07 11:22:39,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2019-12-07 11:22:39,682 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:22:39,682 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:22:39,682 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:22:39,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:22:39,682 INFO L82 PathProgramCache]: Analyzing trace with hash 1227902601, now seen corresponding path program 1 times [2019-12-07 11:22:39,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:22:39,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561505401] [2019-12-07 11:22:39,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:22:39,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:22:39,722 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:22:39,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561505401] [2019-12-07 11:22:39,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:22:39,723 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:22:39,723 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702383498] [2019-12-07 11:22:39,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:22:39,723 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:22:39,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:22:39,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:22:39,723 INFO L87 Difference]: Start difference. First operand 162510 states and 190822 transitions. Second operand 3 states. [2019-12-07 11:22:46,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:22:46,785 INFO L93 Difference]: Finished difference Result 264524 states and 311390 transitions. [2019-12-07 11:22:46,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:22:46,785 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 200 [2019-12-07 11:22:46,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:22:46,904 INFO L225 Difference]: With dead ends: 264524 [2019-12-07 11:22:46,904 INFO L226 Difference]: Without dead ends: 129414 [2019-12-07 11:22:46,963 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:22:47,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129414 states. [2019-12-07 11:22:54,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129414 to 129410. [2019-12-07 11:22:54,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129410 states. [2019-12-07 11:22:54,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129410 states to 129410 states and 151858 transitions. [2019-12-07 11:22:54,182 INFO L78 Accepts]: Start accepts. Automaton has 129410 states and 151858 transitions. Word has length 200 [2019-12-07 11:22:54,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:22:54,182 INFO L462 AbstractCegarLoop]: Abstraction has 129410 states and 151858 transitions. [2019-12-07 11:22:54,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:22:54,182 INFO L276 IsEmpty]: Start isEmpty. Operand 129410 states and 151858 transitions. [2019-12-07 11:22:54,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2019-12-07 11:22:54,232 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:22:54,232 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:22:54,232 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:22:54,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:22:54,233 INFO L82 PathProgramCache]: Analyzing trace with hash -855006846, now seen corresponding path program 1 times [2019-12-07 11:22:54,233 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:22:54,233 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538475984] [2019-12-07 11:22:54,233 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:22:54,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:22:54,281 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:22:54,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538475984] [2019-12-07 11:22:54,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:22:54,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:22:54,282 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930783006] [2019-12-07 11:22:54,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:22:54,282 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:22:54,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:22:54,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:22:54,282 INFO L87 Difference]: Start difference. First operand 129410 states and 151858 transitions. Second operand 3 states. [2019-12-07 11:23:01,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:23:01,397 INFO L93 Difference]: Finished difference Result 241948 states and 284406 transitions. [2019-12-07 11:23:01,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:23:01,398 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 245 [2019-12-07 11:23:01,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:23:01,517 INFO L225 Difference]: With dead ends: 241948 [2019-12-07 11:23:01,517 INFO L226 Difference]: Without dead ends: 129414 [2019-12-07 11:23:01,567 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:01,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129414 states. [2019-12-07 11:23:08,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129414 to 129410. [2019-12-07 11:23:08,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129410 states. [2019-12-07 11:23:08,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129410 states to 129410 states and 151498 transitions. [2019-12-07 11:23:08,820 INFO L78 Accepts]: Start accepts. Automaton has 129410 states and 151498 transitions. Word has length 245 [2019-12-07 11:23:08,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:23:08,820 INFO L462 AbstractCegarLoop]: Abstraction has 129410 states and 151498 transitions. [2019-12-07 11:23:08,820 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:23:08,820 INFO L276 IsEmpty]: Start isEmpty. Operand 129410 states and 151498 transitions. [2019-12-07 11:23:08,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 288 [2019-12-07 11:23:08,877 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:23:08,877 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:23:08,878 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:23:08,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:23:08,878 INFO L82 PathProgramCache]: Analyzing trace with hash 649016126, now seen corresponding path program 1 times [2019-12-07 11:23:08,878 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:23:08,878 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742466018] [2019-12-07 11:23:08,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:23:08,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:23:08,942 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:23:08,942 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742466018] [2019-12-07 11:23:08,942 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:23:08,942 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:23:08,942 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880948497] [2019-12-07 11:23:08,943 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:23:08,943 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:23:08,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:23:08,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:08,943 INFO L87 Difference]: Start difference. First operand 129410 states and 151498 transitions. Second operand 3 states. [2019-12-07 11:23:16,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:23:16,218 INFO L93 Difference]: Finished difference Result 242136 states and 283875 transitions. [2019-12-07 11:23:16,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:23:16,219 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 287 [2019-12-07 11:23:16,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:23:16,338 INFO L225 Difference]: With dead ends: 242136 [2019-12-07 11:23:16,338 INFO L226 Difference]: Without dead ends: 129602 [2019-12-07 11:23:16,386 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:16,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129602 states. [2019-12-07 11:23:23,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129602 to 129410. [2019-12-07 11:23:23,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129410 states. [2019-12-07 11:23:23,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129410 states to 129410 states and 149322 transitions. [2019-12-07 11:23:23,774 INFO L78 Accepts]: Start accepts. Automaton has 129410 states and 149322 transitions. Word has length 287 [2019-12-07 11:23:23,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:23:23,774 INFO L462 AbstractCegarLoop]: Abstraction has 129410 states and 149322 transitions. [2019-12-07 11:23:23,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:23:23,774 INFO L276 IsEmpty]: Start isEmpty. Operand 129410 states and 149322 transitions. [2019-12-07 11:23:23,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 292 [2019-12-07 11:23:23,833 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:23:23,833 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:23:23,833 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:23:23,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:23:23,834 INFO L82 PathProgramCache]: Analyzing trace with hash -1338236076, now seen corresponding path program 1 times [2019-12-07 11:23:23,834 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:23:23,834 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923288229] [2019-12-07 11:23:23,834 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:23:23,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:23:23,902 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 11:23:23,902 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923288229] [2019-12-07 11:23:23,902 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:23:23,902 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:23:23,902 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490570968] [2019-12-07 11:23:23,902 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:23:23,903 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:23:23,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:23:23,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:23:23,903 INFO L87 Difference]: Start difference. First operand 129410 states and 149322 transitions. Second operand 5 states. [2019-12-07 11:23:32,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:23:32,455 INFO L93 Difference]: Finished difference Result 272016 states and 316677 transitions. [2019-12-07 11:23:32,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:23:32,455 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 291 [2019-12-07 11:23:32,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:23:32,598 INFO L225 Difference]: With dead ends: 272016 [2019-12-07 11:23:32,598 INFO L226 Difference]: Without dead ends: 142680 [2019-12-07 11:23:32,684 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:23:32,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142680 states. [2019-12-07 11:23:39,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142680 to 100498. [2019-12-07 11:23:39,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100498 states. [2019-12-07 11:23:39,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100498 states to 100498 states and 114880 transitions. [2019-12-07 11:23:39,165 INFO L78 Accepts]: Start accepts. Automaton has 100498 states and 114880 transitions. Word has length 291 [2019-12-07 11:23:39,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:23:39,165 INFO L462 AbstractCegarLoop]: Abstraction has 100498 states and 114880 transitions. [2019-12-07 11:23:39,165 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:23:39,165 INFO L276 IsEmpty]: Start isEmpty. Operand 100498 states and 114880 transitions. [2019-12-07 11:23:39,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2019-12-07 11:23:39,211 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:23:39,211 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:23:39,211 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:23:39,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:23:39,211 INFO L82 PathProgramCache]: Analyzing trace with hash 2115683789, now seen corresponding path program 1 times [2019-12-07 11:23:39,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:23:39,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357714727] [2019-12-07 11:23:39,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:23:39,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:23:39,275 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:23:39,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357714727] [2019-12-07 11:23:39,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:23:39,275 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:23:39,275 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244199643] [2019-12-07 11:23:39,275 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:23:39,275 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:23:39,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:23:39,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:39,276 INFO L87 Difference]: Start difference. First operand 100498 states and 114880 transitions. Second operand 3 states. [2019-12-07 11:23:45,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:23:45,214 INFO L93 Difference]: Finished difference Result 190740 states and 218348 transitions. [2019-12-07 11:23:45,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:23:45,215 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 293 [2019-12-07 11:23:45,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:23:45,303 INFO L225 Difference]: With dead ends: 190740 [2019-12-07 11:23:45,303 INFO L226 Difference]: Without dead ends: 100502 [2019-12-07 11:23:45,344 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:45,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100502 states. [2019-12-07 11:23:51,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100502 to 100498. [2019-12-07 11:23:51,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100498 states. [2019-12-07 11:23:51,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100498 states to 100498 states and 114400 transitions. [2019-12-07 11:23:51,448 INFO L78 Accepts]: Start accepts. Automaton has 100498 states and 114400 transitions. Word has length 293 [2019-12-07 11:23:51,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:23:51,448 INFO L462 AbstractCegarLoop]: Abstraction has 100498 states and 114400 transitions. [2019-12-07 11:23:51,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:23:51,448 INFO L276 IsEmpty]: Start isEmpty. Operand 100498 states and 114400 transitions. [2019-12-07 11:23:51,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2019-12-07 11:23:51,482 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:23:51,483 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:23:51,483 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:23:51,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:23:51,483 INFO L82 PathProgramCache]: Analyzing trace with hash 1405770907, now seen corresponding path program 1 times [2019-12-07 11:23:51,483 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:23:51,483 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665317897] [2019-12-07 11:23:51,483 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:23:51,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:23:51,574 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:23:51,575 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665317897] [2019-12-07 11:23:51,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:23:51,575 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:23:51,575 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072583027] [2019-12-07 11:23:51,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:23:51,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:23:51,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:23:51,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:51,576 INFO L87 Difference]: Start difference. First operand 100498 states and 114400 transitions. Second operand 3 states. [2019-12-07 11:23:57,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:23:57,536 INFO L93 Difference]: Finished difference Result 176712 states and 201577 transitions. [2019-12-07 11:23:57,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:23:57,537 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 336 [2019-12-07 11:23:57,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:23:57,625 INFO L225 Difference]: With dead ends: 176712 [2019-12-07 11:23:57,625 INFO L226 Difference]: Without dead ends: 100626 [2019-12-07 11:23:57,666 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:23:57,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100626 states. [2019-12-07 11:24:03,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100626 to 100498. [2019-12-07 11:24:03,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100498 states. [2019-12-07 11:24:03,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100498 states to 100498 states and 113008 transitions. [2019-12-07 11:24:03,956 INFO L78 Accepts]: Start accepts. Automaton has 100498 states and 113008 transitions. Word has length 336 [2019-12-07 11:24:03,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:24:03,956 INFO L462 AbstractCegarLoop]: Abstraction has 100498 states and 113008 transitions. [2019-12-07 11:24:03,956 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:24:03,956 INFO L276 IsEmpty]: Start isEmpty. Operand 100498 states and 113008 transitions. [2019-12-07 11:24:03,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 341 [2019-12-07 11:24:03,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:24:03,990 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:24:03,990 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:24:03,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:24:03,991 INFO L82 PathProgramCache]: Analyzing trace with hash -522043604, now seen corresponding path program 1 times [2019-12-07 11:24:03,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:24:03,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696154797] [2019-12-07 11:24:03,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:24:04,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:24:04,072 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:24:04,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696154797] [2019-12-07 11:24:04,073 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:24:04,073 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:24:04,073 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605444359] [2019-12-07 11:24:04,073 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:24:04,073 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:24:04,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:24:04,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:04,074 INFO L87 Difference]: Start difference. First operand 100498 states and 113008 transitions. Second operand 3 states. [2019-12-07 11:24:11,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:24:11,131 INFO L93 Difference]: Finished difference Result 168432 states and 189737 transitions. [2019-12-07 11:24:11,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:24:11,131 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 340 [2019-12-07 11:24:11,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:24:11,217 INFO L225 Difference]: With dead ends: 168432 [2019-12-07 11:24:11,217 INFO L226 Difference]: Without dead ends: 100626 [2019-12-07 11:24:11,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:11,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100626 states. [2019-12-07 11:24:17,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100626 to 100498. [2019-12-07 11:24:17,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100498 states. [2019-12-07 11:24:17,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100498 states to 100498 states and 111808 transitions. [2019-12-07 11:24:17,280 INFO L78 Accepts]: Start accepts. Automaton has 100498 states and 111808 transitions. Word has length 340 [2019-12-07 11:24:17,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:24:17,280 INFO L462 AbstractCegarLoop]: Abstraction has 100498 states and 111808 transitions. [2019-12-07 11:24:17,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:24:17,281 INFO L276 IsEmpty]: Start isEmpty. Operand 100498 states and 111808 transitions. [2019-12-07 11:24:17,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2019-12-07 11:24:17,314 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:24:17,315 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:24:17,315 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:24:17,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:24:17,315 INFO L82 PathProgramCache]: Analyzing trace with hash -461725018, now seen corresponding path program 1 times [2019-12-07 11:24:17,315 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:24:17,315 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711920839] [2019-12-07 11:24:17,315 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:24:17,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:24:17,387 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 11:24:17,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711920839] [2019-12-07 11:24:17,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:24:17,387 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:24:17,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523975158] [2019-12-07 11:24:17,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:24:17,388 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:24:17,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:24:17,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:17,388 INFO L87 Difference]: Start difference. First operand 100498 states and 111808 transitions. Second operand 3 states. [2019-12-07 11:24:21,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:24:21,418 INFO L93 Difference]: Finished difference Result 166480 states and 184379 transitions. [2019-12-07 11:24:21,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:24:21,419 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 344 [2019-12-07 11:24:21,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:24:21,453 INFO L225 Difference]: With dead ends: 166480 [2019-12-07 11:24:21,453 INFO L226 Difference]: Without dead ends: 39644 [2019-12-07 11:24:21,503 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:21,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39644 states. [2019-12-07 11:24:23,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39644 to 38396. [2019-12-07 11:24:23,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38396 states. [2019-12-07 11:24:23,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38396 states to 38396 states and 41594 transitions. [2019-12-07 11:24:23,869 INFO L78 Accepts]: Start accepts. Automaton has 38396 states and 41594 transitions. Word has length 344 [2019-12-07 11:24:23,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:24:23,869 INFO L462 AbstractCegarLoop]: Abstraction has 38396 states and 41594 transitions. [2019-12-07 11:24:23,869 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:24:23,869 INFO L276 IsEmpty]: Start isEmpty. Operand 38396 states and 41594 transitions. [2019-12-07 11:24:23,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 349 [2019-12-07 11:24:23,894 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:24:23,894 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:24:23,894 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:24:23,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:24:23,895 INFO L82 PathProgramCache]: Analyzing trace with hash -787209040, now seen corresponding path program 1 times [2019-12-07 11:24:23,895 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:24:23,895 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611567192] [2019-12-07 11:24:23,895 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:24:23,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:24:23,976 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:24:23,977 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611567192] [2019-12-07 11:24:23,977 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:24:23,977 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:24:23,977 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853835673] [2019-12-07 11:24:23,977 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:24:23,977 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:24:23,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:24:23,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:23,978 INFO L87 Difference]: Start difference. First operand 38396 states and 41594 transitions. Second operand 3 states. [2019-12-07 11:24:26,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:24:26,294 INFO L93 Difference]: Finished difference Result 68182 states and 73937 transitions. [2019-12-07 11:24:26,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:24:26,295 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 348 [2019-12-07 11:24:26,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:24:26,325 INFO L225 Difference]: With dead ends: 68182 [2019-12-07 11:24:26,325 INFO L226 Difference]: Without dead ends: 38396 [2019-12-07 11:24:26,342 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:24:26,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38396 states. [2019-12-07 11:24:28,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38396 to 38396. [2019-12-07 11:24:28,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38396 states. [2019-12-07 11:24:28,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38396 states to 38396 states and 41252 transitions. [2019-12-07 11:24:28,711 INFO L78 Accepts]: Start accepts. Automaton has 38396 states and 41252 transitions. Word has length 348 [2019-12-07 11:24:28,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:24:28,711 INFO L462 AbstractCegarLoop]: Abstraction has 38396 states and 41252 transitions. [2019-12-07 11:24:28,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:24:28,711 INFO L276 IsEmpty]: Start isEmpty. Operand 38396 states and 41252 transitions. [2019-12-07 11:24:28,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2019-12-07 11:24:28,735 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:24:28,736 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:24:28,736 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:24:28,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:24:28,736 INFO L82 PathProgramCache]: Analyzing trace with hash -286182510, now seen corresponding path program 1 times [2019-12-07 11:24:28,736 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:24:28,736 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613926380] [2019-12-07 11:24:28,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:24:28,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:24:28,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:24:28,900 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 11:24:28,900 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 11:24:29,041 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 11:24:29 BoogieIcfgContainer [2019-12-07 11:24:29,041 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 11:24:29,041 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 11:24:29,042 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 11:24:29,042 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 11:24:29,042 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:18:42" (3/4) ... [2019-12-07 11:24:29,044 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 11:24:29,182 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_3874e734-b386-4a48-ae17-fbb336174d31/bin/uautomizer/witness.graphml [2019-12-07 11:24:29,182 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 11:24:29,183 INFO L168 Benchmark]: Toolchain (without parser) took 348213.23 ms. Allocated memory was 1.0 GB in the beginning and 6.7 GB in the end (delta: 5.6 GB). Free memory was 941.9 MB in the beginning and 4.1 GB in the end (delta: -3.2 GB). Peak memory consumption was 2.4 GB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,183 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:24:29,184 INFO L168 Benchmark]: CACSL2BoogieTranslator took 279.54 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.0 MB). Free memory was 941.9 MB in the beginning and 1.1 GB in the end (delta: -154.4 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,184 INFO L168 Benchmark]: Boogie Procedure Inliner took 47.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,184 INFO L168 Benchmark]: Boogie Preprocessor took 40.34 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,184 INFO L168 Benchmark]: RCFGBuilder took 688.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 974.8 MB in the end (delta: 110.8 MB). Peak memory consumption was 110.8 MB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,185 INFO L168 Benchmark]: TraceAbstraction took 347014.34 ms. Allocated memory was 1.1 GB in the beginning and 6.7 GB in the end (delta: 5.5 GB). Free memory was 974.8 MB in the beginning and 4.2 GB in the end (delta: -3.2 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,185 INFO L168 Benchmark]: Witness Printer took 140.34 ms. Allocated memory is still 6.7 GB. Free memory was 4.2 GB in the beginning and 4.1 GB in the end (delta: 80.1 MB). Peak memory consumption was 80.1 MB. Max. memory is 11.5 GB. [2019-12-07 11:24:29,186 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 279.54 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 107.0 MB). Free memory was 941.9 MB in the beginning and 1.1 GB in the end (delta: -154.4 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 47.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 40.34 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 688.52 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 974.8 MB in the end (delta: 110.8 MB). Peak memory consumption was 110.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 347014.34 ms. Allocated memory was 1.1 GB in the beginning and 6.7 GB in the end (delta: 5.5 GB). Free memory was 974.8 MB in the beginning and 4.2 GB in the end (delta: -3.2 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 140.34 ms. Allocated memory is still 6.7 GB. Free memory was 4.2 GB in the beginning and 4.1 GB in the end (delta: 80.1 MB). Peak memory consumption was 80.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0] [L935] int __retres1 ; [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L391] COND TRUE m_i == 1 [L392] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t5_i == 1 [L417] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L576] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L581] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L586] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L269] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L288] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L307] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L326] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L342] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L345] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L355] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L357] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L364] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L374] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L376] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L639] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L644] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L649] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L890] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L893] kernel_st = 1 [L467] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L471] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L462] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L96] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L107] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L131] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L142] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L166] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L177] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L201] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L212] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=0] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L236] COND TRUE t5_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L247] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=0, t5_st=1] [L249] t5_pc = 1 [L250] t5_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L471] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L462] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND TRUE \read(tmp_ndt_1) [L486] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L55] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L66] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L69] E_1 = 1 [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND TRUE E_1 == 1 [L290] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] tmp___0 = is_transmit1_triggered() [L718] COND TRUE \read(tmp___0) [L719] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L71] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L74] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L76] m_pc = 1 [L77] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND TRUE \read(tmp_ndt_2) [L500] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L96] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L99] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L115] E_2 = 1 [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND TRUE E_2 == 1 [L309] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] tmp___1 = is_transmit2_triggered() [L726] COND TRUE \read(tmp___1) [L727] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L117] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L107] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L109] t1_pc = 1 [L110] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND TRUE \read(tmp_ndt_3) [L514] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L131] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L134] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L150] E_3 = 1 [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND TRUE E_3 == 1 [L328] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] tmp___2 = is_transmit3_triggered() [L734] COND TRUE \read(tmp___2) [L735] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L152] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L142] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L144] t2_pc = 1 [L145] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND TRUE \read(tmp_ndt_4) [L528] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L166] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L169] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L185] E_4 = 1 [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND TRUE E_4 == 1 [L347] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] tmp___3 = is_transmit4_triggered() [L742] COND TRUE \read(tmp___3) [L743] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L374] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L187] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L177] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L179] t3_pc = 1 [L180] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND TRUE \read(tmp_ndt_5) [L542] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L201] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L204] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L220] E_5 = 1 [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L269] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L270] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L288] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L289] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L307] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L308] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L326] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L327] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L342] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L345] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L346] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L355] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L357] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L361] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L364] COND TRUE t5_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L365] COND TRUE E_5 == 1 [L366] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L376] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=2] [L748] tmp___4 = is_transmit5_triggered() [L750] COND TRUE \read(tmp___4) [L751] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L222] E_5 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L212] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L214] t4_pc = 1 [L215] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=0] [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND TRUE \read(tmp_ndt_6) [L556] t5_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L236] COND FALSE !(t5_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L239] COND TRUE t5_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2, T5_E=2, t5_i=1, t5_pc=1, t5_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 486 locations, 1 error locations. Result: UNSAFE, OverallTime: 346.8s, OverallIterations: 43, TraceHistogramMax: 2, AutomataDifference: 179.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 30896 SDtfs, 29124 SDslu, 20042 SDs, 0 SdLazy, 931 SolverSat, 486 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 140 GetRequests, 74 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=287414occurred in iteration=31, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 163.8s AutomataMinimizationTime, 42 MinimizatonAttempts, 753374 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 6634 NumberOfCodeBlocks, 6634 NumberOfCodeBlocksAsserted, 43 NumberOfCheckSat, 6240 ConstructedInterpolants, 0 QuantifiedInterpolants, 1667330 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 42 InterpolantComputations, 42 PerfectInterpolantSequences, 495/495 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...