./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0e3598d1a4e9129bf22e72269576449e67f0febd ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 16:24:03,609 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 16:24:03,611 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 16:24:03,618 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 16:24:03,618 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 16:24:03,619 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 16:24:03,620 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 16:24:03,622 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 16:24:03,624 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 16:24:03,625 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 16:24:03,625 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 16:24:03,626 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 16:24:03,627 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 16:24:03,628 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 16:24:03,628 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 16:24:03,629 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 16:24:03,630 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 16:24:03,631 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 16:24:03,632 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 16:24:03,633 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 16:24:03,634 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 16:24:03,635 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 16:24:03,636 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 16:24:03,636 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 16:24:03,638 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 16:24:03,638 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 16:24:03,638 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 16:24:03,638 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 16:24:03,639 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 16:24:03,639 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 16:24:03,639 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 16:24:03,640 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 16:24:03,641 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 16:24:03,641 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 16:24:03,642 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 16:24:03,642 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 16:24:03,643 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 16:24:03,643 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 16:24:03,643 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 16:24:03,644 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 16:24:03,644 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 16:24:03,645 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 16:24:03,657 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 16:24:03,657 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 16:24:03,658 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 16:24:03,658 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 16:24:03,658 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 16:24:03,659 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 16:24:03,659 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 16:24:03,660 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 16:24:03,660 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 16:24:03,660 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 16:24:03,660 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 16:24:03,660 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 16:24:03,660 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:24:03,661 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 16:24:03,661 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 16:24:03,662 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 16:24:03,662 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 16:24:03,662 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 16:24:03,662 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0e3598d1a4e9129bf22e72269576449e67f0febd [2019-12-07 16:24:03,769 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 16:24:03,779 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 16:24:03,782 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 16:24:03,783 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 16:24:03,783 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 16:24:03,784 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-12-07 16:24:03,829 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/data/61cab96dd/8adbddedc39b47778445e2a54f9b8c46/FLAG4ad4e89b4 [2019-12-07 16:24:04,178 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 16:24:04,178 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/sv-benchmarks/c/systemc/transmitter.15.cil.c [2019-12-07 16:24:04,188 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/data/61cab96dd/8adbddedc39b47778445e2a54f9b8c46/FLAG4ad4e89b4 [2019-12-07 16:24:04,197 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/data/61cab96dd/8adbddedc39b47778445e2a54f9b8c46 [2019-12-07 16:24:04,199 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 16:24:04,200 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 16:24:04,201 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 16:24:04,201 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 16:24:04,203 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 16:24:04,203 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,205 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13d86038 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04, skipping insertion in model container [2019-12-07 16:24:04,205 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,210 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 16:24:04,241 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 16:24:04,448 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:24:04,453 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 16:24:04,503 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 16:24:04,524 INFO L208 MainTranslator]: Completed translation [2019-12-07 16:24:04,524 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04 WrapperNode [2019-12-07 16:24:04,524 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 16:24:04,525 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 16:24:04,525 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 16:24:04,525 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 16:24:04,530 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,539 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,603 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 16:24:04,604 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 16:24:04,604 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 16:24:04,604 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 16:24:04,610 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,610 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,620 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,620 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,649 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,677 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,686 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... [2019-12-07 16:24:04,696 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 16:24:04,696 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 16:24:04,696 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 16:24:04,696 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 16:24:04,697 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 16:24:04,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 16:24:04,737 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 16:24:06,386 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 16:24:06,387 INFO L287 CfgBuilder]: Removed 589 assume(true) statements. [2019-12-07 16:24:06,388 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:24:06 BoogieIcfgContainer [2019-12-07 16:24:06,388 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 16:24:06,389 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 16:24:06,389 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 16:24:06,391 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 16:24:06,391 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 04:24:04" (1/3) ... [2019-12-07 16:24:06,391 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@412a61af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:24:06, skipping insertion in model container [2019-12-07 16:24:06,391 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 04:24:04" (2/3) ... [2019-12-07 16:24:06,392 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@412a61af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 04:24:06, skipping insertion in model container [2019-12-07 16:24:06,392 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:24:06" (3/3) ... [2019-12-07 16:24:06,393 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2019-12-07 16:24:06,399 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 16:24:06,404 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 16:24:06,411 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-12-07 16:24:06,441 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 16:24:06,441 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 16:24:06,441 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 16:24:06,441 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 16:24:06,442 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 16:24:06,442 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 16:24:06,442 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 16:24:06,442 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 16:24:06,472 INFO L276 IsEmpty]: Start isEmpty. Operand 1886 states. [2019-12-07 16:24:06,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:06,483 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:06,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:06,484 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:06,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:06,487 INFO L82 PathProgramCache]: Analyzing trace with hash 735925127, now seen corresponding path program 1 times [2019-12-07 16:24:06,493 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:06,493 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938835274] [2019-12-07 16:24:06,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:06,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:06,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:06,675 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938835274] [2019-12-07 16:24:06,676 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:06,676 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:06,677 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825030042] [2019-12-07 16:24:06,681 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:06,682 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:06,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:06,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:06,692 INFO L87 Difference]: Start difference. First operand 1886 states. Second operand 3 states. [2019-12-07 16:24:06,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:06,799 INFO L93 Difference]: Finished difference Result 3767 states and 5677 transitions. [2019-12-07 16:24:06,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:06,800 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:06,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:06,825 INFO L225 Difference]: With dead ends: 3767 [2019-12-07 16:24:06,825 INFO L226 Difference]: Without dead ends: 1882 [2019-12-07 16:24:06,833 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:06,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-12-07 16:24:06,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-12-07 16:24:06,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-12-07 16:24:06,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2802 transitions. [2019-12-07 16:24:06,933 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2802 transitions. Word has length 167 [2019-12-07 16:24:06,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:06,934 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2802 transitions. [2019-12-07 16:24:06,934 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:06,934 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2802 transitions. [2019-12-07 16:24:06,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:06,937 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:06,937 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:06,938 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:06,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:06,938 INFO L82 PathProgramCache]: Analyzing trace with hash 237368325, now seen corresponding path program 1 times [2019-12-07 16:24:06,938 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:06,938 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105378691] [2019-12-07 16:24:06,938 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:06,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:07,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:07,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105378691] [2019-12-07 16:24:07,044 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:07,044 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:07,044 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286110867] [2019-12-07 16:24:07,045 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:07,046 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:07,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:07,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,046 INFO L87 Difference]: Start difference. First operand 1882 states and 2802 transitions. Second operand 3 states. [2019-12-07 16:24:07,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:07,092 INFO L93 Difference]: Finished difference Result 3751 states and 5582 transitions. [2019-12-07 16:24:07,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:07,093 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:07,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:07,100 INFO L225 Difference]: With dead ends: 3751 [2019-12-07 16:24:07,100 INFO L226 Difference]: Without dead ends: 1882 [2019-12-07 16:24:07,103 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2019-12-07 16:24:07,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2019-12-07 16:24:07,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1882 states. [2019-12-07 16:24:07,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2801 transitions. [2019-12-07 16:24:07,142 INFO L78 Accepts]: Start accepts. Automaton has 1882 states and 2801 transitions. Word has length 167 [2019-12-07 16:24:07,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:07,142 INFO L462 AbstractCegarLoop]: Abstraction has 1882 states and 2801 transitions. [2019-12-07 16:24:07,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:07,142 INFO L276 IsEmpty]: Start isEmpty. Operand 1882 states and 2801 transitions. [2019-12-07 16:24:07,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:07,144 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:07,144 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:07,144 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:07,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:07,145 INFO L82 PathProgramCache]: Analyzing trace with hash 2006839939, now seen corresponding path program 1 times [2019-12-07 16:24:07,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:07,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41160835] [2019-12-07 16:24:07,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:07,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:07,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:07,204 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41160835] [2019-12-07 16:24:07,204 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:07,204 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:07,204 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942869409] [2019-12-07 16:24:07,205 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:07,205 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:07,205 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:07,205 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,205 INFO L87 Difference]: Start difference. First operand 1882 states and 2801 transitions. Second operand 3 states. [2019-12-07 16:24:07,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:07,343 INFO L93 Difference]: Finished difference Result 5360 states and 7953 transitions. [2019-12-07 16:24:07,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:07,343 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:07,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:07,357 INFO L225 Difference]: With dead ends: 5360 [2019-12-07 16:24:07,357 INFO L226 Difference]: Without dead ends: 3496 [2019-12-07 16:24:07,360 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3496 states. [2019-12-07 16:24:07,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3496 to 3494. [2019-12-07 16:24:07,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:07,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5163 transitions. [2019-12-07 16:24:07,437 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5163 transitions. Word has length 167 [2019-12-07 16:24:07,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:07,437 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5163 transitions. [2019-12-07 16:24:07,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:07,437 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5163 transitions. [2019-12-07 16:24:07,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:07,439 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:07,439 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:07,439 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:07,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:07,439 INFO L82 PathProgramCache]: Analyzing trace with hash -31533534, now seen corresponding path program 1 times [2019-12-07 16:24:07,439 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:07,440 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165879748] [2019-12-07 16:24:07,440 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:07,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:07,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:07,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165879748] [2019-12-07 16:24:07,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:07,482 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:07,482 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258422575] [2019-12-07 16:24:07,483 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:07,483 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:07,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:07,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,483 INFO L87 Difference]: Start difference. First operand 3494 states and 5163 transitions. Second operand 3 states. [2019-12-07 16:24:07,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:07,592 INFO L93 Difference]: Finished difference Result 6969 states and 10294 transitions. [2019-12-07 16:24:07,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:07,593 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:07,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:07,606 INFO L225 Difference]: With dead ends: 6969 [2019-12-07 16:24:07,606 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:07,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:07,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:07,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:07,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5155 transitions. [2019-12-07 16:24:07,698 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5155 transitions. Word has length 167 [2019-12-07 16:24:07,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:07,698 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5155 transitions. [2019-12-07 16:24:07,698 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:07,699 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5155 transitions. [2019-12-07 16:24:07,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:07,700 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:07,700 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:07,700 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:07,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:07,701 INFO L82 PathProgramCache]: Analyzing trace with hash -675030430, now seen corresponding path program 1 times [2019-12-07 16:24:07,701 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:07,701 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544314925] [2019-12-07 16:24:07,701 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:07,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:07,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:07,786 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544314925] [2019-12-07 16:24:07,786 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:07,786 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:07,786 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206857595] [2019-12-07 16:24:07,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:07,787 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:07,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:07,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,787 INFO L87 Difference]: Start difference. First operand 3494 states and 5155 transitions. Second operand 3 states. [2019-12-07 16:24:07,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:07,870 INFO L93 Difference]: Finished difference Result 6968 states and 10277 transitions. [2019-12-07 16:24:07,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:07,871 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:07,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:07,884 INFO L225 Difference]: With dead ends: 6968 [2019-12-07 16:24:07,884 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:07,889 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:07,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:07,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:07,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:07,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5147 transitions. [2019-12-07 16:24:07,968 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5147 transitions. Word has length 167 [2019-12-07 16:24:07,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:07,968 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5147 transitions. [2019-12-07 16:24:07,968 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:07,968 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5147 transitions. [2019-12-07 16:24:07,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:07,969 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:07,969 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:07,969 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:07,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:07,970 INFO L82 PathProgramCache]: Analyzing trace with hash -939677920, now seen corresponding path program 1 times [2019-12-07 16:24:07,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:07,970 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701513440] [2019-12-07 16:24:07,970 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:07,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:08,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:08,011 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701513440] [2019-12-07 16:24:08,011 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:08,012 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:08,012 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493345586] [2019-12-07 16:24:08,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:08,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:08,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:08,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,013 INFO L87 Difference]: Start difference. First operand 3494 states and 5147 transitions. Second operand 3 states. [2019-12-07 16:24:08,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:08,096 INFO L93 Difference]: Finished difference Result 6966 states and 10258 transitions. [2019-12-07 16:24:08,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:08,096 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:08,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:08,109 INFO L225 Difference]: With dead ends: 6966 [2019-12-07 16:24:08,110 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:08,114 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:08,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:08,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:08,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5139 transitions. [2019-12-07 16:24:08,192 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5139 transitions. Word has length 167 [2019-12-07 16:24:08,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:08,192 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5139 transitions. [2019-12-07 16:24:08,192 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:08,192 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5139 transitions. [2019-12-07 16:24:08,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:08,193 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:08,193 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:08,194 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:08,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:08,194 INFO L82 PathProgramCache]: Analyzing trace with hash 1188104928, now seen corresponding path program 1 times [2019-12-07 16:24:08,194 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:08,194 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107334386] [2019-12-07 16:24:08,194 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:08,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:08,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:08,227 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107334386] [2019-12-07 16:24:08,227 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:08,227 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:08,228 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644001944] [2019-12-07 16:24:08,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:08,228 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:08,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:08,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,229 INFO L87 Difference]: Start difference. First operand 3494 states and 5139 transitions. Second operand 3 states. [2019-12-07 16:24:08,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:08,338 INFO L93 Difference]: Finished difference Result 6965 states and 10241 transitions. [2019-12-07 16:24:08,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:08,339 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:08,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:08,352 INFO L225 Difference]: With dead ends: 6965 [2019-12-07 16:24:08,352 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:08,355 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:08,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:08,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:08,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5131 transitions. [2019-12-07 16:24:08,436 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5131 transitions. Word has length 167 [2019-12-07 16:24:08,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:08,436 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5131 transitions. [2019-12-07 16:24:08,436 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:08,436 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5131 transitions. [2019-12-07 16:24:08,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:08,438 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:08,438 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:08,438 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:08,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:08,438 INFO L82 PathProgramCache]: Analyzing trace with hash 841101088, now seen corresponding path program 1 times [2019-12-07 16:24:08,438 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:08,439 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387377035] [2019-12-07 16:24:08,439 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:08,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:08,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:08,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387377035] [2019-12-07 16:24:08,472 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:08,472 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:08,472 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280700660] [2019-12-07 16:24:08,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:08,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:08,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:08,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,473 INFO L87 Difference]: Start difference. First operand 3494 states and 5131 transitions. Second operand 3 states. [2019-12-07 16:24:08,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:08,553 INFO L93 Difference]: Finished difference Result 6964 states and 10224 transitions. [2019-12-07 16:24:08,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:08,553 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:08,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:08,566 INFO L225 Difference]: With dead ends: 6964 [2019-12-07 16:24:08,566 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:08,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:08,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:08,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:08,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5123 transitions. [2019-12-07 16:24:08,650 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5123 transitions. Word has length 167 [2019-12-07 16:24:08,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:08,650 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5123 transitions. [2019-12-07 16:24:08,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:08,650 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5123 transitions. [2019-12-07 16:24:08,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:08,651 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:08,651 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:08,651 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:08,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:08,652 INFO L82 PathProgramCache]: Analyzing trace with hash 1107002080, now seen corresponding path program 1 times [2019-12-07 16:24:08,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:08,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230278369] [2019-12-07 16:24:08,652 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:08,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:08,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:08,683 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230278369] [2019-12-07 16:24:08,683 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:08,683 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:08,683 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106010129] [2019-12-07 16:24:08,683 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:08,683 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:08,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:08,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,684 INFO L87 Difference]: Start difference. First operand 3494 states and 5123 transitions. Second operand 3 states. [2019-12-07 16:24:08,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:08,765 INFO L93 Difference]: Finished difference Result 6963 states and 10207 transitions. [2019-12-07 16:24:08,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:08,766 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:08,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:08,771 INFO L225 Difference]: With dead ends: 6963 [2019-12-07 16:24:08,772 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:08,776 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:08,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:08,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:08,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5115 transitions. [2019-12-07 16:24:08,858 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5115 transitions. Word has length 167 [2019-12-07 16:24:08,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:08,858 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5115 transitions. [2019-12-07 16:24:08,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:08,858 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5115 transitions. [2019-12-07 16:24:08,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:08,859 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:08,859 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:08,859 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:08,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:08,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1808316192, now seen corresponding path program 1 times [2019-12-07 16:24:08,860 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:08,860 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49976255] [2019-12-07 16:24:08,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:08,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:08,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:08,900 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49976255] [2019-12-07 16:24:08,901 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:08,901 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:08,901 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019171134] [2019-12-07 16:24:08,902 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:08,902 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:08,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:08,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:08,902 INFO L87 Difference]: Start difference. First operand 3494 states and 5115 transitions. Second operand 3 states. [2019-12-07 16:24:09,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:09,042 INFO L93 Difference]: Finished difference Result 6962 states and 10190 transitions. [2019-12-07 16:24:09,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:09,043 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:09,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:09,049 INFO L225 Difference]: With dead ends: 6962 [2019-12-07 16:24:09,049 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:09,054 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:09,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:09,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:09,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5107 transitions. [2019-12-07 16:24:09,128 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5107 transitions. Word has length 167 [2019-12-07 16:24:09,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:09,129 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5107 transitions. [2019-12-07 16:24:09,129 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:09,129 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5107 transitions. [2019-12-07 16:24:09,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:09,130 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:09,130 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:09,130 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:09,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:09,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1969486560, now seen corresponding path program 1 times [2019-12-07 16:24:09,131 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:09,131 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905060683] [2019-12-07 16:24:09,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:09,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:09,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:09,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905060683] [2019-12-07 16:24:09,162 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:09,162 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:09,162 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42107950] [2019-12-07 16:24:09,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:09,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:09,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:09,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,163 INFO L87 Difference]: Start difference. First operand 3494 states and 5107 transitions. Second operand 3 states. [2019-12-07 16:24:09,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:09,263 INFO L93 Difference]: Finished difference Result 6961 states and 10173 transitions. [2019-12-07 16:24:09,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:09,264 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:09,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:09,268 INFO L225 Difference]: With dead ends: 6961 [2019-12-07 16:24:09,268 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:09,272 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:09,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:09,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:09,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5099 transitions. [2019-12-07 16:24:09,339 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5099 transitions. Word has length 167 [2019-12-07 16:24:09,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:09,339 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5099 transitions. [2019-12-07 16:24:09,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:09,339 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5099 transitions. [2019-12-07 16:24:09,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:09,340 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:09,340 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:09,341 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:09,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:09,341 INFO L82 PathProgramCache]: Analyzing trace with hash 1836138272, now seen corresponding path program 1 times [2019-12-07 16:24:09,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:09,341 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417620272] [2019-12-07 16:24:09,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:09,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:09,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:09,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417620272] [2019-12-07 16:24:09,371 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:09,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:09,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197166441] [2019-12-07 16:24:09,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:09,372 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:09,372 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:09,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,372 INFO L87 Difference]: Start difference. First operand 3494 states and 5099 transitions. Second operand 3 states. [2019-12-07 16:24:09,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:09,475 INFO L93 Difference]: Finished difference Result 6960 states and 10156 transitions. [2019-12-07 16:24:09,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:09,475 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:09,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:09,481 INFO L225 Difference]: With dead ends: 6960 [2019-12-07 16:24:09,481 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:09,486 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:09,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:09,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:09,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5091 transitions. [2019-12-07 16:24:09,571 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5091 transitions. Word has length 167 [2019-12-07 16:24:09,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:09,571 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5091 transitions. [2019-12-07 16:24:09,571 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:09,571 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5091 transitions. [2019-12-07 16:24:09,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:09,572 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:09,572 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:09,572 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:09,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:09,572 INFO L82 PathProgramCache]: Analyzing trace with hash -2048218658, now seen corresponding path program 1 times [2019-12-07 16:24:09,573 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:09,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576950602] [2019-12-07 16:24:09,573 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:09,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:09,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:09,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1576950602] [2019-12-07 16:24:09,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:09,604 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:09,604 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206131957] [2019-12-07 16:24:09,604 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:09,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:09,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:09,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,604 INFO L87 Difference]: Start difference. First operand 3494 states and 5091 transitions. Second operand 3 states. [2019-12-07 16:24:09,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:09,731 INFO L93 Difference]: Finished difference Result 6958 states and 10137 transitions. [2019-12-07 16:24:09,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:09,731 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:09,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:09,737 INFO L225 Difference]: With dead ends: 6958 [2019-12-07 16:24:09,737 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:09,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:09,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:09,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:09,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5083 transitions. [2019-12-07 16:24:09,818 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5083 transitions. Word has length 167 [2019-12-07 16:24:09,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:09,818 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5083 transitions. [2019-12-07 16:24:09,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:09,819 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5083 transitions. [2019-12-07 16:24:09,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:09,820 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:09,820 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:09,820 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:09,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:09,820 INFO L82 PathProgramCache]: Analyzing trace with hash 2034093470, now seen corresponding path program 1 times [2019-12-07 16:24:09,820 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:09,820 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225121320] [2019-12-07 16:24:09,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:09,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:09,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:09,862 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225121320] [2019-12-07 16:24:09,862 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:09,862 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:09,862 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955857201] [2019-12-07 16:24:09,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:09,863 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:09,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:09,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,863 INFO L87 Difference]: Start difference. First operand 3494 states and 5083 transitions. Second operand 3 states. [2019-12-07 16:24:09,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:09,973 INFO L93 Difference]: Finished difference Result 6957 states and 10120 transitions. [2019-12-07 16:24:09,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:09,974 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:09,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:09,978 INFO L225 Difference]: With dead ends: 6957 [2019-12-07 16:24:09,978 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:09,982 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:09,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:10,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:10,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:10,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5075 transitions. [2019-12-07 16:24:10,053 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5075 transitions. Word has length 167 [2019-12-07 16:24:10,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:10,053 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5075 transitions. [2019-12-07 16:24:10,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:10,053 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5075 transitions. [2019-12-07 16:24:10,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:10,054 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:10,055 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:10,055 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:10,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:10,055 INFO L82 PathProgramCache]: Analyzing trace with hash -2129186338, now seen corresponding path program 1 times [2019-12-07 16:24:10,055 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:10,055 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200602715] [2019-12-07 16:24:10,055 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:10,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:10,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:10,096 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200602715] [2019-12-07 16:24:10,096 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:10,096 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:10,096 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542196487] [2019-12-07 16:24:10,096 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:10,097 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:10,097 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:10,097 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,097 INFO L87 Difference]: Start difference. First operand 3494 states and 5075 transitions. Second operand 3 states. [2019-12-07 16:24:10,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:10,206 INFO L93 Difference]: Finished difference Result 6956 states and 10103 transitions. [2019-12-07 16:24:10,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:10,207 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:10,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:10,211 INFO L225 Difference]: With dead ends: 6956 [2019-12-07 16:24:10,211 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:10,214 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:10,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:10,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:10,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5039 transitions. [2019-12-07 16:24:10,287 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5039 transitions. Word has length 167 [2019-12-07 16:24:10,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:10,288 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5039 transitions. [2019-12-07 16:24:10,288 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:10,288 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5039 transitions. [2019-12-07 16:24:10,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:10,289 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:10,289 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:10,289 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:10,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:10,290 INFO L82 PathProgramCache]: Analyzing trace with hash 904313021, now seen corresponding path program 1 times [2019-12-07 16:24:10,290 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:10,290 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459717174] [2019-12-07 16:24:10,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:10,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:10,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:10,323 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459717174] [2019-12-07 16:24:10,323 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:10,323 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:10,323 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245810762] [2019-12-07 16:24:10,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:10,324 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:10,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:10,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,324 INFO L87 Difference]: Start difference. First operand 3494 states and 5039 transitions. Second operand 3 states. [2019-12-07 16:24:10,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:10,463 INFO L93 Difference]: Finished difference Result 6955 states and 10030 transitions. [2019-12-07 16:24:10,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:10,464 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:10,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:10,468 INFO L225 Difference]: With dead ends: 6955 [2019-12-07 16:24:10,468 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:10,472 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:10,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:10,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:10,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 5003 transitions. [2019-12-07 16:24:10,576 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 5003 transitions. Word has length 167 [2019-12-07 16:24:10,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:10,576 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 5003 transitions. [2019-12-07 16:24:10,576 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:10,576 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 5003 transitions. [2019-12-07 16:24:10,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:10,577 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:10,577 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:10,578 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:10,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:10,578 INFO L82 PathProgramCache]: Analyzing trace with hash -2125714179, now seen corresponding path program 1 times [2019-12-07 16:24:10,578 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:10,578 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403006707] [2019-12-07 16:24:10,578 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:10,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:10,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:10,641 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403006707] [2019-12-07 16:24:10,641 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:10,641 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:10,641 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385804666] [2019-12-07 16:24:10,642 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:10,642 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:10,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:10,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,642 INFO L87 Difference]: Start difference. First operand 3494 states and 5003 transitions. Second operand 3 states. [2019-12-07 16:24:10,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:10,761 INFO L93 Difference]: Finished difference Result 6954 states and 9957 transitions. [2019-12-07 16:24:10,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:10,762 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:10,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:10,767 INFO L225 Difference]: With dead ends: 6954 [2019-12-07 16:24:10,767 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:10,771 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:10,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:10,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:10,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4967 transitions. [2019-12-07 16:24:10,850 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4967 transitions. Word has length 167 [2019-12-07 16:24:10,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:10,850 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4967 transitions. [2019-12-07 16:24:10,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:10,850 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4967 transitions. [2019-12-07 16:24:10,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:10,851 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:10,852 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:10,852 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:10,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:10,852 INFO L82 PathProgramCache]: Analyzing trace with hash 1803688540, now seen corresponding path program 1 times [2019-12-07 16:24:10,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:10,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535306173] [2019-12-07 16:24:10,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:10,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:10,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:10,887 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535306173] [2019-12-07 16:24:10,888 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:10,888 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:10,888 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48112997] [2019-12-07 16:24:10,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:10,888 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:10,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:10,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:10,889 INFO L87 Difference]: Start difference. First operand 3494 states and 4967 transitions. Second operand 3 states. [2019-12-07 16:24:11,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:11,017 INFO L93 Difference]: Finished difference Result 6953 states and 9884 transitions. [2019-12-07 16:24:11,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:11,017 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:11,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:11,021 INFO L225 Difference]: With dead ends: 6953 [2019-12-07 16:24:11,021 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:11,025 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:11,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:11,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:11,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4931 transitions. [2019-12-07 16:24:11,102 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4931 transitions. Word has length 167 [2019-12-07 16:24:11,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:11,103 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4931 transitions. [2019-12-07 16:24:11,103 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:11,103 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4931 transitions. [2019-12-07 16:24:11,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:11,104 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:11,104 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:11,104 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:11,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:11,104 INFO L82 PathProgramCache]: Analyzing trace with hash -1908957540, now seen corresponding path program 1 times [2019-12-07 16:24:11,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:11,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260394816] [2019-12-07 16:24:11,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:11,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:11,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:11,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260394816] [2019-12-07 16:24:11,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:11,140 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:11,140 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998715745] [2019-12-07 16:24:11,140 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:11,140 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:11,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:11,141 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,141 INFO L87 Difference]: Start difference. First operand 3494 states and 4931 transitions. Second operand 3 states. [2019-12-07 16:24:11,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:11,281 INFO L93 Difference]: Finished difference Result 6952 states and 9811 transitions. [2019-12-07 16:24:11,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:11,282 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:11,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:11,287 INFO L225 Difference]: With dead ends: 6952 [2019-12-07 16:24:11,287 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:11,291 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:11,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:11,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:11,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4895 transitions. [2019-12-07 16:24:11,376 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4895 transitions. Word has length 167 [2019-12-07 16:24:11,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:11,376 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4895 transitions. [2019-12-07 16:24:11,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:11,377 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4895 transitions. [2019-12-07 16:24:11,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:11,377 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:11,377 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:11,377 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:11,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:11,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1048299385, now seen corresponding path program 1 times [2019-12-07 16:24:11,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:11,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053046812] [2019-12-07 16:24:11,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:11,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:11,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:11,415 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053046812] [2019-12-07 16:24:11,416 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:11,416 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:11,416 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204480362] [2019-12-07 16:24:11,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:11,416 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:11,417 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:11,417 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,417 INFO L87 Difference]: Start difference. First operand 3494 states and 4895 transitions. Second operand 3 states. [2019-12-07 16:24:11,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:11,544 INFO L93 Difference]: Finished difference Result 6950 states and 9736 transitions. [2019-12-07 16:24:11,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:11,544 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:11,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:11,551 INFO L225 Difference]: With dead ends: 6950 [2019-12-07 16:24:11,551 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:11,554 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:11,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:11,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:11,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4859 transitions. [2019-12-07 16:24:11,634 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4859 transitions. Word has length 167 [2019-12-07 16:24:11,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:11,634 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4859 transitions. [2019-12-07 16:24:11,634 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:11,634 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4859 transitions. [2019-12-07 16:24:11,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:11,634 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:11,635 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:11,635 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:11,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:11,635 INFO L82 PathProgramCache]: Analyzing trace with hash 1051443672, now seen corresponding path program 1 times [2019-12-07 16:24:11,635 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:11,635 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549419822] [2019-12-07 16:24:11,635 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:11,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:11,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:11,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549419822] [2019-12-07 16:24:11,665 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:11,665 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:11,665 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75718736] [2019-12-07 16:24:11,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:11,665 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:11,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:11,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,665 INFO L87 Difference]: Start difference. First operand 3494 states and 4859 transitions. Second operand 3 states. [2019-12-07 16:24:11,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:11,806 INFO L93 Difference]: Finished difference Result 6949 states and 9663 transitions. [2019-12-07 16:24:11,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:11,806 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:11,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:11,812 INFO L225 Difference]: With dead ends: 6949 [2019-12-07 16:24:11,812 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:11,816 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:11,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:11,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:11,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4823 transitions. [2019-12-07 16:24:11,928 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4823 transitions. Word has length 167 [2019-12-07 16:24:11,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:11,928 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4823 transitions. [2019-12-07 16:24:11,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:11,928 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4823 transitions. [2019-12-07 16:24:11,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:11,929 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:11,929 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:11,929 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:11,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:11,929 INFO L82 PathProgramCache]: Analyzing trace with hash -1890753000, now seen corresponding path program 1 times [2019-12-07 16:24:11,929 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:11,929 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111084602] [2019-12-07 16:24:11,929 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:11,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:11,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:11,963 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111084602] [2019-12-07 16:24:11,963 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:11,964 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:11,964 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974224695] [2019-12-07 16:24:11,964 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:11,964 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:11,964 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:11,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:11,965 INFO L87 Difference]: Start difference. First operand 3494 states and 4823 transitions. Second operand 3 states. [2019-12-07 16:24:12,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:12,068 INFO L93 Difference]: Finished difference Result 6948 states and 9590 transitions. [2019-12-07 16:24:12,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:12,069 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:12,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:12,071 INFO L225 Difference]: With dead ends: 6948 [2019-12-07 16:24:12,071 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:12,074 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:12,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:12,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:12,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4787 transitions. [2019-12-07 16:24:12,150 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4787 transitions. Word has length 167 [2019-12-07 16:24:12,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:12,150 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4787 transitions. [2019-12-07 16:24:12,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:12,150 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4787 transitions. [2019-12-07 16:24:12,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:12,151 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:12,151 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:12,151 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:12,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:12,152 INFO L82 PathProgramCache]: Analyzing trace with hash 2068907767, now seen corresponding path program 1 times [2019-12-07 16:24:12,152 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:12,152 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237335680] [2019-12-07 16:24:12,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:12,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:12,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:12,181 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237335680] [2019-12-07 16:24:12,181 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:12,181 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:12,181 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275169311] [2019-12-07 16:24:12,182 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:12,182 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:12,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:12,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,182 INFO L87 Difference]: Start difference. First operand 3494 states and 4787 transitions. Second operand 3 states. [2019-12-07 16:24:12,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:12,297 INFO L93 Difference]: Finished difference Result 6947 states and 9517 transitions. [2019-12-07 16:24:12,297 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:12,297 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:12,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:12,299 INFO L225 Difference]: With dead ends: 6947 [2019-12-07 16:24:12,299 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:12,301 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:12,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:12,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:12,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4751 transitions. [2019-12-07 16:24:12,414 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4751 transitions. Word has length 167 [2019-12-07 16:24:12,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:12,414 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4751 transitions. [2019-12-07 16:24:12,414 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:12,414 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4751 transitions. [2019-12-07 16:24:12,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:12,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:12,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:12,416 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:12,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:12,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1861907562, now seen corresponding path program 1 times [2019-12-07 16:24:12,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:12,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954926994] [2019-12-07 16:24:12,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:12,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:12,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:12,473 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954926994] [2019-12-07 16:24:12,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:12,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:12,474 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679942763] [2019-12-07 16:24:12,474 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:12,474 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:12,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:12,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,475 INFO L87 Difference]: Start difference. First operand 3494 states and 4751 transitions. Second operand 3 states. [2019-12-07 16:24:12,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:12,596 INFO L93 Difference]: Finished difference Result 6946 states and 9444 transitions. [2019-12-07 16:24:12,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:12,597 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:12,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:12,599 INFO L225 Difference]: With dead ends: 6946 [2019-12-07 16:24:12,599 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:12,601 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:12,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:12,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:12,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4715 transitions. [2019-12-07 16:24:12,682 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4715 transitions. Word has length 167 [2019-12-07 16:24:12,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:12,682 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4715 transitions. [2019-12-07 16:24:12,682 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:12,682 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4715 transitions. [2019-12-07 16:24:12,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:12,683 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:12,683 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:12,683 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:12,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:12,683 INFO L82 PathProgramCache]: Analyzing trace with hash 723537750, now seen corresponding path program 1 times [2019-12-07 16:24:12,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:12,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004990576] [2019-12-07 16:24:12,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:12,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:12,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:12,721 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004990576] [2019-12-07 16:24:12,721 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:12,721 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:12,721 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520345146] [2019-12-07 16:24:12,722 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:12,722 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:12,722 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:12,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,722 INFO L87 Difference]: Start difference. First operand 3494 states and 4715 transitions. Second operand 3 states. [2019-12-07 16:24:12,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:12,832 INFO L93 Difference]: Finished difference Result 6945 states and 9371 transitions. [2019-12-07 16:24:12,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:12,833 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:12,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:12,835 INFO L225 Difference]: With dead ends: 6945 [2019-12-07 16:24:12,835 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:12,838 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:12,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:12,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:12,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4679 transitions. [2019-12-07 16:24:12,926 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4679 transitions. Word has length 167 [2019-12-07 16:24:12,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:12,926 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4679 transitions. [2019-12-07 16:24:12,926 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:12,926 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4679 transitions. [2019-12-07 16:24:12,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:12,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:12,927 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:12,927 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:12,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:12,927 INFO L82 PathProgramCache]: Analyzing trace with hash 1570454133, now seen corresponding path program 1 times [2019-12-07 16:24:12,927 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:12,927 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436662264] [2019-12-07 16:24:12,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:12,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:12,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:12,956 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436662264] [2019-12-07 16:24:12,956 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:12,956 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:12,956 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320975292] [2019-12-07 16:24:12,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:12,957 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:12,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:12,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:12,957 INFO L87 Difference]: Start difference. First operand 3494 states and 4679 transitions. Second operand 3 states. [2019-12-07 16:24:13,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:13,069 INFO L93 Difference]: Finished difference Result 6944 states and 9298 transitions. [2019-12-07 16:24:13,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:13,069 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:13,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:13,072 INFO L225 Difference]: With dead ends: 6944 [2019-12-07 16:24:13,072 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:13,075 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:13,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:13,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:13,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4643 transitions. [2019-12-07 16:24:13,163 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4643 transitions. Word has length 167 [2019-12-07 16:24:13,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:13,163 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4643 transitions. [2019-12-07 16:24:13,163 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:13,163 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4643 transitions. [2019-12-07 16:24:13,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:13,164 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:13,164 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:13,165 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:13,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:13,165 INFO L82 PathProgramCache]: Analyzing trace with hash -1777475277, now seen corresponding path program 1 times [2019-12-07 16:24:13,165 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:13,165 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218040373] [2019-12-07 16:24:13,165 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:13,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:13,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:13,222 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218040373] [2019-12-07 16:24:13,222 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:13,222 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:13,222 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099064513] [2019-12-07 16:24:13,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:13,223 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:13,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:13,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,223 INFO L87 Difference]: Start difference. First operand 3494 states and 4643 transitions. Second operand 3 states. [2019-12-07 16:24:13,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:13,317 INFO L93 Difference]: Finished difference Result 6967 states and 9252 transitions. [2019-12-07 16:24:13,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:13,318 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:13,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:13,320 INFO L225 Difference]: With dead ends: 6967 [2019-12-07 16:24:13,320 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:13,322 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:13,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:13,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:13,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4635 transitions. [2019-12-07 16:24:13,422 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4635 transitions. Word has length 167 [2019-12-07 16:24:13,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:13,423 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4635 transitions. [2019-12-07 16:24:13,423 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:13,423 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4635 transitions. [2019-12-07 16:24:13,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:13,423 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:13,424 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:13,424 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:13,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:13,424 INFO L82 PathProgramCache]: Analyzing trace with hash 2123125233, now seen corresponding path program 1 times [2019-12-07 16:24:13,424 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:13,424 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736472687] [2019-12-07 16:24:13,424 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:13,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:13,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:13,473 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736472687] [2019-12-07 16:24:13,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:13,473 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:13,473 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708673366] [2019-12-07 16:24:13,473 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:13,473 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:13,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:13,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,473 INFO L87 Difference]: Start difference. First operand 3494 states and 4635 transitions. Second operand 3 states. [2019-12-07 16:24:13,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:13,571 INFO L93 Difference]: Finished difference Result 6959 states and 9228 transitions. [2019-12-07 16:24:13,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:13,572 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:13,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:13,574 INFO L225 Difference]: With dead ends: 6959 [2019-12-07 16:24:13,574 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:13,576 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:13,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:13,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:13,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4627 transitions. [2019-12-07 16:24:13,671 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4627 transitions. Word has length 167 [2019-12-07 16:24:13,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:13,671 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4627 transitions. [2019-12-07 16:24:13,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:13,671 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4627 transitions. [2019-12-07 16:24:13,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:13,672 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:13,672 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:13,672 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:13,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:13,672 INFO L82 PathProgramCache]: Analyzing trace with hash 1613652143, now seen corresponding path program 1 times [2019-12-07 16:24:13,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:13,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001894035] [2019-12-07 16:24:13,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:13,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:13,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:13,725 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001894035] [2019-12-07 16:24:13,725 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:13,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 16:24:13,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017349066] [2019-12-07 16:24:13,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:13,725 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:13,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:13,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,726 INFO L87 Difference]: Start difference. First operand 3494 states and 4627 transitions. Second operand 3 states. [2019-12-07 16:24:13,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:13,862 INFO L93 Difference]: Finished difference Result 6951 states and 9204 transitions. [2019-12-07 16:24:13,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:13,862 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:13,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:13,864 INFO L225 Difference]: With dead ends: 6951 [2019-12-07 16:24:13,864 INFO L226 Difference]: Without dead ends: 3494 [2019-12-07 16:24:13,867 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:13,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2019-12-07 16:24:13,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3494. [2019-12-07 16:24:13,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3494 states. [2019-12-07 16:24:13,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3494 states to 3494 states and 4591 transitions. [2019-12-07 16:24:13,962 INFO L78 Accepts]: Start accepts. Automaton has 3494 states and 4591 transitions. Word has length 167 [2019-12-07 16:24:13,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:13,962 INFO L462 AbstractCegarLoop]: Abstraction has 3494 states and 4591 transitions. [2019-12-07 16:24:13,962 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:13,962 INFO L276 IsEmpty]: Start isEmpty. Operand 3494 states and 4591 transitions. [2019-12-07 16:24:13,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2019-12-07 16:24:13,963 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:13,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:13,963 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:13,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:13,963 INFO L82 PathProgramCache]: Analyzing trace with hash 796003693, now seen corresponding path program 1 times [2019-12-07 16:24:13,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:13,963 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694393417] [2019-12-07 16:24:13,963 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:13,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:14,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:14,005 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694393417] [2019-12-07 16:24:14,005 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:14,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 16:24:14,006 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779929107] [2019-12-07 16:24:14,006 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 16:24:14,006 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:14,006 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 16:24:14,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:14,006 INFO L87 Difference]: Start difference. First operand 3494 states and 4591 transitions. Second operand 3 states. [2019-12-07 16:24:14,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:14,221 INFO L93 Difference]: Finished difference Result 10209 states and 13370 transitions. [2019-12-07 16:24:14,221 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 16:24:14,221 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 167 [2019-12-07 16:24:14,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:14,226 INFO L225 Difference]: With dead ends: 10209 [2019-12-07 16:24:14,226 INFO L226 Difference]: Without dead ends: 6884 [2019-12-07 16:24:14,230 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 16:24:14,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6884 states. [2019-12-07 16:24:14,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6884 to 6694. [2019-12-07 16:24:14,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6694 states. [2019-12-07 16:24:14,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6694 states to 6694 states and 8737 transitions. [2019-12-07 16:24:14,530 INFO L78 Accepts]: Start accepts. Automaton has 6694 states and 8737 transitions. Word has length 167 [2019-12-07 16:24:14,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:14,530 INFO L462 AbstractCegarLoop]: Abstraction has 6694 states and 8737 transitions. [2019-12-07 16:24:14,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 16:24:14,530 INFO L276 IsEmpty]: Start isEmpty. Operand 6694 states and 8737 transitions. [2019-12-07 16:24:14,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:14,531 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:14,531 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:14,531 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:14,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:14,531 INFO L82 PathProgramCache]: Analyzing trace with hash -1437788242, now seen corresponding path program 1 times [2019-12-07 16:24:14,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:14,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919989804] [2019-12-07 16:24:14,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:14,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:14,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:14,591 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919989804] [2019-12-07 16:24:14,591 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:14,591 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:14,591 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192461813] [2019-12-07 16:24:14,592 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:14,592 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:14,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:14,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:14,592 INFO L87 Difference]: Start difference. First operand 6694 states and 8737 transitions. Second operand 5 states. [2019-12-07 16:24:15,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:15,192 INFO L93 Difference]: Finished difference Result 18864 states and 24680 transitions. [2019-12-07 16:24:15,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:15,192 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:15,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:15,200 INFO L225 Difference]: With dead ends: 18864 [2019-12-07 16:24:15,200 INFO L226 Difference]: Without dead ends: 12386 [2019-12-07 16:24:15,206 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:15,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12386 states. [2019-12-07 16:24:15,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12386 to 6781. [2019-12-07 16:24:15,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6781 states. [2019-12-07 16:24:15,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6781 states to 6781 states and 8795 transitions. [2019-12-07 16:24:15,508 INFO L78 Accepts]: Start accepts. Automaton has 6781 states and 8795 transitions. Word has length 168 [2019-12-07 16:24:15,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:15,509 INFO L462 AbstractCegarLoop]: Abstraction has 6781 states and 8795 transitions. [2019-12-07 16:24:15,509 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:15,509 INFO L276 IsEmpty]: Start isEmpty. Operand 6781 states and 8795 transitions. [2019-12-07 16:24:15,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:15,509 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:15,510 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:15,510 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:15,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:15,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1575006768, now seen corresponding path program 1 times [2019-12-07 16:24:15,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:15,510 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373015733] [2019-12-07 16:24:15,510 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:15,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:15,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:15,566 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373015733] [2019-12-07 16:24:15,566 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:15,566 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:15,567 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27666409] [2019-12-07 16:24:15,567 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:15,567 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:15,567 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:15,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:15,568 INFO L87 Difference]: Start difference. First operand 6781 states and 8795 transitions. Second operand 5 states. [2019-12-07 16:24:16,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:16,102 INFO L93 Difference]: Finished difference Result 15355 states and 20058 transitions. [2019-12-07 16:24:16,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:16,103 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:16,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:16,108 INFO L225 Difference]: With dead ends: 15355 [2019-12-07 16:24:16,108 INFO L226 Difference]: Without dead ends: 8686 [2019-12-07 16:24:16,112 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:16,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8686 states. [2019-12-07 16:24:16,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8686 to 6787. [2019-12-07 16:24:16,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6787 states. [2019-12-07 16:24:16,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6787 states to 6787 states and 8745 transitions. [2019-12-07 16:24:16,413 INFO L78 Accepts]: Start accepts. Automaton has 6787 states and 8745 transitions. Word has length 168 [2019-12-07 16:24:16,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:16,414 INFO L462 AbstractCegarLoop]: Abstraction has 6787 states and 8745 transitions. [2019-12-07 16:24:16,414 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:16,414 INFO L276 IsEmpty]: Start isEmpty. Operand 6787 states and 8745 transitions. [2019-12-07 16:24:16,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:16,414 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:16,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:16,415 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:16,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:16,415 INFO L82 PathProgramCache]: Analyzing trace with hash -992815566, now seen corresponding path program 1 times [2019-12-07 16:24:16,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:16,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480074999] [2019-12-07 16:24:16,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:16,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:16,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:16,463 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480074999] [2019-12-07 16:24:16,463 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:16,463 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:16,464 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788321304] [2019-12-07 16:24:16,464 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:16,464 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:16,464 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:16,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:16,464 INFO L87 Difference]: Start difference. First operand 6787 states and 8745 transitions. Second operand 5 states. [2019-12-07 16:24:17,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:17,030 INFO L93 Difference]: Finished difference Result 16335 states and 21156 transitions. [2019-12-07 16:24:17,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:17,031 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:17,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:17,036 INFO L225 Difference]: With dead ends: 16335 [2019-12-07 16:24:17,037 INFO L226 Difference]: Without dead ends: 9688 [2019-12-07 16:24:17,040 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:17,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9688 states. [2019-12-07 16:24:17,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9688 to 6799. [2019-12-07 16:24:17,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6799 states. [2019-12-07 16:24:17,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6799 states to 6799 states and 8703 transitions. [2019-12-07 16:24:17,480 INFO L78 Accepts]: Start accepts. Automaton has 6799 states and 8703 transitions. Word has length 168 [2019-12-07 16:24:17,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:17,480 INFO L462 AbstractCegarLoop]: Abstraction has 6799 states and 8703 transitions. [2019-12-07 16:24:17,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:17,480 INFO L276 IsEmpty]: Start isEmpty. Operand 6799 states and 8703 transitions. [2019-12-07 16:24:17,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:17,481 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:17,481 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:17,481 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:17,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:17,481 INFO L82 PathProgramCache]: Analyzing trace with hash 1995009332, now seen corresponding path program 1 times [2019-12-07 16:24:17,481 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:17,481 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899272804] [2019-12-07 16:24:17,481 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:17,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:17,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:17,528 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899272804] [2019-12-07 16:24:17,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:17,528 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:17,528 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975011466] [2019-12-07 16:24:17,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:17,529 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:17,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:17,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:17,529 INFO L87 Difference]: Start difference. First operand 6799 states and 8703 transitions. Second operand 5 states. [2019-12-07 16:24:18,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:18,173 INFO L93 Difference]: Finished difference Result 16679 states and 21436 transitions. [2019-12-07 16:24:18,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:18,173 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:18,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:18,179 INFO L225 Difference]: With dead ends: 16679 [2019-12-07 16:24:18,179 INFO L226 Difference]: Without dead ends: 10034 [2019-12-07 16:24:18,183 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:18,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10034 states. [2019-12-07 16:24:18,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10034 to 6811. [2019-12-07 16:24:18,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6811 states. [2019-12-07 16:24:18,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6811 states to 6811 states and 8661 transitions. [2019-12-07 16:24:18,563 INFO L78 Accepts]: Start accepts. Automaton has 6811 states and 8661 transitions. Word has length 168 [2019-12-07 16:24:18,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:18,563 INFO L462 AbstractCegarLoop]: Abstraction has 6811 states and 8661 transitions. [2019-12-07 16:24:18,563 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:18,563 INFO L276 IsEmpty]: Start isEmpty. Operand 6811 states and 8661 transitions. [2019-12-07 16:24:18,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:18,564 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:18,564 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:18,564 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:18,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:18,564 INFO L82 PathProgramCache]: Analyzing trace with hash -948572746, now seen corresponding path program 1 times [2019-12-07 16:24:18,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:18,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250165425] [2019-12-07 16:24:18,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:18,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:18,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:18,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250165425] [2019-12-07 16:24:18,618 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:18,618 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:18,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181572112] [2019-12-07 16:24:18,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:18,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:18,618 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:18,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:18,619 INFO L87 Difference]: Start difference. First operand 6811 states and 8661 transitions. Second operand 5 states. [2019-12-07 16:24:19,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:19,348 INFO L93 Difference]: Finished difference Result 17023 states and 21716 transitions. [2019-12-07 16:24:19,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:19,348 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:19,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:19,354 INFO L225 Difference]: With dead ends: 17023 [2019-12-07 16:24:19,354 INFO L226 Difference]: Without dead ends: 10380 [2019-12-07 16:24:19,357 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:19,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10380 states. [2019-12-07 16:24:19,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10380 to 6823. [2019-12-07 16:24:19,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6823 states. [2019-12-07 16:24:19,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6823 states to 6823 states and 8619 transitions. [2019-12-07 16:24:19,776 INFO L78 Accepts]: Start accepts. Automaton has 6823 states and 8619 transitions. Word has length 168 [2019-12-07 16:24:19,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:19,776 INFO L462 AbstractCegarLoop]: Abstraction has 6823 states and 8619 transitions. [2019-12-07 16:24:19,776 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:19,777 INFO L276 IsEmpty]: Start isEmpty. Operand 6823 states and 8619 transitions. [2019-12-07 16:24:19,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:19,777 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:19,777 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:19,777 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:19,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:19,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1719306312, now seen corresponding path program 1 times [2019-12-07 16:24:19,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:19,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147933366] [2019-12-07 16:24:19,778 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:19,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:19,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:19,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147933366] [2019-12-07 16:24:19,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:19,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:19,836 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738152828] [2019-12-07 16:24:19,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:19,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:19,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:19,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:19,837 INFO L87 Difference]: Start difference. First operand 6823 states and 8619 transitions. Second operand 5 states. [2019-12-07 16:24:20,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:20,703 INFO L93 Difference]: Finished difference Result 17367 states and 21996 transitions. [2019-12-07 16:24:20,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:20,703 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:20,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:20,711 INFO L225 Difference]: With dead ends: 17367 [2019-12-07 16:24:20,711 INFO L226 Difference]: Without dead ends: 10726 [2019-12-07 16:24:20,715 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:20,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10726 states. [2019-12-07 16:24:21,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10726 to 6835. [2019-12-07 16:24:21,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6835 states. [2019-12-07 16:24:21,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6835 states to 6835 states and 8577 transitions. [2019-12-07 16:24:21,211 INFO L78 Accepts]: Start accepts. Automaton has 6835 states and 8577 transitions. Word has length 168 [2019-12-07 16:24:21,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:21,211 INFO L462 AbstractCegarLoop]: Abstraction has 6835 states and 8577 transitions. [2019-12-07 16:24:21,211 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:21,211 INFO L276 IsEmpty]: Start isEmpty. Operand 6835 states and 8577 transitions. [2019-12-07 16:24:21,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:21,212 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:21,212 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:21,212 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:21,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:21,212 INFO L82 PathProgramCache]: Analyzing trace with hash -394450118, now seen corresponding path program 1 times [2019-12-07 16:24:21,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:21,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612453683] [2019-12-07 16:24:21,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:21,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:21,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:21,262 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612453683] [2019-12-07 16:24:21,262 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:21,263 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:21,263 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151052008] [2019-12-07 16:24:21,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:21,263 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:21,263 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:21,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:21,264 INFO L87 Difference]: Start difference. First operand 6835 states and 8577 transitions. Second operand 5 states. [2019-12-07 16:24:22,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:22,154 INFO L93 Difference]: Finished difference Result 17711 states and 22276 transitions. [2019-12-07 16:24:22,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:22,155 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:22,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:22,162 INFO L225 Difference]: With dead ends: 17711 [2019-12-07 16:24:22,162 INFO L226 Difference]: Without dead ends: 11072 [2019-12-07 16:24:22,166 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:22,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11072 states. [2019-12-07 16:24:22,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11072 to 6847. [2019-12-07 16:24:22,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6847 states. [2019-12-07 16:24:22,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6847 states to 6847 states and 8535 transitions. [2019-12-07 16:24:22,693 INFO L78 Accepts]: Start accepts. Automaton has 6847 states and 8535 transitions. Word has length 168 [2019-12-07 16:24:22,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:22,693 INFO L462 AbstractCegarLoop]: Abstraction has 6847 states and 8535 transitions. [2019-12-07 16:24:22,694 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:22,694 INFO L276 IsEmpty]: Start isEmpty. Operand 6847 states and 8535 transitions. [2019-12-07 16:24:22,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:22,694 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:22,694 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:22,694 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:22,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:22,695 INFO L82 PathProgramCache]: Analyzing trace with hash -367384516, now seen corresponding path program 1 times [2019-12-07 16:24:22,695 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:22,695 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849040486] [2019-12-07 16:24:22,695 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:22,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:22,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:22,746 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849040486] [2019-12-07 16:24:22,746 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:22,746 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:22,746 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455483445] [2019-12-07 16:24:22,747 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:22,747 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:22,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:22,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:22,747 INFO L87 Difference]: Start difference. First operand 6847 states and 8535 transitions. Second operand 5 states. [2019-12-07 16:24:23,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:23,726 INFO L93 Difference]: Finished difference Result 18055 states and 22556 transitions. [2019-12-07 16:24:23,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:23,727 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:23,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:23,734 INFO L225 Difference]: With dead ends: 18055 [2019-12-07 16:24:23,734 INFO L226 Difference]: Without dead ends: 11418 [2019-12-07 16:24:23,738 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:23,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11418 states. [2019-12-07 16:24:24,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11418 to 6859. [2019-12-07 16:24:24,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6859 states. [2019-12-07 16:24:24,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6859 states to 6859 states and 8493 transitions. [2019-12-07 16:24:24,283 INFO L78 Accepts]: Start accepts. Automaton has 6859 states and 8493 transitions. Word has length 168 [2019-12-07 16:24:24,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:24,284 INFO L462 AbstractCegarLoop]: Abstraction has 6859 states and 8493 transitions. [2019-12-07 16:24:24,284 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:24,284 INFO L276 IsEmpty]: Start isEmpty. Operand 6859 states and 8493 transitions. [2019-12-07 16:24:24,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:24,284 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:24,284 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:24,285 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:24,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:24,285 INFO L82 PathProgramCache]: Analyzing trace with hash -1334735170, now seen corresponding path program 1 times [2019-12-07 16:24:24,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:24,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814054807] [2019-12-07 16:24:24,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:24,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:24,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:24,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814054807] [2019-12-07 16:24:24,330 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:24,330 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:24,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245833273] [2019-12-07 16:24:24,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:24,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:24,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:24,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:24,331 INFO L87 Difference]: Start difference. First operand 6859 states and 8493 transitions. Second operand 5 states. [2019-12-07 16:24:25,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:25,475 INFO L93 Difference]: Finished difference Result 18399 states and 22836 transitions. [2019-12-07 16:24:25,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:25,475 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:25,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:25,482 INFO L225 Difference]: With dead ends: 18399 [2019-12-07 16:24:25,482 INFO L226 Difference]: Without dead ends: 11764 [2019-12-07 16:24:25,486 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:25,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11764 states. [2019-12-07 16:24:26,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11764 to 6871. [2019-12-07 16:24:26,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6871 states. [2019-12-07 16:24:26,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6871 states to 6871 states and 8451 transitions. [2019-12-07 16:24:26,082 INFO L78 Accepts]: Start accepts. Automaton has 6871 states and 8451 transitions. Word has length 168 [2019-12-07 16:24:26,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:26,082 INFO L462 AbstractCegarLoop]: Abstraction has 6871 states and 8451 transitions. [2019-12-07 16:24:26,082 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:26,082 INFO L276 IsEmpty]: Start isEmpty. Operand 6871 states and 8451 transitions. [2019-12-07 16:24:26,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:26,083 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:26,083 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:26,083 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:26,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:26,084 INFO L82 PathProgramCache]: Analyzing trace with hash 1274052288, now seen corresponding path program 1 times [2019-12-07 16:24:26,084 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:26,084 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786632115] [2019-12-07 16:24:26,084 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:26,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:26,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:26,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786632115] [2019-12-07 16:24:26,134 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:26,134 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:26,134 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507494161] [2019-12-07 16:24:26,134 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:26,135 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:26,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:26,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:26,135 INFO L87 Difference]: Start difference. First operand 6871 states and 8451 transitions. Second operand 5 states. [2019-12-07 16:24:27,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:27,315 INFO L93 Difference]: Finished difference Result 18743 states and 23116 transitions. [2019-12-07 16:24:27,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:27,315 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:27,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:27,323 INFO L225 Difference]: With dead ends: 18743 [2019-12-07 16:24:27,323 INFO L226 Difference]: Without dead ends: 12110 [2019-12-07 16:24:27,328 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:27,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12110 states. [2019-12-07 16:24:27,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12110 to 6883. [2019-12-07 16:24:27,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6883 states. [2019-12-07 16:24:27,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6883 states to 6883 states and 8409 transitions. [2019-12-07 16:24:27,961 INFO L78 Accepts]: Start accepts. Automaton has 6883 states and 8409 transitions. Word has length 168 [2019-12-07 16:24:27,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:27,962 INFO L462 AbstractCegarLoop]: Abstraction has 6883 states and 8409 transitions. [2019-12-07 16:24:27,962 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:27,962 INFO L276 IsEmpty]: Start isEmpty. Operand 6883 states and 8409 transitions. [2019-12-07 16:24:27,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:27,962 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:27,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:27,963 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:27,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:27,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1834752066, now seen corresponding path program 1 times [2019-12-07 16:24:27,963 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:27,963 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476107699] [2019-12-07 16:24:27,963 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:27,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:28,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:28,012 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476107699] [2019-12-07 16:24:28,012 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:28,012 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:28,012 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153899651] [2019-12-07 16:24:28,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:28,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:28,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:28,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:28,013 INFO L87 Difference]: Start difference. First operand 6883 states and 8409 transitions. Second operand 5 states. [2019-12-07 16:24:29,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:29,405 INFO L93 Difference]: Finished difference Result 19395 states and 23796 transitions. [2019-12-07 16:24:29,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:29,406 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:29,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:29,414 INFO L225 Difference]: With dead ends: 19395 [2019-12-07 16:24:29,414 INFO L226 Difference]: Without dead ends: 12778 [2019-12-07 16:24:29,417 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:29,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12778 states. [2019-12-07 16:24:30,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12778 to 6895. [2019-12-07 16:24:30,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6895 states. [2019-12-07 16:24:30,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6895 states to 6895 states and 8367 transitions. [2019-12-07 16:24:30,093 INFO L78 Accepts]: Start accepts. Automaton has 6895 states and 8367 transitions. Word has length 168 [2019-12-07 16:24:30,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:30,093 INFO L462 AbstractCegarLoop]: Abstraction has 6895 states and 8367 transitions. [2019-12-07 16:24:30,093 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:30,093 INFO L276 IsEmpty]: Start isEmpty. Operand 6895 states and 8367 transitions. [2019-12-07 16:24:30,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:30,094 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:30,094 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:30,094 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:30,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:30,094 INFO L82 PathProgramCache]: Analyzing trace with hash 1481663684, now seen corresponding path program 1 times [2019-12-07 16:24:30,094 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:30,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808173416] [2019-12-07 16:24:30,095 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:30,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 16:24:30,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 16:24:30,145 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808173416] [2019-12-07 16:24:30,146 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 16:24:30,146 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 16:24:30,146 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076215857] [2019-12-07 16:24:30,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 16:24:30,146 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 16:24:30,146 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 16:24:30,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 16:24:30,147 INFO L87 Difference]: Start difference. First operand 6895 states and 8367 transitions. Second operand 5 states. [2019-12-07 16:24:31,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 16:24:31,582 INFO L93 Difference]: Finished difference Result 19739 states and 24076 transitions. [2019-12-07 16:24:31,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 16:24:31,582 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 168 [2019-12-07 16:24:31,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 16:24:31,590 INFO L225 Difference]: With dead ends: 19739 [2019-12-07 16:24:31,590 INFO L226 Difference]: Without dead ends: 13124 [2019-12-07 16:24:31,593 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 16:24:31,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13124 states. [2019-12-07 16:24:32,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13124 to 6907. [2019-12-07 16:24:32,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6907 states. [2019-12-07 16:24:32,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6907 states to 6907 states and 8325 transitions. [2019-12-07 16:24:32,317 INFO L78 Accepts]: Start accepts. Automaton has 6907 states and 8325 transitions. Word has length 168 [2019-12-07 16:24:32,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 16:24:32,317 INFO L462 AbstractCegarLoop]: Abstraction has 6907 states and 8325 transitions. [2019-12-07 16:24:32,317 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 16:24:32,317 INFO L276 IsEmpty]: Start isEmpty. Operand 6907 states and 8325 transitions. [2019-12-07 16:24:32,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2019-12-07 16:24:32,318 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 16:24:32,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 16:24:32,318 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 16:24:32,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 16:24:32,319 INFO L82 PathProgramCache]: Analyzing trace with hash 1905310406, now seen corresponding path program 1 times [2019-12-07 16:24:32,319 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 16:24:32,319 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021684507] [2019-12-07 16:24:32,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 16:24:32,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:24:32,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 16:24:32,427 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 16:24:32,427 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 16:24:32,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 04:24:32 BoogieIcfgContainer [2019-12-07 16:24:32,581 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 16:24:32,581 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 16:24:32,581 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 16:24:32,581 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 16:24:32,581 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 04:24:06" (3/4) ... [2019-12-07 16:24:32,583 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 16:24:32,696 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_6cad1dd1-b458-493e-8622-044dcf206274/bin/uautomizer/witness.graphml [2019-12-07 16:24:32,696 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 16:24:32,698 INFO L168 Benchmark]: Toolchain (without parser) took 28497.76 ms. Allocated memory was 1.0 GB in the beginning and 3.4 GB in the end (delta: 2.4 GB). Free memory was 943.5 MB in the beginning and 2.2 GB in the end (delta: -1.3 GB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,698 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 16:24:32,698 INFO L168 Benchmark]: CACSL2BoogieTranslator took 324.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 105.4 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -145.8 MB). Peak memory consumption was 29.9 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,699 INFO L168 Benchmark]: Boogie Procedure Inliner took 78.65 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,699 INFO L168 Benchmark]: Boogie Preprocessor took 92.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,699 INFO L168 Benchmark]: RCFGBuilder took 1691.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 930.7 MB in the end (delta: 126.4 MB). Peak memory consumption was 235.1 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,699 INFO L168 Benchmark]: TraceAbstraction took 26191.78 ms. Allocated memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: 2.3 GB). Free memory was 925.5 MB in the beginning and 2.3 GB in the end (delta: -1.3 GB). Peak memory consumption was 919.2 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,700 INFO L168 Benchmark]: Witness Printer took 115.80 ms. Allocated memory is still 3.4 GB. Free memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: 66.7 MB). Peak memory consumption was 66.7 MB. Max. memory is 11.5 GB. [2019-12-07 16:24:32,701 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 324.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 105.4 MB). Free memory was 943.5 MB in the beginning and 1.1 GB in the end (delta: -145.8 MB). Peak memory consumption was 29.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 78.65 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 92.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1691.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 930.7 MB in the end (delta: 126.4 MB). Peak memory consumption was 235.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 26191.78 ms. Allocated memory was 1.1 GB in the beginning and 3.4 GB in the end (delta: 2.3 GB). Free memory was 925.5 MB in the beginning and 2.3 GB in the end (delta: -1.3 GB). Peak memory consumption was 919.2 MB. Max. memory is 11.5 GB. * Witness Printer took 115.80 ms. Allocated memory is still 3.4 GB. Free memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: 66.7 MB). Peak memory consumption was 66.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int t5_st ; [L35] int t6_st ; [L36] int t7_st ; [L37] int t8_st ; [L38] int t9_st ; [L39] int t10_st ; [L40] int t11_st ; [L41] int t12_st ; [L42] int t13_st ; [L43] int m_i ; [L44] int t1_i ; [L45] int t2_i ; [L46] int t3_i ; [L47] int t4_i ; [L48] int t5_i ; [L49] int t6_i ; [L50] int t7_i ; [L51] int t8_i ; [L52] int t9_i ; [L53] int t10_i ; [L54] int t11_i ; [L55] int t12_i ; [L56] int t13_i ; [L57] int M_E = 2; [L58] int T1_E = 2; [L59] int T2_E = 2; [L60] int T3_E = 2; [L61] int T4_E = 2; [L62] int T5_E = 2; [L63] int T6_E = 2; [L64] int T7_E = 2; [L65] int T8_E = 2; [L66] int T9_E = 2; [L67] int T10_E = 2; [L68] int T11_E = 2; [L69] int T12_E = 2; [L70] int T13_E = 2; [L71] int E_1 = 2; [L72] int E_2 = 2; [L73] int E_3 = 2; [L74] int E_4 = 2; [L75] int E_5 = 2; [L76] int E_6 = 2; [L77] int E_7 = 2; [L78] int E_8 = 2; [L79] int E_9 = 2; [L80] int E_10 = 2; [L81] int E_11 = 2; [L82] int E_12 = 2; [L83] int E_13 = 2; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=0, m_pc=0, m_st=0, T10_E=2, t10_i=0, t10_pc=0, t10_st=0, T11_E=2, t11_i=0, t11_pc=0, t11_st=0, T12_E=2, t12_i=0, t12_pc=0, t12_st=0, T13_E=2, t13_i=0, t13_pc=0, t13_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0, T8_E=2, t8_i=0, t8_pc=0, t8_st=0, T9_E=2, t9_i=0, t9_pc=0, t9_st=0] [L1927] int __retres1 ; [L1830] m_i = 1 [L1831] t1_i = 1 [L1832] t2_i = 1 [L1833] t3_i = 1 [L1834] t4_i = 1 [L1835] t5_i = 1 [L1836] t6_i = 1 [L1837] t7_i = 1 [L1838] t8_i = 1 [L1839] t9_i = 1 [L1840] t10_i = 1 [L1841] t11_i = 1 [L1842] t12_i = 1 [L1843] t13_i = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1868] int kernel_st ; [L1869] int tmp ; [L1870] int tmp___0 ; [L1874] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L871] COND TRUE m_i == 1 [L872] m_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] COND TRUE t1_i == 1 [L877] t1_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L881] COND TRUE t2_i == 1 [L882] t2_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L886] COND TRUE t3_i == 1 [L887] t3_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L891] COND TRUE t4_i == 1 [L892] t4_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L896] COND TRUE t5_i == 1 [L897] t5_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L901] COND TRUE t6_i == 1 [L902] t6_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L906] COND TRUE t7_i == 1 [L907] t7_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L911] COND TRUE t8_i == 1 [L912] t8_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L916] COND TRUE t9_i == 1 [L917] t9_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L921] COND TRUE t10_i == 1 [L922] t10_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L926] COND TRUE t11_i == 1 [L927] t11_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L931] COND TRUE t12_i == 1 [L932] t12_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L936] COND TRUE t13_i == 1 [L937] t13_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1248] COND FALSE !(M_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1253] COND FALSE !(T1_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(T2_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1263] COND FALSE !(T3_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1268] COND FALSE !(T4_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1273] COND FALSE !(T5_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1278] COND FALSE !(T6_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1283] COND FALSE !(T7_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1288] COND FALSE !(T8_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1293] COND FALSE !(T9_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1298] COND FALSE !(T10_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1303] COND FALSE !(T11_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1308] COND FALSE !(T12_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1313] COND FALSE !(T13_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1318] COND FALSE !(E_1 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1323] COND FALSE !(E_2 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1328] COND FALSE !(E_3 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1333] COND FALSE !(E_4 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1338] COND FALSE !(E_5 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1343] COND FALSE !(E_6 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1348] COND FALSE !(E_7 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1353] COND FALSE !(E_8 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1358] COND FALSE !(E_9 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1363] COND FALSE !(E_10 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1368] COND FALSE !(E_11 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1373] COND FALSE !(E_12 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1378] COND FALSE !(E_13 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1531] int tmp ; [L1532] int tmp___0 ; [L1533] int tmp___1 ; [L1534] int tmp___2 ; [L1535] int tmp___3 ; [L1536] int tmp___4 ; [L1537] int tmp___5 ; [L1538] int tmp___6 ; [L1539] int tmp___7 ; [L1540] int tmp___8 ; [L1541] int tmp___9 ; [L1542] int tmp___10 ; [L1543] int tmp___11 ; [L1544] int tmp___12 ; [L594] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L597] COND FALSE !(m_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L609] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1548] tmp = is_master_triggered() [L1550] COND FALSE !(\read(tmp)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L613] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L616] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L628] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1556] tmp___0 = is_transmit1_triggered() [L1558] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L632] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L635] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L647] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1564] tmp___1 = is_transmit2_triggered() [L1566] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L651] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L654] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L666] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1572] tmp___2 = is_transmit3_triggered() [L1574] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L670] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L673] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L685] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1580] tmp___3 = is_transmit4_triggered() [L1582] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L689] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L692] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L704] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1588] tmp___4 = is_transmit5_triggered() [L1590] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L708] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L711] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L723] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1596] tmp___5 = is_transmit6_triggered() [L1598] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L727] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L730] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L742] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1604] tmp___6 = is_transmit7_triggered() [L1606] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L746] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L749] COND FALSE !(t8_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L761] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1612] tmp___7 = is_transmit8_triggered() [L1614] COND FALSE !(\read(tmp___7)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L765] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L768] COND FALSE !(t9_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L780] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1620] tmp___8 = is_transmit9_triggered() [L1622] COND FALSE !(\read(tmp___8)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L784] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L787] COND FALSE !(t10_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L799] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1628] tmp___9 = is_transmit10_triggered() [L1630] COND FALSE !(\read(tmp___9)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L803] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L806] COND FALSE !(t11_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L818] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1636] tmp___10 = is_transmit11_triggered() [L1638] COND FALSE !(\read(tmp___10)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L822] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L825] COND FALSE !(t12_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L837] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1644] tmp___11 = is_transmit12_triggered() [L1646] COND FALSE !(\read(tmp___11)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L841] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L844] COND FALSE !(t13_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L856] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1652] tmp___12 = is_transmit13_triggered() [L1654] COND FALSE !(\read(tmp___12)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1391] COND FALSE !(M_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1396] COND FALSE !(T1_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(T2_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1406] COND FALSE !(T3_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1411] COND FALSE !(T4_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1416] COND FALSE !(T5_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1421] COND FALSE !(T6_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1426] COND FALSE !(T7_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1431] COND FALSE !(T8_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1436] COND FALSE !(T9_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1441] COND FALSE !(T10_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1446] COND FALSE !(T11_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1451] COND FALSE !(T12_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1456] COND FALSE !(T13_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1461] COND FALSE !(E_1 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1466] COND FALSE !(E_2 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1471] COND FALSE !(E_3 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1476] COND FALSE !(E_4 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1481] COND FALSE !(E_5 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1486] COND FALSE !(E_6 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1491] COND FALSE !(E_7 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1496] COND FALSE !(E_8 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1501] COND FALSE !(E_9 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1506] COND FALSE !(E_10 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1511] COND FALSE !(E_11 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1516] COND FALSE !(E_12 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1521] COND FALSE !(E_13 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1882] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1885] kernel_st = 1 [L1027] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1031] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L946] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L949] COND TRUE m_st == 0 [L950] __retres1 = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1022] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] tmp = exists_runnable_thread() [L1036] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE m_st == 0 [L1042] int tmp_ndt_1; [L1043] tmp_ndt_1 = __VERIFIER_nondet_int() [L1044] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1055] COND TRUE t1_st == 0 [L1056] int tmp_ndt_2; [L1057] tmp_ndt_2 = __VERIFIER_nondet_int() [L1058] COND FALSE !(\read(tmp_ndt_2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 1886 locations, 1 error locations. Result: UNSAFE, OverallTime: 25.9s, OverallIterations: 43, TraceHistogramMax: 1, AutomataDifference: 14.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 108702 SDtfs, 149913 SDslu, 65057 SDs, 0 SdLazy, 1934 SolverSat, 1116 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 147 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=6907occurred in iteration=42, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.7s AutomataMinimizationTime, 42 MinimizatonAttempts, 52260 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 7194 NumberOfCodeBlocks, 7194 NumberOfCodeBlocksAsserted, 43 NumberOfCheckSat, 6984 ConstructedInterpolants, 0 QuantifiedInterpolants, 1620728 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 42 InterpolantComputations, 42 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...