./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05a526ca9d0710db502cdfc74677e2807f071449 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 19:00:02,356 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 19:00:02,357 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 19:00:02,365 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 19:00:02,365 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 19:00:02,366 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 19:00:02,367 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 19:00:02,368 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 19:00:02,369 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 19:00:02,370 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 19:00:02,370 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 19:00:02,371 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 19:00:02,371 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 19:00:02,372 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 19:00:02,373 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 19:00:02,374 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 19:00:02,374 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 19:00:02,375 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 19:00:02,376 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 19:00:02,378 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 19:00:02,379 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 19:00:02,380 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 19:00:02,381 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 19:00:02,381 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 19:00:02,383 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 19:00:02,383 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 19:00:02,383 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 19:00:02,384 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 19:00:02,384 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 19:00:02,385 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 19:00:02,385 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 19:00:02,385 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 19:00:02,385 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 19:00:02,386 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 19:00:02,387 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 19:00:02,387 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 19:00:02,387 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 19:00:02,387 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 19:00:02,387 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 19:00:02,388 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 19:00:02,388 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 19:00:02,389 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 19:00:02,398 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 19:00:02,398 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 19:00:02,399 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 19:00:02,399 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 19:00:02,399 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 19:00:02,399 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 19:00:02,399 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 19:00:02,400 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 19:00:02,401 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 19:00:02,401 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 19:00:02,401 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 19:00:02,401 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 19:00:02,401 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 19:00:02,401 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 19:00:02,401 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 19:00:02,402 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05a526ca9d0710db502cdfc74677e2807f071449 [2019-12-07 19:00:02,503 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 19:00:02,510 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 19:00:02,513 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 19:00:02,513 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 19:00:02,514 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 19:00:02,514 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2019-12-07 19:00:02,552 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/data/e0c2e5181/27c4352741f441168d25156585cccb03/FLAG23f442806 [2019-12-07 19:00:03,021 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 19:00:03,022 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/sv-benchmarks/c/systemc/transmitter.16.cil.c [2019-12-07 19:00:03,033 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/data/e0c2e5181/27c4352741f441168d25156585cccb03/FLAG23f442806 [2019-12-07 19:00:03,044 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/data/e0c2e5181/27c4352741f441168d25156585cccb03 [2019-12-07 19:00:03,046 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 19:00:03,047 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 19:00:03,048 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 19:00:03,048 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 19:00:03,051 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 19:00:03,051 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,053 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15cbaf6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03, skipping insertion in model container [2019-12-07 19:00:03,054 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,058 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 19:00:03,096 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 19:00:03,315 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 19:00:03,320 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 19:00:03,368 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 19:00:03,388 INFO L208 MainTranslator]: Completed translation [2019-12-07 19:00:03,388 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03 WrapperNode [2019-12-07 19:00:03,388 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 19:00:03,389 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 19:00:03,389 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 19:00:03,389 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 19:00:03,394 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,403 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,468 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 19:00:03,469 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 19:00:03,469 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 19:00:03,469 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 19:00:03,476 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,476 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,484 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,484 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,511 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,535 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,541 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... [2019-12-07 19:00:03,551 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 19:00:03,551 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 19:00:03,551 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 19:00:03,551 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 19:00:03,552 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 19:00:03,594 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 19:00:03,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 19:00:05,356 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 19:00:05,356 INFO L287 CfgBuilder]: Removed 624 assume(true) statements. [2019-12-07 19:00:05,358 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 07:00:05 BoogieIcfgContainer [2019-12-07 19:00:05,358 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 19:00:05,359 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 19:00:05,359 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 19:00:05,361 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 19:00:05,361 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 07:00:03" (1/3) ... [2019-12-07 19:00:05,362 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15f1629d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 07:00:05, skipping insertion in model container [2019-12-07 19:00:05,362 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 07:00:03" (2/3) ... [2019-12-07 19:00:05,362 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15f1629d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 07:00:05, skipping insertion in model container [2019-12-07 19:00:05,363 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 07:00:05" (3/3) ... [2019-12-07 19:00:05,364 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.16.cil.c [2019-12-07 19:00:05,371 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 19:00:05,379 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 19:00:05,387 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-12-07 19:00:05,417 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 19:00:05,417 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 19:00:05,417 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 19:00:05,417 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 19:00:05,417 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 19:00:05,417 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 19:00:05,417 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 19:00:05,417 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 19:00:05,447 INFO L276 IsEmpty]: Start isEmpty. Operand 2018 states. [2019-12-07 19:00:05,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:05,457 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:05,457 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:05,458 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:05,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:05,461 INFO L82 PathProgramCache]: Analyzing trace with hash -1186634079, now seen corresponding path program 1 times [2019-12-07 19:00:05,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:05,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141766185] [2019-12-07 19:00:05,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:05,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:05,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:05,649 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141766185] [2019-12-07 19:00:05,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:05,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:05,652 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342015946] [2019-12-07 19:00:05,656 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:05,657 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:05,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:05,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:05,670 INFO L87 Difference]: Start difference. First operand 2018 states. Second operand 3 states. [2019-12-07 19:00:05,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:05,798 INFO L93 Difference]: Finished difference Result 4031 states and 6077 transitions. [2019-12-07 19:00:05,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:05,799 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:05,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:05,820 INFO L225 Difference]: With dead ends: 4031 [2019-12-07 19:00:05,820 INFO L226 Difference]: Without dead ends: 2014 [2019-12-07 19:00:05,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:05,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2014 states. [2019-12-07 19:00:05,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2014 to 2014. [2019-12-07 19:00:05,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2014 states. [2019-12-07 19:00:05,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2014 states to 2014 states and 3000 transitions. [2019-12-07 19:00:05,911 INFO L78 Accepts]: Start accepts. Automaton has 2014 states and 3000 transitions. Word has length 178 [2019-12-07 19:00:05,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:05,912 INFO L462 AbstractCegarLoop]: Abstraction has 2014 states and 3000 transitions. [2019-12-07 19:00:05,912 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:05,912 INFO L276 IsEmpty]: Start isEmpty. Operand 2014 states and 3000 transitions. [2019-12-07 19:00:05,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:05,914 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:05,914 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:05,915 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:05,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:05,915 INFO L82 PathProgramCache]: Analyzing trace with hash -355980445, now seen corresponding path program 1 times [2019-12-07 19:00:05,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:05,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525996403] [2019-12-07 19:00:05,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:05,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:05,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:05,985 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525996403] [2019-12-07 19:00:05,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:05,985 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:05,986 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96756945] [2019-12-07 19:00:05,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:05,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:05,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:05,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:05,988 INFO L87 Difference]: Start difference. First operand 2014 states and 3000 transitions. Second operand 3 states. [2019-12-07 19:00:06,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:06,037 INFO L93 Difference]: Finished difference Result 4015 states and 5978 transitions. [2019-12-07 19:00:06,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:06,037 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:06,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:06,045 INFO L225 Difference]: With dead ends: 4015 [2019-12-07 19:00:06,045 INFO L226 Difference]: Without dead ends: 2014 [2019-12-07 19:00:06,048 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2014 states. [2019-12-07 19:00:06,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2014 to 2014. [2019-12-07 19:00:06,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2014 states. [2019-12-07 19:00:06,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2014 states to 2014 states and 2999 transitions. [2019-12-07 19:00:06,089 INFO L78 Accepts]: Start accepts. Automaton has 2014 states and 2999 transitions. Word has length 178 [2019-12-07 19:00:06,090 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:06,090 INFO L462 AbstractCegarLoop]: Abstraction has 2014 states and 2999 transitions. [2019-12-07 19:00:06,090 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:06,090 INFO L276 IsEmpty]: Start isEmpty. Operand 2014 states and 2999 transitions. [2019-12-07 19:00:06,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:06,092 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:06,092 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:06,092 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:06,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:06,092 INFO L82 PathProgramCache]: Analyzing trace with hash -864759259, now seen corresponding path program 1 times [2019-12-07 19:00:06,092 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:06,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622072913] [2019-12-07 19:00:06,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:06,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:06,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:06,148 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622072913] [2019-12-07 19:00:06,148 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:06,148 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:06,148 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288947815] [2019-12-07 19:00:06,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:06,149 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:06,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:06,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,149 INFO L87 Difference]: Start difference. First operand 2014 states and 2999 transitions. Second operand 3 states. [2019-12-07 19:00:06,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:06,290 INFO L93 Difference]: Finished difference Result 5736 states and 8515 transitions. [2019-12-07 19:00:06,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:06,291 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:06,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:06,306 INFO L225 Difference]: With dead ends: 5736 [2019-12-07 19:00:06,306 INFO L226 Difference]: Without dead ends: 3741 [2019-12-07 19:00:06,309 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3741 states. [2019-12-07 19:00:06,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3741 to 3739. [2019-12-07 19:00:06,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:06,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5529 transitions. [2019-12-07 19:00:06,392 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5529 transitions. Word has length 178 [2019-12-07 19:00:06,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:06,392 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5529 transitions. [2019-12-07 19:00:06,392 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:06,392 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5529 transitions. [2019-12-07 19:00:06,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:06,394 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:06,394 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:06,394 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:06,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:06,394 INFO L82 PathProgramCache]: Analyzing trace with hash 439277764, now seen corresponding path program 1 times [2019-12-07 19:00:06,394 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:06,395 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082108035] [2019-12-07 19:00:06,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:06,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:06,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:06,459 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082108035] [2019-12-07 19:00:06,460 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:06,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:06,460 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739189846] [2019-12-07 19:00:06,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:06,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:06,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:06,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,461 INFO L87 Difference]: Start difference. First operand 3739 states and 5529 transitions. Second operand 3 states. [2019-12-07 19:00:06,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:06,604 INFO L93 Difference]: Finished difference Result 7458 states and 11024 transitions. [2019-12-07 19:00:06,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:06,605 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:06,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:06,624 INFO L225 Difference]: With dead ends: 7458 [2019-12-07 19:00:06,625 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:06,630 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:06,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:06,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:06,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5521 transitions. [2019-12-07 19:00:06,714 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5521 transitions. Word has length 178 [2019-12-07 19:00:06,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:06,714 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5521 transitions. [2019-12-07 19:00:06,714 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:06,714 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5521 transitions. [2019-12-07 19:00:06,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:06,715 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:06,715 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:06,715 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:06,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:06,716 INFO L82 PathProgramCache]: Analyzing trace with hash -265147644, now seen corresponding path program 1 times [2019-12-07 19:00:06,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:06,716 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748495655] [2019-12-07 19:00:06,716 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:06,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:06,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:06,765 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748495655] [2019-12-07 19:00:06,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:06,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:06,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970985626] [2019-12-07 19:00:06,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:06,766 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:06,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:06,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,766 INFO L87 Difference]: Start difference. First operand 3739 states and 5521 transitions. Second operand 3 states. [2019-12-07 19:00:06,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:06,866 INFO L93 Difference]: Finished difference Result 7456 states and 11005 transitions. [2019-12-07 19:00:06,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:06,867 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:06,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:06,881 INFO L225 Difference]: With dead ends: 7456 [2019-12-07 19:00:06,881 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:06,886 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:06,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:06,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:06,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:06,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5513 transitions. [2019-12-07 19:00:06,976 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5513 transitions. Word has length 178 [2019-12-07 19:00:06,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:06,976 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5513 transitions. [2019-12-07 19:00:06,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:06,976 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5513 transitions. [2019-12-07 19:00:06,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:06,977 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:06,977 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:06,978 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:06,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:06,978 INFO L82 PathProgramCache]: Analyzing trace with hash 79680518, now seen corresponding path program 1 times [2019-12-07 19:00:06,978 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:06,978 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700314305] [2019-12-07 19:00:06,978 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:06,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:07,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:07,017 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700314305] [2019-12-07 19:00:07,017 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:07,017 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:07,018 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911205618] [2019-12-07 19:00:07,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:07,018 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:07,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:07,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,018 INFO L87 Difference]: Start difference. First operand 3739 states and 5513 transitions. Second operand 3 states. [2019-12-07 19:00:07,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:07,128 INFO L93 Difference]: Finished difference Result 7455 states and 10988 transitions. [2019-12-07 19:00:07,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:07,128 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:07,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:07,142 INFO L225 Difference]: With dead ends: 7455 [2019-12-07 19:00:07,143 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:07,147 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:07,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:07,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:07,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5505 transitions. [2019-12-07 19:00:07,270 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5505 transitions. Word has length 178 [2019-12-07 19:00:07,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:07,270 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5505 transitions. [2019-12-07 19:00:07,270 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:07,270 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5505 transitions. [2019-12-07 19:00:07,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:07,272 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:07,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:07,272 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:07,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:07,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1720166854, now seen corresponding path program 1 times [2019-12-07 19:00:07,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:07,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759127549] [2019-12-07 19:00:07,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:07,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:07,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:07,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759127549] [2019-12-07 19:00:07,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:07,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:07,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470239864] [2019-12-07 19:00:07,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:07,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:07,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:07,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,315 INFO L87 Difference]: Start difference. First operand 3739 states and 5505 transitions. Second operand 3 states. [2019-12-07 19:00:07,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:07,427 INFO L93 Difference]: Finished difference Result 7454 states and 10971 transitions. [2019-12-07 19:00:07,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:07,427 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:07,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:07,441 INFO L225 Difference]: With dead ends: 7454 [2019-12-07 19:00:07,442 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:07,446 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:07,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:07,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:07,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5497 transitions. [2019-12-07 19:00:07,540 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5497 transitions. Word has length 178 [2019-12-07 19:00:07,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:07,540 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5497 transitions. [2019-12-07 19:00:07,540 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:07,540 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5497 transitions. [2019-12-07 19:00:07,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:07,541 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:07,541 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:07,541 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:07,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:07,542 INFO L82 PathProgramCache]: Analyzing trace with hash -443671546, now seen corresponding path program 1 times [2019-12-07 19:00:07,542 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:07,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702601436] [2019-12-07 19:00:07,542 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:07,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:07,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:07,576 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702601436] [2019-12-07 19:00:07,576 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:07,576 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:07,576 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414675648] [2019-12-07 19:00:07,577 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:07,577 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:07,577 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:07,577 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,577 INFO L87 Difference]: Start difference. First operand 3739 states and 5497 transitions. Second operand 3 states. [2019-12-07 19:00:07,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:07,679 INFO L93 Difference]: Finished difference Result 7453 states and 10954 transitions. [2019-12-07 19:00:07,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:07,680 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:07,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:07,694 INFO L225 Difference]: With dead ends: 7453 [2019-12-07 19:00:07,694 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:07,699 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:07,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:07,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:07,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5489 transitions. [2019-12-07 19:00:07,792 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5489 transitions. Word has length 178 [2019-12-07 19:00:07,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:07,792 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5489 transitions. [2019-12-07 19:00:07,792 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:07,793 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5489 transitions. [2019-12-07 19:00:07,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:07,794 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:07,794 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:07,794 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:07,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:07,794 INFO L82 PathProgramCache]: Analyzing trace with hash -1898946106, now seen corresponding path program 1 times [2019-12-07 19:00:07,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:07,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593106899] [2019-12-07 19:00:07,795 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:07,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:07,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:07,831 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593106899] [2019-12-07 19:00:07,831 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:07,831 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:07,831 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430690691] [2019-12-07 19:00:07,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:07,832 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:07,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:07,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,832 INFO L87 Difference]: Start difference. First operand 3739 states and 5489 transitions. Second operand 3 states. [2019-12-07 19:00:07,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:07,962 INFO L93 Difference]: Finished difference Result 7452 states and 10937 transitions. [2019-12-07 19:00:07,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:07,963 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:07,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:07,971 INFO L225 Difference]: With dead ends: 7452 [2019-12-07 19:00:07,971 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:07,976 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:07,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:08,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:08,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:08,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5481 transitions. [2019-12-07 19:00:08,114 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5481 transitions. Word has length 178 [2019-12-07 19:00:08,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:08,114 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5481 transitions. [2019-12-07 19:00:08,114 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:08,114 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5481 transitions. [2019-12-07 19:00:08,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:08,116 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:08,116 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:08,116 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:08,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:08,116 INFO L82 PathProgramCache]: Analyzing trace with hash -1253153786, now seen corresponding path program 1 times [2019-12-07 19:00:08,116 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:08,116 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72920394] [2019-12-07 19:00:08,116 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:08,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:08,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:08,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72920394] [2019-12-07 19:00:08,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:08,150 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:08,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107594546] [2019-12-07 19:00:08,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:08,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:08,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:08,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,151 INFO L87 Difference]: Start difference. First operand 3739 states and 5481 transitions. Second operand 3 states. [2019-12-07 19:00:08,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,239 INFO L93 Difference]: Finished difference Result 7451 states and 10920 transitions. [2019-12-07 19:00:08,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:08,240 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:08,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,245 INFO L225 Difference]: With dead ends: 7451 [2019-12-07 19:00:08,245 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:08,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:08,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:08,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:08,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5473 transitions. [2019-12-07 19:00:08,327 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5473 transitions. Word has length 178 [2019-12-07 19:00:08,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:08,327 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5473 transitions. [2019-12-07 19:00:08,327 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:08,328 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5473 transitions. [2019-12-07 19:00:08,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:08,329 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:08,329 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:08,329 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:08,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:08,329 INFO L82 PathProgramCache]: Analyzing trace with hash 568793542, now seen corresponding path program 1 times [2019-12-07 19:00:08,329 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:08,329 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354805981] [2019-12-07 19:00:08,330 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:08,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:08,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:08,363 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354805981] [2019-12-07 19:00:08,363 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:08,363 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:08,363 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69064] [2019-12-07 19:00:08,363 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:08,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:08,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:08,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,364 INFO L87 Difference]: Start difference. First operand 3739 states and 5473 transitions. Second operand 3 states. [2019-12-07 19:00:08,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,433 INFO L93 Difference]: Finished difference Result 7450 states and 10903 transitions. [2019-12-07 19:00:08,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:08,433 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:08,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,438 INFO L225 Difference]: With dead ends: 7450 [2019-12-07 19:00:08,438 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:08,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:08,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:08,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:08,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5465 transitions. [2019-12-07 19:00:08,516 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5465 transitions. Word has length 178 [2019-12-07 19:00:08,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:08,517 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5465 transitions. [2019-12-07 19:00:08,517 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:08,517 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5465 transitions. [2019-12-07 19:00:08,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:08,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:08,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:08,518 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:08,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:08,518 INFO L82 PathProgramCache]: Analyzing trace with hash -2004833274, now seen corresponding path program 1 times [2019-12-07 19:00:08,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:08,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580222561] [2019-12-07 19:00:08,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:08,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:08,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:08,552 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580222561] [2019-12-07 19:00:08,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:08,553 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:08,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074664286] [2019-12-07 19:00:08,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:08,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:08,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:08,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,553 INFO L87 Difference]: Start difference. First operand 3739 states and 5465 transitions. Second operand 3 states. [2019-12-07 19:00:08,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,673 INFO L93 Difference]: Finished difference Result 7448 states and 10884 transitions. [2019-12-07 19:00:08,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:08,674 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:08,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,680 INFO L225 Difference]: With dead ends: 7448 [2019-12-07 19:00:08,680 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:08,684 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:08,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:08,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:08,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5457 transitions. [2019-12-07 19:00:08,760 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5457 transitions. Word has length 178 [2019-12-07 19:00:08,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:08,760 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5457 transitions. [2019-12-07 19:00:08,760 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:08,760 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5457 transitions. [2019-12-07 19:00:08,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:08,761 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:08,762 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:08,762 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:08,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:08,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1618970872, now seen corresponding path program 1 times [2019-12-07 19:00:08,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:08,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353855210] [2019-12-07 19:00:08,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:08,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:08,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:08,807 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353855210] [2019-12-07 19:00:08,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:08,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:08,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810251586] [2019-12-07 19:00:08,808 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:08,808 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:08,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:08,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,808 INFO L87 Difference]: Start difference. First operand 3739 states and 5457 transitions. Second operand 3 states. [2019-12-07 19:00:08,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:08,912 INFO L93 Difference]: Finished difference Result 7447 states and 10867 transitions. [2019-12-07 19:00:08,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:08,913 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:08,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:08,917 INFO L225 Difference]: With dead ends: 7447 [2019-12-07 19:00:08,917 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:08,922 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:08,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:09,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:09,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:09,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5449 transitions. [2019-12-07 19:00:09,017 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5449 transitions. Word has length 178 [2019-12-07 19:00:09,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,018 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5449 transitions. [2019-12-07 19:00:09,018 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:09,018 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5449 transitions. [2019-12-07 19:00:09,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:09,020 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,020 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,020 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,020 INFO L82 PathProgramCache]: Analyzing trace with hash -497414968, now seen corresponding path program 1 times [2019-12-07 19:00:09,020 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,021 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870321186] [2019-12-07 19:00:09,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,067 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870321186] [2019-12-07 19:00:09,067 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,067 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:09,067 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278895302] [2019-12-07 19:00:09,068 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:09,068 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,068 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:09,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,068 INFO L87 Difference]: Start difference. First operand 3739 states and 5449 transitions. Second operand 3 states. [2019-12-07 19:00:09,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,178 INFO L93 Difference]: Finished difference Result 7446 states and 10850 transitions. [2019-12-07 19:00:09,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:09,179 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:09,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,183 INFO L225 Difference]: With dead ends: 7446 [2019-12-07 19:00:09,183 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:09,187 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:09,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:09,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:09,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5441 transitions. [2019-12-07 19:00:09,265 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5441 transitions. Word has length 178 [2019-12-07 19:00:09,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,265 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5441 transitions. [2019-12-07 19:00:09,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:09,265 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5441 transitions. [2019-12-07 19:00:09,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:09,266 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,267 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,267 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,267 INFO L82 PathProgramCache]: Analyzing trace with hash 924237576, now seen corresponding path program 1 times [2019-12-07 19:00:09,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274517808] [2019-12-07 19:00:09,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,308 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274517808] [2019-12-07 19:00:09,308 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,308 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:09,308 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397279445] [2019-12-07 19:00:09,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:09,309 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:09,309 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,309 INFO L87 Difference]: Start difference. First operand 3739 states and 5441 transitions. Second operand 3 states. [2019-12-07 19:00:09,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,417 INFO L93 Difference]: Finished difference Result 7445 states and 10833 transitions. [2019-12-07 19:00:09,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:09,417 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:09,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,422 INFO L225 Difference]: With dead ends: 7445 [2019-12-07 19:00:09,422 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:09,427 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:09,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:09,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:09,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5433 transitions. [2019-12-07 19:00:09,555 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5433 transitions. Word has length 178 [2019-12-07 19:00:09,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,555 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5433 transitions. [2019-12-07 19:00:09,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:09,555 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5433 transitions. [2019-12-07 19:00:09,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:09,556 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,557 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,557 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,557 INFO L82 PathProgramCache]: Analyzing trace with hash 1524286664, now seen corresponding path program 1 times [2019-12-07 19:00:09,557 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,557 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374524557] [2019-12-07 19:00:09,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,590 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374524557] [2019-12-07 19:00:09,590 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,590 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:09,591 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128252499] [2019-12-07 19:00:09,591 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:09,591 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:09,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,591 INFO L87 Difference]: Start difference. First operand 3739 states and 5433 transitions. Second operand 3 states. [2019-12-07 19:00:09,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,696 INFO L93 Difference]: Finished difference Result 7444 states and 10816 transitions. [2019-12-07 19:00:09,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:09,696 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:09,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,700 INFO L225 Difference]: With dead ends: 7444 [2019-12-07 19:00:09,700 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:09,704 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:09,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:09,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:09,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5397 transitions. [2019-12-07 19:00:09,783 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5397 transitions. Word has length 178 [2019-12-07 19:00:09,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:09,783 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5397 transitions. [2019-12-07 19:00:09,783 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:09,783 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5397 transitions. [2019-12-07 19:00:09,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:09,784 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:09,784 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:09,785 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:09,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:09,785 INFO L82 PathProgramCache]: Analyzing trace with hash -811661560, now seen corresponding path program 1 times [2019-12-07 19:00:09,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:09,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222394213] [2019-12-07 19:00:09,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:09,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:09,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:09,817 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222394213] [2019-12-07 19:00:09,817 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:09,817 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:09,818 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113278034] [2019-12-07 19:00:09,818 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:09,818 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:09,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:09,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,818 INFO L87 Difference]: Start difference. First operand 3739 states and 5397 transitions. Second operand 3 states. [2019-12-07 19:00:09,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:09,927 INFO L93 Difference]: Finished difference Result 7443 states and 10743 transitions. [2019-12-07 19:00:09,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:09,927 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:09,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:09,931 INFO L225 Difference]: With dead ends: 7443 [2019-12-07 19:00:09,931 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:09,935 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:09,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:10,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:10,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:10,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5361 transitions. [2019-12-07 19:00:10,016 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5361 transitions. Word has length 178 [2019-12-07 19:00:10,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:10,016 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5361 transitions. [2019-12-07 19:00:10,016 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:10,016 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5361 transitions. [2019-12-07 19:00:10,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:10,017 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:10,017 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:10,017 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:10,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:10,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1210080217, now seen corresponding path program 1 times [2019-12-07 19:00:10,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:10,018 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757641392] [2019-12-07 19:00:10,018 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:10,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:10,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:10,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757641392] [2019-12-07 19:00:10,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:10,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:10,051 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279351895] [2019-12-07 19:00:10,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:10,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:10,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:10,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,052 INFO L87 Difference]: Start difference. First operand 3739 states and 5361 transitions. Second operand 3 states. [2019-12-07 19:00:10,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:10,191 INFO L93 Difference]: Finished difference Result 7442 states and 10670 transitions. [2019-12-07 19:00:10,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:10,192 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:10,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:10,196 INFO L225 Difference]: With dead ends: 7442 [2019-12-07 19:00:10,196 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:10,199 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:10,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:10,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:10,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5325 transitions. [2019-12-07 19:00:10,281 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5325 transitions. Word has length 178 [2019-12-07 19:00:10,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:10,281 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5325 transitions. [2019-12-07 19:00:10,282 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:10,282 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5325 transitions. [2019-12-07 19:00:10,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:10,282 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:10,282 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:10,282 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:10,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:10,283 INFO L82 PathProgramCache]: Analyzing trace with hash 85086470, now seen corresponding path program 1 times [2019-12-07 19:00:10,283 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:10,283 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397914648] [2019-12-07 19:00:10,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:10,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:10,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:10,325 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397914648] [2019-12-07 19:00:10,325 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:10,325 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:10,325 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509517926] [2019-12-07 19:00:10,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:10,326 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:10,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:10,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,326 INFO L87 Difference]: Start difference. First operand 3739 states and 5325 transitions. Second operand 3 states. [2019-12-07 19:00:10,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:10,443 INFO L93 Difference]: Finished difference Result 7440 states and 10595 transitions. [2019-12-07 19:00:10,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:10,443 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:10,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:10,448 INFO L225 Difference]: With dead ends: 7440 [2019-12-07 19:00:10,448 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:10,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:10,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:10,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:10,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5289 transitions. [2019-12-07 19:00:10,534 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5289 transitions. Word has length 178 [2019-12-07 19:00:10,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:10,534 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5289 transitions. [2019-12-07 19:00:10,534 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:10,534 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5289 transitions. [2019-12-07 19:00:10,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:10,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:10,535 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:10,535 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:10,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:10,536 INFO L82 PathProgramCache]: Analyzing trace with hash -1073950937, now seen corresponding path program 1 times [2019-12-07 19:00:10,536 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:10,536 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004968433] [2019-12-07 19:00:10,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:10,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:10,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:10,575 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004968433] [2019-12-07 19:00:10,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:10,576 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:10,576 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008750449] [2019-12-07 19:00:10,576 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:10,576 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:10,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:10,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,576 INFO L87 Difference]: Start difference. First operand 3739 states and 5289 transitions. Second operand 3 states. [2019-12-07 19:00:10,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:10,689 INFO L93 Difference]: Finished difference Result 7439 states and 10522 transitions. [2019-12-07 19:00:10,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:10,689 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:10,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:10,692 INFO L225 Difference]: With dead ends: 7439 [2019-12-07 19:00:10,692 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:10,695 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:10,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:10,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:10,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5253 transitions. [2019-12-07 19:00:10,779 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5253 transitions. Word has length 178 [2019-12-07 19:00:10,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:10,780 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5253 transitions. [2019-12-07 19:00:10,780 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:10,780 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5253 transitions. [2019-12-07 19:00:10,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:10,780 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:10,781 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:10,781 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:10,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:10,781 INFO L82 PathProgramCache]: Analyzing trace with hash -240638745, now seen corresponding path program 1 times [2019-12-07 19:00:10,781 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:10,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808872129] [2019-12-07 19:00:10,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:10,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:10,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:10,812 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808872129] [2019-12-07 19:00:10,813 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:10,813 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:10,813 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33676043] [2019-12-07 19:00:10,813 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:10,813 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:10,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:10,813 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,813 INFO L87 Difference]: Start difference. First operand 3739 states and 5253 transitions. Second operand 3 states. [2019-12-07 19:00:10,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:10,920 INFO L93 Difference]: Finished difference Result 7438 states and 10449 transitions. [2019-12-07 19:00:10,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:10,920 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:10,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:10,923 INFO L225 Difference]: With dead ends: 7438 [2019-12-07 19:00:10,923 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:10,925 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:10,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:11,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:11,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:11,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5217 transitions. [2019-12-07 19:00:11,004 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5217 transitions. Word has length 178 [2019-12-07 19:00:11,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,004 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5217 transitions. [2019-12-07 19:00:11,004 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:11,005 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5217 transitions. [2019-12-07 19:00:11,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:11,005 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,005 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,005 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,006 INFO L82 PathProgramCache]: Analyzing trace with hash -1643962682, now seen corresponding path program 1 times [2019-12-07 19:00:11,006 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,006 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263948952] [2019-12-07 19:00:11,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263948952] [2019-12-07 19:00:11,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:11,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703072167] [2019-12-07 19:00:11,052 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:11,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:11,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,053 INFO L87 Difference]: Start difference. First operand 3739 states and 5217 transitions. Second operand 3 states. [2019-12-07 19:00:11,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,189 INFO L93 Difference]: Finished difference Result 7437 states and 10376 transitions. [2019-12-07 19:00:11,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:11,189 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:11,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,192 INFO L225 Difference]: With dead ends: 7437 [2019-12-07 19:00:11,192 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:11,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:11,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:11,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:11,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5181 transitions. [2019-12-07 19:00:11,314 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5181 transitions. Word has length 178 [2019-12-07 19:00:11,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,314 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5181 transitions. [2019-12-07 19:00:11,314 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:11,314 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5181 transitions. [2019-12-07 19:00:11,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:11,315 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,315 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,315 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,316 INFO L82 PathProgramCache]: Analyzing trace with hash -1173822330, now seen corresponding path program 1 times [2019-12-07 19:00:11,316 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,316 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131311257] [2019-12-07 19:00:11,316 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,347 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131311257] [2019-12-07 19:00:11,347 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,347 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:11,347 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042244559] [2019-12-07 19:00:11,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:11,348 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:11,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,348 INFO L87 Difference]: Start difference. First operand 3739 states and 5181 transitions. Second operand 3 states. [2019-12-07 19:00:11,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,468 INFO L93 Difference]: Finished difference Result 7436 states and 10303 transitions. [2019-12-07 19:00:11,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:11,468 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:11,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,470 INFO L225 Difference]: With dead ends: 7436 [2019-12-07 19:00:11,470 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:11,473 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:11,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:11,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:11,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5145 transitions. [2019-12-07 19:00:11,559 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5145 transitions. Word has length 178 [2019-12-07 19:00:11,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,560 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5145 transitions. [2019-12-07 19:00:11,560 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:11,560 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5145 transitions. [2019-12-07 19:00:11,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:11,560 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,560 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,561 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,561 INFO L82 PathProgramCache]: Analyzing trace with hash 1275765989, now seen corresponding path program 1 times [2019-12-07 19:00:11,561 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,561 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101751486] [2019-12-07 19:00:11,561 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,600 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101751486] [2019-12-07 19:00:11,600 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,600 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:11,601 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118862979] [2019-12-07 19:00:11,601 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:11,601 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:11,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,602 INFO L87 Difference]: Start difference. First operand 3739 states and 5145 transitions. Second operand 3 states. [2019-12-07 19:00:11,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,720 INFO L93 Difference]: Finished difference Result 7435 states and 10230 transitions. [2019-12-07 19:00:11,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:11,721 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:11,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,723 INFO L225 Difference]: With dead ends: 7435 [2019-12-07 19:00:11,723 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:11,725 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:11,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:11,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:11,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5109 transitions. [2019-12-07 19:00:11,815 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5109 transitions. Word has length 178 [2019-12-07 19:00:11,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:11,815 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5109 transitions. [2019-12-07 19:00:11,815 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:11,815 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5109 transitions. [2019-12-07 19:00:11,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:11,816 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:11,816 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:11,816 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:11,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:11,816 INFO L82 PathProgramCache]: Analyzing trace with hash 105306789, now seen corresponding path program 1 times [2019-12-07 19:00:11,816 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:11,816 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732974746] [2019-12-07 19:00:11,816 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:11,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:11,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:11,850 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732974746] [2019-12-07 19:00:11,850 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:11,851 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:11,851 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151777476] [2019-12-07 19:00:11,851 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:11,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:11,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:11,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,851 INFO L87 Difference]: Start difference. First operand 3739 states and 5109 transitions. Second operand 3 states. [2019-12-07 19:00:11,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:11,970 INFO L93 Difference]: Finished difference Result 7434 states and 10157 transitions. [2019-12-07 19:00:11,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:11,970 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:11,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:11,972 INFO L225 Difference]: With dead ends: 7434 [2019-12-07 19:00:11,972 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:11,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:11,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:12,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:12,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:12,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5073 transitions. [2019-12-07 19:00:12,066 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5073 transitions. Word has length 178 [2019-12-07 19:00:12,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:12,067 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5073 transitions. [2019-12-07 19:00:12,067 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:12,067 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5073 transitions. [2019-12-07 19:00:12,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:12,067 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:12,067 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:12,068 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:12,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:12,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1188110724, now seen corresponding path program 1 times [2019-12-07 19:00:12,068 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:12,068 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616232117] [2019-12-07 19:00:12,068 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:12,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:12,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:12,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616232117] [2019-12-07 19:00:12,103 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:12,103 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:12,104 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469156959] [2019-12-07 19:00:12,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:12,104 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:12,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:12,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,104 INFO L87 Difference]: Start difference. First operand 3739 states and 5073 transitions. Second operand 3 states. [2019-12-07 19:00:12,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:12,235 INFO L93 Difference]: Finished difference Result 7432 states and 10082 transitions. [2019-12-07 19:00:12,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:12,235 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:12,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:12,237 INFO L225 Difference]: With dead ends: 7432 [2019-12-07 19:00:12,237 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:12,240 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:12,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:12,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:12,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 5037 transitions. [2019-12-07 19:00:12,335 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 5037 transitions. Word has length 178 [2019-12-07 19:00:12,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:12,335 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 5037 transitions. [2019-12-07 19:00:12,335 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:12,335 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 5037 transitions. [2019-12-07 19:00:12,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:12,336 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:12,336 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:12,336 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:12,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:12,336 INFO L82 PathProgramCache]: Analyzing trace with hash 1551577222, now seen corresponding path program 1 times [2019-12-07 19:00:12,336 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:12,336 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237513392] [2019-12-07 19:00:12,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:12,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:12,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:12,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237513392] [2019-12-07 19:00:12,366 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:12,366 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:12,366 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741777772] [2019-12-07 19:00:12,367 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:12,367 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:12,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:12,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,367 INFO L87 Difference]: Start difference. First operand 3739 states and 5037 transitions. Second operand 3 states. [2019-12-07 19:00:12,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:12,488 INFO L93 Difference]: Finished difference Result 7431 states and 10009 transitions. [2019-12-07 19:00:12,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:12,488 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:12,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:12,490 INFO L225 Difference]: With dead ends: 7431 [2019-12-07 19:00:12,490 INFO L226 Difference]: Without dead ends: 3739 [2019-12-07 19:00:12,492 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3739 states. [2019-12-07 19:00:12,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3739 to 3739. [2019-12-07 19:00:12,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3739 states. [2019-12-07 19:00:12,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3739 states to 3739 states and 4999 transitions. [2019-12-07 19:00:12,590 INFO L78 Accepts]: Start accepts. Automaton has 3739 states and 4999 transitions. Word has length 178 [2019-12-07 19:00:12,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:12,590 INFO L462 AbstractCegarLoop]: Abstraction has 3739 states and 4999 transitions. [2019-12-07 19:00:12,590 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:12,590 INFO L276 IsEmpty]: Start isEmpty. Operand 3739 states and 4999 transitions. [2019-12-07 19:00:12,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:12,590 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:12,591 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:12,591 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:12,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:12,591 INFO L82 PathProgramCache]: Analyzing trace with hash -54414171, now seen corresponding path program 1 times [2019-12-07 19:00:12,591 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:12,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332268504] [2019-12-07 19:00:12,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:12,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:12,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:12,639 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332268504] [2019-12-07 19:00:12,639 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:12,639 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:12,639 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821611464] [2019-12-07 19:00:12,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:12,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:12,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:12,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,640 INFO L87 Difference]: Start difference. First operand 3739 states and 4999 transitions. Second operand 3 states. [2019-12-07 19:00:12,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:12,860 INFO L93 Difference]: Finished difference Result 10663 states and 14252 transitions. [2019-12-07 19:00:12,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:12,861 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:12,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:12,865 INFO L225 Difference]: With dead ends: 10663 [2019-12-07 19:00:12,865 INFO L226 Difference]: Without dead ends: 7057 [2019-12-07 19:00:12,868 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:12,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7057 states. [2019-12-07 19:00:13,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7057 to 7051. [2019-12-07 19:00:13,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-12-07 19:00:13,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9394 transitions. [2019-12-07 19:00:13,101 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9394 transitions. Word has length 178 [2019-12-07 19:00:13,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:13,102 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9394 transitions. [2019-12-07 19:00:13,102 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:13,102 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9394 transitions. [2019-12-07 19:00:13,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:13,103 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:13,103 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:13,103 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:13,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:13,103 INFO L82 PathProgramCache]: Analyzing trace with hash -1196061564, now seen corresponding path program 1 times [2019-12-07 19:00:13,103 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:13,103 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966487208] [2019-12-07 19:00:13,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:13,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:13,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:13,170 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966487208] [2019-12-07 19:00:13,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:13,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:13,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802201751] [2019-12-07 19:00:13,171 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:13,171 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:13,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:13,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:13,172 INFO L87 Difference]: Start difference. First operand 7051 states and 9394 transitions. Second operand 3 states. [2019-12-07 19:00:13,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:13,405 INFO L93 Difference]: Finished difference Result 14081 states and 18753 transitions. [2019-12-07 19:00:13,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:13,405 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:13,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:13,409 INFO L225 Difference]: With dead ends: 14081 [2019-12-07 19:00:13,409 INFO L226 Difference]: Without dead ends: 7051 [2019-12-07 19:00:13,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:13,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-12-07 19:00:13,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-12-07 19:00:13,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-12-07 19:00:13,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9380 transitions. [2019-12-07 19:00:13,608 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9380 transitions. Word has length 178 [2019-12-07 19:00:13,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:13,609 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9380 transitions. [2019-12-07 19:00:13,609 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:13,609 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9380 transitions. [2019-12-07 19:00:13,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:13,609 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:13,610 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:13,610 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:13,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:13,610 INFO L82 PathProgramCache]: Analyzing trace with hash 1253538566, now seen corresponding path program 1 times [2019-12-07 19:00:13,610 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:13,610 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011203716] [2019-12-07 19:00:13,610 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:13,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:13,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:13,656 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011203716] [2019-12-07 19:00:13,656 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:13,656 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:13,656 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255623175] [2019-12-07 19:00:13,657 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:13,657 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:13,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:13,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:13,657 INFO L87 Difference]: Start difference. First operand 7051 states and 9380 transitions. Second operand 3 states. [2019-12-07 19:00:13,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:13,860 INFO L93 Difference]: Finished difference Result 14073 states and 18717 transitions. [2019-12-07 19:00:13,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:13,860 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:13,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:13,865 INFO L225 Difference]: With dead ends: 14073 [2019-12-07 19:00:13,865 INFO L226 Difference]: Without dead ends: 7051 [2019-12-07 19:00:13,869 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:13,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-12-07 19:00:14,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-12-07 19:00:14,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-12-07 19:00:14,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9366 transitions. [2019-12-07 19:00:14,068 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9366 transitions. Word has length 178 [2019-12-07 19:00:14,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:14,068 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9366 transitions. [2019-12-07 19:00:14,068 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:14,068 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9366 transitions. [2019-12-07 19:00:14,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:14,069 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:14,069 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:14,069 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:14,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:14,069 INFO L82 PathProgramCache]: Analyzing trace with hash 1955138440, now seen corresponding path program 1 times [2019-12-07 19:00:14,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:14,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94799563] [2019-12-07 19:00:14,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:14,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:14,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:14,116 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94799563] [2019-12-07 19:00:14,116 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:14,116 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:14,116 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148192107] [2019-12-07 19:00:14,116 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:14,117 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:14,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:14,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:14,117 INFO L87 Difference]: Start difference. First operand 7051 states and 9366 transitions. Second operand 3 states. [2019-12-07 19:00:14,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:14,362 INFO L93 Difference]: Finished difference Result 14065 states and 18681 transitions. [2019-12-07 19:00:14,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:14,362 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:14,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:14,366 INFO L225 Difference]: With dead ends: 14065 [2019-12-07 19:00:14,366 INFO L226 Difference]: Without dead ends: 7051 [2019-12-07 19:00:14,369 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:14,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-12-07 19:00:14,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-12-07 19:00:14,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-12-07 19:00:14,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9299 transitions. [2019-12-07 19:00:14,569 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9299 transitions. Word has length 178 [2019-12-07 19:00:14,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:14,570 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9299 transitions. [2019-12-07 19:00:14,570 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:14,570 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9299 transitions. [2019-12-07 19:00:14,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:14,570 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:14,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:14,571 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:14,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:14,571 INFO L82 PathProgramCache]: Analyzing trace with hash 149700106, now seen corresponding path program 1 times [2019-12-07 19:00:14,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:14,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926801695] [2019-12-07 19:00:14,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:14,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:14,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:14,630 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926801695] [2019-12-07 19:00:14,630 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:14,630 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:14,630 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691064074] [2019-12-07 19:00:14,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:14,631 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:14,631 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:14,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:14,631 INFO L87 Difference]: Start difference. First operand 7051 states and 9299 transitions. Second operand 3 states. [2019-12-07 19:00:14,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:14,865 INFO L93 Difference]: Finished difference Result 14057 states and 18539 transitions. [2019-12-07 19:00:14,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:14,865 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:14,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:14,869 INFO L225 Difference]: With dead ends: 14057 [2019-12-07 19:00:14,869 INFO L226 Difference]: Without dead ends: 7051 [2019-12-07 19:00:14,873 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:14,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7051 states. [2019-12-07 19:00:15,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7051 to 7051. [2019-12-07 19:00:15,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-12-07 19:00:15,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9258 transitions. [2019-12-07 19:00:15,079 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9258 transitions. Word has length 178 [2019-12-07 19:00:15,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:15,080 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9258 transitions. [2019-12-07 19:00:15,080 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:15,080 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9258 transitions. [2019-12-07 19:00:15,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-12-07 19:00:15,080 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:15,080 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:15,081 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:15,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:15,081 INFO L82 PathProgramCache]: Analyzing trace with hash -1130163572, now seen corresponding path program 1 times [2019-12-07 19:00:15,081 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:15,081 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874735580] [2019-12-07 19:00:15,081 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:15,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:15,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:15,122 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874735580] [2019-12-07 19:00:15,123 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:15,123 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:15,123 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993784663] [2019-12-07 19:00:15,123 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:15,123 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:15,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:15,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:15,123 INFO L87 Difference]: Start difference. First operand 7051 states and 9258 transitions. Second operand 3 states. [2019-12-07 19:00:15,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:15,733 INFO L93 Difference]: Finished difference Result 20757 states and 27145 transitions. [2019-12-07 19:00:15,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:15,734 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-12-07 19:00:15,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:15,742 INFO L225 Difference]: With dead ends: 20757 [2019-12-07 19:00:15,742 INFO L226 Difference]: Without dead ends: 13886 [2019-12-07 19:00:15,745 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:15,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13886 states. [2019-12-07 19:00:16,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13886 to 13482. [2019-12-07 19:00:16,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13482 states. [2019-12-07 19:00:16,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13482 states to 13482 states and 17576 transitions. [2019-12-07 19:00:16,157 INFO L78 Accepts]: Start accepts. Automaton has 13482 states and 17576 transitions. Word has length 178 [2019-12-07 19:00:16,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:16,157 INFO L462 AbstractCegarLoop]: Abstraction has 13482 states and 17576 transitions. [2019-12-07 19:00:16,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:16,157 INFO L276 IsEmpty]: Start isEmpty. Operand 13482 states and 17576 transitions. [2019-12-07 19:00:16,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:16,158 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:16,158 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:16,158 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:16,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:16,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1040694295, now seen corresponding path program 1 times [2019-12-07 19:00:16,158 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:16,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795841670] [2019-12-07 19:00:16,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:16,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:16,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:16,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795841670] [2019-12-07 19:00:16,230 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:16,230 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:16,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704818824] [2019-12-07 19:00:16,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:16,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:16,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:16,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:16,231 INFO L87 Difference]: Start difference. First operand 13482 states and 17576 transitions. Second operand 5 states. [2019-12-07 19:00:17,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:17,343 INFO L93 Difference]: Finished difference Result 38554 states and 50369 transitions. [2019-12-07 19:00:17,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:17,343 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:17,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:17,358 INFO L225 Difference]: With dead ends: 38554 [2019-12-07 19:00:17,358 INFO L226 Difference]: Without dead ends: 25302 [2019-12-07 19:00:17,364 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:17,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25302 states. [2019-12-07 19:00:17,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25302 to 13650. [2019-12-07 19:00:17,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13650 states. [2019-12-07 19:00:17,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13650 states to 13650 states and 17690 transitions. [2019-12-07 19:00:17,933 INFO L78 Accepts]: Start accepts. Automaton has 13650 states and 17690 transitions. Word has length 179 [2019-12-07 19:00:17,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:17,933 INFO L462 AbstractCegarLoop]: Abstraction has 13650 states and 17690 transitions. [2019-12-07 19:00:17,933 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:17,933 INFO L276 IsEmpty]: Start isEmpty. Operand 13650 states and 17690 transitions. [2019-12-07 19:00:17,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:17,934 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:17,934 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:17,934 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:17,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:17,934 INFO L82 PathProgramCache]: Analyzing trace with hash -1475199893, now seen corresponding path program 1 times [2019-12-07 19:00:17,934 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:17,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078959643] [2019-12-07 19:00:17,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:17,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:17,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:17,990 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078959643] [2019-12-07 19:00:17,991 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:17,991 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:17,991 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708156412] [2019-12-07 19:00:17,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:17,991 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:17,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:17,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:17,991 INFO L87 Difference]: Start difference. First operand 13650 states and 17690 transitions. Second operand 5 states. [2019-12-07 19:00:19,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:19,027 INFO L93 Difference]: Finished difference Result 31118 states and 40645 transitions. [2019-12-07 19:00:19,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:19,028 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:19,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:19,038 INFO L225 Difference]: With dead ends: 31118 [2019-12-07 19:00:19,038 INFO L226 Difference]: Without dead ends: 17586 [2019-12-07 19:00:19,043 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:19,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17586 states. [2019-12-07 19:00:19,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17586 to 13662. [2019-12-07 19:00:19,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13662 states. [2019-12-07 19:00:19,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13662 states to 13662 states and 17596 transitions. [2019-12-07 19:00:19,670 INFO L78 Accepts]: Start accepts. Automaton has 13662 states and 17596 transitions. Word has length 179 [2019-12-07 19:00:19,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:19,670 INFO L462 AbstractCegarLoop]: Abstraction has 13662 states and 17596 transitions. [2019-12-07 19:00:19,670 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:19,670 INFO L276 IsEmpty]: Start isEmpty. Operand 13662 states and 17596 transitions. [2019-12-07 19:00:19,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:19,671 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:19,671 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:19,671 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:19,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:19,671 INFO L82 PathProgramCache]: Analyzing trace with hash -987152787, now seen corresponding path program 1 times [2019-12-07 19:00:19,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:19,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699165914] [2019-12-07 19:00:19,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:19,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:19,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:19,726 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699165914] [2019-12-07 19:00:19,726 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:19,726 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:19,726 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808582440] [2019-12-07 19:00:19,727 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:19,727 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:19,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:19,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:19,727 INFO L87 Difference]: Start difference. First operand 13662 states and 17596 transitions. Second operand 5 states. [2019-12-07 19:00:20,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:20,871 INFO L93 Difference]: Finished difference Result 32500 states and 42101 transitions. [2019-12-07 19:00:20,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:20,872 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:20,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:20,883 INFO L225 Difference]: With dead ends: 32500 [2019-12-07 19:00:20,883 INFO L226 Difference]: Without dead ends: 18970 [2019-12-07 19:00:20,891 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:20,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18970 states. [2019-12-07 19:00:21,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18970 to 13686. [2019-12-07 19:00:21,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13686 states. [2019-12-07 19:00:21,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13686 states to 13686 states and 17518 transitions. [2019-12-07 19:00:21,613 INFO L78 Accepts]: Start accepts. Automaton has 13686 states and 17518 transitions. Word has length 179 [2019-12-07 19:00:21,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:21,613 INFO L462 AbstractCegarLoop]: Abstraction has 13686 states and 17518 transitions. [2019-12-07 19:00:21,613 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:21,613 INFO L276 IsEmpty]: Start isEmpty. Operand 13686 states and 17518 transitions. [2019-12-07 19:00:21,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:21,614 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:21,614 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:21,614 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:21,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:21,614 INFO L82 PathProgramCache]: Analyzing trace with hash 941779439, now seen corresponding path program 1 times [2019-12-07 19:00:21,614 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:21,615 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056649650] [2019-12-07 19:00:21,615 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:21,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:21,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:21,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056649650] [2019-12-07 19:00:21,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:21,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:21,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037927242] [2019-12-07 19:00:21,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:21,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:21,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:21,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:21,672 INFO L87 Difference]: Start difference. First operand 13686 states and 17518 transitions. Second operand 5 states. [2019-12-07 19:00:23,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:23,036 INFO L93 Difference]: Finished difference Result 33174 states and 42657 transitions. [2019-12-07 19:00:23,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:23,037 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:23,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:23,049 INFO L225 Difference]: With dead ends: 33174 [2019-12-07 19:00:23,049 INFO L226 Difference]: Without dead ends: 19634 [2019-12-07 19:00:23,055 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:23,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19634 states. [2019-12-07 19:00:23,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19634 to 13710. [2019-12-07 19:00:23,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13710 states. [2019-12-07 19:00:23,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13710 states to 13710 states and 17440 transitions. [2019-12-07 19:00:23,871 INFO L78 Accepts]: Start accepts. Automaton has 13710 states and 17440 transitions. Word has length 179 [2019-12-07 19:00:23,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:23,871 INFO L462 AbstractCegarLoop]: Abstraction has 13710 states and 17440 transitions. [2019-12-07 19:00:23,871 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:23,871 INFO L276 IsEmpty]: Start isEmpty. Operand 13710 states and 17440 transitions. [2019-12-07 19:00:23,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:23,872 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:23,872 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:23,872 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:23,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:23,872 INFO L82 PathProgramCache]: Analyzing trace with hash -96805135, now seen corresponding path program 1 times [2019-12-07 19:00:23,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:23,872 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329732188] [2019-12-07 19:00:23,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:23,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:23,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:23,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329732188] [2019-12-07 19:00:23,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:23,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:23,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126189669] [2019-12-07 19:00:23,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:23,927 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:23,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:23,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:23,927 INFO L87 Difference]: Start difference. First operand 13710 states and 17440 transitions. Second operand 5 states. [2019-12-07 19:00:25,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:25,407 INFO L93 Difference]: Finished difference Result 34450 states and 43995 transitions. [2019-12-07 19:00:25,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:25,408 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:25,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:25,420 INFO L225 Difference]: With dead ends: 34450 [2019-12-07 19:00:25,421 INFO L226 Difference]: Without dead ends: 20914 [2019-12-07 19:00:25,426 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:25,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20914 states. [2019-12-07 19:00:26,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20914 to 13734. [2019-12-07 19:00:26,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13734 states. [2019-12-07 19:00:26,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13734 states to 13734 states and 17362 transitions. [2019-12-07 19:00:26,322 INFO L78 Accepts]: Start accepts. Automaton has 13734 states and 17362 transitions. Word has length 179 [2019-12-07 19:00:26,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:26,322 INFO L462 AbstractCegarLoop]: Abstraction has 13734 states and 17362 transitions. [2019-12-07 19:00:26,322 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:26,322 INFO L276 IsEmpty]: Start isEmpty. Operand 13734 states and 17362 transitions. [2019-12-07 19:00:26,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:26,324 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:26,324 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:26,324 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:26,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:26,324 INFO L82 PathProgramCache]: Analyzing trace with hash 1504265971, now seen corresponding path program 1 times [2019-12-07 19:00:26,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:26,324 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515290556] [2019-12-07 19:00:26,324 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:26,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:26,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:26,375 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515290556] [2019-12-07 19:00:26,375 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:26,375 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:26,376 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172183930] [2019-12-07 19:00:26,376 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:26,376 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:26,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:26,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:26,376 INFO L87 Difference]: Start difference. First operand 13734 states and 17362 transitions. Second operand 5 states. [2019-12-07 19:00:28,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:28,103 INFO L93 Difference]: Finished difference Result 35124 states and 44551 transitions. [2019-12-07 19:00:28,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:28,103 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:28,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:28,116 INFO L225 Difference]: With dead ends: 35124 [2019-12-07 19:00:28,116 INFO L226 Difference]: Without dead ends: 21578 [2019-12-07 19:00:28,122 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:28,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21578 states. [2019-12-07 19:00:29,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21578 to 13758. [2019-12-07 19:00:29,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13758 states. [2019-12-07 19:00:29,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13758 states to 13758 states and 17284 transitions. [2019-12-07 19:00:29,115 INFO L78 Accepts]: Start accepts. Automaton has 13758 states and 17284 transitions. Word has length 179 [2019-12-07 19:00:29,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:29,115 INFO L462 AbstractCegarLoop]: Abstraction has 13758 states and 17284 transitions. [2019-12-07 19:00:29,115 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:29,116 INFO L276 IsEmpty]: Start isEmpty. Operand 13758 states and 17284 transitions. [2019-12-07 19:00:29,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:29,116 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:29,116 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:29,117 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:29,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:29,117 INFO L82 PathProgramCache]: Analyzing trace with hash -436316043, now seen corresponding path program 1 times [2019-12-07 19:00:29,117 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:29,117 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950071729] [2019-12-07 19:00:29,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:29,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:29,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:29,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950071729] [2019-12-07 19:00:29,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:29,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:29,167 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452512259] [2019-12-07 19:00:29,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:29,168 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:29,168 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:29,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:29,168 INFO L87 Difference]: Start difference. First operand 13758 states and 17284 transitions. Second operand 5 states. [2019-12-07 19:00:31,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:31,021 INFO L93 Difference]: Finished difference Result 35798 states and 45107 transitions. [2019-12-07 19:00:31,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:31,022 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:31,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:31,036 INFO L225 Difference]: With dead ends: 35798 [2019-12-07 19:00:31,036 INFO L226 Difference]: Without dead ends: 22242 [2019-12-07 19:00:31,043 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:31,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22242 states. [2019-12-07 19:00:32,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22242 to 13782. [2019-12-07 19:00:32,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13782 states. [2019-12-07 19:00:32,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13782 states to 13782 states and 17206 transitions. [2019-12-07 19:00:32,160 INFO L78 Accepts]: Start accepts. Automaton has 13782 states and 17206 transitions. Word has length 179 [2019-12-07 19:00:32,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:32,160 INFO L462 AbstractCegarLoop]: Abstraction has 13782 states and 17206 transitions. [2019-12-07 19:00:32,160 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:32,160 INFO L276 IsEmpty]: Start isEmpty. Operand 13782 states and 17206 transitions. [2019-12-07 19:00:32,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:32,161 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:32,161 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:32,161 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:32,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:32,161 INFO L82 PathProgramCache]: Analyzing trace with hash 1440166775, now seen corresponding path program 1 times [2019-12-07 19:00:32,162 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:32,162 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370850680] [2019-12-07 19:00:32,162 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:32,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:32,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:32,222 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370850680] [2019-12-07 19:00:32,222 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:32,222 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:32,222 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332611390] [2019-12-07 19:00:32,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:32,223 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:32,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:32,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:32,223 INFO L87 Difference]: Start difference. First operand 13782 states and 17206 transitions. Second operand 5 states. [2019-12-07 19:00:34,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:34,311 INFO L93 Difference]: Finished difference Result 36472 states and 45663 transitions. [2019-12-07 19:00:34,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:34,312 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:34,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:34,325 INFO L225 Difference]: With dead ends: 36472 [2019-12-07 19:00:34,325 INFO L226 Difference]: Without dead ends: 22906 [2019-12-07 19:00:34,332 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:34,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22906 states. [2019-12-07 19:00:35,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22906 to 13806. [2019-12-07 19:00:35,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13806 states. [2019-12-07 19:00:35,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13806 states to 13806 states and 17128 transitions. [2019-12-07 19:00:35,517 INFO L78 Accepts]: Start accepts. Automaton has 13806 states and 17128 transitions. Word has length 179 [2019-12-07 19:00:35,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:35,517 INFO L462 AbstractCegarLoop]: Abstraction has 13806 states and 17128 transitions. [2019-12-07 19:00:35,517 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:35,517 INFO L276 IsEmpty]: Start isEmpty. Operand 13806 states and 17128 transitions. [2019-12-07 19:00:35,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:35,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:35,518 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:35,518 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:35,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:35,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1680406521, now seen corresponding path program 1 times [2019-12-07 19:00:35,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:35,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248396795] [2019-12-07 19:00:35,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:35,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:35,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:35,570 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248396795] [2019-12-07 19:00:35,570 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:35,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:35,571 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94094170] [2019-12-07 19:00:35,571 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:35,571 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:35,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:35,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:35,572 INFO L87 Difference]: Start difference. First operand 13806 states and 17128 transitions. Second operand 5 states. [2019-12-07 19:00:37,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:37,757 INFO L93 Difference]: Finished difference Result 37146 states and 46219 transitions. [2019-12-07 19:00:37,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:37,757 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:37,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:37,771 INFO L225 Difference]: With dead ends: 37146 [2019-12-07 19:00:37,771 INFO L226 Difference]: Without dead ends: 23570 [2019-12-07 19:00:37,779 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:37,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23570 states. [2019-12-07 19:00:39,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23570 to 13830. [2019-12-07 19:00:39,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13830 states. [2019-12-07 19:00:39,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13830 states to 13830 states and 17050 transitions. [2019-12-07 19:00:39,060 INFO L78 Accepts]: Start accepts. Automaton has 13830 states and 17050 transitions. Word has length 179 [2019-12-07 19:00:39,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:39,060 INFO L462 AbstractCegarLoop]: Abstraction has 13830 states and 17050 transitions. [2019-12-07 19:00:39,060 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:39,060 INFO L276 IsEmpty]: Start isEmpty. Operand 13830 states and 17050 transitions. [2019-12-07 19:00:39,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:39,061 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:39,061 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:39,061 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:39,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:39,061 INFO L82 PathProgramCache]: Analyzing trace with hash -230636037, now seen corresponding path program 1 times [2019-12-07 19:00:39,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:39,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296681301] [2019-12-07 19:00:39,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:39,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:39,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:39,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296681301] [2019-12-07 19:00:39,134 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:39,134 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:39,134 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108990080] [2019-12-07 19:00:39,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:39,135 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:39,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:39,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:39,135 INFO L87 Difference]: Start difference. First operand 13830 states and 17050 transitions. Second operand 5 states. [2019-12-07 19:00:41,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:41,670 INFO L93 Difference]: Finished difference Result 37820 states and 46775 transitions. [2019-12-07 19:00:41,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:41,670 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:41,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:41,685 INFO L225 Difference]: With dead ends: 37820 [2019-12-07 19:00:41,685 INFO L226 Difference]: Without dead ends: 24234 [2019-12-07 19:00:41,694 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:41,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24234 states. [2019-12-07 19:00:43,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24234 to 13854. [2019-12-07 19:00:43,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13854 states. [2019-12-07 19:00:43,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13854 states to 13854 states and 16972 transitions. [2019-12-07 19:00:43,074 INFO L78 Accepts]: Start accepts. Automaton has 13854 states and 16972 transitions. Word has length 179 [2019-12-07 19:00:43,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:43,074 INFO L462 AbstractCegarLoop]: Abstraction has 13854 states and 16972 transitions. [2019-12-07 19:00:43,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:43,074 INFO L276 IsEmpty]: Start isEmpty. Operand 13854 states and 16972 transitions. [2019-12-07 19:00:43,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:43,075 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:43,075 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:43,075 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:43,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:43,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1446789763, now seen corresponding path program 1 times [2019-12-07 19:00:43,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:43,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691437961] [2019-12-07 19:00:43,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:43,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:43,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:43,119 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691437961] [2019-12-07 19:00:43,119 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:43,119 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:43,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388668682] [2019-12-07 19:00:43,119 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:43,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:43,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:43,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:43,119 INFO L87 Difference]: Start difference. First operand 13854 states and 16972 transitions. Second operand 5 states. [2019-12-07 19:00:45,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:45,738 INFO L93 Difference]: Finished difference Result 38494 states and 47331 transitions. [2019-12-07 19:00:45,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:45,739 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:45,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:45,755 INFO L225 Difference]: With dead ends: 38494 [2019-12-07 19:00:45,755 INFO L226 Difference]: Without dead ends: 24898 [2019-12-07 19:00:45,765 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:45,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24898 states. [2019-12-07 19:00:47,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24898 to 13878. [2019-12-07 19:00:47,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13878 states. [2019-12-07 19:00:47,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13878 states to 13878 states and 16894 transitions. [2019-12-07 19:00:47,408 INFO L78 Accepts]: Start accepts. Automaton has 13878 states and 16894 transitions. Word has length 179 [2019-12-07 19:00:47,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:47,408 INFO L462 AbstractCegarLoop]: Abstraction has 13878 states and 16894 transitions. [2019-12-07 19:00:47,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:47,408 INFO L276 IsEmpty]: Start isEmpty. Operand 13878 states and 16894 transitions. [2019-12-07 19:00:47,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:47,409 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:47,409 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:47,409 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:47,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:47,409 INFO L82 PathProgramCache]: Analyzing trace with hash 514784895, now seen corresponding path program 1 times [2019-12-07 19:00:47,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:47,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015624388] [2019-12-07 19:00:47,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:47,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:47,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:47,464 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015624388] [2019-12-07 19:00:47,464 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:47,465 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:47,465 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636614324] [2019-12-07 19:00:47,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:47,465 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:47,465 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:47,465 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:47,465 INFO L87 Difference]: Start difference. First operand 13878 states and 16894 transitions. Second operand 5 states. [2019-12-07 19:00:49,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:49,708 INFO L93 Difference]: Finished difference Result 33517 states and 40902 transitions. [2019-12-07 19:00:49,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:00:49,709 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:49,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:49,721 INFO L225 Difference]: With dead ends: 33517 [2019-12-07 19:00:49,721 INFO L226 Difference]: Without dead ends: 19909 [2019-12-07 19:00:49,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:49,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19909 states. [2019-12-07 19:00:51,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19909 to 13890. [2019-12-07 19:00:51,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13890 states. [2019-12-07 19:00:51,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13890 states to 13890 states and 16800 transitions. [2019-12-07 19:00:51,321 INFO L78 Accepts]: Start accepts. Automaton has 13890 states and 16800 transitions. Word has length 179 [2019-12-07 19:00:51,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:51,321 INFO L462 AbstractCegarLoop]: Abstraction has 13890 states and 16800 transitions. [2019-12-07 19:00:51,321 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:51,321 INFO L276 IsEmpty]: Start isEmpty. Operand 13890 states and 16800 transitions. [2019-12-07 19:00:51,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:51,322 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:51,322 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:51,322 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:51,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:51,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1901570305, now seen corresponding path program 1 times [2019-12-07 19:00:51,323 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:51,323 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091352358] [2019-12-07 19:00:51,323 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:51,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:51,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:51,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2091352358] [2019-12-07 19:00:51,366 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:51,366 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:00:51,366 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868903632] [2019-12-07 19:00:51,367 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:00:51,367 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:51,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:00:51,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:51,367 INFO L87 Difference]: Start difference. First operand 13890 states and 16800 transitions. Second operand 5 states. [2019-12-07 19:00:53,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:53,014 INFO L93 Difference]: Finished difference Result 27482 states and 33243 transitions. [2019-12-07 19:00:53,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:53,015 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 179 [2019-12-07 19:00:53,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:53,024 INFO L225 Difference]: With dead ends: 27482 [2019-12-07 19:00:53,024 INFO L226 Difference]: Without dead ends: 13890 [2019-12-07 19:00:53,031 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:00:53,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13890 states. [2019-12-07 19:00:54,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13890 to 13890. [2019-12-07 19:00:54,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13890 states. [2019-12-07 19:00:54,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13890 states to 13890 states and 16690 transitions. [2019-12-07 19:00:54,553 INFO L78 Accepts]: Start accepts. Automaton has 13890 states and 16690 transitions. Word has length 179 [2019-12-07 19:00:54,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:54,553 INFO L462 AbstractCegarLoop]: Abstraction has 13890 states and 16690 transitions. [2019-12-07 19:00:54,553 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:00:54,553 INFO L276 IsEmpty]: Start isEmpty. Operand 13890 states and 16690 transitions. [2019-12-07 19:00:54,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-12-07 19:00:54,554 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:54,554 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:54,554 INFO L410 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:54,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:54,554 INFO L82 PathProgramCache]: Analyzing trace with hash 1004177027, now seen corresponding path program 1 times [2019-12-07 19:00:54,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:54,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581703156] [2019-12-07 19:00:54,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:54,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:00:54,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:00:54,656 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 19:00:54,656 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 19:00:54,811 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 07:00:54 BoogieIcfgContainer [2019-12-07 19:00:54,811 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 19:00:54,812 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 19:00:54,812 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 19:00:54,812 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 19:00:54,812 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 07:00:05" (3/4) ... [2019-12-07 19:00:54,814 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 19:00:54,940 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_d5915b58-f565-4a6e-977a-7dd0bfc51b9a/bin/uautomizer/witness.graphml [2019-12-07 19:00:54,940 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 19:00:54,941 INFO L168 Benchmark]: Toolchain (without parser) took 51894.04 ms. Allocated memory was 1.0 GB in the beginning and 4.9 GB in the end (delta: 3.9 GB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -166.3 MB). Peak memory consumption was 3.7 GB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,942 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:00:54,942 INFO L168 Benchmark]: CACSL2BoogieTranslator took 340.56 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 90.7 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -132.6 MB). Peak memory consumption was 26.5 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,942 INFO L168 Benchmark]: Boogie Procedure Inliner took 79.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,942 INFO L168 Benchmark]: Boogie Preprocessor took 82.17 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,943 INFO L168 Benchmark]: RCFGBuilder took 1807.26 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 876.8 MB in the end (delta: 160.2 MB). Peak memory consumption was 230.8 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,943 INFO L168 Benchmark]: TraceAbstraction took 49452.42 ms. Allocated memory was 1.1 GB in the beginning and 4.9 GB in the end (delta: 3.8 GB). Free memory was 876.8 MB in the beginning and 1.2 GB in the end (delta: -335.2 MB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,943 INFO L168 Benchmark]: Witness Printer took 128.09 ms. Allocated memory is still 4.9 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 105.1 MB). Peak memory consumption was 105.1 MB. Max. memory is 11.5 GB. [2019-12-07 19:00:54,944 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 340.56 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 90.7 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -132.6 MB). Peak memory consumption was 26.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 79.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 82.17 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1807.26 ms. Allocated memory is still 1.1 GB. Free memory was 1.0 GB in the beginning and 876.8 MB in the end (delta: 160.2 MB). Peak memory consumption was 230.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 49452.42 ms. Allocated memory was 1.1 GB in the beginning and 4.9 GB in the end (delta: 3.8 GB). Free memory was 876.8 MB in the beginning and 1.2 GB in the end (delta: -335.2 MB). Peak memory consumption was 3.5 GB. Max. memory is 11.5 GB. * Witness Printer took 128.09 ms. Allocated memory is still 4.9 GB. Free memory was 1.2 GB in the beginning and 1.1 GB in the end (delta: 105.1 MB). Peak memory consumption was 105.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int t14_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int t6_st ; [L37] int t7_st ; [L38] int t8_st ; [L39] int t9_st ; [L40] int t10_st ; [L41] int t11_st ; [L42] int t12_st ; [L43] int t13_st ; [L44] int t14_st ; [L45] int m_i ; [L46] int t1_i ; [L47] int t2_i ; [L48] int t3_i ; [L49] int t4_i ; [L50] int t5_i ; [L51] int t6_i ; [L52] int t7_i ; [L53] int t8_i ; [L54] int t9_i ; [L55] int t10_i ; [L56] int t11_i ; [L57] int t12_i ; [L58] int t13_i ; [L59] int t14_i ; [L60] int M_E = 2; [L61] int T1_E = 2; [L62] int T2_E = 2; [L63] int T3_E = 2; [L64] int T4_E = 2; [L65] int T5_E = 2; [L66] int T6_E = 2; [L67] int T7_E = 2; [L68] int T8_E = 2; [L69] int T9_E = 2; [L70] int T10_E = 2; [L71] int T11_E = 2; [L72] int T12_E = 2; [L73] int T13_E = 2; [L74] int T14_E = 2; [L75] int E_1 = 2; [L76] int E_2 = 2; [L77] int E_3 = 2; [L78] int E_4 = 2; [L79] int E_5 = 2; [L80] int E_6 = 2; [L81] int E_7 = 2; [L82] int E_8 = 2; [L83] int E_9 = 2; [L84] int E_10 = 2; [L85] int E_11 = 2; [L86] int E_12 = 2; [L87] int E_13 = 2; [L88] int E_14 = 2; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=0, m_pc=0, m_st=0, T10_E=2, t10_i=0, t10_pc=0, t10_st=0, T11_E=2, t11_i=0, t11_pc=0, t11_st=0, T12_E=2, t12_i=0, t12_pc=0, t12_st=0, T13_E=2, t13_i=0, t13_pc=0, t13_st=0, T14_E=2, t14_i=0, t14_pc=0, t14_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0, T5_E=2, t5_i=0, t5_pc=0, t5_st=0, T6_E=2, t6_i=0, t6_pc=0, t6_st=0, T7_E=2, t7_i=0, t7_pc=0, t7_st=0, T8_E=2, t8_i=0, t8_pc=0, t8_st=0, T9_E=2, t9_i=0, t9_pc=0, t9_st=0] [L2052] int __retres1 ; [L1954] m_i = 1 [L1955] t1_i = 1 [L1956] t2_i = 1 [L1957] t3_i = 1 [L1958] t4_i = 1 [L1959] t5_i = 1 [L1960] t6_i = 1 [L1961] t7_i = 1 [L1962] t8_i = 1 [L1963] t9_i = 1 [L1964] t10_i = 1 [L1965] t11_i = 1 [L1966] t12_i = 1 [L1967] t13_i = 1 [L1968] t14_i = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1993] int kernel_st ; [L1994] int tmp ; [L1995] int tmp___0 ; [L1999] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L929] COND TRUE m_i == 1 [L930] m_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L934] COND TRUE t1_i == 1 [L935] t1_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L939] COND TRUE t2_i == 1 [L940] t2_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L944] COND TRUE t3_i == 1 [L945] t3_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L949] COND TRUE t4_i == 1 [L950] t4_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L954] COND TRUE t5_i == 1 [L955] t5_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L959] COND TRUE t6_i == 1 [L960] t6_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L964] COND TRUE t7_i == 1 [L965] t7_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L969] COND TRUE t8_i == 1 [L970] t8_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L974] COND TRUE t9_i == 1 [L975] t9_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L979] COND TRUE t10_i == 1 [L980] t10_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L984] COND TRUE t11_i == 1 [L985] t11_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L989] COND TRUE t12_i == 1 [L990] t12_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L994] COND TRUE t13_i == 1 [L995] t13_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L999] COND TRUE t14_i == 1 [L1000] t14_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1332] COND FALSE !(M_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1337] COND FALSE !(T1_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(T2_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1347] COND FALSE !(T3_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1352] COND FALSE !(T4_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1357] COND FALSE !(T5_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1362] COND FALSE !(T6_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1367] COND FALSE !(T7_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1372] COND FALSE !(T8_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1377] COND FALSE !(T9_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1382] COND FALSE !(T10_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1387] COND FALSE !(T11_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1392] COND FALSE !(T12_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1397] COND FALSE !(T13_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1402] COND FALSE !(T14_E == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1407] COND FALSE !(E_1 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1412] COND FALSE !(E_2 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1417] COND FALSE !(E_3 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1422] COND FALSE !(E_4 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1427] COND FALSE !(E_5 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1432] COND FALSE !(E_6 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1437] COND FALSE !(E_7 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1442] COND FALSE !(E_8 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1447] COND FALSE !(E_9 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1452] COND FALSE !(E_10 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1457] COND FALSE !(E_11 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1462] COND FALSE !(E_12 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1467] COND FALSE !(E_13 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1472] COND FALSE !(E_14 == 0) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1635] int tmp ; [L1636] int tmp___0 ; [L1637] int tmp___1 ; [L1638] int tmp___2 ; [L1639] int tmp___3 ; [L1640] int tmp___4 ; [L1641] int tmp___5 ; [L1642] int tmp___6 ; [L1643] int tmp___7 ; [L1644] int tmp___8 ; [L1645] int tmp___9 ; [L1646] int tmp___10 ; [L1647] int tmp___11 ; [L1648] int tmp___12 ; [L1649] int tmp___13 ; [L633] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] COND FALSE !(m_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L648] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1654] tmp = is_master_triggered() [L1656] COND FALSE !(\read(tmp)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L652] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L667] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1662] tmp___0 = is_transmit1_triggered() [L1664] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L671] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L686] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1670] tmp___1 = is_transmit2_triggered() [L1672] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L690] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L705] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1678] tmp___2 = is_transmit3_triggered() [L1680] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L709] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L724] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1686] tmp___3 = is_transmit4_triggered() [L1688] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L728] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L743] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1694] tmp___4 = is_transmit5_triggered() [L1696] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L747] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L762] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1702] tmp___5 = is_transmit6_triggered() [L1704] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L766] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L781] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1710] tmp___6 = is_transmit7_triggered() [L1712] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L785] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] COND FALSE !(t8_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L800] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1718] tmp___7 = is_transmit8_triggered() [L1720] COND FALSE !(\read(tmp___7)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L804] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] COND FALSE !(t9_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L819] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1726] tmp___8 = is_transmit9_triggered() [L1728] COND FALSE !(\read(tmp___8)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L823] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] COND FALSE !(t10_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L838] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1734] tmp___9 = is_transmit10_triggered() [L1736] COND FALSE !(\read(tmp___9)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L842] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] COND FALSE !(t11_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L857] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1742] tmp___10 = is_transmit11_triggered() [L1744] COND FALSE !(\read(tmp___10)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L861] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] COND FALSE !(t12_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1750] tmp___11 = is_transmit12_triggered() [L1752] COND FALSE !(\read(tmp___11)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L880] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L883] COND FALSE !(t13_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L895] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1758] tmp___12 = is_transmit13_triggered() [L1760] COND FALSE !(\read(tmp___12)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L899] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L902] COND FALSE !(t14_pc == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] __retres1 = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L914] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1766] tmp___13 = is_transmit14_triggered() [L1768] COND FALSE !(\read(tmp___13)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1485] COND FALSE !(M_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1490] COND FALSE !(T1_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(T2_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1500] COND FALSE !(T3_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1505] COND FALSE !(T4_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1510] COND FALSE !(T5_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1515] COND FALSE !(T6_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1520] COND FALSE !(T7_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1525] COND FALSE !(T8_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1530] COND FALSE !(T9_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1535] COND FALSE !(T10_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1540] COND FALSE !(T11_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1545] COND FALSE !(T12_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1550] COND FALSE !(T13_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1555] COND FALSE !(T14_E == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1560] COND FALSE !(E_1 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1565] COND FALSE !(E_2 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1570] COND FALSE !(E_3 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1575] COND FALSE !(E_4 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1580] COND FALSE !(E_5 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1585] COND FALSE !(E_6 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1590] COND FALSE !(E_7 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1595] COND FALSE !(E_8 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1600] COND FALSE !(E_9 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1605] COND FALSE !(E_10 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1610] COND FALSE !(E_11 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1615] COND FALSE !(E_12 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1620] COND FALSE !(E_13 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1625] COND FALSE !(E_14 == 1) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2007] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2010] kernel_st = 1 [L1096] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1100] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1009] int __retres1 ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1012] COND TRUE m_st == 0 [L1013] __retres1 = 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1091] return (__retres1); VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] tmp = exists_runnable_thread() [L1105] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE m_st == 0 [L1111] int tmp_ndt_1; [L1112] tmp_ndt_1 = __VERIFIER_nondet_int() [L1113] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1124] COND TRUE t1_st == 0 [L1125] int tmp_ndt_2; [L1126] tmp_ndt_2 = __VERIFIER_nondet_int() [L1127] COND FALSE !(\read(tmp_ndt_2)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 2018 locations, 1 error locations. Result: UNSAFE, OverallTime: 49.2s, OverallIterations: 47, TraceHistogramMax: 1, AutomataDifference: 28.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 127614 SDtfs, 174983 SDslu, 71134 SDs, 0 SdLazy, 2123 SolverSat, 1215 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 160 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=13890occurred in iteration=45, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 18.1s AutomataMinimizationTime, 46 MinimizatonAttempts, 96915 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 8380 NumberOfCodeBlocks, 8380 NumberOfCodeBlocksAsserted, 47 NumberOfCheckSat, 8155 ConstructedInterpolants, 0 QuantifiedInterpolants, 2077177 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 46 InterpolantComputations, 46 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...