./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/triangular-longer-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/triangular-longer-2.i -s /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 85b94be996486a7516ccc33e88e36127bb614ed5 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 15:07:56,435 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 15:07:56,437 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 15:07:56,444 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 15:07:56,444 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 15:07:56,445 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 15:07:56,446 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 15:07:56,447 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 15:07:56,448 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 15:07:56,449 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 15:07:56,449 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 15:07:56,450 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 15:07:56,450 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 15:07:56,451 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 15:07:56,451 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 15:07:56,452 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 15:07:56,453 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 15:07:56,453 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 15:07:56,455 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 15:07:56,456 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 15:07:56,457 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 15:07:56,458 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 15:07:56,459 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 15:07:56,459 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 15:07:56,461 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 15:07:56,461 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 15:07:56,461 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 15:07:56,461 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 15:07:56,462 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 15:07:56,462 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 15:07:56,462 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 15:07:56,463 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 15:07:56,463 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 15:07:56,463 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 15:07:56,464 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 15:07:56,464 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 15:07:56,465 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 15:07:56,465 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 15:07:56,465 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 15:07:56,465 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 15:07:56,466 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 15:07:56,466 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 15:07:56,475 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 15:07:56,475 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 15:07:56,476 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 15:07:56,476 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 15:07:56,476 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 15:07:56,476 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 15:07:56,476 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 15:07:56,476 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 15:07:56,476 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 15:07:56,477 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 15:07:56,477 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:07:56,478 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 15:07:56,478 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 15:07:56,479 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 15:07:56,479 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 15:07:56,479 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 85b94be996486a7516ccc33e88e36127bb614ed5 [2019-12-07 15:07:56,579 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 15:07:56,586 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 15:07:56,589 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 15:07:56,590 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 15:07:56,590 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 15:07:56,590 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/../../sv-benchmarks/c/pthread/triangular-longer-2.i [2019-12-07 15:07:56,628 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/data/8f6149c07/634ebe473fb44efaaabddedcf07a8d90/FLAG4014be0f3 [2019-12-07 15:07:57,011 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 15:07:57,012 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/sv-benchmarks/c/pthread/triangular-longer-2.i [2019-12-07 15:07:57,021 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/data/8f6149c07/634ebe473fb44efaaabddedcf07a8d90/FLAG4014be0f3 [2019-12-07 15:07:57,370 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/data/8f6149c07/634ebe473fb44efaaabddedcf07a8d90 [2019-12-07 15:07:57,372 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 15:07:57,373 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 15:07:57,374 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 15:07:57,374 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 15:07:57,376 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 15:07:57,377 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,378 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1fe18d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57, skipping insertion in model container [2019-12-07 15:07:57,379 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,384 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 15:07:57,409 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 15:07:57,656 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:07:57,662 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 15:07:57,698 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 15:07:57,744 INFO L208 MainTranslator]: Completed translation [2019-12-07 15:07:57,745 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57 WrapperNode [2019-12-07 15:07:57,745 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 15:07:57,746 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 15:07:57,746 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 15:07:57,746 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 15:07:57,752 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,765 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,779 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 15:07:57,779 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 15:07:57,779 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 15:07:57,780 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 15:07:57,785 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,786 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,787 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,788 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,791 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,794 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,795 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... [2019-12-07 15:07:57,797 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 15:07:57,798 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 15:07:57,798 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 15:07:57,798 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 15:07:57,798 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2019-12-07 15:07:57,839 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2019-12-07 15:07:57,839 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 15:07:57,839 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 15:07:57,839 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 15:07:57,840 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 15:07:58,003 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 15:07:58,004 INFO L287 CfgBuilder]: Removed 6 assume(true) statements. [2019-12-07 15:07:58,004 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:58 BoogieIcfgContainer [2019-12-07 15:07:58,004 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 15:07:58,005 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 15:07:58,005 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 15:07:58,007 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 15:07:58,007 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 03:07:57" (1/3) ... [2019-12-07 15:07:58,008 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@68621122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:07:58, skipping insertion in model container [2019-12-07 15:07:58,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 03:07:57" (2/3) ... [2019-12-07 15:07:58,008 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@68621122 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 03:07:58, skipping insertion in model container [2019-12-07 15:07:58,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:58" (3/3) ... [2019-12-07 15:07:58,009 INFO L109 eAbstractionObserver]: Analyzing ICFG triangular-longer-2.i [2019-12-07 15:07:58,015 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 15:07:58,015 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 15:07:58,020 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 15:07:58,020 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 15:07:58,036 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,037 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,038 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,039 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,040 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 15:07:58,053 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-12-07 15:07:58,065 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 15:07:58,065 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 15:07:58,065 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 15:07:58,065 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 15:07:58,065 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 15:07:58,066 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 15:07:58,066 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 15:07:58,066 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 15:07:58,074 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 53 places, 51 transitions [2019-12-07 15:07:58,075 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 53 places, 51 transitions [2019-12-07 15:07:58,098 INFO L134 PetriNetUnfolder]: 5/49 cut-off events. [2019-12-07 15:07:58,098 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:07:58,102 INFO L76 FinitePrefix]: Finished finitePrefix Result has 56 conditions, 49 events. 5/49 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 7. Compared 92 event pairs. 6/49 useless extension candidates. Maximal degree in co-relation 37. Up to 2 conditions per place. [2019-12-07 15:07:58,104 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 53 places, 51 transitions [2019-12-07 15:07:58,113 INFO L134 PetriNetUnfolder]: 5/49 cut-off events. [2019-12-07 15:07:58,113 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 15:07:58,114 INFO L76 FinitePrefix]: Finished finitePrefix Result has 56 conditions, 49 events. 5/49 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 7. Compared 92 event pairs. 6/49 useless extension candidates. Maximal degree in co-relation 37. Up to 2 conditions per place. [2019-12-07 15:07:58,115 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 740 [2019-12-07 15:07:58,116 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 15:07:58,776 INFO L206 etLargeBlockEncoding]: Checked pairs total: 604 [2019-12-07 15:07:58,777 INFO L214 etLargeBlockEncoding]: Total number of compositions: 41 [2019-12-07 15:07:58,779 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 16 places, 14 transitions [2019-12-07 15:07:58,786 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 35 states. [2019-12-07 15:07:58,787 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states. [2019-12-07 15:07:58,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 15:07:58,791 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:58,791 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 15:07:58,791 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:58,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:58,795 INFO L82 PathProgramCache]: Analyzing trace with hash 205828742, now seen corresponding path program 1 times [2019-12-07 15:07:58,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:58,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623627532] [2019-12-07 15:07:58,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:58,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:58,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:58,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623627532] [2019-12-07 15:07:58,959 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:58,959 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 15:07:58,960 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980020717] [2019-12-07 15:07:58,963 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 15:07:58,963 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:07:58,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 15:07:58,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:07:58,974 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 3 states. [2019-12-07 15:07:58,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:58,996 INFO L93 Difference]: Finished difference Result 44 states and 107 transitions. [2019-12-07 15:07:58,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 15:07:58,997 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 15:07:58,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:59,005 INFO L225 Difference]: With dead ends: 44 [2019-12-07 15:07:59,005 INFO L226 Difference]: Without dead ends: 26 [2019-12-07 15:07:59,006 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 15:07:59,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-12-07 15:07:59,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2019-12-07 15:07:59,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-12-07 15:07:59,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 56 transitions. [2019-12-07 15:07:59,031 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 56 transitions. Word has length 5 [2019-12-07 15:07:59,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:59,031 INFO L462 AbstractCegarLoop]: Abstraction has 26 states and 56 transitions. [2019-12-07 15:07:59,032 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 15:07:59,032 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 56 transitions. [2019-12-07 15:07:59,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 15:07:59,032 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:59,032 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:59,032 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:59,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:59,033 INFO L82 PathProgramCache]: Analyzing trace with hash 232910220, now seen corresponding path program 1 times [2019-12-07 15:07:59,033 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:59,033 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526017420] [2019-12-07 15:07:59,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:59,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:59,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,099 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526017420] [2019-12-07 15:07:59,099 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:59,099 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 15:07:59,100 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449533125] [2019-12-07 15:07:59,100 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 15:07:59,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:07:59,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 15:07:59,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 15:07:59,101 INFO L87 Difference]: Start difference. First operand 26 states and 56 transitions. Second operand 4 states. [2019-12-07 15:07:59,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:59,138 INFO L93 Difference]: Finished difference Result 40 states and 82 transitions. [2019-12-07 15:07:59,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:07:59,138 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 7 [2019-12-07 15:07:59,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:59,139 INFO L225 Difference]: With dead ends: 40 [2019-12-07 15:07:59,139 INFO L226 Difference]: Without dead ends: 30 [2019-12-07 15:07:59,139 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:07:59,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2019-12-07 15:07:59,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 26. [2019-12-07 15:07:59,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-12-07 15:07:59,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 54 transitions. [2019-12-07 15:07:59,143 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 54 transitions. Word has length 7 [2019-12-07 15:07:59,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:59,143 INFO L462 AbstractCegarLoop]: Abstraction has 26 states and 54 transitions. [2019-12-07 15:07:59,143 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 15:07:59,144 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 54 transitions. [2019-12-07 15:07:59,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 15:07:59,144 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:59,144 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:59,144 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:59,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:59,145 INFO L82 PathProgramCache]: Analyzing trace with hash 484474390, now seen corresponding path program 1 times [2019-12-07 15:07:59,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:59,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333656030] [2019-12-07 15:07:59,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:59,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,208 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333656030] [2019-12-07 15:07:59,208 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 15:07:59,208 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 15:07:59,208 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450254480] [2019-12-07 15:07:59,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 15:07:59,209 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:07:59,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 15:07:59,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 15:07:59,209 INFO L87 Difference]: Start difference. First operand 26 states and 54 transitions. Second operand 5 states. [2019-12-07 15:07:59,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:59,241 INFO L93 Difference]: Finished difference Result 34 states and 70 transitions. [2019-12-07 15:07:59,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 15:07:59,242 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 9 [2019-12-07 15:07:59,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:59,242 INFO L225 Difference]: With dead ends: 34 [2019-12-07 15:07:59,243 INFO L226 Difference]: Without dead ends: 28 [2019-12-07 15:07:59,243 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:07:59,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-12-07 15:07:59,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2019-12-07 15:07:59,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-12-07 15:07:59,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 58 transitions. [2019-12-07 15:07:59,247 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 58 transitions. Word has length 9 [2019-12-07 15:07:59,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:59,248 INFO L462 AbstractCegarLoop]: Abstraction has 28 states and 58 transitions. [2019-12-07 15:07:59,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 15:07:59,248 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 58 transitions. [2019-12-07 15:07:59,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2019-12-07 15:07:59,248 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:59,249 INFO L410 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:59,249 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:59,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:59,249 INFO L82 PathProgramCache]: Analyzing trace with hash 2133804259, now seen corresponding path program 2 times [2019-12-07 15:07:59,249 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:59,250 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239547493] [2019-12-07 15:07:59,250 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:59,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:59,318 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,318 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239547493] [2019-12-07 15:07:59,318 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [399690622] [2019-12-07 15:07:59,319 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:07:59,356 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 15:07:59,357 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:07:59,358 INFO L264 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 15:07:59,361 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:07:59,379 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,380 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:07:59,380 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2019-12-07 15:07:59,380 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059257206] [2019-12-07 15:07:59,380 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:07:59,380 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:07:59,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:07:59,381 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:07:59,381 INFO L87 Difference]: Start difference. First operand 28 states and 58 transitions. Second operand 7 states. [2019-12-07 15:07:59,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:59,408 INFO L93 Difference]: Finished difference Result 32 states and 66 transitions. [2019-12-07 15:07:59,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 15:07:59,409 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 10 [2019-12-07 15:07:59,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:59,409 INFO L225 Difference]: With dead ends: 32 [2019-12-07 15:07:59,409 INFO L226 Difference]: Without dead ends: 29 [2019-12-07 15:07:59,410 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:07:59,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2019-12-07 15:07:59,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2019-12-07 15:07:59,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-12-07 15:07:59,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 46 transitions. [2019-12-07 15:07:59,412 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 46 transitions. Word has length 10 [2019-12-07 15:07:59,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:59,412 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 46 transitions. [2019-12-07 15:07:59,413 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:07:59,413 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 46 transitions. [2019-12-07 15:07:59,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2019-12-07 15:07:59,413 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:59,413 INFO L410 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:59,613 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:07:59,614 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:59,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:59,614 INFO L82 PathProgramCache]: Analyzing trace with hash 2117948007, now seen corresponding path program 3 times [2019-12-07 15:07:59,615 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:59,615 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266782348] [2019-12-07 15:07:59,615 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:07:59,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:07:59,676 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,676 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266782348] [2019-12-07 15:07:59,676 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1524279629] [2019-12-07 15:07:59,676 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:07:59,713 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-12-07 15:07:59,713 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:07:59,714 INFO L264 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 15:07:59,715 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:07:59,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:07:59,729 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:07:59,729 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2019-12-07 15:07:59,730 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070215045] [2019-12-07 15:07:59,730 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 15:07:59,730 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:07:59,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 15:07:59,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 15:07:59,730 INFO L87 Difference]: Start difference. First operand 22 states and 46 transitions. Second operand 7 states. [2019-12-07 15:07:59,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:07:59,782 INFO L93 Difference]: Finished difference Result 37 states and 76 transitions. [2019-12-07 15:07:59,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:07:59,783 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 10 [2019-12-07 15:07:59,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:07:59,783 INFO L225 Difference]: With dead ends: 37 [2019-12-07 15:07:59,784 INFO L226 Difference]: Without dead ends: 31 [2019-12-07 15:07:59,784 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=56, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:07:59,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2019-12-07 15:07:59,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 25. [2019-12-07 15:07:59,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-12-07 15:07:59,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 52 transitions. [2019-12-07 15:07:59,788 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 52 transitions. Word has length 10 [2019-12-07 15:07:59,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:07:59,788 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 52 transitions. [2019-12-07 15:07:59,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 15:07:59,788 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 52 transitions. [2019-12-07 15:07:59,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 15:07:59,789 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:07:59,789 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:07:59,989 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:07:59,990 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:07:59,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:07:59,990 INFO L82 PathProgramCache]: Analyzing trace with hash 1723422894, now seen corresponding path program 4 times [2019-12-07 15:07:59,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:07:59,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339618266] [2019-12-07 15:07:59,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:00,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:00,058 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:00,058 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339618266] [2019-12-07 15:08:00,058 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1974165333] [2019-12-07 15:08:00,058 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:00,092 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 15:08:00,092 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:00,093 INFO L264 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 15:08:00,094 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:00,103 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:00,103 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:00,103 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2019-12-07 15:08:00,104 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637258151] [2019-12-07 15:08:00,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 15:08:00,104 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:00,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 15:08:00,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 15:08:00,104 INFO L87 Difference]: Start difference. First operand 25 states and 52 transitions. Second operand 8 states. [2019-12-07 15:08:00,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:00,155 INFO L93 Difference]: Finished difference Result 41 states and 84 transitions. [2019-12-07 15:08:00,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 15:08:00,156 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 11 [2019-12-07 15:08:00,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:00,156 INFO L225 Difference]: With dead ends: 41 [2019-12-07 15:08:00,156 INFO L226 Difference]: Without dead ends: 37 [2019-12-07 15:08:00,156 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2019-12-07 15:08:00,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-12-07 15:08:00,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 34. [2019-12-07 15:08:00,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2019-12-07 15:08:00,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 71 transitions. [2019-12-07 15:08:00,159 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 71 transitions. Word has length 11 [2019-12-07 15:08:00,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:00,160 INFO L462 AbstractCegarLoop]: Abstraction has 34 states and 71 transitions. [2019-12-07 15:08:00,160 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 15:08:00,160 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 71 transitions. [2019-12-07 15:08:00,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-12-07 15:08:00,160 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:00,160 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:00,361 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:00,361 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:00,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:00,362 INFO L82 PathProgramCache]: Analyzing trace with hash -466461505, now seen corresponding path program 5 times [2019-12-07 15:08:00,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:00,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228204171] [2019-12-07 15:08:00,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:00,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:00,444 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:00,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228204171] [2019-12-07 15:08:00,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [728199326] [2019-12-07 15:08:00,445 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:00,479 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2019-12-07 15:08:00,479 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:00,480 INFO L264 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 15:08:00,481 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:00,493 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:00,493 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:00,494 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2019-12-07 15:08:00,494 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625780776] [2019-12-07 15:08:00,494 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 15:08:00,494 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:00,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 15:08:00,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:08:00,495 INFO L87 Difference]: Start difference. First operand 34 states and 71 transitions. Second operand 9 states. [2019-12-07 15:08:00,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:00,586 INFO L93 Difference]: Finished difference Result 43 states and 88 transitions. [2019-12-07 15:08:00,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 15:08:00,586 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 12 [2019-12-07 15:08:00,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:00,587 INFO L225 Difference]: With dead ends: 43 [2019-12-07 15:08:00,587 INFO L226 Difference]: Without dead ends: 37 [2019-12-07 15:08:00,587 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=65, Invalid=117, Unknown=0, NotChecked=0, Total=182 [2019-12-07 15:08:00,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-12-07 15:08:00,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2019-12-07 15:08:00,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-12-07 15:08:00,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 75 transitions. [2019-12-07 15:08:00,590 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 75 transitions. Word has length 12 [2019-12-07 15:08:00,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:00,590 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 75 transitions. [2019-12-07 15:08:00,590 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 15:08:00,590 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 75 transitions. [2019-12-07 15:08:00,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:08:00,591 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:00,591 INFO L410 BasicCegarLoop]: trace histogram [4, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:00,791 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:00,792 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:00,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:00,792 INFO L82 PathProgramCache]: Analyzing trace with hash -1647973298, now seen corresponding path program 6 times [2019-12-07 15:08:00,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:00,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500869023] [2019-12-07 15:08:00,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:00,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:00,911 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:00,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500869023] [2019-12-07 15:08:00,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [328199185] [2019-12-07 15:08:00,911 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:00,952 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2019-12-07 15:08:00,952 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:00,953 INFO L264 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 15:08:00,954 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:00,964 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:00,965 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:00,965 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2019-12-07 15:08:00,965 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787097877] [2019-12-07 15:08:00,965 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 15:08:00,966 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:00,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 15:08:00,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2019-12-07 15:08:00,966 INFO L87 Difference]: Start difference. First operand 36 states and 75 transitions. Second operand 9 states. [2019-12-07 15:08:01,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:01,018 INFO L93 Difference]: Finished difference Result 41 states and 84 transitions. [2019-12-07 15:08:01,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 15:08:01,018 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 13 [2019-12-07 15:08:01,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:01,019 INFO L225 Difference]: With dead ends: 41 [2019-12-07 15:08:01,019 INFO L226 Difference]: Without dead ends: 37 [2019-12-07 15:08:01,020 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:08:01,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-12-07 15:08:01,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 27. [2019-12-07 15:08:01,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-12-07 15:08:01,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 56 transitions. [2019-12-07 15:08:01,023 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 56 transitions. Word has length 13 [2019-12-07 15:08:01,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:01,023 INFO L462 AbstractCegarLoop]: Abstraction has 27 states and 56 transitions. [2019-12-07 15:08:01,023 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 15:08:01,023 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 56 transitions. [2019-12-07 15:08:01,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 15:08:01,024 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:01,024 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:01,224 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:01,225 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:01,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:01,225 INFO L82 PathProgramCache]: Analyzing trace with hash -1647973050, now seen corresponding path program 7 times [2019-12-07 15:08:01,226 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:01,226 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793804310] [2019-12-07 15:08:01,226 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:01,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:01,360 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:01,361 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793804310] [2019-12-07 15:08:01,361 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [910902583] [2019-12-07 15:08:01,361 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:01,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:01,401 INFO L264 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 15:08:01,401 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:01,412 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:01,412 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:01,412 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2019-12-07 15:08:01,412 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355301462] [2019-12-07 15:08:01,413 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 15:08:01,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:01,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 15:08:01,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2019-12-07 15:08:01,413 INFO L87 Difference]: Start difference. First operand 27 states and 56 transitions. Second operand 10 states. [2019-12-07 15:08:01,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:01,493 INFO L93 Difference]: Finished difference Result 45 states and 92 transitions. [2019-12-07 15:08:01,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 15:08:01,493 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 13 [2019-12-07 15:08:01,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:01,494 INFO L225 Difference]: With dead ends: 45 [2019-12-07 15:08:01,494 INFO L226 Difference]: Without dead ends: 41 [2019-12-07 15:08:01,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=85, Invalid=155, Unknown=0, NotChecked=0, Total=240 [2019-12-07 15:08:01,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-12-07 15:08:01,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 38. [2019-12-07 15:08:01,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-12-07 15:08:01,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 79 transitions. [2019-12-07 15:08:01,497 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 79 transitions. Word has length 13 [2019-12-07 15:08:01,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:01,497 INFO L462 AbstractCegarLoop]: Abstraction has 38 states and 79 transitions. [2019-12-07 15:08:01,497 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 15:08:01,497 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 79 transitions. [2019-12-07 15:08:01,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2019-12-07 15:08:01,498 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:01,498 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:01,698 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:01,699 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:01,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:01,699 INFO L82 PathProgramCache]: Analyzing trace with hash -1592905449, now seen corresponding path program 8 times [2019-12-07 15:08:01,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:01,700 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708155598] [2019-12-07 15:08:01,700 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:01,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:01,777 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:01,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708155598] [2019-12-07 15:08:01,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [564350569] [2019-12-07 15:08:01,777 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:01,814 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 15:08:01,814 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:01,815 INFO L264 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 15:08:01,816 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:01,826 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:01,827 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:01,827 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2019-12-07 15:08:01,827 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507743066] [2019-12-07 15:08:01,827 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 15:08:01,827 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:01,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 15:08:01,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:08:01,828 INFO L87 Difference]: Start difference. First operand 38 states and 79 transitions. Second operand 11 states. [2019-12-07 15:08:01,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:01,916 INFO L93 Difference]: Finished difference Result 47 states and 96 transitions. [2019-12-07 15:08:01,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:08:01,916 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 14 [2019-12-07 15:08:01,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:01,917 INFO L225 Difference]: With dead ends: 47 [2019-12-07 15:08:01,917 INFO L226 Difference]: Without dead ends: 41 [2019-12-07 15:08:01,917 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=106, Invalid=200, Unknown=0, NotChecked=0, Total=306 [2019-12-07 15:08:01,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-12-07 15:08:01,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2019-12-07 15:08:01,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2019-12-07 15:08:01,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 83 transitions. [2019-12-07 15:08:01,920 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 83 transitions. Word has length 14 [2019-12-07 15:08:01,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:01,920 INFO L462 AbstractCegarLoop]: Abstraction has 40 states and 83 transitions. [2019-12-07 15:08:01,920 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 15:08:01,920 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 83 transitions. [2019-12-07 15:08:01,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 15:08:01,920 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:01,920 INFO L410 BasicCegarLoop]: trace histogram [5, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:02,121 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:02,121 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:02,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:02,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1140832998, now seen corresponding path program 9 times [2019-12-07 15:08:02,122 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:02,122 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221627887] [2019-12-07 15:08:02,122 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:02,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:02,202 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:02,202 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221627887] [2019-12-07 15:08:02,202 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [57000684] [2019-12-07 15:08:02,202 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:02,242 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-12-07 15:08:02,242 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:02,243 INFO L264 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 15:08:02,243 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:02,255 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:02,256 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:02,256 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2019-12-07 15:08:02,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664088793] [2019-12-07 15:08:02,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 15:08:02,256 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:02,256 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 15:08:02,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 15:08:02,257 INFO L87 Difference]: Start difference. First operand 40 states and 83 transitions. Second operand 11 states. [2019-12-07 15:08:02,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:02,338 INFO L93 Difference]: Finished difference Result 50 states and 102 transitions. [2019-12-07 15:08:02,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 15:08:02,339 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 15 [2019-12-07 15:08:02,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:02,339 INFO L225 Difference]: With dead ends: 50 [2019-12-07 15:08:02,339 INFO L226 Difference]: Without dead ends: 45 [2019-12-07 15:08:02,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=176, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:08:02,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-12-07 15:08:02,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 41. [2019-12-07 15:08:02,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 15:08:02,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 85 transitions. [2019-12-07 15:08:02,342 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 85 transitions. Word has length 15 [2019-12-07 15:08:02,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:02,342 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 85 transitions. [2019-12-07 15:08:02,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 15:08:02,342 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 85 transitions. [2019-12-07 15:08:02,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 15:08:02,343 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:02,343 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:02,543 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:02,544 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:02,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:02,544 INFO L82 PathProgramCache]: Analyzing trace with hash 1006092315, now seen corresponding path program 10 times [2019-12-07 15:08:02,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:02,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29650604] [2019-12-07 15:08:02,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:02,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:02,634 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:02,634 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29650604] [2019-12-07 15:08:02,634 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1380223364] [2019-12-07 15:08:02,634 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:02,667 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 15:08:02,667 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:02,668 INFO L264 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 15:08:02,669 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:02,680 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:02,681 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:02,681 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2019-12-07 15:08:02,681 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698475924] [2019-12-07 15:08:02,681 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 15:08:02,681 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:02,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 15:08:02,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:08:02,682 INFO L87 Difference]: Start difference. First operand 41 states and 85 transitions. Second operand 13 states. [2019-12-07 15:08:02,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:02,789 INFO L93 Difference]: Finished difference Result 50 states and 102 transitions. [2019-12-07 15:08:02,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 15:08:02,789 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 16 [2019-12-07 15:08:02,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:02,789 INFO L225 Difference]: With dead ends: 50 [2019-12-07 15:08:02,790 INFO L226 Difference]: Without dead ends: 42 [2019-12-07 15:08:02,790 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=274, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:08:02,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2019-12-07 15:08:02,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 28. [2019-12-07 15:08:02,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-12-07 15:08:02,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 58 transitions. [2019-12-07 15:08:02,792 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 58 transitions. Word has length 16 [2019-12-07 15:08:02,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:02,793 INFO L462 AbstractCegarLoop]: Abstraction has 28 states and 58 transitions. [2019-12-07 15:08:02,793 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 15:08:02,793 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 58 transitions. [2019-12-07 15:08:02,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 15:08:02,793 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:02,793 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:02,994 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:02,994 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:02,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:02,995 INFO L82 PathProgramCache]: Analyzing trace with hash -1773777041, now seen corresponding path program 11 times [2019-12-07 15:08:02,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:02,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892324683] [2019-12-07 15:08:02,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:03,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:03,085 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:03,086 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892324683] [2019-12-07 15:08:03,086 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1234396538] [2019-12-07 15:08:03,086 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:03,118 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2019-12-07 15:08:03,118 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:03,119 INFO L264 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 15:08:03,120 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:03,131 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:03,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:03,131 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2019-12-07 15:08:03,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964743313] [2019-12-07 15:08:03,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 15:08:03,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:03,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 15:08:03,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2019-12-07 15:08:03,132 INFO L87 Difference]: Start difference. First operand 28 states and 58 transitions. Second operand 13 states. [2019-12-07 15:08:03,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:03,242 INFO L93 Difference]: Finished difference Result 49 states and 100 transitions. [2019-12-07 15:08:03,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 15:08:03,242 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 16 [2019-12-07 15:08:03,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:03,243 INFO L225 Difference]: With dead ends: 49 [2019-12-07 15:08:03,243 INFO L226 Difference]: Without dead ends: 43 [2019-12-07 15:08:03,243 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=157, Invalid=305, Unknown=0, NotChecked=0, Total=462 [2019-12-07 15:08:03,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2019-12-07 15:08:03,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 31. [2019-12-07 15:08:03,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-12-07 15:08:03,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 64 transitions. [2019-12-07 15:08:03,245 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 64 transitions. Word has length 16 [2019-12-07 15:08:03,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:03,245 INFO L462 AbstractCegarLoop]: Abstraction has 31 states and 64 transitions. [2019-12-07 15:08:03,246 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 15:08:03,246 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 64 transitions. [2019-12-07 15:08:03,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-12-07 15:08:03,246 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:03,246 INFO L410 BasicCegarLoop]: trace histogram [5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:03,447 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:03,448 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:03,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:03,448 INFO L82 PathProgramCache]: Analyzing trace with hash 1124090998, now seen corresponding path program 12 times [2019-12-07 15:08:03,448 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:03,449 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686110359] [2019-12-07 15:08:03,449 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:03,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:03,555 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:03,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686110359] [2019-12-07 15:08:03,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [266737039] [2019-12-07 15:08:03,555 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:03,589 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2019-12-07 15:08:03,589 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:03,589 INFO L264 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 15:08:03,590 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:03,603 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:03,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:03,604 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2019-12-07 15:08:03,604 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213561030] [2019-12-07 15:08:03,604 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 15:08:03,604 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:03,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 15:08:03,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=135, Unknown=0, NotChecked=0, Total=182 [2019-12-07 15:08:03,604 INFO L87 Difference]: Start difference. First operand 31 states and 64 transitions. Second operand 14 states. [2019-12-07 15:08:03,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:03,722 INFO L93 Difference]: Finished difference Result 51 states and 104 transitions. [2019-12-07 15:08:03,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 15:08:03,722 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 17 [2019-12-07 15:08:03,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:03,722 INFO L225 Difference]: With dead ends: 51 [2019-12-07 15:08:03,722 INFO L226 Difference]: Without dead ends: 45 [2019-12-07 15:08:03,723 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=158, Invalid=348, Unknown=0, NotChecked=0, Total=506 [2019-12-07 15:08:03,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-12-07 15:08:03,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 30. [2019-12-07 15:08:03,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-12-07 15:08:03,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 62 transitions. [2019-12-07 15:08:03,725 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 62 transitions. Word has length 17 [2019-12-07 15:08:03,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:03,725 INFO L462 AbstractCegarLoop]: Abstraction has 30 states and 62 transitions. [2019-12-07 15:08:03,725 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 15:08:03,725 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 62 transitions. [2019-12-07 15:08:03,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 15:08:03,726 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:03,726 INFO L410 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:03,926 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:03,927 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:03,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:03,927 INFO L82 PathProgramCache]: Analyzing trace with hash 502282183, now seen corresponding path program 13 times [2019-12-07 15:08:03,927 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:03,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933269799] [2019-12-07 15:08:03,928 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:03,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:04,030 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:04,030 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933269799] [2019-12-07 15:08:04,031 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846018026] [2019-12-07 15:08:04,031 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:04,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:04,067 INFO L264 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 15:08:04,068 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:04,082 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:04,082 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:04,082 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2019-12-07 15:08:04,082 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871835608] [2019-12-07 15:08:04,082 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 15:08:04,082 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:04,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 15:08:04,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=156, Unknown=0, NotChecked=0, Total=210 [2019-12-07 15:08:04,083 INFO L87 Difference]: Start difference. First operand 30 states and 62 transitions. Second operand 15 states. [2019-12-07 15:08:04,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:04,218 INFO L93 Difference]: Finished difference Result 53 states and 108 transitions. [2019-12-07 15:08:04,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:08:04,218 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 18 [2019-12-07 15:08:04,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:04,219 INFO L225 Difference]: With dead ends: 53 [2019-12-07 15:08:04,219 INFO L226 Difference]: Without dead ends: 47 [2019-12-07 15:08:04,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=218, Invalid=432, Unknown=0, NotChecked=0, Total=650 [2019-12-07 15:08:04,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2019-12-07 15:08:04,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 33. [2019-12-07 15:08:04,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2019-12-07 15:08:04,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 68 transitions. [2019-12-07 15:08:04,221 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 68 transitions. Word has length 18 [2019-12-07 15:08:04,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:04,221 INFO L462 AbstractCegarLoop]: Abstraction has 33 states and 68 transitions. [2019-12-07 15:08:04,221 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 15:08:04,221 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 68 transitions. [2019-12-07 15:08:04,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 15:08:04,222 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:04,222 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:04,422 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:04,422 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:04,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:04,423 INFO L82 PathProgramCache]: Analyzing trace with hash -2080307442, now seen corresponding path program 14 times [2019-12-07 15:08:04,423 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:04,423 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84761289] [2019-12-07 15:08:04,423 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:04,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:04,507 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:04,507 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84761289] [2019-12-07 15:08:04,507 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [675743111] [2019-12-07 15:08:04,508 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:04,542 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 15:08:04,542 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:04,543 INFO L264 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 15:08:04,544 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:04,560 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:04,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:04,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2019-12-07 15:08:04,561 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057183982] [2019-12-07 15:08:04,561 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 15:08:04,561 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:04,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 15:08:04,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2019-12-07 15:08:04,561 INFO L87 Difference]: Start difference. First operand 33 states and 68 transitions. Second operand 16 states. [2019-12-07 15:08:04,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:04,718 INFO L93 Difference]: Finished difference Result 57 states and 116 transitions. [2019-12-07 15:08:04,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 15:08:04,719 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 19 [2019-12-07 15:08:04,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:04,719 INFO L225 Difference]: With dead ends: 57 [2019-12-07 15:08:04,719 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 15:08:04,720 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 110 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=253, Invalid=503, Unknown=0, NotChecked=0, Total=756 [2019-12-07 15:08:04,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 15:08:04,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 50. [2019-12-07 15:08:04,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-12-07 15:08:04,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 103 transitions. [2019-12-07 15:08:04,723 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 103 transitions. Word has length 19 [2019-12-07 15:08:04,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:04,724 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 103 transitions. [2019-12-07 15:08:04,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 15:08:04,724 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 103 transitions. [2019-12-07 15:08:04,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 15:08:04,724 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:04,724 INFO L410 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:04,925 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:04,925 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:04,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:04,926 INFO L82 PathProgramCache]: Analyzing trace with hash 1656842783, now seen corresponding path program 15 times [2019-12-07 15:08:04,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:04,926 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274972222] [2019-12-07 15:08:04,926 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:04,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:05,044 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:05,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274972222] [2019-12-07 15:08:05,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1014823408] [2019-12-07 15:08:05,044 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:05,079 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2019-12-07 15:08:05,079 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:05,079 INFO L264 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 15:08:05,080 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:05,094 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:05,095 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:05,095 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2019-12-07 15:08:05,095 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534211890] [2019-12-07 15:08:05,095 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 15:08:05,095 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:05,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 15:08:05,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:08:05,095 INFO L87 Difference]: Start difference. First operand 50 states and 103 transitions. Second operand 17 states. [2019-12-07 15:08:05,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:05,272 INFO L93 Difference]: Finished difference Result 60 states and 122 transitions. [2019-12-07 15:08:05,272 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 15:08:05,272 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 20 [2019-12-07 15:08:05,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:05,273 INFO L225 Difference]: With dead ends: 60 [2019-12-07 15:08:05,273 INFO L226 Difference]: Without dead ends: 56 [2019-12-07 15:08:05,273 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=273, Invalid=597, Unknown=0, NotChecked=0, Total=870 [2019-12-07 15:08:05,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2019-12-07 15:08:05,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 37. [2019-12-07 15:08:05,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-12-07 15:08:05,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 76 transitions. [2019-12-07 15:08:05,275 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 76 transitions. Word has length 20 [2019-12-07 15:08:05,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:05,275 INFO L462 AbstractCegarLoop]: Abstraction has 37 states and 76 transitions. [2019-12-07 15:08:05,275 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 15:08:05,275 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 76 transitions. [2019-12-07 15:08:05,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 15:08:05,276 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:05,276 INFO L410 BasicCegarLoop]: trace histogram [8, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:05,476 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:05,476 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:05,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:05,477 INFO L82 PathProgramCache]: Analyzing trace with hash -2015657298, now seen corresponding path program 16 times [2019-12-07 15:08:05,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:05,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080926822] [2019-12-07 15:08:05,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:05,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:05,595 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:05,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080926822] [2019-12-07 15:08:05,596 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [803218868] [2019-12-07 15:08:05,596 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:05,627 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 15:08:05,627 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:05,628 INFO L264 TraceCheckSpWp]: Trace formula consists of 138 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 15:08:05,629 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:05,643 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:05,644 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:05,644 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2019-12-07 15:08:05,644 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594871636] [2019-12-07 15:08:05,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 15:08:05,644 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:05,644 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 15:08:05,644 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2019-12-07 15:08:05,645 INFO L87 Difference]: Start difference. First operand 37 states and 76 transitions. Second operand 17 states. [2019-12-07 15:08:05,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:05,810 INFO L93 Difference]: Finished difference Result 59 states and 120 transitions. [2019-12-07 15:08:05,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 15:08:05,810 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 21 [2019-12-07 15:08:05,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:05,811 INFO L225 Difference]: With dead ends: 59 [2019-12-07 15:08:05,811 INFO L226 Difference]: Without dead ends: 55 [2019-12-07 15:08:05,811 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=274, Invalid=538, Unknown=0, NotChecked=0, Total=812 [2019-12-07 15:08:05,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2019-12-07 15:08:05,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 52. [2019-12-07 15:08:05,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2019-12-07 15:08:05,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 107 transitions. [2019-12-07 15:08:05,814 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 107 transitions. Word has length 21 [2019-12-07 15:08:05,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:05,814 INFO L462 AbstractCegarLoop]: Abstraction has 52 states and 107 transitions. [2019-12-07 15:08:05,815 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 15:08:05,815 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 107 transitions. [2019-12-07 15:08:05,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 15:08:05,815 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:05,815 INFO L410 BasicCegarLoop]: trace histogram [7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:06,016 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:06,016 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:06,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:06,016 INFO L82 PathProgramCache]: Analyzing trace with hash -2015657050, now seen corresponding path program 17 times [2019-12-07 15:08:06,017 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:06,017 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96541639] [2019-12-07 15:08:06,017 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:06,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:06,143 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:06,144 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96541639] [2019-12-07 15:08:06,144 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [250767313] [2019-12-07 15:08:06,144 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:06,179 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2019-12-07 15:08:06,179 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:06,180 INFO L264 TraceCheckSpWp]: Trace formula consists of 138 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 15:08:06,180 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:06,194 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:06,194 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:06,194 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2019-12-07 15:08:06,195 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732303992] [2019-12-07 15:08:06,195 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 15:08:06,195 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:06,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 15:08:06,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=229, Unknown=0, NotChecked=0, Total=306 [2019-12-07 15:08:06,195 INFO L87 Difference]: Start difference. First operand 52 states and 107 transitions. Second operand 18 states. [2019-12-07 15:08:06,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:06,384 INFO L93 Difference]: Finished difference Result 61 states and 124 transitions. [2019-12-07 15:08:06,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 15:08:06,384 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 21 [2019-12-07 15:08:06,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:06,384 INFO L225 Difference]: With dead ends: 61 [2019-12-07 15:08:06,385 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 15:08:06,385 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=329, Invalid=663, Unknown=0, NotChecked=0, Total=992 [2019-12-07 15:08:06,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 15:08:06,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 34. [2019-12-07 15:08:06,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2019-12-07 15:08:06,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 70 transitions. [2019-12-07 15:08:06,387 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 70 transitions. Word has length 21 [2019-12-07 15:08:06,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:06,387 INFO L462 AbstractCegarLoop]: Abstraction has 34 states and 70 transitions. [2019-12-07 15:08:06,387 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 15:08:06,387 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 70 transitions. [2019-12-07 15:08:06,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 15:08:06,387 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:06,387 INFO L410 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:06,588 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:06,589 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:06,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:06,589 INFO L82 PathProgramCache]: Analyzing trace with hash -1206950281, now seen corresponding path program 18 times [2019-12-07 15:08:06,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:06,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440789997] [2019-12-07 15:08:06,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:06,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:06,718 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:06,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440789997] [2019-12-07 15:08:06,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1427623347] [2019-12-07 15:08:06,719 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:06,756 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2019-12-07 15:08:06,756 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:06,757 INFO L264 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 15:08:06,757 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:06,775 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:06,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:06,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2019-12-07 15:08:06,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221327632] [2019-12-07 15:08:06,775 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 15:08:06,775 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:06,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 15:08:06,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=256, Unknown=0, NotChecked=0, Total=342 [2019-12-07 15:08:06,776 INFO L87 Difference]: Start difference. First operand 34 states and 70 transitions. Second operand 19 states. [2019-12-07 15:08:06,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:06,983 INFO L93 Difference]: Finished difference Result 62 states and 126 transitions. [2019-12-07 15:08:06,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 15:08:06,984 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 22 [2019-12-07 15:08:06,984 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:06,984 INFO L225 Difference]: With dead ends: 62 [2019-12-07 15:08:06,984 INFO L226 Difference]: Without dead ends: 58 [2019-12-07 15:08:06,985 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 187 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=348, Invalid=774, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 15:08:06,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2019-12-07 15:08:06,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2019-12-07 15:08:06,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2019-12-07 15:08:06,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 115 transitions. [2019-12-07 15:08:06,987 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 115 transitions. Word has length 22 [2019-12-07 15:08:06,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:06,987 INFO L462 AbstractCegarLoop]: Abstraction has 56 states and 115 transitions. [2019-12-07 15:08:06,987 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 15:08:06,987 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 115 transitions. [2019-12-07 15:08:06,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2019-12-07 15:08:06,987 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:06,988 INFO L410 BasicCegarLoop]: trace histogram [8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:07,188 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:07,188 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:07,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:07,189 INFO L82 PathProgramCache]: Analyzing trace with hash -16172482, now seen corresponding path program 19 times [2019-12-07 15:08:07,189 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:07,189 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239901349] [2019-12-07 15:08:07,189 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:07,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:07,330 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:07,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239901349] [2019-12-07 15:08:07,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1614811080] [2019-12-07 15:08:07,331 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:07,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:07,362 INFO L264 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 15:08:07,363 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:07,378 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:07,378 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:07,378 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2019-12-07 15:08:07,378 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771675013] [2019-12-07 15:08:07,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 15:08:07,379 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:07,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 15:08:07,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2019-12-07 15:08:07,379 INFO L87 Difference]: Start difference. First operand 56 states and 115 transitions. Second operand 20 states. [2019-12-07 15:08:07,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:07,615 INFO L93 Difference]: Finished difference Result 65 states and 132 transitions. [2019-12-07 15:08:07,616 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 15:08:07,616 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 23 [2019-12-07 15:08:07,616 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:07,616 INFO L225 Difference]: With dead ends: 65 [2019-12-07 15:08:07,616 INFO L226 Difference]: Without dead ends: 61 [2019-12-07 15:08:07,617 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=415, Invalid=845, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 15:08:07,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2019-12-07 15:08:07,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 38. [2019-12-07 15:08:07,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-12-07 15:08:07,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 78 transitions. [2019-12-07 15:08:07,619 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 78 transitions. Word has length 23 [2019-12-07 15:08:07,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:07,619 INFO L462 AbstractCegarLoop]: Abstraction has 38 states and 78 transitions. [2019-12-07 15:08:07,619 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 15:08:07,619 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 78 transitions. [2019-12-07 15:08:07,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-12-07 15:08:07,620 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:07,620 INFO L410 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:07,820 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:07,821 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:07,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:07,821 INFO L82 PathProgramCache]: Analyzing trace with hash -238048297, now seen corresponding path program 20 times [2019-12-07 15:08:07,822 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:07,822 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213744699] [2019-12-07 15:08:07,822 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:07,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:07,967 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:07,967 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213744699] [2019-12-07 15:08:07,967 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522595524] [2019-12-07 15:08:07,967 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:08,001 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 15:08:08,001 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:08,001 INFO L264 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 15:08:08,002 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:08,018 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:08,018 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:08,018 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2019-12-07 15:08:08,018 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108854195] [2019-12-07 15:08:08,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 15:08:08,018 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:08,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 15:08:08,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=284, Unknown=0, NotChecked=0, Total=380 [2019-12-07 15:08:08,019 INFO L87 Difference]: Start difference. First operand 38 states and 78 transitions. Second operand 20 states. [2019-12-07 15:08:08,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:08,237 INFO L93 Difference]: Finished difference Result 65 states and 132 transitions. [2019-12-07 15:08:08,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 15:08:08,237 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 24 [2019-12-07 15:08:08,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:08,238 INFO L225 Difference]: With dead ends: 65 [2019-12-07 15:08:08,238 INFO L226 Difference]: Without dead ends: 61 [2019-12-07 15:08:08,238 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=429, Invalid=831, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 15:08:08,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2019-12-07 15:08:08,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 58. [2019-12-07 15:08:08,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2019-12-07 15:08:08,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 119 transitions. [2019-12-07 15:08:08,240 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 119 transitions. Word has length 24 [2019-12-07 15:08:08,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:08,240 INFO L462 AbstractCegarLoop]: Abstraction has 58 states and 119 transitions. [2019-12-07 15:08:08,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 15:08:08,240 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 119 transitions. [2019-12-07 15:08:08,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-12-07 15:08:08,241 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:08,241 INFO L410 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:08,441 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:08,441 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:08,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:08,442 INFO L82 PathProgramCache]: Analyzing trace with hash -238048049, now seen corresponding path program 21 times [2019-12-07 15:08:08,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:08,443 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157059333] [2019-12-07 15:08:08,443 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:08,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:08,594 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:08,594 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157059333] [2019-12-07 15:08:08,594 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [196038035] [2019-12-07 15:08:08,594 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:08,630 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-12-07 15:08:08,630 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:08,631 INFO L264 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 15:08:08,632 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:08,647 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:08,647 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:08,647 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2019-12-07 15:08:08,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047944629] [2019-12-07 15:08:08,647 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 15:08:08,647 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:08,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 15:08:08,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:08:08,648 INFO L87 Difference]: Start difference. First operand 58 states and 119 transitions. Second operand 21 states. [2019-12-07 15:08:08,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:08,884 INFO L93 Difference]: Finished difference Result 68 states and 138 transitions. [2019-12-07 15:08:08,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:08:08,884 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 24 [2019-12-07 15:08:08,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:08,885 INFO L225 Difference]: With dead ends: 68 [2019-12-07 15:08:08,885 INFO L226 Difference]: Without dead ends: 64 [2019-12-07 15:08:08,886 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 240 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=432, Invalid=974, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 15:08:08,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2019-12-07 15:08:08,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 41. [2019-12-07 15:08:08,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 15:08:08,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 84 transitions. [2019-12-07 15:08:08,887 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 84 transitions. Word has length 24 [2019-12-07 15:08:08,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:08,888 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 84 transitions. [2019-12-07 15:08:08,888 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 15:08:08,888 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 84 transitions. [2019-12-07 15:08:08,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 15:08:08,888 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:08,888 INFO L410 BasicCegarLoop]: trace histogram [10, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:09,089 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:09,089 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:09,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:09,090 INFO L82 PathProgramCache]: Analyzing trace with hash 1638115806, now seen corresponding path program 22 times [2019-12-07 15:08:09,090 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:09,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152537023] [2019-12-07 15:08:09,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:09,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:09,215 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:09,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152537023] [2019-12-07 15:08:09,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1097052188] [2019-12-07 15:08:09,215 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:09,249 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 15:08:09,249 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:09,250 INFO L264 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 15:08:09,251 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:09,270 INFO L134 CoverageAnalysis]: Checked inductivity of 73 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 15:08:09,270 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:09,270 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2019-12-07 15:08:09,271 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425528481] [2019-12-07 15:08:09,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 15:08:09,271 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:09,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 15:08:09,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2019-12-07 15:08:09,271 INFO L87 Difference]: Start difference. First operand 41 states and 84 transitions. Second operand 21 states. [2019-12-07 15:08:09,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:09,505 INFO L93 Difference]: Finished difference Result 73 states and 148 transitions. [2019-12-07 15:08:09,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 15:08:09,506 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 25 [2019-12-07 15:08:09,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:09,506 INFO L225 Difference]: With dead ends: 73 [2019-12-07 15:08:09,506 INFO L226 Difference]: Without dead ends: 68 [2019-12-07 15:08:09,507 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 206 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=441, Invalid=891, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 15:08:09,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2019-12-07 15:08:09,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 61. [2019-12-07 15:08:09,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2019-12-07 15:08:09,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 124 transitions. [2019-12-07 15:08:09,508 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 124 transitions. Word has length 25 [2019-12-07 15:08:09,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:09,508 INFO L462 AbstractCegarLoop]: Abstraction has 61 states and 124 transitions. [2019-12-07 15:08:09,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 15:08:09,508 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 124 transitions. [2019-12-07 15:08:09,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 15:08:09,509 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:09,509 INFO L410 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:09,709 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:09,710 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:09,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:09,710 INFO L82 PathProgramCache]: Analyzing trace with hash -758009821, now seen corresponding path program 23 times [2019-12-07 15:08:09,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:09,710 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251602966] [2019-12-07 15:08:09,711 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:09,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:09,862 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:09,862 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251602966] [2019-12-07 15:08:09,863 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2095310032] [2019-12-07 15:08:09,863 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:09,902 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2019-12-07 15:08:09,903 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:09,904 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 15:08:09,904 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:09,921 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:09,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:09,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2019-12-07 15:08:09,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173915518] [2019-12-07 15:08:09,921 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 15:08:09,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:09,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 15:08:09,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=379, Unknown=0, NotChecked=0, Total=506 [2019-12-07 15:08:09,922 INFO L87 Difference]: Start difference. First operand 61 states and 124 transitions. Second operand 23 states. [2019-12-07 15:08:10,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:10,217 INFO L93 Difference]: Finished difference Result 72 states and 146 transitions. [2019-12-07 15:08:10,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 15:08:10,217 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 26 [2019-12-07 15:08:10,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:10,218 INFO L225 Difference]: With dead ends: 72 [2019-12-07 15:08:10,218 INFO L226 Difference]: Without dead ends: 62 [2019-12-07 15:08:10,218 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 259 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=541, Invalid=1099, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 15:08:10,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2019-12-07 15:08:10,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 38. [2019-12-07 15:08:10,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-12-07 15:08:10,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 78 transitions. [2019-12-07 15:08:10,220 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 78 transitions. Word has length 26 [2019-12-07 15:08:10,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:10,220 INFO L462 AbstractCegarLoop]: Abstraction has 38 states and 78 transitions. [2019-12-07 15:08:10,220 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 15:08:10,220 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 78 transitions. [2019-12-07 15:08:10,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 15:08:10,220 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:10,221 INFO L410 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:10,421 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:10,421 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:10,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:10,421 INFO L82 PathProgramCache]: Analyzing trace with hash -1130906329, now seen corresponding path program 24 times [2019-12-07 15:08:10,421 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:10,421 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760458309] [2019-12-07 15:08:10,421 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:10,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 15:08:10,576 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:10,577 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760458309] [2019-12-07 15:08:10,577 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2139639845] [2019-12-07 15:08:10,577 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:10,621 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2019-12-07 15:08:10,621 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 15:08:10,621 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 15:08:10,622 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 15:08:10,642 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 15:08:10,642 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 15:08:10,642 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2019-12-07 15:08:10,642 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672225076] [2019-12-07 15:08:10,643 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 15:08:10,643 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 15:08:10,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 15:08:10,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=380, Unknown=0, NotChecked=0, Total=506 [2019-12-07 15:08:10,643 INFO L87 Difference]: Start difference. First operand 38 states and 78 transitions. Second operand 23 states. [2019-12-07 15:08:10,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 15:08:10,914 INFO L93 Difference]: Finished difference Result 69 states and 140 transitions. [2019-12-07 15:08:10,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 15:08:10,915 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 26 [2019-12-07 15:08:10,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 15:08:10,915 INFO L225 Difference]: With dead ends: 69 [2019-12-07 15:08:10,915 INFO L226 Difference]: Without dead ends: 63 [2019-12-07 15:08:10,916 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=525, Invalid=1197, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 15:08:10,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2019-12-07 15:08:10,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 41. [2019-12-07 15:08:10,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 15:08:10,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 84 transitions. [2019-12-07 15:08:10,917 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 84 transitions. Word has length 26 [2019-12-07 15:08:10,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 15:08:10,918 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 84 transitions. [2019-12-07 15:08:10,918 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 15:08:10,918 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 84 transitions. [2019-12-07 15:08:10,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 15:08:10,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 15:08:10,918 INFO L410 BasicCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 15:08:11,118 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 15:08:11,119 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 15:08:11,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 15:08:11,119 INFO L82 PathProgramCache]: Analyzing trace with hash -2023467666, now seen corresponding path program 25 times [2019-12-07 15:08:11,119 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 15:08:11,119 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446606347] [2019-12-07 15:08:11,119 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 15:08:11,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:08:11,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 15:08:11,151 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 15:08:11,151 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 15:08:11,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [187] [187] ULTIMATE.startENTRY-->L694: Formula: (let ((.cse0 (store |v_#valid_39| 0 0))) (let ((.cse1 (store .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20| 1))) (and (= 0 |v_#NULL.base_4|) (= v_ULTIMATE.start_main_~argv.base_8 |v_ULTIMATE.start_main_#in~argv.base_9|) (= 0 |v_ULTIMATE.start_main_~#id1~0.offset_16|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| |v_ULTIMATE.start_#in~argv.offset_5|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20|) |v_ULTIMATE.start_main_~#id1~0.offset_16| 0)) |v_#memory_int_11|) (= |v_ULTIMATE.start_#in~argv.base_5| |v_ULTIMATE.start_main_#in~argv.base_9|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| v_ULTIMATE.start_main_~argv.offset_8) (= v_~i~0_33 3) (= 0 |v_ULTIMATE.start_main_~#id2~0.offset_16|) (< 0 |v_#StackHeapBarrier_11|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20|)) (= (store (store |v_#length_15| |v_ULTIMATE.start_main_~#id1~0.base_20| 4) |v_ULTIMATE.start_main_~#id2~0.base_20| 4) |v_#length_14|) (= |v_#NULL.offset_4| 0) (= v_~j~0_37 6) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id1~0.base_20|) (= v_ULTIMATE.start_main_~argc_7 |v_ULTIMATE.start_main_#in~argc_9|) (= (select .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20|) 0) (= (store .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20| 1) |v_#valid_37|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id2~0.base_20|) (= |v_ULTIMATE.start_#in~argc_5| |v_ULTIMATE.start_main_#in~argc_9|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_12|, #length=|v_#length_15|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|} OutVars{ULTIMATE.start_main_~argv.offset=v_ULTIMATE.start_main_~argv.offset_8, ~j~0=v_~j~0_37, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_7|, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_18|, ULTIMATE.start_main_~#id1~0.base=|v_ULTIMATE.start_main_~#id1~0.base_20|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_main_~argv.base=v_ULTIMATE.start_main_~argv.base_8, ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_20|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_16|, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_22, ULTIMATE.start_main_~argc=v_ULTIMATE.start_main_~argc_7, #length=|v_#length_14|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|, ULTIMATE.start_main_#in~argv.base=|v_ULTIMATE.start_main_#in~argv.base_9|, ULTIMATE.start_main_#in~argv.offset=|v_ULTIMATE.start_main_#in~argv.offset_9|, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_22, ~i~0=v_~i~0_33, #NULL.base=|v_#NULL.base_4|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_37|, ULTIMATE.start_main_#in~argc=|v_ULTIMATE.start_main_#in~argc_9|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#id1~0.offset=|v_ULTIMATE.start_main_~#id1~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#in~argv.base, ULTIMATE.start_main_~argv.offset, ~j~0, ULTIMATE.start_main_#in~argv.offset, ULTIMATE.start_main_#t~nondet4, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5, ~i~0, ULTIMATE.start_main_~#id1~0.base, #NULL.offset, #NULL.base, ULTIMATE.start_main_~argv.base, ULTIMATE.start_main_~#id2~0.base, ULTIMATE.start_main_~#id2~0.offset, ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#in~argc, #memory_int, ULTIMATE.start_main_~argc, #length, ULTIMATE.start_main_~#id1~0.offset] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [153] [153] L694-1-->L695-1: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6|) |v_ULTIMATE.start_main_~#id2~0.offset_6| 1))) InVars {ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, #memory_int=|v_#memory_int_6|} OutVars{ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_3|, #memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4, #memory_int] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [155] [155] t1ENTRY-->L677-6: Formula: (and (= v_t1Thread1of1ForFork1_~arg.offset_2 |v_t1Thread1of1ForFork1_#in~arg.offset_4|) (= v_t1Thread1of1ForFork1_~k~0_10 0) (= v_t1Thread1of1ForFork1_~arg.base_2 |v_t1Thread1of1ForFork1_#in~arg.base_4|)) InVars {t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} OutVars{t1Thread1of1ForFork1_~arg.base=v_t1Thread1of1ForFork1_~arg.base_2, t1Thread1of1ForFork1_~arg.offset=v_t1Thread1of1ForFork1_~arg.offset_2, t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_10, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} AuxVars[] AssignedVars[t1Thread1of1ForFork1_~arg.base, t1Thread1of1ForFork1_~arg.offset, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [159] [159] t2ENTRY-->L685-6: Formula: (and (= |v_t2Thread1of1ForFork0_#in~arg.base_4| v_t2Thread1of1ForFork0_~arg.base_2) (= v_t2Thread1of1ForFork0_~arg.offset_2 |v_t2Thread1of1ForFork0_#in~arg.offset_4|) (= 0 v_t2Thread1of1ForFork0_~k~1_10)) InVars {t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} OutVars{t2Thread1of1ForFork0_~arg.offset=v_t2Thread1of1ForFork0_~arg.offset_2, t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_~arg.base=v_t2Thread1of1ForFork0_~arg.base_2, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_10, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} AuxVars[] AssignedVars[t2Thread1of1ForFork0_~arg.offset, t2Thread1of1ForFork0_~arg.base, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [181] [181] L695-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start_main_~condJ~0_15 (ite (<= 26 v_~j~0_27) 1 0)) (or (not (= v_ULTIMATE.start_main_~condI~0_15 0)) (not (= v_ULTIMATE.start_main_~condJ~0_15 0))) (= v_ULTIMATE.start_main_~condI~0_15 (ite (<= 26 v_~i~0_25) 1 0))) InVars {~j~0=v_~j~0_27, ~i~0=v_~i~0_25} OutVars{~j~0=v_~j~0_27, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_15, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_15, ~i~0=v_~i~0_25, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5] because there is no mapped edge [2019-12-07 15:08:11,167 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 03:08:11 BasicIcfg [2019-12-07 15:08:11,167 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 15:08:11,168 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 15:08:11,168 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 15:08:11,168 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 15:08:11,168 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 03:07:58" (3/4) ... [2019-12-07 15:08:11,170 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 15:08:11,170 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [187] [187] ULTIMATE.startENTRY-->L694: Formula: (let ((.cse0 (store |v_#valid_39| 0 0))) (let ((.cse1 (store .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20| 1))) (and (= 0 |v_#NULL.base_4|) (= v_ULTIMATE.start_main_~argv.base_8 |v_ULTIMATE.start_main_#in~argv.base_9|) (= 0 |v_ULTIMATE.start_main_~#id1~0.offset_16|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| |v_ULTIMATE.start_#in~argv.offset_5|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20|) |v_ULTIMATE.start_main_~#id1~0.offset_16| 0)) |v_#memory_int_11|) (= |v_ULTIMATE.start_#in~argv.base_5| |v_ULTIMATE.start_main_#in~argv.base_9|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| v_ULTIMATE.start_main_~argv.offset_8) (= v_~i~0_33 3) (= 0 |v_ULTIMATE.start_main_~#id2~0.offset_16|) (< 0 |v_#StackHeapBarrier_11|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20|)) (= (store (store |v_#length_15| |v_ULTIMATE.start_main_~#id1~0.base_20| 4) |v_ULTIMATE.start_main_~#id2~0.base_20| 4) |v_#length_14|) (= |v_#NULL.offset_4| 0) (= v_~j~0_37 6) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id1~0.base_20|) (= v_ULTIMATE.start_main_~argc_7 |v_ULTIMATE.start_main_#in~argc_9|) (= (select .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20|) 0) (= (store .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20| 1) |v_#valid_37|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id2~0.base_20|) (= |v_ULTIMATE.start_#in~argc_5| |v_ULTIMATE.start_main_#in~argc_9|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_12|, #length=|v_#length_15|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|} OutVars{ULTIMATE.start_main_~argv.offset=v_ULTIMATE.start_main_~argv.offset_8, ~j~0=v_~j~0_37, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_7|, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_18|, ULTIMATE.start_main_~#id1~0.base=|v_ULTIMATE.start_main_~#id1~0.base_20|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_main_~argv.base=v_ULTIMATE.start_main_~argv.base_8, ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_20|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_16|, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_22, ULTIMATE.start_main_~argc=v_ULTIMATE.start_main_~argc_7, #length=|v_#length_14|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|, ULTIMATE.start_main_#in~argv.base=|v_ULTIMATE.start_main_#in~argv.base_9|, ULTIMATE.start_main_#in~argv.offset=|v_ULTIMATE.start_main_#in~argv.offset_9|, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_22, ~i~0=v_~i~0_33, #NULL.base=|v_#NULL.base_4|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_37|, ULTIMATE.start_main_#in~argc=|v_ULTIMATE.start_main_#in~argc_9|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#id1~0.offset=|v_ULTIMATE.start_main_~#id1~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#in~argv.base, ULTIMATE.start_main_~argv.offset, ~j~0, ULTIMATE.start_main_#in~argv.offset, ULTIMATE.start_main_#t~nondet4, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5, ~i~0, ULTIMATE.start_main_~#id1~0.base, #NULL.offset, #NULL.base, ULTIMATE.start_main_~argv.base, ULTIMATE.start_main_~#id2~0.base, ULTIMATE.start_main_~#id2~0.offset, ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#in~argc, #memory_int, ULTIMATE.start_main_~argc, #length, ULTIMATE.start_main_~#id1~0.offset] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [153] [153] L694-1-->L695-1: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6|) |v_ULTIMATE.start_main_~#id2~0.offset_6| 1))) InVars {ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, #memory_int=|v_#memory_int_6|} OutVars{ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_3|, #memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4, #memory_int] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [155] [155] t1ENTRY-->L677-6: Formula: (and (= v_t1Thread1of1ForFork1_~arg.offset_2 |v_t1Thread1of1ForFork1_#in~arg.offset_4|) (= v_t1Thread1of1ForFork1_~k~0_10 0) (= v_t1Thread1of1ForFork1_~arg.base_2 |v_t1Thread1of1ForFork1_#in~arg.base_4|)) InVars {t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} OutVars{t1Thread1of1ForFork1_~arg.base=v_t1Thread1of1ForFork1_~arg.base_2, t1Thread1of1ForFork1_~arg.offset=v_t1Thread1of1ForFork1_~arg.offset_2, t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_10, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} AuxVars[] AssignedVars[t1Thread1of1ForFork1_~arg.base, t1Thread1of1ForFork1_~arg.offset, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [159] [159] t2ENTRY-->L685-6: Formula: (and (= |v_t2Thread1of1ForFork0_#in~arg.base_4| v_t2Thread1of1ForFork0_~arg.base_2) (= v_t2Thread1of1ForFork0_~arg.offset_2 |v_t2Thread1of1ForFork0_#in~arg.offset_4|) (= 0 v_t2Thread1of1ForFork0_~k~1_10)) InVars {t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} OutVars{t2Thread1of1ForFork0_~arg.offset=v_t2Thread1of1ForFork0_~arg.offset_2, t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_~arg.base=v_t2Thread1of1ForFork0_~arg.base_2, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_10, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} AuxVars[] AssignedVars[t2Thread1of1ForFork0_~arg.offset, t2Thread1of1ForFork0_~arg.base, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,171 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (< v_t1Thread1of1ForFork1_~k~0_18 10) (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1))) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (< v_t2Thread1of1ForFork0_~k~1_32 10) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 15:08:11,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [181] [181] L695-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start_main_~condJ~0_15 (ite (<= 26 v_~j~0_27) 1 0)) (or (not (= v_ULTIMATE.start_main_~condI~0_15 0)) (not (= v_ULTIMATE.start_main_~condJ~0_15 0))) (= v_ULTIMATE.start_main_~condI~0_15 (ite (<= 26 v_~i~0_25) 1 0))) InVars {~j~0=v_~j~0_27, ~i~0=v_~i~0_25} OutVars{~j~0=v_~j~0_27, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_15, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_15, ~i~0=v_~i~0_25, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5] because there is no mapped edge [2019-12-07 15:08:11,198 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_2bacb540-a822-40ae-8abb-0a149c6db6ef/bin/uautomizer/witness.graphml [2019-12-07 15:08:11,198 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 15:08:11,200 INFO L168 Benchmark]: Toolchain (without parser) took 13826.84 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 222.3 MB). Free memory was 940.6 MB in the beginning and 925.3 MB in the end (delta: 15.3 MB). Peak memory consumption was 237.6 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,200 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 15:08:11,201 INFO L168 Benchmark]: CACSL2BoogieTranslator took 371.83 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 95.9 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -123.2 MB). Peak memory consumption was 20.8 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,201 INFO L168 Benchmark]: Boogie Procedure Inliner took 33.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,201 INFO L168 Benchmark]: Boogie Preprocessor took 17.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,202 INFO L168 Benchmark]: RCFGBuilder took 207.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 25.2 MB). Peak memory consumption was 25.2 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,202 INFO L168 Benchmark]: TraceAbstraction took 13162.42 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 126.4 MB). Free memory was 1.0 GB in the beginning and 935.7 MB in the end (delta: 98.9 MB). Peak memory consumption was 225.2 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,202 INFO L168 Benchmark]: Witness Printer took 30.77 ms. Allocated memory is still 1.3 GB. Free memory was 935.7 MB in the beginning and 925.3 MB in the end (delta: 10.3 MB). Peak memory consumption was 10.3 MB. Max. memory is 11.5 GB. [2019-12-07 15:08:11,204 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 371.83 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 95.9 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -123.2 MB). Peak memory consumption was 20.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 33.60 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 17.91 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 207.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 25.2 MB). Peak memory consumption was 25.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 13162.42 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 126.4 MB). Free memory was 1.0 GB in the beginning and 935.7 MB in the end (delta: 98.9 MB). Peak memory consumption was 225.2 MB. Max. memory is 11.5 GB. * Witness Printer took 30.77 ms. Allocated memory is still 1.3 GB. Free memory was 935.7 MB in the beginning and 925.3 MB in the end (delta: 10.3 MB). Peak memory consumption was 10.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 0.7s, 53 ProgramPointsBefore, 16 ProgramPointsAfterwards, 51 TransitionsBefore, 14 TransitionsAfterwards, 740 CoEnabledTransitionPairs, 6 FixpointIterations, 12 TrivialSequentialCompositions, 21 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 8 ConcurrentYvCompositions, 3 ChoiceCompositions, 380 VarBasedMoverChecksPositive, 7 VarBasedMoverChecksNegative, 0 SemBasedMoverChecksPositive, 9 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.0s, 0 MoverChecksTotal, 604 CheckedPairsTotal, 41 TotalNumberOfCompositions - CounterExampleResult [Line: 703]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L694] FCALL, FORK 0 pthread_create(&id1, ((void *)0), t1, ((void *)0)) VAL [arg={0:0}, i=3, j=6] [L695] FCALL, FORK 0 pthread_create(&id2, ((void *)0), t2, ((void *)0)) VAL [arg={0:0}, arg={0:0}, i=3, j=6] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 47 locations, 1 error locations. Result: UNSAFE, OverallTime: 13.0s, OverallIterations: 27, TraceHistogramMax: 10, AutomataDifference: 3.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 289 SDtfs, 847 SDslu, 833 SDs, 0 SdLazy, 1100 SolverSat, 927 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 917 GetRequests, 370 SyntacticMatches, 0 SemanticMatches, 547 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2562 ImplicationChecksByTransitivity, 4.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=61occurred in iteration=24, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 26 MinimizatonAttempts, 242 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 880 NumberOfCodeBlocks, 880 NumberOfCodeBlocksAsserted, 119 NumberOfCheckSat, 804 ConstructedInterpolants, 0 QuantifiedInterpolants, 48348 SizeOfPredicates, 227 NumberOfNonLiveVariables, 2839 ConjunctsInSsa, 393 ConjunctsInUnsatCore, 49 InterpolantComputations, 3 PerfectInterpolantSequences, 10/1478 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...