./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/triangular-longest-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/triangular-longest-2.i -s /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash faab412b2ab361cad3ea824ae769b15468801bfa ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 11:01:31,697 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 11:01:31,699 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 11:01:31,706 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 11:01:31,706 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 11:01:31,707 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 11:01:31,708 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 11:01:31,709 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 11:01:31,710 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 11:01:31,711 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 11:01:31,712 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 11:01:31,712 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 11:01:31,713 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 11:01:31,713 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 11:01:31,714 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 11:01:31,715 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 11:01:31,715 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 11:01:31,716 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 11:01:31,717 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 11:01:31,719 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 11:01:31,720 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 11:01:31,720 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 11:01:31,721 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 11:01:31,721 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 11:01:31,723 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 11:01:31,723 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 11:01:31,723 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 11:01:31,724 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 11:01:31,724 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 11:01:31,725 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 11:01:31,725 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 11:01:31,725 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 11:01:31,726 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 11:01:31,726 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 11:01:31,727 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 11:01:31,727 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 11:01:31,727 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 11:01:31,727 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 11:01:31,727 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 11:01:31,728 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 11:01:31,729 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 11:01:31,729 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 11:01:31,738 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 11:01:31,739 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 11:01:31,739 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 11:01:31,739 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 11:01:31,740 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 11:01:31,740 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 11:01:31,741 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 11:01:31,741 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:01:31,742 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 11:01:31,742 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 11:01:31,743 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> faab412b2ab361cad3ea824ae769b15468801bfa [2019-12-07 11:01:31,840 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 11:01:31,849 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 11:01:31,851 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 11:01:31,852 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 11:01:31,853 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 11:01:31,853 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/../../sv-benchmarks/c/pthread/triangular-longest-2.i [2019-12-07 11:01:31,892 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/data/fdca4bcd9/a8ccba2d5cb64c71ba61d9fff76873cd/FLAGb9df81c3f [2019-12-07 11:01:32,335 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 11:01:32,335 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/sv-benchmarks/c/pthread/triangular-longest-2.i [2019-12-07 11:01:32,345 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/data/fdca4bcd9/a8ccba2d5cb64c71ba61d9fff76873cd/FLAGb9df81c3f [2019-12-07 11:01:32,354 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/data/fdca4bcd9/a8ccba2d5cb64c71ba61d9fff76873cd [2019-12-07 11:01:32,356 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 11:01:32,357 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 11:01:32,357 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 11:01:32,357 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 11:01:32,360 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 11:01:32,360 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,362 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c77c204 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32, skipping insertion in model container [2019-12-07 11:01:32,362 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,367 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 11:01:32,397 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 11:01:32,678 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:01:32,686 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 11:01:32,713 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:01:32,758 INFO L208 MainTranslator]: Completed translation [2019-12-07 11:01:32,758 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32 WrapperNode [2019-12-07 11:01:32,758 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 11:01:32,759 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 11:01:32,759 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 11:01:32,759 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 11:01:32,764 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,775 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,788 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 11:01:32,789 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 11:01:32,789 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 11:01:32,789 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 11:01:32,795 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,795 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,797 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,797 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,801 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,804 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,805 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... [2019-12-07 11:01:32,807 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 11:01:32,807 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 11:01:32,807 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 11:01:32,807 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 11:01:32,808 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:01:32,849 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2019-12-07 11:01:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2019-12-07 11:01:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 11:01:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 11:01:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 11:01:32,851 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 11:01:33,032 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 11:01:33,032 INFO L287 CfgBuilder]: Removed 6 assume(true) statements. [2019-12-07 11:01:33,033 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:01:33 BoogieIcfgContainer [2019-12-07 11:01:33,033 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 11:01:33,033 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 11:01:33,034 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 11:01:33,035 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 11:01:33,035 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 11:01:32" (1/3) ... [2019-12-07 11:01:33,036 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f3969aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:01:33, skipping insertion in model container [2019-12-07 11:01:33,036 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:01:32" (2/3) ... [2019-12-07 11:01:33,036 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@f3969aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:01:33, skipping insertion in model container [2019-12-07 11:01:33,036 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:01:33" (3/3) ... [2019-12-07 11:01:33,037 INFO L109 eAbstractionObserver]: Analyzing ICFG triangular-longest-2.i [2019-12-07 11:01:33,043 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 11:01:33,043 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 11:01:33,047 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-07 11:01:33,048 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 11:01:33,065 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,065 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,065 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,065 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,065 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,066 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe t1Thread1of1ForFork1_~k~0 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,067 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,068 WARN L315 ript$VariableManager]: TermVariabe t2Thread1of1ForFork0_~k~1 not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,069 WARN L315 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork0_#t~post3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 11:01:33,081 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-12-07 11:01:33,095 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 11:01:33,095 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 11:01:33,095 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 11:01:33,095 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 11:01:33,095 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 11:01:33,095 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 11:01:33,095 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 11:01:33,095 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 11:01:33,106 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 53 places, 51 transitions [2019-12-07 11:01:33,108 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 53 places, 51 transitions [2019-12-07 11:01:33,135 INFO L134 PetriNetUnfolder]: 5/49 cut-off events. [2019-12-07 11:01:33,135 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:01:33,140 INFO L76 FinitePrefix]: Finished finitePrefix Result has 56 conditions, 49 events. 5/49 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 7. Compared 92 event pairs. 6/49 useless extension candidates. Maximal degree in co-relation 37. Up to 2 conditions per place. [2019-12-07 11:01:33,142 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 53 places, 51 transitions [2019-12-07 11:01:33,151 INFO L134 PetriNetUnfolder]: 5/49 cut-off events. [2019-12-07 11:01:33,151 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 11:01:33,152 INFO L76 FinitePrefix]: Finished finitePrefix Result has 56 conditions, 49 events. 5/49 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 7. Compared 92 event pairs. 6/49 useless extension candidates. Maximal degree in co-relation 37. Up to 2 conditions per place. [2019-12-07 11:01:33,154 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 740 [2019-12-07 11:01:33,154 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 11:01:33,836 INFO L206 etLargeBlockEncoding]: Checked pairs total: 604 [2019-12-07 11:01:33,837 INFO L214 etLargeBlockEncoding]: Total number of compositions: 41 [2019-12-07 11:01:33,839 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 16 places, 14 transitions [2019-12-07 11:01:33,846 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 35 states. [2019-12-07 11:01:33,847 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states. [2019-12-07 11:01:33,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 11:01:33,851 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:33,851 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 11:01:33,851 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:33,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:33,855 INFO L82 PathProgramCache]: Analyzing trace with hash 205828742, now seen corresponding path program 1 times [2019-12-07 11:01:33,861 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:33,861 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189907276] [2019-12-07 11:01:33,861 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:33,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,006 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189907276] [2019-12-07 11:01:34,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:01:34,007 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 11:01:34,008 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385346368] [2019-12-07 11:01:34,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:01:34,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:01:34,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:01:34,025 INFO L87 Difference]: Start difference. First operand 35 states. Second operand 3 states. [2019-12-07 11:01:34,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,046 INFO L93 Difference]: Finished difference Result 44 states and 107 transitions. [2019-12-07 11:01:34,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:01:34,047 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 11:01:34,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,056 INFO L225 Difference]: With dead ends: 44 [2019-12-07 11:01:34,056 INFO L226 Difference]: Without dead ends: 26 [2019-12-07 11:01:34,057 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:01:34,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-12-07 11:01:34,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2019-12-07 11:01:34,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-12-07 11:01:34,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 56 transitions. [2019-12-07 11:01:34,084 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 56 transitions. Word has length 5 [2019-12-07 11:01:34,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,084 INFO L462 AbstractCegarLoop]: Abstraction has 26 states and 56 transitions. [2019-12-07 11:01:34,084 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:01:34,084 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 56 transitions. [2019-12-07 11:01:34,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 11:01:34,085 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,085 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:34,085 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:34,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:34,085 INFO L82 PathProgramCache]: Analyzing trace with hash 232910220, now seen corresponding path program 1 times [2019-12-07 11:01:34,085 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:34,086 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706897572] [2019-12-07 11:01:34,086 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:34,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706897572] [2019-12-07 11:01:34,160 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:01:34,160 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:01:34,160 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765104691] [2019-12-07 11:01:34,161 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:01:34,161 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:01:34,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:01:34,162 INFO L87 Difference]: Start difference. First operand 26 states and 56 transitions. Second operand 4 states. [2019-12-07 11:01:34,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,184 INFO L93 Difference]: Finished difference Result 36 states and 74 transitions. [2019-12-07 11:01:34,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:01:34,185 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 7 [2019-12-07 11:01:34,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,185 INFO L225 Difference]: With dead ends: 36 [2019-12-07 11:01:34,186 INFO L226 Difference]: Without dead ends: 30 [2019-12-07 11:01:34,186 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:01:34,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2019-12-07 11:01:34,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2019-12-07 11:01:34,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-12-07 11:01:34,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 62 transitions. [2019-12-07 11:01:34,190 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 62 transitions. Word has length 7 [2019-12-07 11:01:34,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,191 INFO L462 AbstractCegarLoop]: Abstraction has 30 states and 62 transitions. [2019-12-07 11:01:34,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:01:34,191 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 62 transitions. [2019-12-07 11:01:34,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 11:01:34,191 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,191 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:34,192 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:34,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:34,192 INFO L82 PathProgramCache]: Analyzing trace with hash 484474390, now seen corresponding path program 1 times [2019-12-07 11:01:34,192 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:34,192 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458528688] [2019-12-07 11:01:34,192 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:34,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,247 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458528688] [2019-12-07 11:01:34,248 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:01:34,248 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:01:34,248 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387914213] [2019-12-07 11:01:34,248 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:01:34,248 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:01:34,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:01:34,249 INFO L87 Difference]: Start difference. First operand 30 states and 62 transitions. Second operand 5 states. [2019-12-07 11:01:34,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,280 INFO L93 Difference]: Finished difference Result 34 states and 70 transitions. [2019-12-07 11:01:34,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 11:01:34,280 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 9 [2019-12-07 11:01:34,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,281 INFO L225 Difference]: With dead ends: 34 [2019-12-07 11:01:34,281 INFO L226 Difference]: Without dead ends: 28 [2019-12-07 11:01:34,281 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:01:34,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-12-07 11:01:34,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 22. [2019-12-07 11:01:34,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-12-07 11:01:34,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 46 transitions. [2019-12-07 11:01:34,284 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 46 transitions. Word has length 9 [2019-12-07 11:01:34,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,284 INFO L462 AbstractCegarLoop]: Abstraction has 22 states and 46 transitions. [2019-12-07 11:01:34,285 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:01:34,285 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 46 transitions. [2019-12-07 11:01:34,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-12-07 11:01:34,285 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,285 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:34,285 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:34,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:34,286 INFO L82 PathProgramCache]: Analyzing trace with hash 483962890, now seen corresponding path program 2 times [2019-12-07 11:01:34,286 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:34,286 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949155679] [2019-12-07 11:01:34,286 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:34,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,337 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949155679] [2019-12-07 11:01:34,337 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:01:34,337 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:01:34,338 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386236830] [2019-12-07 11:01:34,338 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:01:34,338 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:01:34,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:01:34,338 INFO L87 Difference]: Start difference. First operand 22 states and 46 transitions. Second operand 5 states. [2019-12-07 11:01:34,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,367 INFO L93 Difference]: Finished difference Result 32 states and 66 transitions. [2019-12-07 11:01:34,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:01:34,368 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 9 [2019-12-07 11:01:34,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,368 INFO L225 Difference]: With dead ends: 32 [2019-12-07 11:01:34,368 INFO L226 Difference]: Without dead ends: 28 [2019-12-07 11:01:34,369 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:01:34,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-12-07 11:01:34,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2019-12-07 11:01:34,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-12-07 11:01:34,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 58 transitions. [2019-12-07 11:01:34,371 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 58 transitions. Word has length 9 [2019-12-07 11:01:34,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,372 INFO L462 AbstractCegarLoop]: Abstraction has 28 states and 58 transitions. [2019-12-07 11:01:34,372 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:01:34,372 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 58 transitions. [2019-12-07 11:01:34,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2019-12-07 11:01:34,372 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,372 INFO L410 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:34,372 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:34,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:34,373 INFO L82 PathProgramCache]: Analyzing trace with hash 2133804259, now seen corresponding path program 3 times [2019-12-07 11:01:34,373 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:34,373 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562555920] [2019-12-07 11:01:34,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:34,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,422 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,422 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562555920] [2019-12-07 11:01:34,422 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [454825473] [2019-12-07 11:01:34,422 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:34,459 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-12-07 11:01:34,460 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:34,461 INFO L264 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 11:01:34,464 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:34,484 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:34,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2019-12-07 11:01:34,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559435664] [2019-12-07 11:01:34,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 11:01:34,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 11:01:34,485 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:01:34,485 INFO L87 Difference]: Start difference. First operand 28 states and 58 transitions. Second operand 7 states. [2019-12-07 11:01:34,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,515 INFO L93 Difference]: Finished difference Result 36 states and 74 transitions. [2019-12-07 11:01:34,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:01:34,516 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 10 [2019-12-07 11:01:34,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,516 INFO L225 Difference]: With dead ends: 36 [2019-12-07 11:01:34,517 INFO L226 Difference]: Without dead ends: 32 [2019-12-07 11:01:34,517 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:01:34,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2019-12-07 11:01:34,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 25. [2019-12-07 11:01:34,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-12-07 11:01:34,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 52 transitions. [2019-12-07 11:01:34,520 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 52 transitions. Word has length 10 [2019-12-07 11:01:34,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,520 INFO L462 AbstractCegarLoop]: Abstraction has 25 states and 52 transitions. [2019-12-07 11:01:34,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 11:01:34,520 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 52 transitions. [2019-12-07 11:01:34,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 11:01:34,520 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,521 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:34,721 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:34,722 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:34,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:34,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1231878834, now seen corresponding path program 4 times [2019-12-07 11:01:34,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:34,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441175701] [2019-12-07 11:01:34,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:34,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:34,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,869 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441175701] [2019-12-07 11:01:34,869 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [489040716] [2019-12-07 11:01:34,869 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:34,910 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:34,910 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:34,911 INFO L264 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 11:01:34,912 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:34,922 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:34,922 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:34,922 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2019-12-07 11:01:34,923 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772310465] [2019-12-07 11:01:34,923 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 11:01:34,923 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:34,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 11:01:34,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 11:01:34,924 INFO L87 Difference]: Start difference. First operand 25 states and 52 transitions. Second operand 8 states. [2019-12-07 11:01:34,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:34,981 INFO L93 Difference]: Finished difference Result 48 states and 98 transitions. [2019-12-07 11:01:34,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 11:01:34,981 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 11 [2019-12-07 11:01:34,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:34,982 INFO L225 Difference]: With dead ends: 48 [2019-12-07 11:01:34,982 INFO L226 Difference]: Without dead ends: 39 [2019-12-07 11:01:34,982 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=82, Unknown=0, NotChecked=0, Total=132 [2019-12-07 11:01:34,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2019-12-07 11:01:34,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 28. [2019-12-07 11:01:34,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-12-07 11:01:34,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 58 transitions. [2019-12-07 11:01:34,986 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 58 transitions. Word has length 11 [2019-12-07 11:01:34,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:34,986 INFO L462 AbstractCegarLoop]: Abstraction has 28 states and 58 transitions. [2019-12-07 11:01:34,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 11:01:34,986 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 58 transitions. [2019-12-07 11:01:34,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-12-07 11:01:34,987 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:34,987 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:35,187 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:35,188 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:35,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:35,189 INFO L82 PathProgramCache]: Analyzing trace with hash 1886502219, now seen corresponding path program 5 times [2019-12-07 11:01:35,189 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:35,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256576725] [2019-12-07 11:01:35,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:35,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:35,351 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:35,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256576725] [2019-12-07 11:01:35,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1850572125] [2019-12-07 11:01:35,352 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:35,384 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2019-12-07 11:01:35,385 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:35,385 INFO L264 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 11:01:35,386 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:35,396 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:35,396 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:35,396 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2019-12-07 11:01:35,396 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290972238] [2019-12-07 11:01:35,396 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 11:01:35,396 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:35,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 11:01:35,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:01:35,397 INFO L87 Difference]: Start difference. First operand 28 states and 58 transitions. Second operand 9 states. [2019-12-07 11:01:35,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:35,456 INFO L93 Difference]: Finished difference Result 49 states and 100 transitions. [2019-12-07 11:01:35,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 11:01:35,456 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 12 [2019-12-07 11:01:35,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:35,457 INFO L225 Difference]: With dead ends: 49 [2019-12-07 11:01:35,457 INFO L226 Difference]: Without dead ends: 40 [2019-12-07 11:01:35,457 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=99, Unknown=0, NotChecked=0, Total=156 [2019-12-07 11:01:35,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2019-12-07 11:01:35,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 27. [2019-12-07 11:01:35,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-12-07 11:01:35,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 56 transitions. [2019-12-07 11:01:35,460 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 56 transitions. Word has length 12 [2019-12-07 11:01:35,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:35,461 INFO L462 AbstractCegarLoop]: Abstraction has 27 states and 56 transitions. [2019-12-07 11:01:35,461 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 11:01:35,461 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 56 transitions. [2019-12-07 11:01:35,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 11:01:35,461 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:35,461 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:35,662 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:35,663 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:35,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:35,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1575404710, now seen corresponding path program 6 times [2019-12-07 11:01:35,664 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:35,665 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670673739] [2019-12-07 11:01:35,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:35,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:35,797 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:35,797 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670673739] [2019-12-07 11:01:35,797 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [702407774] [2019-12-07 11:01:35,797 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:35,833 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2019-12-07 11:01:35,834 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:35,834 INFO L264 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 11:01:35,835 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:35,847 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:35,847 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:35,847 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2019-12-07 11:01:35,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940549371] [2019-12-07 11:01:35,848 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 11:01:35,848 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:35,848 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 11:01:35,848 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2019-12-07 11:01:35,848 INFO L87 Difference]: Start difference. First operand 27 states and 56 transitions. Second operand 10 states. [2019-12-07 11:01:35,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:35,938 INFO L93 Difference]: Finished difference Result 47 states and 96 transitions. [2019-12-07 11:01:35,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:01:35,939 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 13 [2019-12-07 11:01:35,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:35,939 INFO L225 Difference]: With dead ends: 47 [2019-12-07 11:01:35,939 INFO L226 Difference]: Without dead ends: 39 [2019-12-07 11:01:35,940 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=151, Unknown=0, NotChecked=0, Total=240 [2019-12-07 11:01:35,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2019-12-07 11:01:35,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 37. [2019-12-07 11:01:35,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-12-07 11:01:35,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 77 transitions. [2019-12-07 11:01:35,942 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 77 transitions. Word has length 13 [2019-12-07 11:01:35,943 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:35,943 INFO L462 AbstractCegarLoop]: Abstraction has 37 states and 77 transitions. [2019-12-07 11:01:35,943 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 11:01:35,943 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 77 transitions. [2019-12-07 11:01:35,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2019-12-07 11:01:35,943 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:35,943 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:36,144 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:36,144 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:36,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:36,144 INFO L82 PathProgramCache]: Analyzing trace with hash 452443059, now seen corresponding path program 7 times [2019-12-07 11:01:36,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:36,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273291264] [2019-12-07 11:01:36,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:36,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:36,230 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:36,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273291264] [2019-12-07 11:01:36,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [479304598] [2019-12-07 11:01:36,230 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:36,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:36,265 INFO L264 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 11:01:36,266 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:36,278 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:36,279 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:36,279 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2019-12-07 11:01:36,279 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892351947] [2019-12-07 11:01:36,279 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 11:01:36,279 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:36,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 11:01:36,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 11:01:36,280 INFO L87 Difference]: Start difference. First operand 37 states and 77 transitions. Second operand 11 states. [2019-12-07 11:01:36,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:36,365 INFO L93 Difference]: Finished difference Result 50 states and 102 transitions. [2019-12-07 11:01:36,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 11:01:36,366 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 14 [2019-12-07 11:01:36,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:36,366 INFO L225 Difference]: With dead ends: 50 [2019-12-07 11:01:36,366 INFO L226 Difference]: Without dead ends: 41 [2019-12-07 11:01:36,367 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=176, Unknown=0, NotChecked=0, Total=272 [2019-12-07 11:01:36,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-12-07 11:01:36,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 29. [2019-12-07 11:01:36,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-12-07 11:01:36,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 60 transitions. [2019-12-07 11:01:36,369 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 60 transitions. Word has length 14 [2019-12-07 11:01:36,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:36,369 INFO L462 AbstractCegarLoop]: Abstraction has 29 states and 60 transitions. [2019-12-07 11:01:36,369 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 11:01:36,369 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 60 transitions. [2019-12-07 11:01:36,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 11:01:36,370 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:36,370 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:36,570 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:36,571 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:36,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:36,572 INFO L82 PathProgramCache]: Analyzing trace with hash -2135428606, now seen corresponding path program 8 times [2019-12-07 11:01:36,572 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:36,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776657060] [2019-12-07 11:01:36,573 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:36,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:36,728 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:36,729 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776657060] [2019-12-07 11:01:36,729 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1065871803] [2019-12-07 11:01:36,729 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:36,768 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:01:36,768 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:36,768 INFO L264 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 11:01:36,769 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:36,780 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:36,780 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:36,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2019-12-07 11:01:36,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804821662] [2019-12-07 11:01:36,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 11:01:36,781 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:36,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 11:01:36,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2019-12-07 11:01:36,781 INFO L87 Difference]: Start difference. First operand 29 states and 60 transitions. Second operand 12 states. [2019-12-07 11:01:36,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:36,888 INFO L93 Difference]: Finished difference Result 56 states and 114 transitions. [2019-12-07 11:01:36,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 11:01:36,888 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 15 [2019-12-07 11:01:36,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:36,889 INFO L225 Difference]: With dead ends: 56 [2019-12-07 11:01:36,889 INFO L226 Difference]: Without dead ends: 47 [2019-12-07 11:01:36,889 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=136, Invalid=244, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:01:36,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2019-12-07 11:01:36,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 32. [2019-12-07 11:01:36,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2019-12-07 11:01:36,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 66 transitions. [2019-12-07 11:01:36,892 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 66 transitions. Word has length 15 [2019-12-07 11:01:36,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:36,892 INFO L462 AbstractCegarLoop]: Abstraction has 32 states and 66 transitions. [2019-12-07 11:01:36,892 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 11:01:36,892 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 66 transitions. [2019-12-07 11:01:36,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 11:01:36,893 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:36,893 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:37,093 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:37,094 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:37,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:37,095 INFO L82 PathProgramCache]: Analyzing trace with hash 1006092315, now seen corresponding path program 9 times [2019-12-07 11:01:37,096 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:37,096 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630646113] [2019-12-07 11:01:37,096 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:37,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:37,203 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:37,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630646113] [2019-12-07 11:01:37,204 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [163265921] [2019-12-07 11:01:37,204 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:37,244 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2019-12-07 11:01:37,244 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:37,245 INFO L264 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 11:01:37,246 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:37,259 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:37,259 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:37,260 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2019-12-07 11:01:37,260 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492317253] [2019-12-07 11:01:37,260 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 11:01:37,260 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:37,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 11:01:37,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2019-12-07 11:01:37,260 INFO L87 Difference]: Start difference. First operand 32 states and 66 transitions. Second operand 13 states. [2019-12-07 11:01:37,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:37,365 INFO L93 Difference]: Finished difference Result 53 states and 108 transitions. [2019-12-07 11:01:37,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 11:01:37,365 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 16 [2019-12-07 11:01:37,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:37,366 INFO L225 Difference]: With dead ends: 53 [2019-12-07 11:01:37,366 INFO L226 Difference]: Without dead ends: 45 [2019-12-07 11:01:37,367 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=274, Unknown=0, NotChecked=0, Total=420 [2019-12-07 11:01:37,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-12-07 11:01:37,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 43. [2019-12-07 11:01:37,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-12-07 11:01:37,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 89 transitions. [2019-12-07 11:01:37,370 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 89 transitions. Word has length 16 [2019-12-07 11:01:37,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:37,370 INFO L462 AbstractCegarLoop]: Abstraction has 43 states and 89 transitions. [2019-12-07 11:01:37,370 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 11:01:37,371 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 89 transitions. [2019-12-07 11:01:37,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-12-07 11:01:37,371 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:37,371 INFO L410 BasicCegarLoop]: trace histogram [5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:37,572 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:37,573 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:37,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:37,573 INFO L82 PathProgramCache]: Analyzing trace with hash 1124090998, now seen corresponding path program 10 times [2019-12-07 11:01:37,574 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:37,574 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037155074] [2019-12-07 11:01:37,575 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:37,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:37,762 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:37,762 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037155074] [2019-12-07 11:01:37,762 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [546759093] [2019-12-07 11:01:37,762 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:37,797 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:37,797 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:37,798 INFO L264 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 16 conjunts are in the unsatisfiable core [2019-12-07 11:01:37,798 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:37,814 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:37,814 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:37,814 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2019-12-07 11:01:37,814 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915777187] [2019-12-07 11:01:37,815 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 11:01:37,815 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:37,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 11:01:37,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=135, Unknown=0, NotChecked=0, Total=182 [2019-12-07 11:01:37,815 INFO L87 Difference]: Start difference. First operand 43 states and 89 transitions. Second operand 14 states. [2019-12-07 11:01:37,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:37,949 INFO L93 Difference]: Finished difference Result 52 states and 106 transitions. [2019-12-07 11:01:37,950 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 11:01:37,950 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 17 [2019-12-07 11:01:37,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:37,950 INFO L225 Difference]: With dead ends: 52 [2019-12-07 11:01:37,950 INFO L226 Difference]: Without dead ends: 43 [2019-12-07 11:01:37,951 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=187, Invalid=365, Unknown=0, NotChecked=0, Total=552 [2019-12-07 11:01:37,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2019-12-07 11:01:37,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 30. [2019-12-07 11:01:37,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-12-07 11:01:37,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 62 transitions. [2019-12-07 11:01:37,953 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 62 transitions. Word has length 17 [2019-12-07 11:01:37,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:37,953 INFO L462 AbstractCegarLoop]: Abstraction has 30 states and 62 transitions. [2019-12-07 11:01:37,953 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 11:01:37,953 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 62 transitions. [2019-12-07 11:01:37,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 11:01:37,954 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:37,954 INFO L410 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:38,154 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:38,155 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:38,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:38,156 INFO L82 PathProgramCache]: Analyzing trace with hash 502282183, now seen corresponding path program 11 times [2019-12-07 11:01:38,156 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:38,157 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853233233] [2019-12-07 11:01:38,157 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:38,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:38,351 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:38,351 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853233233] [2019-12-07 11:01:38,351 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2015425178] [2019-12-07 11:01:38,351 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:38,398 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2019-12-07 11:01:38,398 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:38,399 INFO L264 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 11:01:38,400 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:38,427 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:38,427 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:38,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2019-12-07 11:01:38,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030366030] [2019-12-07 11:01:38,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 11:01:38,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:38,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 11:01:38,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=156, Unknown=0, NotChecked=0, Total=210 [2019-12-07 11:01:38,428 INFO L87 Difference]: Start difference. First operand 30 states and 62 transitions. Second operand 15 states. [2019-12-07 11:01:38,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:38,570 INFO L93 Difference]: Finished difference Result 54 states and 110 transitions. [2019-12-07 11:01:38,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 11:01:38,570 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 18 [2019-12-07 11:01:38,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:38,571 INFO L225 Difference]: With dead ends: 54 [2019-12-07 11:01:38,571 INFO L226 Difference]: Without dead ends: 50 [2019-12-07 11:01:38,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=218, Invalid=432, Unknown=0, NotChecked=0, Total=650 [2019-12-07 11:01:38,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2019-12-07 11:01:38,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 48. [2019-12-07 11:01:38,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-12-07 11:01:38,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 99 transitions. [2019-12-07 11:01:38,575 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 99 transitions. Word has length 18 [2019-12-07 11:01:38,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:38,575 INFO L462 AbstractCegarLoop]: Abstraction has 48 states and 99 transitions. [2019-12-07 11:01:38,575 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 11:01:38,575 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 99 transitions. [2019-12-07 11:01:38,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 11:01:38,576 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:38,576 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:38,776 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:38,778 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:38,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:38,778 INFO L82 PathProgramCache]: Analyzing trace with hash -2080307442, now seen corresponding path program 12 times [2019-12-07 11:01:38,779 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:38,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028938132] [2019-12-07 11:01:38,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:38,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:38,905 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:38,905 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028938132] [2019-12-07 11:01:38,905 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [969220424] [2019-12-07 11:01:38,905 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:38,940 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2019-12-07 11:01:38,940 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:38,941 INFO L264 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 11:01:38,942 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:38,957 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:38,957 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:38,957 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2019-12-07 11:01:38,958 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931503161] [2019-12-07 11:01:38,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 11:01:38,958 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:38,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 11:01:38,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2019-12-07 11:01:38,958 INFO L87 Difference]: Start difference. First operand 48 states and 99 transitions. Second operand 16 states. [2019-12-07 11:01:39,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:39,122 INFO L93 Difference]: Finished difference Result 57 states and 116 transitions. [2019-12-07 11:01:39,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 11:01:39,122 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 19 [2019-12-07 11:01:39,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:39,123 INFO L225 Difference]: With dead ends: 57 [2019-12-07 11:01:39,123 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 11:01:39,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=216, Invalid=486, Unknown=0, NotChecked=0, Total=702 [2019-12-07 11:01:39,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 11:01:39,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 34. [2019-12-07 11:01:39,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2019-12-07 11:01:39,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 70 transitions. [2019-12-07 11:01:39,126 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 70 transitions. Word has length 19 [2019-12-07 11:01:39,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:39,126 INFO L462 AbstractCegarLoop]: Abstraction has 34 states and 70 transitions. [2019-12-07 11:01:39,126 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 11:01:39,126 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 70 transitions. [2019-12-07 11:01:39,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 11:01:39,126 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:39,127 INFO L410 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:39,327 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:39,328 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:39,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:39,329 INFO L82 PathProgramCache]: Analyzing trace with hash 1656842535, now seen corresponding path program 13 times [2019-12-07 11:01:39,330 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:39,330 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671202758] [2019-12-07 11:01:39,331 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:39,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:39,453 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:39,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671202758] [2019-12-07 11:01:39,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [424126525] [2019-12-07 11:01:39,453 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:39,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:39,486 INFO L264 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 11:01:39,487 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:39,504 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:39,504 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:39,504 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2019-12-07 11:01:39,504 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712241165] [2019-12-07 11:01:39,504 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 11:01:39,504 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:39,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 11:01:39,505 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=178, Unknown=0, NotChecked=0, Total=240 [2019-12-07 11:01:39,505 INFO L87 Difference]: Start difference. First operand 34 states and 70 transitions. Second operand 16 states. [2019-12-07 11:01:39,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:39,666 INFO L93 Difference]: Finished difference Result 57 states and 116 transitions. [2019-12-07 11:01:39,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 11:01:39,666 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 20 [2019-12-07 11:01:39,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:39,666 INFO L225 Difference]: With dead ends: 57 [2019-12-07 11:01:39,667 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 11:01:39,667 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=263, Invalid=493, Unknown=0, NotChecked=0, Total=756 [2019-12-07 11:01:39,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 11:01:39,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 50. [2019-12-07 11:01:39,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-12-07 11:01:39,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 103 transitions. [2019-12-07 11:01:39,671 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 103 transitions. Word has length 20 [2019-12-07 11:01:39,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:39,671 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 103 transitions. [2019-12-07 11:01:39,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 11:01:39,671 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 103 transitions. [2019-12-07 11:01:39,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 11:01:39,672 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:39,672 INFO L410 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:39,872 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:39,873 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:39,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:39,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1656842783, now seen corresponding path program 14 times [2019-12-07 11:01:39,874 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:39,874 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537101045] [2019-12-07 11:01:39,874 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:39,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:40,024 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:40,024 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537101045] [2019-12-07 11:01:40,024 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1152643840] [2019-12-07 11:01:40,024 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:40,071 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:01:40,071 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:40,072 INFO L264 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 11:01:40,073 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:40,093 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:40,093 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:40,093 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2019-12-07 11:01:40,094 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378165602] [2019-12-07 11:01:40,094 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 11:01:40,094 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:40,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 11:01:40,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=203, Unknown=0, NotChecked=0, Total=272 [2019-12-07 11:01:40,094 INFO L87 Difference]: Start difference. First operand 50 states and 103 transitions. Second operand 17 states. [2019-12-07 11:01:40,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:40,285 INFO L93 Difference]: Finished difference Result 59 states and 120 transitions. [2019-12-07 11:01:40,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 11:01:40,286 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 20 [2019-12-07 11:01:40,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:40,286 INFO L225 Difference]: With dead ends: 59 [2019-12-07 11:01:40,286 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 11:01:40,287 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 147 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=289, Invalid=581, Unknown=0, NotChecked=0, Total=870 [2019-12-07 11:01:40,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 11:01:40,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 52. [2019-12-07 11:01:40,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2019-12-07 11:01:40,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 107 transitions. [2019-12-07 11:01:40,289 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 107 transitions. Word has length 20 [2019-12-07 11:01:40,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:40,289 INFO L462 AbstractCegarLoop]: Abstraction has 52 states and 107 transitions. [2019-12-07 11:01:40,289 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 11:01:40,289 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 107 transitions. [2019-12-07 11:01:40,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 11:01:40,290 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:40,290 INFO L410 BasicCegarLoop]: trace histogram [8, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:40,490 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:40,491 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:40,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:40,491 INFO L82 PathProgramCache]: Analyzing trace with hash -2015657298, now seen corresponding path program 15 times [2019-12-07 11:01:40,492 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:40,492 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805880540] [2019-12-07 11:01:40,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:40,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:40,619 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:40,620 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805880540] [2019-12-07 11:01:40,620 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1502187821] [2019-12-07 11:01:40,620 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:40,655 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2019-12-07 11:01:40,656 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:40,656 INFO L264 TraceCheckSpWp]: Trace formula consists of 138 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 11:01:40,657 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:40,672 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:40,673 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:40,673 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2019-12-07 11:01:40,673 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307578591] [2019-12-07 11:01:40,673 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 11:01:40,673 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:40,673 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 11:01:40,673 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2019-12-07 11:01:40,673 INFO L87 Difference]: Start difference. First operand 52 states and 107 transitions. Second operand 17 states. [2019-12-07 11:01:40,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:40,843 INFO L93 Difference]: Finished difference Result 57 states and 116 transitions. [2019-12-07 11:01:40,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 11:01:40,843 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 21 [2019-12-07 11:01:40,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:40,843 INFO L225 Difference]: With dead ends: 57 [2019-12-07 11:01:40,843 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 11:01:40,844 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=274, Invalid=538, Unknown=0, NotChecked=0, Total=812 [2019-12-07 11:01:40,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 11:01:40,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 35. [2019-12-07 11:01:40,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2019-12-07 11:01:40,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 72 transitions. [2019-12-07 11:01:40,846 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 72 transitions. Word has length 21 [2019-12-07 11:01:40,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:40,846 INFO L462 AbstractCegarLoop]: Abstraction has 35 states and 72 transitions. [2019-12-07 11:01:40,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 11:01:40,846 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 72 transitions. [2019-12-07 11:01:40,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 11:01:40,846 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:40,846 INFO L410 BasicCegarLoop]: trace histogram [7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:41,047 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:41,047 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:41,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:41,048 INFO L82 PathProgramCache]: Analyzing trace with hash -2015657050, now seen corresponding path program 16 times [2019-12-07 11:01:41,048 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:41,049 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394800039] [2019-12-07 11:01:41,049 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:41,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:41,185 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:41,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394800039] [2019-12-07 11:01:41,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [397302847] [2019-12-07 11:01:41,185 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:41,224 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:41,224 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:41,225 INFO L264 TraceCheckSpWp]: Trace formula consists of 138 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 11:01:41,226 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:41,240 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:41,240 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:41,240 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2019-12-07 11:01:41,240 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386730418] [2019-12-07 11:01:41,240 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 11:01:41,240 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:41,241 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 11:01:41,241 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=229, Unknown=0, NotChecked=0, Total=306 [2019-12-07 11:01:41,241 INFO L87 Difference]: Start difference. First operand 35 states and 72 transitions. Second operand 18 states. [2019-12-07 11:01:41,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:41,434 INFO L93 Difference]: Finished difference Result 59 states and 120 transitions. [2019-12-07 11:01:41,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 11:01:41,434 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 21 [2019-12-07 11:01:41,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:41,435 INFO L225 Difference]: With dead ends: 59 [2019-12-07 11:01:41,435 INFO L226 Difference]: Without dead ends: 53 [2019-12-07 11:01:41,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=329, Invalid=663, Unknown=0, NotChecked=0, Total=992 [2019-12-07 11:01:41,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2019-12-07 11:01:41,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 34. [2019-12-07 11:01:41,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2019-12-07 11:01:41,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 70 transitions. [2019-12-07 11:01:41,437 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 70 transitions. Word has length 21 [2019-12-07 11:01:41,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:41,437 INFO L462 AbstractCegarLoop]: Abstraction has 34 states and 70 transitions. [2019-12-07 11:01:41,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 11:01:41,437 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 70 transitions. [2019-12-07 11:01:41,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 11:01:41,437 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:41,437 INFO L410 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:41,638 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:41,638 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:41,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:41,638 INFO L82 PathProgramCache]: Analyzing trace with hash -1206950281, now seen corresponding path program 17 times [2019-12-07 11:01:41,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:41,638 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950171061] [2019-12-07 11:01:41,638 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:41,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:41,746 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:41,747 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950171061] [2019-12-07 11:01:41,747 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1333890718] [2019-12-07 11:01:41,747 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:41,782 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2019-12-07 11:01:41,782 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:41,782 INFO L264 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 11:01:41,783 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:41,798 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:41,798 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:41,798 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2019-12-07 11:01:41,798 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708853183] [2019-12-07 11:01:41,798 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 11:01:41,798 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:41,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 11:01:41,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=256, Unknown=0, NotChecked=0, Total=342 [2019-12-07 11:01:41,799 INFO L87 Difference]: Start difference. First operand 34 states and 70 transitions. Second operand 19 states. [2019-12-07 11:01:42,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:42,007 INFO L93 Difference]: Finished difference Result 62 states and 126 transitions. [2019-12-07 11:01:42,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 11:01:42,008 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 22 [2019-12-07 11:01:42,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:42,008 INFO L225 Difference]: With dead ends: 62 [2019-12-07 11:01:42,008 INFO L226 Difference]: Without dead ends: 58 [2019-12-07 11:01:42,009 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=370, Invalid=752, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 11:01:42,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2019-12-07 11:01:42,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2019-12-07 11:01:42,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2019-12-07 11:01:42,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 115 transitions. [2019-12-07 11:01:42,011 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 115 transitions. Word has length 22 [2019-12-07 11:01:42,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:42,011 INFO L462 AbstractCegarLoop]: Abstraction has 56 states and 115 transitions. [2019-12-07 11:01:42,011 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 11:01:42,011 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 115 transitions. [2019-12-07 11:01:42,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2019-12-07 11:01:42,011 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:42,011 INFO L410 BasicCegarLoop]: trace histogram [8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:42,212 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:42,212 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:42,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:42,213 INFO L82 PathProgramCache]: Analyzing trace with hash -16172482, now seen corresponding path program 18 times [2019-12-07 11:01:42,213 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:42,214 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242855320] [2019-12-07 11:01:42,214 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:42,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:42,374 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:42,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242855320] [2019-12-07 11:01:42,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1877624617] [2019-12-07 11:01:42,374 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:42,412 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2019-12-07 11:01:42,412 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:42,413 INFO L264 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 11:01:42,414 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:42,430 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:42,430 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:42,430 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2019-12-07 11:01:42,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435050979] [2019-12-07 11:01:42,430 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 11:01:42,430 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:42,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 11:01:42,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=285, Unknown=0, NotChecked=0, Total=380 [2019-12-07 11:01:42,431 INFO L87 Difference]: Start difference. First operand 56 states and 115 transitions. Second operand 20 states. [2019-12-07 11:01:42,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:42,647 INFO L93 Difference]: Finished difference Result 65 states and 132 transitions. [2019-12-07 11:01:42,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 11:01:42,648 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 23 [2019-12-07 11:01:42,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:42,648 INFO L225 Difference]: With dead ends: 65 [2019-12-07 11:01:42,648 INFO L226 Difference]: Without dead ends: 57 [2019-12-07 11:01:42,649 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 182 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=359, Invalid=831, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 11:01:42,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2019-12-07 11:01:42,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 36. [2019-12-07 11:01:42,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-12-07 11:01:42,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 74 transitions. [2019-12-07 11:01:42,650 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 74 transitions. Word has length 23 [2019-12-07 11:01:42,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:42,650 INFO L462 AbstractCegarLoop]: Abstraction has 36 states and 74 transitions. [2019-12-07 11:01:42,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 11:01:42,650 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 74 transitions. [2019-12-07 11:01:42,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2019-12-07 11:01:42,651 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:42,651 INFO L410 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:42,851 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:42,851 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:42,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:42,852 INFO L82 PathProgramCache]: Analyzing trace with hash -238048049, now seen corresponding path program 19 times [2019-12-07 11:01:42,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:42,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737877545] [2019-12-07 11:01:42,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:42,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:42,983 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:42,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737877545] [2019-12-07 11:01:42,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2108962450] [2019-12-07 11:01:42,983 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:43,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:43,022 INFO L264 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 11:01:43,023 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:43,041 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:43,041 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:43,041 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2019-12-07 11:01:43,041 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811249383] [2019-12-07 11:01:43,041 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 11:01:43,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:43,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 11:01:43,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2019-12-07 11:01:43,042 INFO L87 Difference]: Start difference. First operand 36 states and 74 transitions. Second operand 21 states. [2019-12-07 11:01:43,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:43,302 INFO L93 Difference]: Finished difference Result 65 states and 132 transitions. [2019-12-07 11:01:43,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 11:01:43,302 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 24 [2019-12-07 11:01:43,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:43,302 INFO L225 Difference]: With dead ends: 65 [2019-12-07 11:01:43,302 INFO L226 Difference]: Without dead ends: 59 [2019-12-07 11:01:43,303 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=461, Invalid=945, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 11:01:43,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2019-12-07 11:01:43,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 39. [2019-12-07 11:01:43,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-12-07 11:01:43,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 80 transitions. [2019-12-07 11:01:43,304 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 80 transitions. Word has length 24 [2019-12-07 11:01:43,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:43,304 INFO L462 AbstractCegarLoop]: Abstraction has 39 states and 80 transitions. [2019-12-07 11:01:43,304 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 11:01:43,305 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 80 transitions. [2019-12-07 11:01:43,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 11:01:43,305 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:43,305 INFO L410 BasicCegarLoop]: trace histogram [9, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:43,505 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:43,506 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:43,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:43,507 INFO L82 PathProgramCache]: Analyzing trace with hash 1638116054, now seen corresponding path program 20 times [2019-12-07 11:01:43,507 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:43,507 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575423539] [2019-12-07 11:01:43,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:43,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:43,646 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:43,647 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575423539] [2019-12-07 11:01:43,647 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1097310972] [2019-12-07 11:01:43,647 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:43,681 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:01:43,681 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:43,682 INFO L264 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 11:01:43,682 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:43,698 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:43,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:43,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2019-12-07 11:01:43,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769358746] [2019-12-07 11:01:43,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 11:01:43,699 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:43,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 11:01:43,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2019-12-07 11:01:43,699 INFO L87 Difference]: Start difference. First operand 39 states and 80 transitions. Second operand 22 states. [2019-12-07 11:01:43,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:43,973 INFO L93 Difference]: Finished difference Result 67 states and 136 transitions. [2019-12-07 11:01:43,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 11:01:43,974 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 25 [2019-12-07 11:01:43,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:43,974 INFO L225 Difference]: With dead ends: 67 [2019-12-07 11:01:43,974 INFO L226 Difference]: Without dead ends: 61 [2019-12-07 11:01:43,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 248 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=511, Invalid=1049, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 11:01:43,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2019-12-07 11:01:43,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 38. [2019-12-07 11:01:43,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-12-07 11:01:43,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 78 transitions. [2019-12-07 11:01:43,976 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 78 transitions. Word has length 25 [2019-12-07 11:01:43,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:43,976 INFO L462 AbstractCegarLoop]: Abstraction has 38 states and 78 transitions. [2019-12-07 11:01:43,977 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 11:01:43,977 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 78 transitions. [2019-12-07 11:01:43,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 11:01:43,977 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:43,977 INFO L410 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:44,177 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:44,178 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:44,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:44,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1130906329, now seen corresponding path program 21 times [2019-12-07 11:01:44,179 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:44,179 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898268642] [2019-12-07 11:01:44,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:44,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:44,356 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:44,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898268642] [2019-12-07 11:01:44,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2060293589] [2019-12-07 11:01:44,357 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:44,396 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2019-12-07 11:01:44,396 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:44,397 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 11:01:44,398 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:44,414 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:44,414 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:44,414 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2019-12-07 11:01:44,415 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766263231] [2019-12-07 11:01:44,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2019-12-07 11:01:44,415 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:44,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 11:01:44,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=380, Unknown=0, NotChecked=0, Total=506 [2019-12-07 11:01:44,415 INFO L87 Difference]: Start difference. First operand 38 states and 78 transitions. Second operand 23 states. [2019-12-07 11:01:44,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:44,704 INFO L93 Difference]: Finished difference Result 69 states and 140 transitions. [2019-12-07 11:01:44,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 11:01:44,704 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 26 [2019-12-07 11:01:44,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:44,705 INFO L225 Difference]: With dead ends: 69 [2019-12-07 11:01:44,705 INFO L226 Difference]: Without dead ends: 63 [2019-12-07 11:01:44,705 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=525, Invalid=1197, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 11:01:44,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2019-12-07 11:01:44,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 41. [2019-12-07 11:01:44,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 11:01:44,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 84 transitions. [2019-12-07 11:01:44,707 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 84 transitions. Word has length 26 [2019-12-07 11:01:44,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:44,707 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 84 transitions. [2019-12-07 11:01:44,707 INFO L463 AbstractCegarLoop]: Interpolant automaton has 23 states. [2019-12-07 11:01:44,707 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 84 transitions. [2019-12-07 11:01:44,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 11:01:44,707 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:44,707 INFO L410 BasicCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:44,908 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:44,908 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:44,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:44,909 INFO L82 PathProgramCache]: Analyzing trace with hash -2023467666, now seen corresponding path program 22 times [2019-12-07 11:01:44,909 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:44,910 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429952393] [2019-12-07 11:01:44,910 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:44,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:45,113 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:45,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429952393] [2019-12-07 11:01:45,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [547623710] [2019-12-07 11:01:45,114 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:45,149 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:45,149 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:45,150 INFO L264 TraceCheckSpWp]: Trace formula consists of 168 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 11:01:45,151 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:45,170 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:45,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:45,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 22 [2019-12-07 11:01:45,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024863057] [2019-12-07 11:01:45,171 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 11:01:45,172 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:45,172 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 11:01:45,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=415, Unknown=0, NotChecked=0, Total=552 [2019-12-07 11:01:45,172 INFO L87 Difference]: Start difference. First operand 41 states and 84 transitions. Second operand 24 states. [2019-12-07 11:01:45,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:45,507 INFO L93 Difference]: Finished difference Result 73 states and 148 transitions. [2019-12-07 11:01:45,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 11:01:45,507 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 27 [2019-12-07 11:01:45,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:45,508 INFO L225 Difference]: With dead ends: 73 [2019-12-07 11:01:45,508 INFO L226 Difference]: Without dead ends: 69 [2019-12-07 11:01:45,508 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=617, Invalid=1275, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 11:01:45,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-12-07 11:01:45,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 66. [2019-12-07 11:01:45,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2019-12-07 11:01:45,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 135 transitions. [2019-12-07 11:01:45,511 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 135 transitions. Word has length 27 [2019-12-07 11:01:45,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:45,511 INFO L462 AbstractCegarLoop]: Abstraction has 66 states and 135 transitions. [2019-12-07 11:01:45,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 11:01:45,511 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 135 transitions. [2019-12-07 11:01:45,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 11:01:45,511 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:45,511 INFO L410 BasicCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:45,712 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:45,712 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:45,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:45,713 INFO L82 PathProgramCache]: Analyzing trace with hash -174254209, now seen corresponding path program 23 times [2019-12-07 11:01:45,713 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:45,713 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790373552] [2019-12-07 11:01:45,714 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:45,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:45,918 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:45,918 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790373552] [2019-12-07 11:01:45,918 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1133699997] [2019-12-07 11:01:45,919 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:45,958 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2019-12-07 11:01:45,958 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:45,959 INFO L264 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 11:01:45,960 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:45,979 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:45,980 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:45,980 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 23 [2019-12-07 11:01:45,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120317987] [2019-12-07 11:01:45,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 11:01:45,980 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:45,980 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 11:01:45,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=149, Invalid=451, Unknown=0, NotChecked=0, Total=600 [2019-12-07 11:01:45,981 INFO L87 Difference]: Start difference. First operand 66 states and 135 transitions. Second operand 25 states. [2019-12-07 11:01:46,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:46,313 INFO L93 Difference]: Finished difference Result 75 states and 152 transitions. [2019-12-07 11:01:46,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 11:01:46,313 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 28 [2019-12-07 11:01:46,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:46,314 INFO L225 Difference]: With dead ends: 75 [2019-12-07 11:01:46,314 INFO L226 Difference]: Without dead ends: 69 [2019-12-07 11:01:46,314 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 379 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=673, Invalid=1397, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 11:01:46,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-12-07 11:01:46,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 68. [2019-12-07 11:01:46,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2019-12-07 11:01:46,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 139 transitions. [2019-12-07 11:01:46,316 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 139 transitions. Word has length 28 [2019-12-07 11:01:46,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:46,316 INFO L462 AbstractCegarLoop]: Abstraction has 68 states and 139 transitions. [2019-12-07 11:01:46,316 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 11:01:46,316 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 139 transitions. [2019-12-07 11:01:46,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 11:01:46,316 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:46,316 INFO L410 BasicCegarLoop]: trace histogram [12, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:46,517 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:46,517 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:46,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:46,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1067759886, now seen corresponding path program 24 times [2019-12-07 11:01:46,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:46,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221210910] [2019-12-07 11:01:46,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:46,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:46,739 INFO L134 CoverageAnalysis]: Checked inductivity of 111 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:46,739 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221210910] [2019-12-07 11:01:46,739 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [829722231] [2019-12-07 11:01:46,739 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:46,786 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2019-12-07 11:01:46,786 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:46,787 INFO L264 TraceCheckSpWp]: Trace formula consists of 178 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 11:01:46,788 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:46,809 INFO L134 CoverageAnalysis]: Checked inductivity of 111 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:46,810 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:46,810 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 23 [2019-12-07 11:01:46,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178474594] [2019-12-07 11:01:46,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2019-12-07 11:01:46,810 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:46,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 11:01:46,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=150, Invalid=450, Unknown=0, NotChecked=0, Total=600 [2019-12-07 11:01:46,811 INFO L87 Difference]: Start difference. First operand 68 states and 139 transitions. Second operand 25 states. [2019-12-07 11:01:47,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:47,171 INFO L93 Difference]: Finished difference Result 73 states and 148 transitions. [2019-12-07 11:01:47,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 11:01:47,171 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 29 [2019-12-07 11:01:47,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:47,172 INFO L225 Difference]: With dead ends: 73 [2019-12-07 11:01:47,172 INFO L226 Difference]: Without dead ends: 69 [2019-12-07 11:01:47,172 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 318 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=650, Invalid=1330, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 11:01:47,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-12-07 11:01:47,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 43. [2019-12-07 11:01:47,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-12-07 11:01:47,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 88 transitions. [2019-12-07 11:01:47,174 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 88 transitions. Word has length 29 [2019-12-07 11:01:47,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:47,174 INFO L462 AbstractCegarLoop]: Abstraction has 43 states and 88 transitions. [2019-12-07 11:01:47,174 INFO L463 AbstractCegarLoop]: Interpolant automaton has 25 states. [2019-12-07 11:01:47,174 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 88 transitions. [2019-12-07 11:01:47,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 11:01:47,174 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:47,174 INFO L410 BasicCegarLoop]: trace histogram [11, 11, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:47,375 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:47,376 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:47,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:47,376 INFO L82 PathProgramCache]: Analyzing trace with hash 1067760134, now seen corresponding path program 25 times [2019-12-07 11:01:47,377 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:47,377 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075166627] [2019-12-07 11:01:47,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:47,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:47,710 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:47,710 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075166627] [2019-12-07 11:01:47,710 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [539339291] [2019-12-07 11:01:47,710 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:47,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:47,747 INFO L264 TraceCheckSpWp]: Trace formula consists of 178 conjuncts, 28 conjunts are in the unsatisfiable core [2019-12-07 11:01:47,747 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:47,764 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:47,764 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:47,764 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 24 [2019-12-07 11:01:47,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006380497] [2019-12-07 11:01:47,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2019-12-07 11:01:47,765 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:47,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 11:01:47,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 11:01:47,765 INFO L87 Difference]: Start difference. First operand 43 states and 88 transitions. Second operand 26 states. [2019-12-07 11:01:48,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:48,119 INFO L93 Difference]: Finished difference Result 75 states and 152 transitions. [2019-12-07 11:01:48,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 11:01:48,119 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 29 [2019-12-07 11:01:48,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:48,120 INFO L225 Difference]: With dead ends: 75 [2019-12-07 11:01:48,120 INFO L226 Difference]: Without dead ends: 69 [2019-12-07 11:01:48,120 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 370 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 11:01:48,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2019-12-07 11:01:48,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 42. [2019-12-07 11:01:48,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2019-12-07 11:01:48,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 86 transitions. [2019-12-07 11:01:48,122 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 86 transitions. Word has length 29 [2019-12-07 11:01:48,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:48,122 INFO L462 AbstractCegarLoop]: Abstraction has 42 states and 86 transitions. [2019-12-07 11:01:48,122 INFO L463 AbstractCegarLoop]: Interpolant automaton has 26 states. [2019-12-07 11:01:48,122 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 86 transitions. [2019-12-07 11:01:48,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 11:01:48,122 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:48,122 INFO L410 BasicCegarLoop]: trace histogram [12, 11, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:48,323 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:48,323 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:48,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:48,324 INFO L82 PathProgramCache]: Analyzing trace with hash 45431767, now seen corresponding path program 26 times [2019-12-07 11:01:48,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:48,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083027508] [2019-12-07 11:01:48,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:48,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:48,553 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:48,554 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083027508] [2019-12-07 11:01:48,554 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [803593375] [2019-12-07 11:01:48,554 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:48,590 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:01:48,591 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:48,591 INFO L264 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 29 conjunts are in the unsatisfiable core [2019-12-07 11:01:48,592 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:48,610 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:48,610 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:48,610 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 25 [2019-12-07 11:01:48,610 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571770950] [2019-12-07 11:01:48,611 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 11:01:48,611 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:48,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 11:01:48,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=174, Invalid=528, Unknown=0, NotChecked=0, Total=702 [2019-12-07 11:01:48,611 INFO L87 Difference]: Start difference. First operand 42 states and 86 transitions. Second operand 27 states. [2019-12-07 11:01:49,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:49,006 INFO L93 Difference]: Finished difference Result 77 states and 156 transitions. [2019-12-07 11:01:49,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 11:01:49,006 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 30 [2019-12-07 11:01:49,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:49,007 INFO L225 Difference]: With dead ends: 77 [2019-12-07 11:01:49,007 INFO L226 Difference]: Without dead ends: 71 [2019-12-07 11:01:49,008 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 452 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=794, Invalid=1656, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 11:01:49,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2019-12-07 11:01:49,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 45. [2019-12-07 11:01:49,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-12-07 11:01:49,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 92 transitions. [2019-12-07 11:01:49,009 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 92 transitions. Word has length 30 [2019-12-07 11:01:49,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:49,009 INFO L462 AbstractCegarLoop]: Abstraction has 45 states and 92 transitions. [2019-12-07 11:01:49,009 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 11:01:49,009 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 92 transitions. [2019-12-07 11:01:49,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 11:01:49,010 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:49,010 INFO L410 BasicCegarLoop]: trace histogram [12, 12, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:49,210 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:49,211 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:49,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:49,211 INFO L82 PathProgramCache]: Analyzing trace with hash -379692898, now seen corresponding path program 27 times [2019-12-07 11:01:49,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:49,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364150191] [2019-12-07 11:01:49,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:49,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:49,447 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:49,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364150191] [2019-12-07 11:01:49,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [189054893] [2019-12-07 11:01:49,447 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:49,491 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-12-07 11:01:49,491 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:49,492 INFO L264 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 11:01:49,492 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:49,510 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:49,510 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:49,510 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 26 [2019-12-07 11:01:49,510 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994532111] [2019-12-07 11:01:49,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 11:01:49,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:49,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 11:01:49,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=569, Unknown=0, NotChecked=0, Total=756 [2019-12-07 11:01:49,511 INFO L87 Difference]: Start difference. First operand 45 states and 92 transitions. Second operand 28 states. [2019-12-07 11:01:49,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:49,923 INFO L93 Difference]: Finished difference Result 81 states and 164 transitions. [2019-12-07 11:01:49,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 11:01:49,923 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 31 [2019-12-07 11:01:49,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:49,924 INFO L225 Difference]: With dead ends: 81 [2019-12-07 11:01:49,924 INFO L226 Difference]: Without dead ends: 77 [2019-12-07 11:01:49,924 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=859, Invalid=1793, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 11:01:49,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2019-12-07 11:01:49,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 74. [2019-12-07 11:01:49,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2019-12-07 11:01:49,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 151 transitions. [2019-12-07 11:01:49,926 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 151 transitions. Word has length 31 [2019-12-07 11:01:49,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:49,926 INFO L462 AbstractCegarLoop]: Abstraction has 74 states and 151 transitions. [2019-12-07 11:01:49,926 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 11:01:49,926 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 151 transitions. [2019-12-07 11:01:49,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 11:01:49,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:49,927 INFO L410 BasicCegarLoop]: trace histogram [13, 12, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:50,127 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:50,128 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:50,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:50,129 INFO L82 PathProgramCache]: Analyzing trace with hash 710257199, now seen corresponding path program 28 times [2019-12-07 11:01:50,129 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:50,129 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729717582] [2019-12-07 11:01:50,129 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:50,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:50,371 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:50,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729717582] [2019-12-07 11:01:50,372 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [819161303] [2019-12-07 11:01:50,372 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:50,407 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:50,407 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:50,408 INFO L264 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 11:01:50,409 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:50,429 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:50,429 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:50,429 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 27 [2019-12-07 11:01:50,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211122330] [2019-12-07 11:01:50,430 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-12-07 11:01:50,430 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:50,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 11:01:50,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=201, Invalid=611, Unknown=0, NotChecked=0, Total=812 [2019-12-07 11:01:50,430 INFO L87 Difference]: Start difference. First operand 74 states and 151 transitions. Second operand 29 states. [2019-12-07 11:01:50,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:50,850 INFO L93 Difference]: Finished difference Result 83 states and 168 transitions. [2019-12-07 11:01:50,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 11:01:50,850 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 32 [2019-12-07 11:01:50,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:50,851 INFO L225 Difference]: With dead ends: 83 [2019-12-07 11:01:50,851 INFO L226 Difference]: Without dead ends: 77 [2019-12-07 11:01:50,852 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=925, Invalid=1937, Unknown=0, NotChecked=0, Total=2862 [2019-12-07 11:01:50,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2019-12-07 11:01:50,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 76. [2019-12-07 11:01:50,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2019-12-07 11:01:50,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 155 transitions. [2019-12-07 11:01:50,853 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 155 transitions. Word has length 32 [2019-12-07 11:01:50,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:50,853 INFO L462 AbstractCegarLoop]: Abstraction has 76 states and 155 transitions. [2019-12-07 11:01:50,854 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-12-07 11:01:50,854 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 155 transitions. [2019-12-07 11:01:50,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 11:01:50,854 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:50,854 INFO L410 BasicCegarLoop]: trace histogram [14, 12, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:51,054 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:51,055 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:51,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:51,055 INFO L82 PathProgramCache]: Analyzing trace with hash 187347006, now seen corresponding path program 29 times [2019-12-07 11:01:51,056 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:51,056 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414843090] [2019-12-07 11:01:51,056 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:51,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:51,329 INFO L134 CoverageAnalysis]: Checked inductivity of 157 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:51,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414843090] [2019-12-07 11:01:51,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [192280585] [2019-12-07 11:01:51,330 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:51,376 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2019-12-07 11:01:51,376 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:51,377 INFO L264 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 11:01:51,377 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:51,403 INFO L134 CoverageAnalysis]: Checked inductivity of 157 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:51,404 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:51,404 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 27 [2019-12-07 11:01:51,404 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523993239] [2019-12-07 11:01:51,404 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-12-07 11:01:51,404 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:51,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 11:01:51,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=610, Unknown=0, NotChecked=0, Total=812 [2019-12-07 11:01:51,405 INFO L87 Difference]: Start difference. First operand 76 states and 155 transitions. Second operand 29 states. [2019-12-07 11:01:51,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:51,820 INFO L93 Difference]: Finished difference Result 81 states and 164 transitions. [2019-12-07 11:01:51,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 11:01:51,820 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 33 [2019-12-07 11:01:51,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:51,821 INFO L225 Difference]: With dead ends: 81 [2019-12-07 11:01:51,821 INFO L226 Difference]: Without dead ends: 77 [2019-12-07 11:01:51,822 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 454 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=898, Invalid=1858, Unknown=0, NotChecked=0, Total=2756 [2019-12-07 11:01:51,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2019-12-07 11:01:51,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 47. [2019-12-07 11:01:51,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2019-12-07 11:01:51,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 96 transitions. [2019-12-07 11:01:51,823 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 96 transitions. Word has length 33 [2019-12-07 11:01:51,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:51,823 INFO L462 AbstractCegarLoop]: Abstraction has 47 states and 96 transitions. [2019-12-07 11:01:51,823 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-12-07 11:01:51,823 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 96 transitions. [2019-12-07 11:01:51,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 11:01:51,824 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:51,824 INFO L410 BasicCegarLoop]: trace histogram [13, 13, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:52,024 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:52,025 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:52,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:52,025 INFO L82 PathProgramCache]: Analyzing trace with hash 187347254, now seen corresponding path program 30 times [2019-12-07 11:01:52,026 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:52,026 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952676049] [2019-12-07 11:01:52,026 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:52,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:52,275 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:52,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952676049] [2019-12-07 11:01:52,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872712449] [2019-12-07 11:01:52,275 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:52,320 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2019-12-07 11:01:52,320 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:52,321 INFO L264 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 11:01:52,321 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:52,346 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:52,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:52,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 28 [2019-12-07 11:01:52,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78848716] [2019-12-07 11:01:52,346 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2019-12-07 11:01:52,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:52,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 11:01:52,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=215, Invalid=655, Unknown=0, NotChecked=0, Total=870 [2019-12-07 11:01:52,347 INFO L87 Difference]: Start difference. First operand 47 states and 96 transitions. Second operand 30 states. [2019-12-07 11:01:52,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:52,778 INFO L93 Difference]: Finished difference Result 85 states and 172 transitions. [2019-12-07 11:01:52,779 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 11:01:52,779 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 33 [2019-12-07 11:01:52,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:52,779 INFO L225 Difference]: With dead ends: 85 [2019-12-07 11:01:52,779 INFO L226 Difference]: Without dead ends: 81 [2019-12-07 11:01:52,780 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 492 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=874, Invalid=2096, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 11:01:52,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2019-12-07 11:01:52,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 78. [2019-12-07 11:01:52,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-12-07 11:01:52,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 159 transitions. [2019-12-07 11:01:52,782 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 159 transitions. Word has length 33 [2019-12-07 11:01:52,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:52,782 INFO L462 AbstractCegarLoop]: Abstraction has 78 states and 159 transitions. [2019-12-07 11:01:52,782 INFO L463 AbstractCegarLoop]: Interpolant automaton has 30 states. [2019-12-07 11:01:52,782 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 159 transitions. [2019-12-07 11:01:52,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 11:01:52,782 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:52,782 INFO L410 BasicCegarLoop]: trace histogram [14, 13, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:52,982 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:52,983 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:52,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:52,983 INFO L82 PathProgramCache]: Analyzing trace with hash -342629753, now seen corresponding path program 31 times [2019-12-07 11:01:52,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:52,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065898466] [2019-12-07 11:01:52,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:52,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:53,229 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:53,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065898466] [2019-12-07 11:01:53,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1933432468] [2019-12-07 11:01:53,230 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:53,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:53,266 INFO L264 TraceCheckSpWp]: Trace formula consists of 203 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 11:01:53,267 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:53,286 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:53,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:53,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 29 [2019-12-07 11:01:53,286 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836510352] [2019-12-07 11:01:53,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2019-12-07 11:01:53,287 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:53,287 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 11:01:53,287 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=230, Invalid=700, Unknown=0, NotChecked=0, Total=930 [2019-12-07 11:01:53,287 INFO L87 Difference]: Start difference. First operand 78 states and 159 transitions. Second operand 31 states. [2019-12-07 11:01:53,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:53,768 INFO L93 Difference]: Finished difference Result 87 states and 176 transitions. [2019-12-07 11:01:53,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 11:01:53,768 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 34 [2019-12-07 11:01:53,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:53,769 INFO L225 Difference]: With dead ends: 87 [2019-12-07 11:01:53,769 INFO L226 Difference]: Without dead ends: 81 [2019-12-07 11:01:53,770 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 616 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1066, Invalid=2240, Unknown=0, NotChecked=0, Total=3306 [2019-12-07 11:01:53,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2019-12-07 11:01:53,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 80. [2019-12-07 11:01:53,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2019-12-07 11:01:53,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 163 transitions. [2019-12-07 11:01:53,772 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 163 transitions. Word has length 34 [2019-12-07 11:01:53,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:53,772 INFO L462 AbstractCegarLoop]: Abstraction has 80 states and 163 transitions. [2019-12-07 11:01:53,772 INFO L463 AbstractCegarLoop]: Interpolant automaton has 31 states. [2019-12-07 11:01:53,772 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 163 transitions. [2019-12-07 11:01:53,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-12-07 11:01:53,772 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:53,772 INFO L410 BasicCegarLoop]: trace histogram [15, 13, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:53,972 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:53,973 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:53,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:53,974 INFO L82 PathProgramCache]: Analyzing trace with hash -347913514, now seen corresponding path program 32 times [2019-12-07 11:01:53,974 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:53,974 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105877148] [2019-12-07 11:01:53,974 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:53,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:54,241 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:54,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105877148] [2019-12-07 11:01:54,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1134661635] [2019-12-07 11:01:54,242 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:54,279 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:01:54,279 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:54,280 INFO L264 TraceCheckSpWp]: Trace formula consists of 208 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 11:01:54,281 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:54,299 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:01:54,300 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:54,300 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 29 [2019-12-07 11:01:54,300 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174094525] [2019-12-07 11:01:54,300 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2019-12-07 11:01:54,300 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:54,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 11:01:54,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=230, Invalid=700, Unknown=0, NotChecked=0, Total=930 [2019-12-07 11:01:54,301 INFO L87 Difference]: Start difference. First operand 80 states and 163 transitions. Second operand 31 states. [2019-12-07 11:01:54,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:54,787 INFO L93 Difference]: Finished difference Result 90 states and 182 transitions. [2019-12-07 11:01:54,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 11:01:54,787 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 35 [2019-12-07 11:01:54,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:54,788 INFO L225 Difference]: With dead ends: 90 [2019-12-07 11:01:54,788 INFO L226 Difference]: Without dead ends: 85 [2019-12-07 11:01:54,788 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1036, Invalid=2156, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 11:01:54,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2019-12-07 11:01:54,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 81. [2019-12-07 11:01:54,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2019-12-07 11:01:54,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 165 transitions. [2019-12-07 11:01:54,790 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 165 transitions. Word has length 35 [2019-12-07 11:01:54,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:54,790 INFO L462 AbstractCegarLoop]: Abstraction has 81 states and 165 transitions. [2019-12-07 11:01:54,790 INFO L463 AbstractCegarLoop]: Interpolant automaton has 31 states. [2019-12-07 11:01:54,791 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 165 transitions. [2019-12-07 11:01:54,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 11:01:54,791 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:54,791 INFO L410 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:54,991 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:54,992 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:54,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:54,992 INFO L82 PathProgramCache]: Analyzing trace with hash 2099590699, now seen corresponding path program 33 times [2019-12-07 11:01:54,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:54,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460583814] [2019-12-07 11:01:54,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:55,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:55,294 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:55,294 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460583814] [2019-12-07 11:01:55,294 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2138396932] [2019-12-07 11:01:55,294 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:55,343 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-12-07 11:01:55,343 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:55,344 INFO L264 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 11:01:55,345 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:55,369 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:55,369 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:55,369 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2019-12-07 11:01:55,369 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694222455] [2019-12-07 11:01:55,369 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 11:01:55,369 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:55,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 11:01:55,370 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=794, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 11:01:55,370 INFO L87 Difference]: Start difference. First operand 81 states and 165 transitions. Second operand 33 states. [2019-12-07 11:01:55,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:55,906 INFO L93 Difference]: Finished difference Result 90 states and 182 transitions. [2019-12-07 11:01:55,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 11:01:55,907 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 36 [2019-12-07 11:01:55,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:55,907 INFO L225 Difference]: With dead ends: 90 [2019-12-07 11:01:55,907 INFO L226 Difference]: Without dead ends: 82 [2019-12-07 11:01:55,909 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 614 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1186, Invalid=2474, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 11:01:55,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2019-12-07 11:01:55,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 48. [2019-12-07 11:01:55,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-12-07 11:01:55,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 98 transitions. [2019-12-07 11:01:55,911 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 98 transitions. Word has length 36 [2019-12-07 11:01:55,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:55,911 INFO L462 AbstractCegarLoop]: Abstraction has 48 states and 98 transitions. [2019-12-07 11:01:55,911 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 11:01:55,911 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 98 transitions. [2019-12-07 11:01:55,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-12-07 11:01:55,912 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:55,912 INFO L410 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:56,112 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:56,112 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:56,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:56,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1445291231, now seen corresponding path program 34 times [2019-12-07 11:01:56,113 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:56,113 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317004893] [2019-12-07 11:01:56,113 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:56,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:56,380 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:56,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317004893] [2019-12-07 11:01:56,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [576521864] [2019-12-07 11:01:56,381 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:56,418 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:01:56,419 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:56,419 INFO L264 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 11:01:56,420 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:56,440 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:56,440 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:56,440 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2019-12-07 11:01:56,440 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107880219] [2019-12-07 11:01:56,440 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 11:01:56,440 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:56,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 11:01:56,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=261, Invalid=795, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 11:01:56,441 INFO L87 Difference]: Start difference. First operand 48 states and 98 transitions. Second operand 33 states. [2019-12-07 11:01:56,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:56,989 INFO L93 Difference]: Finished difference Result 89 states and 180 transitions. [2019-12-07 11:01:56,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 11:01:56,990 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 36 [2019-12-07 11:01:56,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:56,990 INFO L225 Difference]: With dead ends: 89 [2019-12-07 11:01:56,990 INFO L226 Difference]: Without dead ends: 83 [2019-12-07 11:01:56,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 707 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1217, Invalid=2565, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 11:01:56,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2019-12-07 11:01:56,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 51. [2019-12-07 11:01:56,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2019-12-07 11:01:56,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 104 transitions. [2019-12-07 11:01:56,992 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 104 transitions. Word has length 36 [2019-12-07 11:01:56,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:56,992 INFO L462 AbstractCegarLoop]: Abstraction has 51 states and 104 transitions. [2019-12-07 11:01:56,992 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 11:01:56,993 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 104 transitions. [2019-12-07 11:01:56,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-12-07 11:01:56,993 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:56,993 INFO L410 BasicCegarLoop]: trace histogram [15, 15, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:57,193 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:57,194 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:57,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:57,194 INFO L82 PathProgramCache]: Analyzing trace with hash 662802534, now seen corresponding path program 35 times [2019-12-07 11:01:57,195 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:57,195 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839978429] [2019-12-07 11:01:57,195 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:57,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:57,487 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:57,488 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839978429] [2019-12-07 11:01:57,488 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [819038949] [2019-12-07 11:01:57,488 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:57,535 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 15 check-sat command(s) [2019-12-07 11:01:57,535 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:57,536 INFO L264 TraceCheckSpWp]: Trace formula consists of 218 conjuncts, 36 conjunts are in the unsatisfiable core [2019-12-07 11:01:57,537 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:57,567 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:57,567 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:57,567 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 32 [2019-12-07 11:01:57,567 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92441336] [2019-12-07 11:01:57,568 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2019-12-07 11:01:57,568 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:57,568 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-12-07 11:01:57,568 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=277, Invalid=845, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 11:01:57,568 INFO L87 Difference]: Start difference. First operand 51 states and 104 transitions. Second operand 34 states. [2019-12-07 11:01:58,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:58,155 INFO L93 Difference]: Finished difference Result 91 states and 184 transitions. [2019-12-07 11:01:58,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 11:01:58,155 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 37 [2019-12-07 11:01:58,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:58,155 INFO L225 Difference]: With dead ends: 91 [2019-12-07 11:01:58,156 INFO L226 Difference]: Without dead ends: 85 [2019-12-07 11:01:58,156 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1297, Invalid=2735, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 11:01:58,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2019-12-07 11:01:58,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 50. [2019-12-07 11:01:58,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-12-07 11:01:58,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 102 transitions. [2019-12-07 11:01:58,157 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 102 transitions. Word has length 37 [2019-12-07 11:01:58,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:58,158 INFO L462 AbstractCegarLoop]: Abstraction has 50 states and 102 transitions. [2019-12-07 11:01:58,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 34 states. [2019-12-07 11:01:58,158 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 102 transitions. [2019-12-07 11:01:58,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-12-07 11:01:58,158 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:58,158 INFO L410 BasicCegarLoop]: trace histogram [16, 15, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:58,358 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:58,359 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:58,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:58,360 INFO L82 PathProgramCache]: Analyzing trace with hash 1650438455, now seen corresponding path program 36 times [2019-12-07 11:01:58,360 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:58,360 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861913620] [2019-12-07 11:01:58,361 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:58,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:58,706 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:58,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861913620] [2019-12-07 11:01:58,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [51923553] [2019-12-07 11:01:58,706 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:58,760 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2019-12-07 11:01:58,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:01:58,762 INFO L264 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 11:01:58,762 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:58,783 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:58,783 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:58,783 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 33 [2019-12-07 11:01:58,784 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417583272] [2019-12-07 11:01:58,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2019-12-07 11:01:58,784 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:58,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-12-07 11:01:58,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=294, Invalid=896, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 11:01:58,784 INFO L87 Difference]: Start difference. First operand 50 states and 102 transitions. Second operand 35 states. [2019-12-07 11:01:59,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:01:59,359 INFO L93 Difference]: Finished difference Result 94 states and 190 transitions. [2019-12-07 11:01:59,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 11:01:59,359 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 38 [2019-12-07 11:01:59,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:01:59,360 INFO L225 Difference]: With dead ends: 94 [2019-12-07 11:01:59,360 INFO L226 Difference]: Without dead ends: 90 [2019-12-07 11:01:59,360 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 779 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1272, Invalid=3018, Unknown=0, NotChecked=0, Total=4290 [2019-12-07 11:01:59,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2019-12-07 11:01:59,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 88. [2019-12-07 11:01:59,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2019-12-07 11:01:59,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 179 transitions. [2019-12-07 11:01:59,362 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 179 transitions. Word has length 38 [2019-12-07 11:01:59,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:01:59,363 INFO L462 AbstractCegarLoop]: Abstraction has 88 states and 179 transitions. [2019-12-07 11:01:59,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 35 states. [2019-12-07 11:01:59,363 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 179 transitions. [2019-12-07 11:01:59,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 11:01:59,363 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:01:59,363 INFO L410 BasicCegarLoop]: trace histogram [16, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:01:59,564 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:59,564 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:01:59,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:01:59,565 INFO L82 PathProgramCache]: Analyzing trace with hash 1298077438, now seen corresponding path program 37 times [2019-12-07 11:01:59,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:01:59,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139037554] [2019-12-07 11:01:59,566 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:01:59,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:59,911 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:59,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139037554] [2019-12-07 11:01:59,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1717675178] [2019-12-07 11:01:59,911 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:01:59,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:01:59,952 INFO L264 TraceCheckSpWp]: Trace formula consists of 228 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 11:01:59,953 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:01:59,977 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:01:59,977 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:01:59,977 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2019-12-07 11:01:59,978 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795564224] [2019-12-07 11:01:59,978 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-12-07 11:01:59,978 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:01:59,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-12-07 11:01:59,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=949, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 11:01:59,978 INFO L87 Difference]: Start difference. First operand 88 states and 179 transitions. Second operand 36 states. [2019-12-07 11:02:00,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:00,631 INFO L93 Difference]: Finished difference Result 97 states and 196 transitions. [2019-12-07 11:02:00,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 11:02:00,632 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 39 [2019-12-07 11:02:00,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:00,632 INFO L225 Difference]: With dead ends: 97 [2019-12-07 11:02:00,632 INFO L226 Difference]: Without dead ends: 93 [2019-12-07 11:02:00,632 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 780 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1463, Invalid=3093, Unknown=0, NotChecked=0, Total=4556 [2019-12-07 11:02:00,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-12-07 11:02:00,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 54. [2019-12-07 11:02:00,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-12-07 11:02:00,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 110 transitions. [2019-12-07 11:02:00,634 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 110 transitions. Word has length 39 [2019-12-07 11:02:00,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:00,634 INFO L462 AbstractCegarLoop]: Abstraction has 54 states and 110 transitions. [2019-12-07 11:02:00,634 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-12-07 11:02:00,634 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 110 transitions. [2019-12-07 11:02:00,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 11:02:00,635 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:00,635 INFO L410 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:00,835 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:00,835 INFO L410 AbstractCegarLoop]: === Iteration 40 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:00,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:00,836 INFO L82 PathProgramCache]: Analyzing trace with hash 1228424855, now seen corresponding path program 38 times [2019-12-07 11:02:00,836 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:00,836 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457883292] [2019-12-07 11:02:00,837 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:00,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:01,166 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:02:01,166 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457883292] [2019-12-07 11:02:01,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [647985994] [2019-12-07 11:02:01,167 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:01,206 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:02:01,207 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:01,208 INFO L264 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 11:02:01,208 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:01,229 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:02:01,229 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:01,229 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2019-12-07 11:02:01,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043906098] [2019-12-07 11:02:01,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2019-12-07 11:02:01,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:01,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-12-07 11:02:01,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=948, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 11:02:01,230 INFO L87 Difference]: Start difference. First operand 54 states and 110 transitions. Second operand 36 states. [2019-12-07 11:02:01,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:01,835 INFO L93 Difference]: Finished difference Result 97 states and 196 transitions. [2019-12-07 11:02:01,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 11:02:01,836 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 40 [2019-12-07 11:02:01,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:01,836 INFO L225 Difference]: With dead ends: 97 [2019-12-07 11:02:01,836 INFO L226 Difference]: Without dead ends: 93 [2019-12-07 11:02:01,837 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 857 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1493, Invalid=3063, Unknown=0, NotChecked=0, Total=4556 [2019-12-07 11:02:01,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-12-07 11:02:01,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 90. [2019-12-07 11:02:01,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2019-12-07 11:02:01,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 183 transitions. [2019-12-07 11:02:01,839 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 183 transitions. Word has length 40 [2019-12-07 11:02:01,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:01,839 INFO L462 AbstractCegarLoop]: Abstraction has 90 states and 183 transitions. [2019-12-07 11:02:01,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 36 states. [2019-12-07 11:02:01,839 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 183 transitions. [2019-12-07 11:02:01,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 11:02:01,840 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:01,840 INFO L410 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:02,040 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:02,041 INFO L410 AbstractCegarLoop]: === Iteration 41 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:02,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:02,041 INFO L82 PathProgramCache]: Analyzing trace with hash 1228425103, now seen corresponding path program 39 times [2019-12-07 11:02:02,042 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:02,042 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137318338] [2019-12-07 11:02:02,042 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:02,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:02,400 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:02,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137318338] [2019-12-07 11:02:02,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1459607865] [2019-12-07 11:02:02,401 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:02,454 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2019-12-07 11:02:02,454 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:02,455 INFO L264 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 40 conjunts are in the unsatisfiable core [2019-12-07 11:02:02,456 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:02,479 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:02,479 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:02,479 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 35 [2019-12-07 11:02:02,479 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025926796] [2019-12-07 11:02:02,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-12-07 11:02:02,479 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:02,479 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 11:02:02,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1003, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 11:02:02,480 INFO L87 Difference]: Start difference. First operand 90 states and 183 transitions. Second operand 37 states. [2019-12-07 11:02:03,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:03,090 INFO L93 Difference]: Finished difference Result 99 states and 200 transitions. [2019-12-07 11:02:03,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 11:02:03,091 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 40 [2019-12-07 11:02:03,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:03,091 INFO L225 Difference]: With dead ends: 99 [2019-12-07 11:02:03,091 INFO L226 Difference]: Without dead ends: 93 [2019-12-07 11:02:03,092 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 880 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1428, Invalid=3402, Unknown=0, NotChecked=0, Total=4830 [2019-12-07 11:02:03,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2019-12-07 11:02:03,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 92. [2019-12-07 11:02:03,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2019-12-07 11:02:03,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 187 transitions. [2019-12-07 11:02:03,094 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 187 transitions. Word has length 40 [2019-12-07 11:02:03,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:03,094 INFO L462 AbstractCegarLoop]: Abstraction has 92 states and 187 transitions. [2019-12-07 11:02:03,094 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-12-07 11:02:03,094 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 187 transitions. [2019-12-07 11:02:03,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 11:02:03,094 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:03,094 INFO L410 BasicCegarLoop]: trace histogram [18, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:03,295 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:03,295 INFO L410 AbstractCegarLoop]: === Iteration 42 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:03,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:03,295 INFO L82 PathProgramCache]: Analyzing trace with hash 1911903902, now seen corresponding path program 40 times [2019-12-07 11:02:03,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:03,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291303833] [2019-12-07 11:02:03,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:03,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:03,635 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:02:03,635 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291303833] [2019-12-07 11:02:03,635 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [994302358] [2019-12-07 11:02:03,635 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:03,676 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 11:02:03,676 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:03,677 INFO L264 TraceCheckSpWp]: Trace formula consists of 238 conjuncts, 39 conjunts are in the unsatisfiable core [2019-12-07 11:02:03,678 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:03,701 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 11:02:03,701 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:03,701 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 35 [2019-12-07 11:02:03,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158653617] [2019-12-07 11:02:03,701 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-12-07 11:02:03,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:03,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 11:02:03,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=329, Invalid=1003, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 11:02:03,702 INFO L87 Difference]: Start difference. First operand 92 states and 187 transitions. Second operand 37 states. [2019-12-07 11:02:04,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:04,357 INFO L93 Difference]: Finished difference Result 102 states and 206 transitions. [2019-12-07 11:02:04,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 11:02:04,358 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 41 [2019-12-07 11:02:04,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:04,358 INFO L225 Difference]: With dead ends: 102 [2019-12-07 11:02:04,358 INFO L226 Difference]: Without dead ends: 97 [2019-12-07 11:02:04,359 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 798 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1513, Invalid=3179, Unknown=0, NotChecked=0, Total=4692 [2019-12-07 11:02:04,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2019-12-07 11:02:04,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 93. [2019-12-07 11:02:04,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-12-07 11:02:04,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 189 transitions. [2019-12-07 11:02:04,361 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 189 transitions. Word has length 41 [2019-12-07 11:02:04,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:04,361 INFO L462 AbstractCegarLoop]: Abstraction has 93 states and 189 transitions. [2019-12-07 11:02:04,361 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-12-07 11:02:04,361 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 189 transitions. [2019-12-07 11:02:04,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 11:02:04,361 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:04,361 INFO L410 BasicCegarLoop]: trace histogram [18, 17, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:04,562 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:04,562 INFO L410 AbstractCegarLoop]: === Iteration 43 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:04,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:04,563 INFO L82 PathProgramCache]: Analyzing trace with hash -860513437, now seen corresponding path program 41 times [2019-12-07 11:02:04,563 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:04,564 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286598537] [2019-12-07 11:02:04,564 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:04,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:04,956 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:04,956 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286598537] [2019-12-07 11:02:04,956 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2029423590] [2019-12-07 11:02:04,956 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:05,005 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2019-12-07 11:02:05,005 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:05,006 INFO L264 TraceCheckSpWp]: Trace formula consists of 243 conjuncts, 41 conjunts are in the unsatisfiable core [2019-12-07 11:02:05,006 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:05,029 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:05,029 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:05,029 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 37 [2019-12-07 11:02:05,029 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835457250] [2019-12-07 11:02:05,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-12-07 11:02:05,030 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:05,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-12-07 11:02:05,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=366, Invalid=1116, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 11:02:05,030 INFO L87 Difference]: Start difference. First operand 93 states and 189 transitions. Second operand 39 states. [2019-12-07 11:02:05,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:05,795 INFO L93 Difference]: Finished difference Result 106 states and 214 transitions. [2019-12-07 11:02:05,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 11:02:05,795 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 42 [2019-12-07 11:02:05,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:05,796 INFO L225 Difference]: With dead ends: 106 [2019-12-07 11:02:05,796 INFO L226 Difference]: Without dead ends: 97 [2019-12-07 11:02:05,796 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 899 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1692, Invalid=3564, Unknown=0, NotChecked=0, Total=5256 [2019-12-07 11:02:05,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2019-12-07 11:02:05,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 57. [2019-12-07 11:02:05,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2019-12-07 11:02:05,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 116 transitions. [2019-12-07 11:02:05,798 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 116 transitions. Word has length 42 [2019-12-07 11:02:05,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:05,798 INFO L462 AbstractCegarLoop]: Abstraction has 57 states and 116 transitions. [2019-12-07 11:02:05,798 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-12-07 11:02:05,798 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 116 transitions. [2019-12-07 11:02:05,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-12-07 11:02:05,799 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:05,799 INFO L410 BasicCegarLoop]: trace histogram [18, 18, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:05,999 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:05,999 INFO L410 AbstractCegarLoop]: === Iteration 44 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:06,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:06,000 INFO L82 PathProgramCache]: Analyzing trace with hash -1404021454, now seen corresponding path program 42 times [2019-12-07 11:02:06,000 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:06,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544133668] [2019-12-07 11:02:06,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:06,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:06,401 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:06,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544133668] [2019-12-07 11:02:06,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1422724491] [2019-12-07 11:02:06,401 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:06,457 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 18 check-sat command(s) [2019-12-07 11:02:06,457 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:06,458 INFO L264 TraceCheckSpWp]: Trace formula consists of 248 conjuncts, 42 conjunts are in the unsatisfiable core [2019-12-07 11:02:06,459 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:06,481 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:06,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:06,482 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 38 [2019-12-07 11:02:06,482 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489184618] [2019-12-07 11:02:06,482 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-12-07 11:02:06,482 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:06,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 11:02:06,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=385, Invalid=1175, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 11:02:06,483 INFO L87 Difference]: Start difference. First operand 57 states and 116 transitions. Second operand 40 states. [2019-12-07 11:02:07,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:07,224 INFO L93 Difference]: Finished difference Result 112 states and 226 transitions. [2019-12-07 11:02:07,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 11:02:07,224 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 43 [2019-12-07 11:02:07,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:07,225 INFO L225 Difference]: With dead ends: 112 [2019-12-07 11:02:07,225 INFO L226 Difference]: Without dead ends: 103 [2019-12-07 11:02:07,226 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1075 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1858, Invalid=3842, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 11:02:07,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2019-12-07 11:02:07,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 60. [2019-12-07 11:02:07,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-12-07 11:02:07,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 122 transitions. [2019-12-07 11:02:07,227 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 122 transitions. Word has length 43 [2019-12-07 11:02:07,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:07,227 INFO L462 AbstractCegarLoop]: Abstraction has 60 states and 122 transitions. [2019-12-07 11:02:07,227 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-12-07 11:02:07,227 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 122 transitions. [2019-12-07 11:02:07,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 11:02:07,228 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:07,228 INFO L410 BasicCegarLoop]: trace histogram [19, 18, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:07,428 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:07,429 INFO L410 AbstractCegarLoop]: === Iteration 45 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:07,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:07,429 INFO L82 PathProgramCache]: Analyzing trace with hash 1975284683, now seen corresponding path program 43 times [2019-12-07 11:02:07,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:07,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598405461] [2019-12-07 11:02:07,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:07,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:07,860 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:07,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598405461] [2019-12-07 11:02:07,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [852678202] [2019-12-07 11:02:07,861 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:07,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:07,901 INFO L264 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 43 conjunts are in the unsatisfiable core [2019-12-07 11:02:07,902 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:07,925 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:07,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:07,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 39 [2019-12-07 11:02:07,926 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546091263] [2019-12-07 11:02:07,926 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2019-12-07 11:02:07,926 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:07,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 11:02:07,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=1234, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 11:02:07,927 INFO L87 Difference]: Start difference. First operand 60 states and 122 transitions. Second operand 41 states. [2019-12-07 11:02:08,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:08,707 INFO L93 Difference]: Finished difference Result 109 states and 220 transitions. [2019-12-07 11:02:08,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 11:02:08,708 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 44 [2019-12-07 11:02:08,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:08,708 INFO L225 Difference]: With dead ends: 109 [2019-12-07 11:02:08,708 INFO L226 Difference]: Without dead ends: 101 [2019-12-07 11:02:08,709 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1006 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1882, Invalid=3970, Unknown=0, NotChecked=0, Total=5852 [2019-12-07 11:02:08,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2019-12-07 11:02:08,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 99. [2019-12-07 11:02:08,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2019-12-07 11:02:08,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 201 transitions. [2019-12-07 11:02:08,710 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 201 transitions. Word has length 44 [2019-12-07 11:02:08,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:08,711 INFO L462 AbstractCegarLoop]: Abstraction has 99 states and 201 transitions. [2019-12-07 11:02:08,711 INFO L463 AbstractCegarLoop]: Interpolant automaton has 41 states. [2019-12-07 11:02:08,711 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 201 transitions. [2019-12-07 11:02:08,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-12-07 11:02:08,711 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:08,711 INFO L410 BasicCegarLoop]: trace histogram [19, 19, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:08,911 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:08,912 INFO L410 AbstractCegarLoop]: === Iteration 46 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:08,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:08,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1104283334, now seen corresponding path program 44 times [2019-12-07 11:02:08,913 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:08,913 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180982180] [2019-12-07 11:02:08,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:08,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:09,352 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:09,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180982180] [2019-12-07 11:02:09,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [329725125] [2019-12-07 11:02:09,352 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:09,393 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 11:02:09,393 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:09,394 INFO L264 TraceCheckSpWp]: Trace formula consists of 258 conjuncts, 44 conjunts are in the unsatisfiable core [2019-12-07 11:02:09,395 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:09,419 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:09,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:09,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 40 [2019-12-07 11:02:09,419 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408967990] [2019-12-07 11:02:09,419 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2019-12-07 11:02:09,419 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:09,419 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2019-12-07 11:02:09,420 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=425, Invalid=1297, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 11:02:09,420 INFO L87 Difference]: Start difference. First operand 99 states and 201 transitions. Second operand 42 states. [2019-12-07 11:02:10,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:10,245 INFO L93 Difference]: Finished difference Result 108 states and 218 transitions. [2019-12-07 11:02:10,245 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 11:02:10,246 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 45 [2019-12-07 11:02:10,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:10,246 INFO L225 Difference]: With dead ends: 108 [2019-12-07 11:02:10,246 INFO L226 Difference]: Without dead ends: 99 [2019-12-07 11:02:10,247 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1098 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2021, Invalid=4299, Unknown=0, NotChecked=0, Total=6320 [2019-12-07 11:02:10,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2019-12-07 11:02:10,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 58. [2019-12-07 11:02:10,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2019-12-07 11:02:10,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 118 transitions. [2019-12-07 11:02:10,248 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 118 transitions. Word has length 45 [2019-12-07 11:02:10,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:10,248 INFO L462 AbstractCegarLoop]: Abstraction has 58 states and 118 transitions. [2019-12-07 11:02:10,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 42 states. [2019-12-07 11:02:10,248 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 118 transitions. [2019-12-07 11:02:10,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 11:02:10,248 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:10,248 INFO L410 BasicCegarLoop]: trace histogram [20, 19, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:10,449 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:10,449 INFO L410 AbstractCegarLoop]: === Iteration 47 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:10,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:10,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1483654807, now seen corresponding path program 45 times [2019-12-07 11:02:10,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:10,450 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349106518] [2019-12-07 11:02:10,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:10,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:02:10,904 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:10,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349106518] [2019-12-07 11:02:10,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1095639726] [2019-12-07 11:02:10,904 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:10,964 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2019-12-07 11:02:10,964 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 11:02:10,965 INFO L264 TraceCheckSpWp]: Trace formula consists of 263 conjuncts, 46 conjunts are in the unsatisfiable core [2019-12-07 11:02:10,966 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:02:10,991 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:02:10,991 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:02:10,991 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 41 [2019-12-07 11:02:10,991 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061558937] [2019-12-07 11:02:10,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2019-12-07 11:02:10,991 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:02:10,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-12-07 11:02:10,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=446, Invalid=1360, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 11:02:10,992 INFO L87 Difference]: Start difference. First operand 58 states and 118 transitions. Second operand 43 states. [2019-12-07 11:02:11,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:02:11,839 INFO L93 Difference]: Finished difference Result 110 states and 222 transitions. [2019-12-07 11:02:11,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-12-07 11:02:11,839 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 46 [2019-12-07 11:02:11,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:02:11,840 INFO L225 Difference]: With dead ends: 110 [2019-12-07 11:02:11,840 INFO L226 Difference]: Without dead ends: 106 [2019-12-07 11:02:11,840 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1219 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1950, Invalid=4692, Unknown=0, NotChecked=0, Total=6642 [2019-12-07 11:02:11,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2019-12-07 11:02:11,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 104. [2019-12-07 11:02:11,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2019-12-07 11:02:11,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 211 transitions. [2019-12-07 11:02:11,842 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 211 transitions. Word has length 46 [2019-12-07 11:02:11,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:02:11,843 INFO L462 AbstractCegarLoop]: Abstraction has 104 states and 211 transitions. [2019-12-07 11:02:11,843 INFO L463 AbstractCegarLoop]: Interpolant automaton has 43 states. [2019-12-07 11:02:11,843 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 211 transitions. [2019-12-07 11:02:11,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-12-07 11:02:11,843 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:02:11,843 INFO L410 BasicCegarLoop]: trace histogram [20, 20, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:02:12,043 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:02:12,044 INFO L410 AbstractCegarLoop]: === Iteration 48 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:02:12,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:02:12,045 INFO L82 PathProgramCache]: Analyzing trace with hash 359363934, now seen corresponding path program 46 times [2019-12-07 11:02:12,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:02:12,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497951571] [2019-12-07 11:02:12,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:02:12,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:02:12,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:02:12,116 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 11:02:12,116 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 11:02:12,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [187] [187] ULTIMATE.startENTRY-->L694: Formula: (let ((.cse0 (store |v_#valid_39| 0 0))) (let ((.cse1 (store .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20| 1))) (and (= 0 |v_#NULL.base_4|) (= v_ULTIMATE.start_main_~argv.base_8 |v_ULTIMATE.start_main_#in~argv.base_9|) (= 0 |v_ULTIMATE.start_main_~#id1~0.offset_16|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| |v_ULTIMATE.start_#in~argv.offset_5|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20|) |v_ULTIMATE.start_main_~#id1~0.offset_16| 0)) |v_#memory_int_11|) (= |v_ULTIMATE.start_#in~argv.base_5| |v_ULTIMATE.start_main_#in~argv.base_9|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| v_ULTIMATE.start_main_~argv.offset_8) (= v_~i~0_33 3) (= 0 |v_ULTIMATE.start_main_~#id2~0.offset_16|) (< 0 |v_#StackHeapBarrier_11|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20|)) (= (store (store |v_#length_15| |v_ULTIMATE.start_main_~#id1~0.base_20| 4) |v_ULTIMATE.start_main_~#id2~0.base_20| 4) |v_#length_14|) (= |v_#NULL.offset_4| 0) (= v_~j~0_37 6) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id1~0.base_20|) (= v_ULTIMATE.start_main_~argc_7 |v_ULTIMATE.start_main_#in~argc_9|) (= (select .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20|) 0) (= (store .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20| 1) |v_#valid_37|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id2~0.base_20|) (= |v_ULTIMATE.start_#in~argc_5| |v_ULTIMATE.start_main_#in~argc_9|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_12|, #length=|v_#length_15|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|} OutVars{ULTIMATE.start_main_~argv.offset=v_ULTIMATE.start_main_~argv.offset_8, ~j~0=v_~j~0_37, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_7|, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_18|, ULTIMATE.start_main_~#id1~0.base=|v_ULTIMATE.start_main_~#id1~0.base_20|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_main_~argv.base=v_ULTIMATE.start_main_~argv.base_8, ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_20|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_16|, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_22, ULTIMATE.start_main_~argc=v_ULTIMATE.start_main_~argc_7, #length=|v_#length_14|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|, ULTIMATE.start_main_#in~argv.base=|v_ULTIMATE.start_main_#in~argv.base_9|, ULTIMATE.start_main_#in~argv.offset=|v_ULTIMATE.start_main_#in~argv.offset_9|, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_22, ~i~0=v_~i~0_33, #NULL.base=|v_#NULL.base_4|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_37|, ULTIMATE.start_main_#in~argc=|v_ULTIMATE.start_main_#in~argc_9|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#id1~0.offset=|v_ULTIMATE.start_main_~#id1~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#in~argv.base, ULTIMATE.start_main_~argv.offset, ~j~0, ULTIMATE.start_main_#in~argv.offset, ULTIMATE.start_main_#t~nondet4, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5, ~i~0, ULTIMATE.start_main_~#id1~0.base, #NULL.offset, #NULL.base, ULTIMATE.start_main_~argv.base, ULTIMATE.start_main_~#id2~0.base, ULTIMATE.start_main_~#id2~0.offset, ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#in~argc, #memory_int, ULTIMATE.start_main_~argc, #length, ULTIMATE.start_main_~#id1~0.offset] because there is no mapped edge [2019-12-07 11:02:12,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [153] [153] L694-1-->L695-1: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6|) |v_ULTIMATE.start_main_~#id2~0.offset_6| 1))) InVars {ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, #memory_int=|v_#memory_int_6|} OutVars{ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_3|, #memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4, #memory_int] because there is no mapped edge [2019-12-07 11:02:12,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [155] [155] t1ENTRY-->L677-6: Formula: (and (= v_t1Thread1of1ForFork1_~arg.offset_2 |v_t1Thread1of1ForFork1_#in~arg.offset_4|) (= v_t1Thread1of1ForFork1_~k~0_10 0) (= v_t1Thread1of1ForFork1_~arg.base_2 |v_t1Thread1of1ForFork1_#in~arg.base_4|)) InVars {t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} OutVars{t1Thread1of1ForFork1_~arg.base=v_t1Thread1of1ForFork1_~arg.base_2, t1Thread1of1ForFork1_~arg.offset=v_t1Thread1of1ForFork1_~arg.offset_2, t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_10, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} AuxVars[] AssignedVars[t1Thread1of1ForFork1_~arg.base, t1Thread1of1ForFork1_~arg.offset, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [159] [159] t2ENTRY-->L685-6: Formula: (and (= |v_t2Thread1of1ForFork0_#in~arg.base_4| v_t2Thread1of1ForFork0_~arg.base_2) (= v_t2Thread1of1ForFork0_~arg.offset_2 |v_t2Thread1of1ForFork0_#in~arg.offset_4|) (= 0 v_t2Thread1of1ForFork0_~k~1_10)) InVars {t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} OutVars{t2Thread1of1ForFork0_~arg.offset=v_t2Thread1of1ForFork0_~arg.offset_2, t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_~arg.base=v_t2Thread1of1ForFork0_~arg.base_2, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_10, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} AuxVars[] AssignedVars[t2Thread1of1ForFork0_~arg.offset, t2Thread1of1ForFork0_~arg.base, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,122 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,123 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,124 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,125 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [181] [181] L695-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start_main_~condJ~0_15 (ite (<= 46 v_~j~0_27) 1 0)) (or (not (= v_ULTIMATE.start_main_~condI~0_15 0)) (not (= v_ULTIMATE.start_main_~condJ~0_15 0))) (= (ite (<= 46 v_~i~0_25) 1 0) v_ULTIMATE.start_main_~condI~0_15)) InVars {~j~0=v_~j~0_27, ~i~0=v_~i~0_25} OutVars{~j~0=v_~j~0_27, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_15, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_15, ~i~0=v_~i~0_25, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5] because there is no mapped edge [2019-12-07 11:02:12,135 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 11:02:12 BasicIcfg [2019-12-07 11:02:12,135 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 11:02:12,136 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 11:02:12,136 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 11:02:12,136 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 11:02:12,136 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:01:33" (3/4) ... [2019-12-07 11:02:12,138 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 11:02:12,138 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [187] [187] ULTIMATE.startENTRY-->L694: Formula: (let ((.cse0 (store |v_#valid_39| 0 0))) (let ((.cse1 (store .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20| 1))) (and (= 0 |v_#NULL.base_4|) (= v_ULTIMATE.start_main_~argv.base_8 |v_ULTIMATE.start_main_#in~argv.base_9|) (= 0 |v_ULTIMATE.start_main_~#id1~0.offset_16|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| |v_ULTIMATE.start_#in~argv.offset_5|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#id1~0.base_20|) |v_ULTIMATE.start_main_~#id1~0.offset_16| 0)) |v_#memory_int_11|) (= |v_ULTIMATE.start_#in~argv.base_5| |v_ULTIMATE.start_main_#in~argv.base_9|) (= |v_ULTIMATE.start_main_#in~argv.offset_9| v_ULTIMATE.start_main_~argv.offset_8) (= v_~i~0_33 3) (= 0 |v_ULTIMATE.start_main_~#id2~0.offset_16|) (< 0 |v_#StackHeapBarrier_11|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#id1~0.base_20|)) (= (store (store |v_#length_15| |v_ULTIMATE.start_main_~#id1~0.base_20| 4) |v_ULTIMATE.start_main_~#id2~0.base_20| 4) |v_#length_14|) (= |v_#NULL.offset_4| 0) (= v_~j~0_37 6) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id1~0.base_20|) (= v_ULTIMATE.start_main_~argc_7 |v_ULTIMATE.start_main_#in~argc_9|) (= (select .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20|) 0) (= (store .cse1 |v_ULTIMATE.start_main_~#id2~0.base_20| 1) |v_#valid_37|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#id2~0.base_20|) (= |v_ULTIMATE.start_#in~argc_5| |v_ULTIMATE.start_main_#in~argc_9|)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_12|, #length=|v_#length_15|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|} OutVars{ULTIMATE.start_main_~argv.offset=v_ULTIMATE.start_main_~argv.offset_8, ~j~0=v_~j~0_37, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_7|, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_18|, ULTIMATE.start_main_~#id1~0.base=|v_ULTIMATE.start_main_~#id1~0.base_20|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_#in~argv.offset=|v_ULTIMATE.start_#in~argv.offset_5|, ULTIMATE.start_main_~argv.base=v_ULTIMATE.start_main_~argv.base_8, ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_20|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_16|, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_22, ULTIMATE.start_main_~argc=v_ULTIMATE.start_main_~argc_7, #length=|v_#length_14|, ULTIMATE.start_#in~argc=|v_ULTIMATE.start_#in~argc_5|, ULTIMATE.start_#in~argv.base=|v_ULTIMATE.start_#in~argv.base_5|, ULTIMATE.start_main_#in~argv.base=|v_ULTIMATE.start_main_#in~argv.base_9|, ULTIMATE.start_main_#in~argv.offset=|v_ULTIMATE.start_main_#in~argv.offset_9|, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_22, ~i~0=v_~i~0_33, #NULL.base=|v_#NULL.base_4|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_37|, ULTIMATE.start_main_#in~argc=|v_ULTIMATE.start_main_#in~argc_9|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#id1~0.offset=|v_ULTIMATE.start_main_~#id1~0.offset_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#in~argv.base, ULTIMATE.start_main_~argv.offset, ~j~0, ULTIMATE.start_main_#in~argv.offset, ULTIMATE.start_main_#t~nondet4, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5, ~i~0, ULTIMATE.start_main_~#id1~0.base, #NULL.offset, #NULL.base, ULTIMATE.start_main_~argv.base, ULTIMATE.start_main_~#id2~0.base, ULTIMATE.start_main_~#id2~0.offset, ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_#res, #valid, ULTIMATE.start_main_#in~argc, #memory_int, ULTIMATE.start_main_~argc, #length, ULTIMATE.start_main_~#id1~0.offset] because there is no mapped edge [2019-12-07 11:02:12,138 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [153] [153] L694-1-->L695-1: Formula: (= |v_#memory_int_5| (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#id2~0.base_6|) |v_ULTIMATE.start_main_~#id2~0.offset_6| 1))) InVars {ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, #memory_int=|v_#memory_int_6|} OutVars{ULTIMATE.start_main_~#id2~0.base=|v_ULTIMATE.start_main_~#id2~0.base_6|, ULTIMATE.start_main_~#id2~0.offset=|v_ULTIMATE.start_main_~#id2~0.offset_6|, ULTIMATE.start_main_#t~nondet4=|v_ULTIMATE.start_main_#t~nondet4_3|, #memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4, #memory_int] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [155] [155] t1ENTRY-->L677-6: Formula: (and (= v_t1Thread1of1ForFork1_~arg.offset_2 |v_t1Thread1of1ForFork1_#in~arg.offset_4|) (= v_t1Thread1of1ForFork1_~k~0_10 0) (= v_t1Thread1of1ForFork1_~arg.base_2 |v_t1Thread1of1ForFork1_#in~arg.base_4|)) InVars {t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} OutVars{t1Thread1of1ForFork1_~arg.base=v_t1Thread1of1ForFork1_~arg.base_2, t1Thread1of1ForFork1_~arg.offset=v_t1Thread1of1ForFork1_~arg.offset_2, t1Thread1of1ForFork1_#in~arg.base=|v_t1Thread1of1ForFork1_#in~arg.base_4|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_10, t1Thread1of1ForFork1_#in~arg.offset=|v_t1Thread1of1ForFork1_#in~arg.offset_4|} AuxVars[] AssignedVars[t1Thread1of1ForFork1_~arg.base, t1Thread1of1ForFork1_~arg.offset, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [159] [159] t2ENTRY-->L685-6: Formula: (and (= |v_t2Thread1of1ForFork0_#in~arg.base_4| v_t2Thread1of1ForFork0_~arg.base_2) (= v_t2Thread1of1ForFork0_~arg.offset_2 |v_t2Thread1of1ForFork0_#in~arg.offset_4|) (= 0 v_t2Thread1of1ForFork0_~k~1_10)) InVars {t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} OutVars{t2Thread1of1ForFork0_~arg.offset=v_t2Thread1of1ForFork0_~arg.offset_2, t2Thread1of1ForFork0_#in~arg.offset=|v_t2Thread1of1ForFork0_#in~arg.offset_4|, t2Thread1of1ForFork0_~arg.base=v_t2Thread1of1ForFork0_~arg.base_2, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_10, t2Thread1of1ForFork0_#in~arg.base=|v_t2Thread1of1ForFork0_#in~arg.base_4|} AuxVars[] AssignedVars[t2Thread1of1ForFork0_~arg.offset, t2Thread1of1ForFork0_~arg.base, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,139 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,140 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,141 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,142 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,142 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [177] [177] L677-6-->L677-6: Formula: (and (= (+ v_~j~0_25 1) v_~i~0_23) (= v_t1Thread1of1ForFork1_~k~0_17 (+ v_t1Thread1of1ForFork1_~k~0_18 1)) (< v_t1Thread1of1ForFork1_~k~0_18 20)) InVars {~j~0=v_~j~0_25, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_18} OutVars{~j~0=v_~j~0_25, ~i~0=v_~i~0_23, t1Thread1of1ForFork1_#t~post2=|v_t1Thread1of1ForFork1_#t~post2_11|, t1Thread1of1ForFork1_~k~0=v_t1Thread1of1ForFork1_~k~0_17} AuxVars[] AssignedVars[~i~0, t1Thread1of1ForFork1_#t~post2, t1Thread1of1ForFork1_~k~0] because there is no mapped edge [2019-12-07 11:02:12,142 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [185] [185] L685-6-->L685-6: Formula: (and (= v_~j~0_35 (+ v_~i~0_31 1)) (= (+ v_t2Thread1of1ForFork0_~k~1_32 1) v_t2Thread1of1ForFork0_~k~1_31) (< v_t2Thread1of1ForFork0_~k~1_32 20)) InVars {~i~0=v_~i~0_31, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_32} OutVars{~j~0=v_~j~0_35, ~i~0=v_~i~0_31, t2Thread1of1ForFork0_#t~post3=|v_t2Thread1of1ForFork0_#t~post3_10|, t2Thread1of1ForFork0_~k~1=v_t2Thread1of1ForFork0_~k~1_31} AuxVars[] AssignedVars[~j~0, t2Thread1of1ForFork0_#t~post3, t2Thread1of1ForFork0_~k~1] because there is no mapped edge [2019-12-07 11:02:12,142 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [181] [181] L695-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start_main_~condJ~0_15 (ite (<= 46 v_~j~0_27) 1 0)) (or (not (= v_ULTIMATE.start_main_~condI~0_15 0)) (not (= v_ULTIMATE.start_main_~condJ~0_15 0))) (= (ite (<= 46 v_~i~0_25) 1 0) v_ULTIMATE.start_main_~condI~0_15)) InVars {~j~0=v_~j~0_27, ~i~0=v_~i~0_25} OutVars{~j~0=v_~j~0_27, ULTIMATE.start_main_~condJ~0=v_ULTIMATE.start_main_~condJ~0_15, ULTIMATE.start_main_~condI~0=v_ULTIMATE.start_main_~condI~0_15, ~i~0=v_~i~0_25, ULTIMATE.start_main_#t~nondet5=|v_ULTIMATE.start_main_#t~nondet5_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_~condJ~0, ULTIMATE.start_main_~condI~0, ULTIMATE.start_main_#t~nondet5] because there is no mapped edge [2019-12-07 11:02:12,165 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_6d48706c-3c04-4b26-8cd1-d3f348bf7bee/bin/uautomizer/witness.graphml [2019-12-07 11:02:12,166 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 11:02:12,167 INFO L168 Benchmark]: Toolchain (without parser) took 39810.18 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 296.7 MB). Free memory was 940.9 MB in the beginning and 924.7 MB in the end (delta: 16.2 MB). Peak memory consumption was 313.0 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,167 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:02:12,167 INFO L168 Benchmark]: CACSL2BoogieTranslator took 401.53 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 940.9 MB in the beginning and 1.1 GB in the end (delta: -123.4 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,168 INFO L168 Benchmark]: Boogie Procedure Inliner took 29.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,168 INFO L168 Benchmark]: Boogie Preprocessor took 18.20 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:02:12,168 INFO L168 Benchmark]: RCFGBuilder took 225.82 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 23.5 MB). Peak memory consumption was 23.5 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,168 INFO L168 Benchmark]: TraceAbstraction took 39102.08 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 205.5 MB). Free memory was 1.0 GB in the beginning and 928.0 MB in the end (delta: 102.1 MB). Peak memory consumption was 307.6 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,169 INFO L168 Benchmark]: Witness Printer took 29.93 ms. Allocated memory is still 1.3 GB. Free memory was 928.0 MB in the beginning and 924.7 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2019-12-07 11:02:12,170 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 401.53 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 940.9 MB in the beginning and 1.1 GB in the end (delta: -123.4 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 29.57 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 18.20 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 225.82 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 23.5 MB). Peak memory consumption was 23.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 39102.08 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 205.5 MB). Free memory was 1.0 GB in the beginning and 928.0 MB in the end (delta: 102.1 MB). Peak memory consumption was 307.6 MB. Max. memory is 11.5 GB. * Witness Printer took 29.93 ms. Allocated memory is still 1.3 GB. Free memory was 928.0 MB in the beginning and 924.7 MB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 0.7s, 53 ProgramPointsBefore, 16 ProgramPointsAfterwards, 51 TransitionsBefore, 14 TransitionsAfterwards, 740 CoEnabledTransitionPairs, 6 FixpointIterations, 12 TrivialSequentialCompositions, 21 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 8 ConcurrentYvCompositions, 3 ChoiceCompositions, 380 VarBasedMoverChecksPositive, 7 VarBasedMoverChecksNegative, 0 SemBasedMoverChecksPositive, 9 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.0s, 0 MoverChecksTotal, 604 CheckedPairsTotal, 41 TotalNumberOfCompositions - CounterExampleResult [Line: 703]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L694] FCALL, FORK 0 pthread_create(&id1, ((void *)0), t1, ((void *)0)) VAL [arg={0:0}, i=3, j=6] [L695] FCALL, FORK 0 pthread_create(&id2, ((void *)0), t2, ((void *)0)) VAL [arg={0:0}, arg={0:0}, i=3, j=6] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 47 locations, 1 error locations. Result: UNSAFE, OverallTime: 39.0s, OverallIterations: 48, TraceHistogramMax: 20, AutomataDifference: 16.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 522 SDtfs, 1653 SDslu, 2393 SDs, 0 SdLazy, 3297 SolverSat, 3335 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3027 GetRequests, 1129 SyntacticMatches, 0 SemanticMatches, 1898 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18478 ImplicationChecksByTransitivity, 21.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=104occurred in iteration=47, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 47 MinimizatonAttempts, 634 StatesRemovedByMinimization, 44 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 1.3s SatisfiabilityAnalysisTime, 10.2s InterpolantComputationTime, 2507 NumberOfCodeBlocks, 2507 NumberOfCodeBlocksAsserted, 320 NumberOfCheckSat, 2370 ConstructedInterpolants, 0 QuantifiedInterpolants, 231448 SizeOfPredicates, 864 NumberOfNonLiveVariables, 7494 ConjunctsInSsa, 1172 ConjunctsInUnsatCore, 90 InterpolantComputations, 4 PerfectInterpolantSequences, 14/11102 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...