./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NO_13.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NO_13.c -s /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c0d0ad10124da460587cca853afd7fd9944c9aa2 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:13:39,089 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:13:39,090 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:13:39,098 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:13:39,098 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:13:39,098 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:13:39,099 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:13:39,101 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:13:39,102 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:13:39,103 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:13:39,103 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:13:39,104 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:13:39,104 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:13:39,105 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:13:39,106 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:13:39,106 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:13:39,107 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:13:39,108 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:13:39,109 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:13:39,110 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:13:39,112 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:13:39,112 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:13:39,113 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:13:39,113 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:13:39,115 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:13:39,115 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:13:39,115 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:13:39,116 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:13:39,116 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:13:39,117 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:13:39,117 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:13:39,117 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:13:39,118 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:13:39,118 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:13:39,119 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:13:39,119 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:13:39,119 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:13:39,119 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:13:39,119 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:13:39,120 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:13:39,120 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:13:39,121 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/config/svcomp-Termination-64bit-Automizer_Default.epf [2019-12-07 12:13:39,132 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:13:39,132 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:13:39,133 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 12:13:39,133 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 12:13:39,133 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 12:13:39,133 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 12:13:39,134 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 12:13:39,134 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:13:39,135 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 12:13:39,136 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:13:39,136 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 12:13:39,136 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 12:13:39,136 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:13:39,136 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 12:13:39,136 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:13:39,136 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 12:13:39,137 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 12:13:39,137 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c0d0ad10124da460587cca853afd7fd9944c9aa2 [2019-12-07 12:13:39,233 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:13:39,241 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:13:39,243 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:13:39,244 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:13:39,245 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:13:39,245 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/../../sv-benchmarks/c/termination-restricted-15/NO_13.c [2019-12-07 12:13:39,282 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/data/ccd89d13e/39040ad3df2041b8aa6f62f40fde6fd3/FLAG5c5af84bf [2019-12-07 12:13:39,605 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:13:39,605 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/sv-benchmarks/c/termination-restricted-15/NO_13.c [2019-12-07 12:13:39,608 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/data/ccd89d13e/39040ad3df2041b8aa6f62f40fde6fd3/FLAG5c5af84bf [2019-12-07 12:13:39,617 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/data/ccd89d13e/39040ad3df2041b8aa6f62f40fde6fd3 [2019-12-07 12:13:39,619 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:13:39,620 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:13:39,620 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:13:39,621 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:13:39,623 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:13:39,623 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,625 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3d1f8437 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39, skipping insertion in model container [2019-12-07 12:13:39,625 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,630 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:13:39,639 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:13:39,733 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:13:39,737 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:13:39,781 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:13:39,791 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:13:39,791 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39 WrapperNode [2019-12-07 12:13:39,791 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:13:39,792 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:13:39,792 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:13:39,792 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:13:39,798 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,802 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,814 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:13:39,814 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:13:39,814 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:13:39,814 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:13:39,820 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,820 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,821 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,821 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,822 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,825 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,825 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... [2019-12-07 12:13:39,826 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:13:39,826 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:13:39,826 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:13:39,826 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:13:39,827 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:39,866 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:13:39,866 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:13:39,946 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:13:39,946 INFO L287 CfgBuilder]: Removed 5 assume(true) statements. [2019-12-07 12:13:39,947 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:13:39 BoogieIcfgContainer [2019-12-07 12:13:39,947 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:13:39,947 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 12:13:39,947 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 12:13:39,949 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 12:13:39,950 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:13:39,950 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:13:39" (1/3) ... [2019-12-07 12:13:39,950 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d910434 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:13:39, skipping insertion in model container [2019-12-07 12:13:39,950 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:13:39,951 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:13:39" (2/3) ... [2019-12-07 12:13:39,951 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d910434 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:13:39, skipping insertion in model container [2019-12-07 12:13:39,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:13:39,951 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:13:39" (3/3) ... [2019-12-07 12:13:39,952 INFO L371 chiAutomizerObserver]: Analyzing ICFG NO_13.c [2019-12-07 12:13:39,980 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 12:13:39,981 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 12:13:39,981 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 12:13:39,981 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:13:39,981 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:13:39,981 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 12:13:39,981 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:13:39,981 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 12:13:39,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states. [2019-12-07 12:13:40,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:40,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:40,006 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1] [2019-12-07 12:13:40,006 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 12:13:40,006 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 12:13:40,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states. [2019-12-07 12:13:40,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:40,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:40,007 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1] [2019-12-07 12:13:40,007 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 12:13:40,012 INFO L794 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3#L12-2true [2019-12-07 12:13:40,012 INFO L796 eck$LassoCheckResult]: Loop: 3#L12-2true assume !!(main_~i~0 < main_~j~0); 6#L12true assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3#L12-2true [2019-12-07 12:13:40,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,016 INFO L82 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2019-12-07 12:13:40,021 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,021 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314461262] [2019-12-07 12:13:40,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,083 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:40,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,084 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 1 times [2019-12-07 12:13:40,084 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,084 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206685323] [2019-12-07 12:13:40,084 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,095 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:40,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,096 INFO L82 PathProgramCache]: Analyzing trace with hash 31075, now seen corresponding path program 1 times [2019-12-07 12:13:40,097 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,097 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088172889] [2019-12-07 12:13:40,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,106 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:40,140 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,141 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,141 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,141 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,141 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 12:13:40,141 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,141 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,141 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,142 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration1_Loop [2019-12-07 12:13:40,142 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,142 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,156 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,163 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,167 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,242 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,242 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,247 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,247 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,254 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 12:13:40,254 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,258 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,259 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,262 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 12:13:40,262 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,266 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,266 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,275 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 12:13:40,275 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,286 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 12:13:40,287 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,287 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,287 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,288 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,288 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 12:13:40,288 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,288 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,288 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,288 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration1_Loop [2019-12-07 12:13:40,288 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,288 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,290 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,294 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,344 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,347 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,351 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,353 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,354 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,354 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,354 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,358 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 12:13:40,358 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 12:13:40,362 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,366 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,368 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,368 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,368 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,368 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,371 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 12:13:40,371 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 12:13:40,374 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,378 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,379 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,380 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 12:13:40,380 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,380 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,380 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,382 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 12:13:40,382 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 12:13:40,384 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 12:13:40,386 INFO L443 ModelExtractionUtils]: Simplification made 2 calls to the SMT solver. [2019-12-07 12:13:40,386 INFO L444 ModelExtractionUtils]: 2 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,390 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 12:13:40,390 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 12:13:40,390 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 12:13:40,391 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2019-12-07 12:13:40,394 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 12:13:40,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,415 INFO L264 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,416 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,422 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,423 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,435 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 12:13:40,436 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states. Second operand 3 states. [2019-12-07 12:13:40,463 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states.. Second operand 3 states. Result 23 states and 30 transitions. Complement of second has 6 states. [2019-12-07 12:13:40,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:40,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:40,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2019-12-07 12:13:40,465 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 2 letters. [2019-12-07 12:13:40,466 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,466 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 3 letters. Loop has 2 letters. [2019-12-07 12:13:40,466 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,466 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 1 letters. Loop has 4 letters. [2019-12-07 12:13:40,466 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 30 transitions. [2019-12-07 12:13:40,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 7 states and 10 transitions. [2019-12-07 12:13:40,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2019-12-07 12:13:40,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2019-12-07 12:13:40,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 10 transitions. [2019-12-07 12:13:40,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:40,472 INFO L688 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 12:13:40,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 10 transitions. [2019-12-07 12:13:40,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2019-12-07 12:13:40,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7 states. [2019-12-07 12:13:40,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 10 transitions. [2019-12-07 12:13:40,489 INFO L711 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 12:13:40,489 INFO L591 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 12:13:40,489 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 12:13:40,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 10 transitions. [2019-12-07 12:13:40,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:40,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:40,490 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1] [2019-12-07 12:13:40,490 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 12:13:40,490 INFO L794 eck$LassoCheckResult]: Stem: 68#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 69#L12-2 assume !!(main_~i~0 < main_~j~0); 67#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 63#L12-2 [2019-12-07 12:13:40,490 INFO L796 eck$LassoCheckResult]: Loop: 63#L12-2 assume !!(main_~i~0 < main_~j~0); 64#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 63#L12-2 [2019-12-07 12:13:40,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,490 INFO L82 PathProgramCache]: Analyzing trace with hash 31077, now seen corresponding path program 1 times [2019-12-07 12:13:40,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128221780] [2019-12-07 12:13:40,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,517 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128221780] [2019-12-07 12:13:40,517 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:13:40,517 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 12:13:40,518 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996590633] [2019-12-07 12:13:40,520 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:13:40,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,520 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 2 times [2019-12-07 12:13:40,521 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,521 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682114426] [2019-12-07 12:13:40,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,526 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:40,539 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,539 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,539 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,540 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,540 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 12:13:40,540 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,540 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,540 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,540 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration2_Loop [2019-12-07 12:13:40,540 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,540 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,541 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,546 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,587 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,588 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,590 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,590 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,594 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 12:13:40,594 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,598 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,598 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,601 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 12:13:40,602 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,605 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,605 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,612 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 12:13:40,612 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,620 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 12:13:40,621 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,621 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,621 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,621 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,621 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 12:13:40,621 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,621 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,621 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,621 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration2_Loop [2019-12-07 12:13:40,622 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,622 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,625 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,633 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,670 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,670 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,673 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,674 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,675 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,675 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,675 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,678 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 12:13:40,678 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 12:13:40,681 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,686 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,687 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,687 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 12:13:40,687 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,687 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,688 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,689 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 12:13:40,689 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 12:13:40,692 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 12:13:40,696 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 12:13:40,696 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,704 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 12:13:40,704 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 12:13:40,704 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 12:13:40,704 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2019-12-07 12:13:40,705 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 12:13:40,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,719 INFO L264 TraceCheckSpWp]: Trace formula consists of 12 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,719 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,722 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,722 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,723 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 12:13:40,723 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5 Second operand 3 states. [2019-12-07 12:13:40,732 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5. Second operand 3 states. Result 11 states and 16 transitions. Complement of second has 5 states. [2019-12-07 12:13:40,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:40,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:40,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2019-12-07 12:13:40,733 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 2 letters. [2019-12-07 12:13:40,733 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,733 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 5 letters. Loop has 2 letters. [2019-12-07 12:13:40,734 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,734 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 3 letters. Loop has 4 letters. [2019-12-07 12:13:40,734 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 16 transitions. [2019-12-07 12:13:40,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 16 transitions. [2019-12-07 12:13:40,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 12:13:40,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2019-12-07 12:13:40,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 16 transitions. [2019-12-07 12:13:40,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:40,736 INFO L688 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2019-12-07 12:13:40,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 16 transitions. [2019-12-07 12:13:40,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-12-07 12:13:40,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-12-07 12:13:40,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 16 transitions. [2019-12-07 12:13:40,738 INFO L711 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2019-12-07 12:13:40,738 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:40,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:13:40,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:13:40,742 INFO L87 Difference]: Start difference. First operand 11 states and 16 transitions. Second operand 3 states. [2019-12-07 12:13:40,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:40,753 INFO L93 Difference]: Finished difference Result 13 states and 17 transitions. [2019-12-07 12:13:40,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:13:40,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 17 transitions. [2019-12-07 12:13:40,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 16 transitions. [2019-12-07 12:13:40,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2019-12-07 12:13:40,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2019-12-07 12:13:40,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 16 transitions. [2019-12-07 12:13:40,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:40,755 INFO L688 BuchiCegarLoop]: Abstraction has 12 states and 16 transitions. [2019-12-07 12:13:40,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 16 transitions. [2019-12-07 12:13:40,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2019-12-07 12:13:40,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-12-07 12:13:40,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2019-12-07 12:13:40,756 INFO L711 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2019-12-07 12:13:40,757 INFO L591 BuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2019-12-07 12:13:40,757 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 12:13:40,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2019-12-07 12:13:40,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 12:13:40,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:40,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:40,758 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1, 1] [2019-12-07 12:13:40,758 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 12:13:40,758 INFO L794 eck$LassoCheckResult]: Stem: 144#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 139#L12-2 assume !!(main_~i~0 < main_~j~0); 140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 149#L12-2 assume !!(main_~i~0 < main_~j~0); 148#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 146#L12-2 assume !!(main_~i~0 < main_~j~0); 142#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 145#L12-2 [2019-12-07 12:13:40,758 INFO L796 eck$LassoCheckResult]: Loop: 145#L12-2 assume !!(main_~i~0 < main_~j~0); 147#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 145#L12-2 [2019-12-07 12:13:40,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1366043347, now seen corresponding path program 1 times [2019-12-07 12:13:40,758 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,759 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964391728] [2019-12-07 12:13:40,759 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,776 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,776 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964391728] [2019-12-07 12:13:40,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2042347993] [2019-12-07 12:13:40,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:40,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,793 INFO L264 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 3 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,794 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,803 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,803 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:40,804 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2019-12-07 12:13:40,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281765757] [2019-12-07 12:13:40,804 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:13:40,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,804 INFO L82 PathProgramCache]: Analyzing trace with hash 1284, now seen corresponding path program 3 times [2019-12-07 12:13:40,804 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:40,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879984377] [2019-12-07 12:13:40,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:40,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:40,810 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:40,825 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,826 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,826 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,826 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,826 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 12:13:40,826 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,826 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,826 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,826 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration3_Loop [2019-12-07 12:13:40,826 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,826 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,827 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,837 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,839 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,878 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,878 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,881 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:40,881 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,888 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 12:13:40,888 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:40,900 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 12:13:40,901 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:40,901 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:40,901 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:40,902 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:40,902 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 12:13:40,902 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,902 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:40,902 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:40,902 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration3_Loop [2019-12-07 12:13:40,902 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:40,902 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:40,903 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,911 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,913 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:40,950 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:40,951 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,953 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:40,954 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:40,955 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 12:13:40,955 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:40,955 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:40,955 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:40,956 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 12:13:40,956 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 12:13:40,958 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 12:13:40,961 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 12:13:40,962 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:40,964 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 12:13:40,964 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 12:13:40,964 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 12:13:40,965 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = 1*ULTIMATE.start_main_~j~0 Supporting invariants [] [2019-12-07 12:13:40,966 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 12:13:40,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:40,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,981 INFO L264 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,982 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:40,985 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:40,986 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:40,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:40,986 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 12:13:40,986 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand 3 states. [2019-12-07 12:13:40,996 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand 3 states. Result 13 states and 19 transitions. Complement of second has 5 states. [2019-12-07 12:13:40,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:40,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:40,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2019-12-07 12:13:40,997 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2019-12-07 12:13:40,997 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:40,997 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 12:13:41,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,013 INFO L264 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,013 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,017 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,017 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,018 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 12:13:41,018 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand 3 states. [2019-12-07 12:13:41,023 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand 3 states. Result 13 states and 19 transitions. Complement of second has 5 states. [2019-12-07 12:13:41,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:41,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:41,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2019-12-07 12:13:41,024 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 7 letters. Loop has 2 letters. [2019-12-07 12:13:41,025 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,025 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 12:13:41,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,040 INFO L264 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,041 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,044 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,044 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,045 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 12:13:41,045 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7 Second operand 3 states. [2019-12-07 12:13:41,054 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 7. Second operand 3 states. Result 15 states and 22 transitions. Complement of second has 4 states. [2019-12-07 12:13:41,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:41,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:41,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 7 transitions. [2019-12-07 12:13:41,055 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 2 letters. [2019-12-07 12:13:41,055 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,055 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 9 letters. Loop has 2 letters. [2019-12-07 12:13:41,055 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,056 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 7 letters. Loop has 4 letters. [2019-12-07 12:13:41,056 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 22 transitions. [2019-12-07 12:13:41,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2019-12-07 12:13:41,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 13 states and 18 transitions. [2019-12-07 12:13:41,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2019-12-07 12:13:41,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2019-12-07 12:13:41,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 18 transitions. [2019-12-07 12:13:41,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,058 INFO L688 BuchiCegarLoop]: Abstraction has 13 states and 18 transitions. [2019-12-07 12:13:41,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 18 transitions. [2019-12-07 12:13:41,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 6. [2019-12-07 12:13:41,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2019-12-07 12:13:41,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 8 transitions. [2019-12-07 12:13:41,059 INFO L711 BuchiCegarLoop]: Abstraction has 6 states and 8 transitions. [2019-12-07 12:13:41,060 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,060 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 12:13:41,060 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 12:13:41,060 INFO L87 Difference]: Start difference. First operand 6 states and 8 transitions. Second operand 4 states. [2019-12-07 12:13:41,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,070 INFO L93 Difference]: Finished difference Result 10 states and 12 transitions. [2019-12-07 12:13:41,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 12:13:41,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 12 transitions. [2019-12-07 12:13:41,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2019-12-07 12:13:41,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 9 states and 11 transitions. [2019-12-07 12:13:41,071 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4 [2019-12-07 12:13:41,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4 [2019-12-07 12:13:41,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2019-12-07 12:13:41,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,072 INFO L688 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2019-12-07 12:13:41,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2019-12-07 12:13:41,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2019-12-07 12:13:41,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2019-12-07 12:13:41,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 10 transitions. [2019-12-07 12:13:41,073 INFO L711 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2019-12-07 12:13:41,073 INFO L591 BuchiCegarLoop]: Abstraction has 8 states and 10 transitions. [2019-12-07 12:13:41,073 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 12:13:41,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 10 transitions. [2019-12-07 12:13:41,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2019-12-07 12:13:41,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,074 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [3, 2, 1] [2019-12-07 12:13:41,074 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 12:13:41,074 INFO L794 eck$LassoCheckResult]: Stem: 339#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 335#L12-2 assume !!(main_~i~0 < main_~j~0); 336#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 337#L12-2 assume !!(main_~i~0 < main_~j~0); 338#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 342#L12-2 assume !!(main_~i~0 < main_~j~0); 340#L12 [2019-12-07 12:13:41,075 INFO L796 eck$LassoCheckResult]: Loop: 340#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 341#L12-2 assume !!(main_~i~0 < main_~j~0); 340#L12 [2019-12-07 12:13:41,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,075 INFO L82 PathProgramCache]: Analyzing trace with hash 925765348, now seen corresponding path program 2 times [2019-12-07 12:13:41,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573867834] [2019-12-07 12:13:41,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,086 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1436, now seen corresponding path program 1 times [2019-12-07 12:13:41,087 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,087 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205356700] [2019-12-07 12:13:41,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,093 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,093 INFO L82 PathProgramCache]: Analyzing trace with hash 602269631, now seen corresponding path program 2 times [2019-12-07 12:13:41,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146790551] [2019-12-07 12:13:41,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,116 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,117 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146790551] [2019-12-07 12:13:41,117 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1466532328] [2019-12-07 12:13:41,117 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,141 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:41,141 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:41,141 INFO L264 TraceCheckSpWp]: Trace formula consists of 25 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,142 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,145 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,145 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,145 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2019-12-07 12:13:41,145 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444500216] [2019-12-07 12:13:41,156 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:41,156 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:41,156 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:41,156 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:41,156 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 12:13:41,156 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,157 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:41,157 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:41,157 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration4_Loop [2019-12-07 12:13:41,157 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:41,157 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:41,158 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,160 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,165 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,197 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:41,197 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,200 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:41,200 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:41,204 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 12:13:41,204 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_7=1} Honda state: {v_rep~unnamed0~0~true_7=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,208 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 12:13:41,208 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,214 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 12:13:41,214 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 12:13:41,221 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 12:13:41,222 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 12:13:41,222 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 12:13:41,222 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 12:13:41,222 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 12:13:41,223 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 12:13:41,223 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,223 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 12:13:41,223 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 12:13:41,223 INFO L133 ssoRankerPreferences]: Filename of dumped script: NO_13.c_Iteration4_Loop [2019-12-07 12:13:41,223 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 12:13:41,223 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 12:13:41,224 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,231 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,233 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 12:13:41,258 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 12:13:41,259 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,261 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 12:13:41,262 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 12:13:41,262 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 12:13:41,262 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 12:13:41,262 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 12:13:41,262 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 12:13:41,263 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 12:13:41,263 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 12:13:41,265 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 12:13:41,267 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 12:13:41,267 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:13:41,270 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 12:13:41,270 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 12:13:41,270 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 12:13:41,270 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~j~0) = -2*ULTIMATE.start_main_~j~0 + 103 Supporting invariants [] [2019-12-07 12:13:41,271 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 12:13:41,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,287 INFO L264 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,287 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,289 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,290 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,298 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 12:13:41,298 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand 3 states. [2019-12-07 12:13:41,301 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand 3 states. Result 8 states and 10 transitions. Complement of second has 3 states. [2019-12-07 12:13:41,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:41,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:41,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2019-12-07 12:13:41,302 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2019-12-07 12:13:41,302 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,302 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 12:13:41,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,312 INFO L264 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,312 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,315 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,315 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,325 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 12:13:41,325 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand 3 states. [2019-12-07 12:13:41,328 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand 3 states. Result 8 states and 10 transitions. Complement of second has 3 states. [2019-12-07 12:13:41,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:41,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:41,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2019-12-07 12:13:41,329 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 6 letters. Loop has 2 letters. [2019-12-07 12:13:41,329 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,329 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 12:13:41,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,344 INFO L264 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,344 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,347 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,347 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:13:41,355 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 12:13:41,356 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3 Second operand 3 states. [2019-12-07 12:13:41,362 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 10 transitions. cyclomatic complexity: 3. Second operand 3 states. Result 12 states and 14 transitions. Complement of second has 4 states. [2019-12-07 12:13:41,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 12:13:41,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 12:13:41,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2019-12-07 12:13:41,363 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 2 letters. [2019-12-07 12:13:41,363 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,363 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 8 letters. Loop has 2 letters. [2019-12-07 12:13:41,363 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,363 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 6 letters. Loop has 4 letters. [2019-12-07 12:13:41,363 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 12:13:41,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 14 transitions. [2019-12-07 12:13:41,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2019-12-07 12:13:41,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 10 states and 12 transitions. [2019-12-07 12:13:41,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 12 transitions. [2019-12-07 12:13:41,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,365 INFO L688 BuchiCegarLoop]: Abstraction has 10 states and 12 transitions. [2019-12-07 12:13:41,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 12 transitions. [2019-12-07 12:13:41,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 9. [2019-12-07 12:13:41,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-12-07 12:13:41,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2019-12-07 12:13:41,366 INFO L711 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2019-12-07 12:13:41,366 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:13:41,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:13:41,367 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. Second operand 5 states. [2019-12-07 12:13:41,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,375 INFO L93 Difference]: Finished difference Result 13 states and 15 transitions. [2019-12-07 12:13:41,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 12:13:41,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 15 transitions. [2019-12-07 12:13:41,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 12 states and 14 transitions. [2019-12-07 12:13:41,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 14 transitions. [2019-12-07 12:13:41,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,376 INFO L688 BuchiCegarLoop]: Abstraction has 12 states and 14 transitions. [2019-12-07 12:13:41,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 14 transitions. [2019-12-07 12:13:41,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2019-12-07 12:13:41,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-12-07 12:13:41,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 13 transitions. [2019-12-07 12:13:41,377 INFO L711 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2019-12-07 12:13:41,377 INFO L591 BuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2019-12-07 12:13:41,377 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 12:13:41,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 13 transitions. [2019-12-07 12:13:41,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,378 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [4, 3, 1] [2019-12-07 12:13:41,378 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,378 INFO L794 eck$LassoCheckResult]: Stem: 519#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 515#L12-2 assume !!(main_~i~0 < main_~j~0); 516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 517#L12-2 assume !!(main_~i~0 < main_~j~0); 518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 525#L12-2 assume !!(main_~i~0 < main_~j~0); 524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 523#L12-2 assume !!(main_~i~0 < main_~j~0); 520#L12 [2019-12-07 12:13:41,378 INFO L796 eck$LassoCheckResult]: Loop: 520#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 521#L12-2 assume !!(main_~i~0 < main_~j~0); 524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 523#L12-2 assume !!(main_~i~0 < main_~j~0); 520#L12 [2019-12-07 12:13:41,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,378 INFO L82 PathProgramCache]: Analyzing trace with hash 602269569, now seen corresponding path program 3 times [2019-12-07 12:13:41,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844118610] [2019-12-07 12:13:41,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,389 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,389 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 1 times [2019-12-07 12:13:41,390 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,390 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492243670] [2019-12-07 12:13:41,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,395 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,395 INFO L82 PathProgramCache]: Analyzing trace with hash 1740322745, now seen corresponding path program 3 times [2019-12-07 12:13:41,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547606402] [2019-12-07 12:13:41,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,421 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547606402] [2019-12-07 12:13:41,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2007142713] [2019-12-07 12:13:41,421 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,442 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2019-12-07 12:13:41,442 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:41,442 INFO L264 TraceCheckSpWp]: Trace formula consists of 37 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,443 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,445 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-12-07 12:13:41,446 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349777773] [2019-12-07 12:13:41,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 12:13:41,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 12:13:41,472 INFO L87 Difference]: Start difference. First operand 11 states and 13 transitions. cyclomatic complexity: 3 Second operand 6 states. [2019-12-07 12:13:41,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,483 INFO L93 Difference]: Finished difference Result 15 states and 17 transitions. [2019-12-07 12:13:41,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:13:41,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 17 transitions. [2019-12-07 12:13:41,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 14 states and 16 transitions. [2019-12-07 12:13:41,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2019-12-07 12:13:41,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,485 INFO L688 BuchiCegarLoop]: Abstraction has 14 states and 16 transitions. [2019-12-07 12:13:41,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2019-12-07 12:13:41,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2019-12-07 12:13:41,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-12-07 12:13:41,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2019-12-07 12:13:41,487 INFO L711 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2019-12-07 12:13:41,487 INFO L591 BuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2019-12-07 12:13:41,487 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 12:13:41,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2019-12-07 12:13:41,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,488 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [5, 4, 1] [2019-12-07 12:13:41,488 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,488 INFO L794 eck$LassoCheckResult]: Stem: 589#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 585#L12-2 assume !!(main_~i~0 < main_~j~0); 586#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 587#L12-2 assume !!(main_~i~0 < main_~j~0); 588#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 597#L12-2 assume !!(main_~i~0 < main_~j~0); 596#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 595#L12-2 assume !!(main_~i~0 < main_~j~0); 594#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 593#L12-2 assume !!(main_~i~0 < main_~j~0); 590#L12 [2019-12-07 12:13:41,488 INFO L796 eck$LassoCheckResult]: Loop: 590#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 591#L12-2 assume !!(main_~i~0 < main_~j~0); 594#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 593#L12-2 assume !!(main_~i~0 < main_~j~0); 590#L12 [2019-12-07 12:13:41,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,489 INFO L82 PathProgramCache]: Analyzing trace with hash -1039528738, now seen corresponding path program 4 times [2019-12-07 12:13:41,489 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,489 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269359984] [2019-12-07 12:13:41,489 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,501 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,501 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 2 times [2019-12-07 12:13:41,501 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,501 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350395943] [2019-12-07 12:13:41,502 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,507 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1650681494, now seen corresponding path program 4 times [2019-12-07 12:13:41,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544420240] [2019-12-07 12:13:41,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,540 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,541 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544420240] [2019-12-07 12:13:41,541 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1243073214] [2019-12-07 12:13:41,541 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,559 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:41,559 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:41,559 INFO L264 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,560 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,563 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 15 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,563 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,563 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2019-12-07 12:13:41,563 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310360080] [2019-12-07 12:13:41,587 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 12:13:41,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2019-12-07 12:13:41,587 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 3 Second operand 7 states. [2019-12-07 12:13:41,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,600 INFO L93 Difference]: Finished difference Result 17 states and 19 transitions. [2019-12-07 12:13:41,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:13:41,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 19 transitions. [2019-12-07 12:13:41,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 16 states and 18 transitions. [2019-12-07 12:13:41,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 18 transitions. [2019-12-07 12:13:41,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,602 INFO L688 BuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2019-12-07 12:13:41,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 18 transitions. [2019-12-07 12:13:41,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-12-07 12:13:41,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-12-07 12:13:41,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 17 transitions. [2019-12-07 12:13:41,604 INFO L711 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2019-12-07 12:13:41,604 INFO L591 BuchiCegarLoop]: Abstraction has 15 states and 17 transitions. [2019-12-07 12:13:41,604 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 12:13:41,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 17 transitions. [2019-12-07 12:13:41,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,605 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 1] [2019-12-07 12:13:41,605 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,605 INFO L794 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 666#L12-2 assume !!(main_~i~0 < main_~j~0); 667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 668#L12-2 assume !!(main_~i~0 < main_~j~0); 669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 680#L12-2 assume !!(main_~i~0 < main_~j~0); 679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 678#L12-2 assume !!(main_~i~0 < main_~j~0); 676#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 675#L12-2 assume !!(main_~i~0 < main_~j~0); 674#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 673#L12-2 assume !!(main_~i~0 < main_~j~0); 671#L12 [2019-12-07 12:13:41,605 INFO L796 eck$LassoCheckResult]: Loop: 671#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 672#L12-2 assume !!(main_~i~0 < main_~j~0); 674#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 673#L12-2 assume !!(main_~i~0 < main_~j~0); 671#L12 [2019-12-07 12:13:41,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,605 INFO L82 PathProgramCache]: Analyzing trace with hash 1740263163, now seen corresponding path program 5 times [2019-12-07 12:13:41,605 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905511134] [2019-12-07 12:13:41,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,618 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,618 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 3 times [2019-12-07 12:13:41,618 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,618 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415465703] [2019-12-07 12:13:41,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,624 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,624 INFO L82 PathProgramCache]: Analyzing trace with hash 1404785203, now seen corresponding path program 5 times [2019-12-07 12:13:41,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756611647] [2019-12-07 12:13:41,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,657 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,657 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756611647] [2019-12-07 12:13:41,657 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2049372382] [2019-12-07 12:13:41,657 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,677 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2019-12-07 12:13:41,678 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:41,678 INFO L264 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 7 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,679 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,683 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 30 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,683 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,683 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-12-07 12:13:41,684 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519800904] [2019-12-07 12:13:41,710 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 12:13:41,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2019-12-07 12:13:41,710 INFO L87 Difference]: Start difference. First operand 15 states and 17 transitions. cyclomatic complexity: 3 Second operand 8 states. [2019-12-07 12:13:41,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,724 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2019-12-07 12:13:41,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 12:13:41,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2019-12-07 12:13:41,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 18 states and 20 transitions. [2019-12-07 12:13:41,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 20 transitions. [2019-12-07 12:13:41,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,726 INFO L688 BuchiCegarLoop]: Abstraction has 18 states and 20 transitions. [2019-12-07 12:13:41,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 20 transitions. [2019-12-07 12:13:41,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 17. [2019-12-07 12:13:41,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-12-07 12:13:41,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 19 transitions. [2019-12-07 12:13:41,727 INFO L711 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2019-12-07 12:13:41,727 INFO L591 BuchiCegarLoop]: Abstraction has 17 states and 19 transitions. [2019-12-07 12:13:41,727 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 12:13:41,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 19 transitions. [2019-12-07 12:13:41,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,728 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [7, 6, 1] [2019-12-07 12:13:41,728 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,728 INFO L794 eck$LassoCheckResult]: Stem: 762#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 758#L12-2 assume !!(main_~i~0 < main_~j~0); 759#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 760#L12-2 assume !!(main_~i~0 < main_~j~0); 761#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 765#L12-2 assume !!(main_~i~0 < main_~j~0); 774#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 773#L12-2 assume !!(main_~i~0 < main_~j~0); 772#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 771#L12-2 assume !!(main_~i~0 < main_~j~0); 769#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 768#L12-2 assume !!(main_~i~0 < main_~j~0); 767#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 766#L12-2 assume !!(main_~i~0 < main_~j~0); 763#L12 [2019-12-07 12:13:41,728 INFO L796 eck$LassoCheckResult]: Loop: 763#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 764#L12-2 assume !!(main_~i~0 < main_~j~0); 767#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 766#L12-2 assume !!(main_~i~0 < main_~j~0); 763#L12 [2019-12-07 12:13:41,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,728 INFO L82 PathProgramCache]: Analyzing trace with hash 1650621912, now seen corresponding path program 6 times [2019-12-07 12:13:41,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832966618] [2019-12-07 12:13:41,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,737 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 4 times [2019-12-07 12:13:41,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366829506] [2019-12-07 12:13:41,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,741 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,741 INFO L82 PathProgramCache]: Analyzing trace with hash 1321650832, now seen corresponding path program 6 times [2019-12-07 12:13:41,741 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,741 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455917769] [2019-12-07 12:13:41,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,777 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455917769] [2019-12-07 12:13:41,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1050506380] [2019-12-07 12:13:41,777 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,796 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2019-12-07 12:13:41,796 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:41,796 INFO L264 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,797 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,800 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 21 proven. 42 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,800 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2019-12-07 12:13:41,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354804880] [2019-12-07 12:13:41,825 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 12:13:41,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2019-12-07 12:13:41,826 INFO L87 Difference]: Start difference. First operand 17 states and 19 transitions. cyclomatic complexity: 3 Second operand 9 states. [2019-12-07 12:13:41,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,842 INFO L93 Difference]: Finished difference Result 21 states and 23 transitions. [2019-12-07 12:13:41,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 12:13:41,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 23 transitions. [2019-12-07 12:13:41,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 20 states and 22 transitions. [2019-12-07 12:13:41,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 22 transitions. [2019-12-07 12:13:41,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,844 INFO L688 BuchiCegarLoop]: Abstraction has 20 states and 22 transitions. [2019-12-07 12:13:41,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 22 transitions. [2019-12-07 12:13:41,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 19. [2019-12-07 12:13:41,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-12-07 12:13:41,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2019-12-07 12:13:41,845 INFO L711 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2019-12-07 12:13:41,845 INFO L591 BuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2019-12-07 12:13:41,845 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 12:13:41,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2019-12-07 12:13:41,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,846 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 1] [2019-12-07 12:13:41,846 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,846 INFO L794 eck$LassoCheckResult]: Stem: 865#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 861#L12-2 assume !!(main_~i~0 < main_~j~0); 862#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 863#L12-2 assume !!(main_~i~0 < main_~j~0); 864#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 868#L12-2 assume !!(main_~i~0 < main_~j~0); 879#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 878#L12-2 assume !!(main_~i~0 < main_~j~0); 877#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 876#L12-2 assume !!(main_~i~0 < main_~j~0); 875#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 874#L12-2 assume !!(main_~i~0 < main_~j~0); 872#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 871#L12-2 assume !!(main_~i~0 < main_~j~0); 870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 869#L12-2 assume !!(main_~i~0 < main_~j~0); 866#L12 [2019-12-07 12:13:41,846 INFO L796 eck$LassoCheckResult]: Loop: 866#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 867#L12-2 assume !!(main_~i~0 < main_~j~0); 870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 869#L12-2 assume !!(main_~i~0 < main_~j~0); 866#L12 [2019-12-07 12:13:41,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1404725621, now seen corresponding path program 7 times [2019-12-07 12:13:41,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140189612] [2019-12-07 12:13:41,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,855 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 5 times [2019-12-07 12:13:41,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677570296] [2019-12-07 12:13:41,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,858 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,859 INFO L82 PathProgramCache]: Analyzing trace with hash -1261068371, now seen corresponding path program 7 times [2019-12-07 12:13:41,859 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624914810] [2019-12-07 12:13:41,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,902 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,902 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624914810] [2019-12-07 12:13:41,902 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1067935897] [2019-12-07 12:13:41,902 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:41,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:41,920 INFO L264 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 12:13:41,920 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:41,924 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 24 proven. 56 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:41,924 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:41,924 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2019-12-07 12:13:41,925 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428972615] [2019-12-07 12:13:41,948 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:41,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 12:13:41,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2019-12-07 12:13:41,948 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 3 Second operand 10 states. [2019-12-07 12:13:41,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:41,966 INFO L93 Difference]: Finished difference Result 23 states and 25 transitions. [2019-12-07 12:13:41,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 12:13:41,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 25 transitions. [2019-12-07 12:13:41,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 22 states and 24 transitions. [2019-12-07 12:13:41,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:41,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:41,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 24 transitions. [2019-12-07 12:13:41,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:41,968 INFO L688 BuchiCegarLoop]: Abstraction has 22 states and 24 transitions. [2019-12-07 12:13:41,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 24 transitions. [2019-12-07 12:13:41,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2019-12-07 12:13:41,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-12-07 12:13:41,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 23 transitions. [2019-12-07 12:13:41,969 INFO L711 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2019-12-07 12:13:41,969 INFO L591 BuchiCegarLoop]: Abstraction has 21 states and 23 transitions. [2019-12-07 12:13:41,970 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 12:13:41,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 23 transitions. [2019-12-07 12:13:41,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:41,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:41,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:41,971 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [9, 8, 1] [2019-12-07 12:13:41,971 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:41,971 INFO L794 eck$LassoCheckResult]: Stem: 979#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 975#L12-2 assume !!(main_~i~0 < main_~j~0); 976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 977#L12-2 assume !!(main_~i~0 < main_~j~0); 978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 982#L12-2 assume !!(main_~i~0 < main_~j~0); 995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 994#L12-2 assume !!(main_~i~0 < main_~j~0); 993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 992#L12-2 assume !!(main_~i~0 < main_~j~0); 991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 990#L12-2 assume !!(main_~i~0 < main_~j~0); 989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 988#L12-2 assume !!(main_~i~0 < main_~j~0); 986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 985#L12-2 assume !!(main_~i~0 < main_~j~0); 984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 983#L12-2 assume !!(main_~i~0 < main_~j~0); 980#L12 [2019-12-07 12:13:41,971 INFO L796 eck$LassoCheckResult]: Loop: 980#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 981#L12-2 assume !!(main_~i~0 < main_~j~0); 984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 983#L12-2 assume !!(main_~i~0 < main_~j~0); 980#L12 [2019-12-07 12:13:41,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,971 INFO L82 PathProgramCache]: Analyzing trace with hash 1321591250, now seen corresponding path program 8 times [2019-12-07 12:13:41,971 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,972 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919692571] [2019-12-07 12:13:41,972 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,983 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,983 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 6 times [2019-12-07 12:13:41,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714153163] [2019-12-07 12:13:41,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:41,988 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:41,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:41,988 INFO L82 PathProgramCache]: Analyzing trace with hash -763125366, now seen corresponding path program 8 times [2019-12-07 12:13:41,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:41,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525882095] [2019-12-07 12:13:41,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:41,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,039 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525882095] [2019-12-07 12:13:42,040 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1800580786] [2019-12-07 12:13:42,040 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,058 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:42,058 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:42,059 INFO L264 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,060 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,065 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 27 proven. 72 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,065 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,065 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-12-07 12:13:42,065 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154613761] [2019-12-07 12:13:42,090 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:42,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 12:13:42,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2019-12-07 12:13:42,091 INFO L87 Difference]: Start difference. First operand 21 states and 23 transitions. cyclomatic complexity: 3 Second operand 11 states. [2019-12-07 12:13:42,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:42,109 INFO L93 Difference]: Finished difference Result 25 states and 27 transitions. [2019-12-07 12:13:42,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 12:13:42,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 27 transitions. [2019-12-07 12:13:42,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 24 states and 26 transitions. [2019-12-07 12:13:42,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:42,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:42,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 26 transitions. [2019-12-07 12:13:42,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:42,110 INFO L688 BuchiCegarLoop]: Abstraction has 24 states and 26 transitions. [2019-12-07 12:13:42,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 26 transitions. [2019-12-07 12:13:42,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 23. [2019-12-07 12:13:42,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2019-12-07 12:13:42,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 25 transitions. [2019-12-07 12:13:42,112 INFO L711 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2019-12-07 12:13:42,112 INFO L591 BuchiCegarLoop]: Abstraction has 23 states and 25 transitions. [2019-12-07 12:13:42,112 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 12:13:42,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 25 transitions. [2019-12-07 12:13:42,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:42,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:42,113 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 1] [2019-12-07 12:13:42,113 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:42,113 INFO L794 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1100#L12-2 assume !!(main_~i~0 < main_~j~0); 1101#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1102#L12-2 assume !!(main_~i~0 < main_~j~0); 1103#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1107#L12-2 assume !!(main_~i~0 < main_~j~0); 1122#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1121#L12-2 assume !!(main_~i~0 < main_~j~0); 1120#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1119#L12-2 assume !!(main_~i~0 < main_~j~0); 1118#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1117#L12-2 assume !!(main_~i~0 < main_~j~0); 1116#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1115#L12-2 assume !!(main_~i~0 < main_~j~0); 1114#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1113#L12-2 assume !!(main_~i~0 < main_~j~0); 1111#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1110#L12-2 assume !!(main_~i~0 < main_~j~0); 1109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1108#L12-2 assume !!(main_~i~0 < main_~j~0); 1105#L12 [2019-12-07 12:13:42,113 INFO L796 eck$LassoCheckResult]: Loop: 1105#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1106#L12-2 assume !!(main_~i~0 < main_~j~0); 1109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1108#L12-2 assume !!(main_~i~0 < main_~j~0); 1105#L12 [2019-12-07 12:13:42,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,113 INFO L82 PathProgramCache]: Analyzing trace with hash -1261127953, now seen corresponding path program 9 times [2019-12-07 12:13:42,113 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,113 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131619770] [2019-12-07 12:13:42,113 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,120 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,121 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 7 times [2019-12-07 12:13:42,121 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,121 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822945822] [2019-12-07 12:13:42,121 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,124 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,124 INFO L82 PathProgramCache]: Analyzing trace with hash 1018732583, now seen corresponding path program 9 times [2019-12-07 12:13:42,124 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,124 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152538663] [2019-12-07 12:13:42,124 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,184 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152538663] [2019-12-07 12:13:42,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [602366571] [2019-12-07 12:13:42,184 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,211 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-12-07 12:13:42,211 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:42,212 INFO L264 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,213 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,217 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 30 proven. 90 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,217 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,217 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2019-12-07 12:13:42,217 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73079545] [2019-12-07 12:13:42,242 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:42,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 12:13:42,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2019-12-07 12:13:42,242 INFO L87 Difference]: Start difference. First operand 23 states and 25 transitions. cyclomatic complexity: 3 Second operand 12 states. [2019-12-07 12:13:42,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:42,264 INFO L93 Difference]: Finished difference Result 27 states and 29 transitions. [2019-12-07 12:13:42,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 12:13:42,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 29 transitions. [2019-12-07 12:13:42,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 26 states and 28 transitions. [2019-12-07 12:13:42,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:42,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:42,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 28 transitions. [2019-12-07 12:13:42,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:42,265 INFO L688 BuchiCegarLoop]: Abstraction has 26 states and 28 transitions. [2019-12-07 12:13:42,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 28 transitions. [2019-12-07 12:13:42,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2019-12-07 12:13:42,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-12-07 12:13:42,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 27 transitions. [2019-12-07 12:13:42,267 INFO L711 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2019-12-07 12:13:42,267 INFO L591 BuchiCegarLoop]: Abstraction has 25 states and 27 transitions. [2019-12-07 12:13:42,267 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 12:13:42,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 27 transitions. [2019-12-07 12:13:42,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:42,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:42,268 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [11, 10, 1] [2019-12-07 12:13:42,268 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:42,268 INFO L794 eck$LassoCheckResult]: Stem: 1240#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1236#L12-2 assume !!(main_~i~0 < main_~j~0); 1237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1238#L12-2 assume !!(main_~i~0 < main_~j~0); 1239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1243#L12-2 assume !!(main_~i~0 < main_~j~0); 1260#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1259#L12-2 assume !!(main_~i~0 < main_~j~0); 1258#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1257#L12-2 assume !!(main_~i~0 < main_~j~0); 1256#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1255#L12-2 assume !!(main_~i~0 < main_~j~0); 1254#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1253#L12-2 assume !!(main_~i~0 < main_~j~0); 1252#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1251#L12-2 assume !!(main_~i~0 < main_~j~0); 1250#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1249#L12-2 assume !!(main_~i~0 < main_~j~0); 1247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1246#L12-2 assume !!(main_~i~0 < main_~j~0); 1245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1244#L12-2 assume !!(main_~i~0 < main_~j~0); 1241#L12 [2019-12-07 12:13:42,268 INFO L796 eck$LassoCheckResult]: Loop: 1241#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1242#L12-2 assume !!(main_~i~0 < main_~j~0); 1245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1244#L12-2 assume !!(main_~i~0 < main_~j~0); 1241#L12 [2019-12-07 12:13:42,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,268 INFO L82 PathProgramCache]: Analyzing trace with hash -763184948, now seen corresponding path program 10 times [2019-12-07 12:13:42,268 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,268 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748554147] [2019-12-07 12:13:42,268 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,275 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,276 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 8 times [2019-12-07 12:13:42,276 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,276 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781727128] [2019-12-07 12:13:42,276 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,279 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,279 INFO L82 PathProgramCache]: Analyzing trace with hash -307729532, now seen corresponding path program 10 times [2019-12-07 12:13:42,279 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,279 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194916680] [2019-12-07 12:13:42,279 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,348 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194916680] [2019-12-07 12:13:42,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [628217856] [2019-12-07 12:13:42,348 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,372 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:42,372 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:42,372 INFO L264 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,373 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,380 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 33 proven. 110 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,380 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,380 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2019-12-07 12:13:42,381 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438472789] [2019-12-07 12:13:42,409 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:42,409 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 12:13:42,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2019-12-07 12:13:42,410 INFO L87 Difference]: Start difference. First operand 25 states and 27 transitions. cyclomatic complexity: 3 Second operand 13 states. [2019-12-07 12:13:42,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:42,438 INFO L93 Difference]: Finished difference Result 29 states and 31 transitions. [2019-12-07 12:13:42,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 12:13:42,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 31 transitions. [2019-12-07 12:13:42,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 28 states and 30 transitions. [2019-12-07 12:13:42,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:42,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:42,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 30 transitions. [2019-12-07 12:13:42,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:42,440 INFO L688 BuchiCegarLoop]: Abstraction has 28 states and 30 transitions. [2019-12-07 12:13:42,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 30 transitions. [2019-12-07 12:13:42,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2019-12-07 12:13:42,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-12-07 12:13:42,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 29 transitions. [2019-12-07 12:13:42,441 INFO L711 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2019-12-07 12:13:42,441 INFO L591 BuchiCegarLoop]: Abstraction has 27 states and 29 transitions. [2019-12-07 12:13:42,441 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 12:13:42,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 29 transitions. [2019-12-07 12:13:42,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:42,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:42,442 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 1] [2019-12-07 12:13:42,442 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:42,442 INFO L794 eck$LassoCheckResult]: Stem: 1387#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1383#L12-2 assume !!(main_~i~0 < main_~j~0); 1384#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1385#L12-2 assume !!(main_~i~0 < main_~j~0); 1386#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1390#L12-2 assume !!(main_~i~0 < main_~j~0); 1409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1408#L12-2 assume !!(main_~i~0 < main_~j~0); 1407#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1406#L12-2 assume !!(main_~i~0 < main_~j~0); 1405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1404#L12-2 assume !!(main_~i~0 < main_~j~0); 1403#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1402#L12-2 assume !!(main_~i~0 < main_~j~0); 1401#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1400#L12-2 assume !!(main_~i~0 < main_~j~0); 1399#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1398#L12-2 assume !!(main_~i~0 < main_~j~0); 1397#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1396#L12-2 assume !!(main_~i~0 < main_~j~0); 1394#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1393#L12-2 assume !!(main_~i~0 < main_~j~0); 1392#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1391#L12-2 assume !!(main_~i~0 < main_~j~0); 1388#L12 [2019-12-07 12:13:42,442 INFO L796 eck$LassoCheckResult]: Loop: 1388#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1389#L12-2 assume !!(main_~i~0 < main_~j~0); 1392#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1391#L12-2 assume !!(main_~i~0 < main_~j~0); 1388#L12 [2019-12-07 12:13:42,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,442 INFO L82 PathProgramCache]: Analyzing trace with hash 1018673001, now seen corresponding path program 11 times [2019-12-07 12:13:42,443 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,443 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802172143] [2019-12-07 12:13:42,443 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,450 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 9 times [2019-12-07 12:13:42,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,451 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606574499] [2019-12-07 12:13:42,451 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,453 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,453 INFO L82 PathProgramCache]: Analyzing trace with hash 567464865, now seen corresponding path program 11 times [2019-12-07 12:13:42,453 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295654325] [2019-12-07 12:13:42,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,530 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295654325] [2019-12-07 12:13:42,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [807929943] [2019-12-07 12:13:42,530 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,554 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2019-12-07 12:13:42,554 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:42,555 INFO L264 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,556 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,563 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 36 proven. 132 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,564 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,564 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2019-12-07 12:13:42,564 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636288155] [2019-12-07 12:13:42,592 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:42,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 12:13:42,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2019-12-07 12:13:42,592 INFO L87 Difference]: Start difference. First operand 27 states and 29 transitions. cyclomatic complexity: 3 Second operand 14 states. [2019-12-07 12:13:42,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:42,619 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2019-12-07 12:13:42,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 12:13:42,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2019-12-07 12:13:42,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 30 states and 32 transitions. [2019-12-07 12:13:42,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:42,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:42,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 32 transitions. [2019-12-07 12:13:42,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:42,621 INFO L688 BuchiCegarLoop]: Abstraction has 30 states and 32 transitions. [2019-12-07 12:13:42,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 32 transitions. [2019-12-07 12:13:42,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2019-12-07 12:13:42,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-12-07 12:13:42,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 31 transitions. [2019-12-07 12:13:42,623 INFO L711 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2019-12-07 12:13:42,623 INFO L591 BuchiCegarLoop]: Abstraction has 29 states and 31 transitions. [2019-12-07 12:13:42,623 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 12:13:42,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 31 transitions. [2019-12-07 12:13:42,623 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:42,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:42,624 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [13, 12, 1] [2019-12-07 12:13:42,624 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:42,624 INFO L794 eck$LassoCheckResult]: Stem: 1545#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1541#L12-2 assume !!(main_~i~0 < main_~j~0); 1542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1543#L12-2 assume !!(main_~i~0 < main_~j~0); 1544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1548#L12-2 assume !!(main_~i~0 < main_~j~0); 1569#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1568#L12-2 assume !!(main_~i~0 < main_~j~0); 1567#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1566#L12-2 assume !!(main_~i~0 < main_~j~0); 1565#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1564#L12-2 assume !!(main_~i~0 < main_~j~0); 1563#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1562#L12-2 assume !!(main_~i~0 < main_~j~0); 1561#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1560#L12-2 assume !!(main_~i~0 < main_~j~0); 1559#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1558#L12-2 assume !!(main_~i~0 < main_~j~0); 1557#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1556#L12-2 assume !!(main_~i~0 < main_~j~0); 1555#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1554#L12-2 assume !!(main_~i~0 < main_~j~0); 1552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1551#L12-2 assume !!(main_~i~0 < main_~j~0); 1550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1549#L12-2 assume !!(main_~i~0 < main_~j~0); 1546#L12 [2019-12-07 12:13:42,625 INFO L796 eck$LassoCheckResult]: Loop: 1546#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1547#L12-2 assume !!(main_~i~0 < main_~j~0); 1550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1549#L12-2 assume !!(main_~i~0 < main_~j~0); 1546#L12 [2019-12-07 12:13:42,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,625 INFO L82 PathProgramCache]: Analyzing trace with hash -307789114, now seen corresponding path program 12 times [2019-12-07 12:13:42,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495088416] [2019-12-07 12:13:42,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,636 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 10 times [2019-12-07 12:13:42,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,637 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678060720] [2019-12-07 12:13:42,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,640 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,640 INFO L82 PathProgramCache]: Analyzing trace with hash -184309634, now seen corresponding path program 12 times [2019-12-07 12:13:42,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157716199] [2019-12-07 12:13:42,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,732 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,732 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157716199] [2019-12-07 12:13:42,732 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [774310829] [2019-12-07 12:13:42,732 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,761 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2019-12-07 12:13:42,761 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:42,762 INFO L264 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,763 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,770 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 39 proven. 156 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,770 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,771 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2019-12-07 12:13:42,771 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080861728] [2019-12-07 12:13:42,801 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:42,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 12:13:42,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2019-12-07 12:13:42,801 INFO L87 Difference]: Start difference. First operand 29 states and 31 transitions. cyclomatic complexity: 3 Second operand 15 states. [2019-12-07 12:13:42,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:42,832 INFO L93 Difference]: Finished difference Result 33 states and 35 transitions. [2019-12-07 12:13:42,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 12:13:42,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 35 transitions. [2019-12-07 12:13:42,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 32 states and 34 transitions. [2019-12-07 12:13:42,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:42,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:42,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 34 transitions. [2019-12-07 12:13:42,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:42,834 INFO L688 BuchiCegarLoop]: Abstraction has 32 states and 34 transitions. [2019-12-07 12:13:42,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 34 transitions. [2019-12-07 12:13:42,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 31. [2019-12-07 12:13:42,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-12-07 12:13:42,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2019-12-07 12:13:42,835 INFO L711 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2019-12-07 12:13:42,835 INFO L591 BuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2019-12-07 12:13:42,835 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 12:13:42,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2019-12-07 12:13:42,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:42,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:42,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:42,836 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [14, 13, 1] [2019-12-07 12:13:42,836 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:42,837 INFO L794 eck$LassoCheckResult]: Stem: 1714#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1710#L12-2 assume !!(main_~i~0 < main_~j~0); 1711#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1712#L12-2 assume !!(main_~i~0 < main_~j~0); 1713#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1717#L12-2 assume !!(main_~i~0 < main_~j~0); 1740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1739#L12-2 assume !!(main_~i~0 < main_~j~0); 1738#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1737#L12-2 assume !!(main_~i~0 < main_~j~0); 1736#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1735#L12-2 assume !!(main_~i~0 < main_~j~0); 1734#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1733#L12-2 assume !!(main_~i~0 < main_~j~0); 1732#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1731#L12-2 assume !!(main_~i~0 < main_~j~0); 1730#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1729#L12-2 assume !!(main_~i~0 < main_~j~0); 1728#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1727#L12-2 assume !!(main_~i~0 < main_~j~0); 1726#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1725#L12-2 assume !!(main_~i~0 < main_~j~0); 1724#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1723#L12-2 assume !!(main_~i~0 < main_~j~0); 1721#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1720#L12-2 assume !!(main_~i~0 < main_~j~0); 1719#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1718#L12-2 assume !!(main_~i~0 < main_~j~0); 1715#L12 [2019-12-07 12:13:42,837 INFO L796 eck$LassoCheckResult]: Loop: 1715#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1716#L12-2 assume !!(main_~i~0 < main_~j~0); 1719#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1718#L12-2 assume !!(main_~i~0 < main_~j~0); 1715#L12 [2019-12-07 12:13:42,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,837 INFO L82 PathProgramCache]: Analyzing trace with hash 567405283, now seen corresponding path program 13 times [2019-12-07 12:13:42,837 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,837 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736493241] [2019-12-07 12:13:42,837 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,846 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 11 times [2019-12-07 12:13:42,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179286011] [2019-12-07 12:13:42,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:42,849 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:42,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:42,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1085097445, now seen corresponding path program 13 times [2019-12-07 12:13:42,850 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:42,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167626350] [2019-12-07 12:13:42,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:42,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,953 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167626350] [2019-12-07 12:13:42,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2063822245] [2019-12-07 12:13:42,954 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:42,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:42,976 INFO L264 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 12:13:42,977 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:42,982 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 42 proven. 182 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:42,982 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:42,982 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2019-12-07 12:13:42,983 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763650427] [2019-12-07 12:13:43,007 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:43,007 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 12:13:43,007 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2019-12-07 12:13:43,007 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 3 Second operand 16 states. [2019-12-07 12:13:43,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:43,037 INFO L93 Difference]: Finished difference Result 35 states and 37 transitions. [2019-12-07 12:13:43,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 12:13:43,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 37 transitions. [2019-12-07 12:13:43,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 34 states and 36 transitions. [2019-12-07 12:13:43,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:43,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:43,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 36 transitions. [2019-12-07 12:13:43,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:43,039 INFO L688 BuchiCegarLoop]: Abstraction has 34 states and 36 transitions. [2019-12-07 12:13:43,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 36 transitions. [2019-12-07 12:13:43,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2019-12-07 12:13:43,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2019-12-07 12:13:43,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2019-12-07 12:13:43,041 INFO L711 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2019-12-07 12:13:43,041 INFO L591 BuchiCegarLoop]: Abstraction has 33 states and 35 transitions. [2019-12-07 12:13:43,041 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 12:13:43,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 35 transitions. [2019-12-07 12:13:43,041 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:43,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:43,042 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [15, 14, 1] [2019-12-07 12:13:43,042 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:43,042 INFO L794 eck$LassoCheckResult]: Stem: 1894#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 1890#L12-2 assume !!(main_~i~0 < main_~j~0); 1891#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1892#L12-2 assume !!(main_~i~0 < main_~j~0); 1893#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1897#L12-2 assume !!(main_~i~0 < main_~j~0); 1922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1921#L12-2 assume !!(main_~i~0 < main_~j~0); 1920#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1919#L12-2 assume !!(main_~i~0 < main_~j~0); 1918#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1917#L12-2 assume !!(main_~i~0 < main_~j~0); 1916#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1915#L12-2 assume !!(main_~i~0 < main_~j~0); 1914#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1913#L12-2 assume !!(main_~i~0 < main_~j~0); 1912#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1911#L12-2 assume !!(main_~i~0 < main_~j~0); 1910#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1909#L12-2 assume !!(main_~i~0 < main_~j~0); 1908#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1907#L12-2 assume !!(main_~i~0 < main_~j~0); 1906#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1905#L12-2 assume !!(main_~i~0 < main_~j~0); 1904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1903#L12-2 assume !!(main_~i~0 < main_~j~0); 1901#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1900#L12-2 assume !!(main_~i~0 < main_~j~0); 1899#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1898#L12-2 assume !!(main_~i~0 < main_~j~0); 1895#L12 [2019-12-07 12:13:43,042 INFO L796 eck$LassoCheckResult]: Loop: 1895#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 1896#L12-2 assume !!(main_~i~0 < main_~j~0); 1899#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 1898#L12-2 assume !!(main_~i~0 < main_~j~0); 1895#L12 [2019-12-07 12:13:43,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,043 INFO L82 PathProgramCache]: Analyzing trace with hash -184369216, now seen corresponding path program 14 times [2019-12-07 12:13:43,043 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,043 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84605616] [2019-12-07 12:13:43,043 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,055 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,055 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 12 times [2019-12-07 12:13:43,055 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,056 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671121365] [2019-12-07 12:13:43,056 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,058 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,059 INFO L82 PathProgramCache]: Analyzing trace with hash 841209976, now seen corresponding path program 14 times [2019-12-07 12:13:43,059 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,059 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615499836] [2019-12-07 12:13:43,059 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:43,167 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615499836] [2019-12-07 12:13:43,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [628607576] [2019-12-07 12:13:43,167 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:43,187 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:43,187 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:43,188 INFO L264 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 16 conjunts are in the unsatisfiable core [2019-12-07 12:13:43,189 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:43,194 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 45 proven. 210 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:43,195 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2019-12-07 12:13:43,195 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811539065] [2019-12-07 12:13:43,219 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:43,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 12:13:43,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2019-12-07 12:13:43,219 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. cyclomatic complexity: 3 Second operand 17 states. [2019-12-07 12:13:43,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:43,261 INFO L93 Difference]: Finished difference Result 37 states and 39 transitions. [2019-12-07 12:13:43,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 12:13:43,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 39 transitions. [2019-12-07 12:13:43,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 36 states and 38 transitions. [2019-12-07 12:13:43,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:43,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:43,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 38 transitions. [2019-12-07 12:13:43,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:43,263 INFO L688 BuchiCegarLoop]: Abstraction has 36 states and 38 transitions. [2019-12-07 12:13:43,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 38 transitions. [2019-12-07 12:13:43,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2019-12-07 12:13:43,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2019-12-07 12:13:43,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 37 transitions. [2019-12-07 12:13:43,264 INFO L711 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2019-12-07 12:13:43,264 INFO L591 BuchiCegarLoop]: Abstraction has 35 states and 37 transitions. [2019-12-07 12:13:43,265 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 12:13:43,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 37 transitions. [2019-12-07 12:13:43,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:43,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:43,265 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [16, 15, 1] [2019-12-07 12:13:43,265 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:43,266 INFO L794 eck$LassoCheckResult]: Stem: 2085#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2081#L12-2 assume !!(main_~i~0 < main_~j~0); 2082#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2083#L12-2 assume !!(main_~i~0 < main_~j~0); 2084#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2088#L12-2 assume !!(main_~i~0 < main_~j~0); 2115#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2114#L12-2 assume !!(main_~i~0 < main_~j~0); 2113#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2112#L12-2 assume !!(main_~i~0 < main_~j~0); 2111#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2110#L12-2 assume !!(main_~i~0 < main_~j~0); 2109#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2108#L12-2 assume !!(main_~i~0 < main_~j~0); 2107#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2106#L12-2 assume !!(main_~i~0 < main_~j~0); 2105#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2104#L12-2 assume !!(main_~i~0 < main_~j~0); 2103#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2102#L12-2 assume !!(main_~i~0 < main_~j~0); 2101#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2100#L12-2 assume !!(main_~i~0 < main_~j~0); 2099#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2098#L12-2 assume !!(main_~i~0 < main_~j~0); 2097#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2096#L12-2 assume !!(main_~i~0 < main_~j~0); 2095#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2094#L12-2 assume !!(main_~i~0 < main_~j~0); 2092#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2091#L12-2 assume !!(main_~i~0 < main_~j~0); 2090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2089#L12-2 assume !!(main_~i~0 < main_~j~0); 2086#L12 [2019-12-07 12:13:43,266 INFO L796 eck$LassoCheckResult]: Loop: 2086#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2087#L12-2 assume !!(main_~i~0 < main_~j~0); 2090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2089#L12-2 assume !!(main_~i~0 < main_~j~0); 2086#L12 [2019-12-07 12:13:43,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,266 INFO L82 PathProgramCache]: Analyzing trace with hash -1085157027, now seen corresponding path program 15 times [2019-12-07 12:13:43,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932588942] [2019-12-07 12:13:43,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,278 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,278 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 13 times [2019-12-07 12:13:43,279 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,279 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425426655] [2019-12-07 12:13:43,279 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,282 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,283 INFO L82 PathProgramCache]: Analyzing trace with hash 891736981, now seen corresponding path program 15 times [2019-12-07 12:13:43,283 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,283 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639840341] [2019-12-07 12:13:43,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:43,409 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,409 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639840341] [2019-12-07 12:13:43,409 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [205668027] [2019-12-07 12:13:43,409 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:43,441 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-12-07 12:13:43,441 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:43,442 INFO L264 TraceCheckSpWp]: Trace formula consists of 109 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 12:13:43,442 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:43,449 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 48 proven. 240 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,450 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:43,450 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2019-12-07 12:13:43,450 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933055241] [2019-12-07 12:13:43,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:43,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 12:13:43,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2019-12-07 12:13:43,476 INFO L87 Difference]: Start difference. First operand 35 states and 37 transitions. cyclomatic complexity: 3 Second operand 18 states. [2019-12-07 12:13:43,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:43,506 INFO L93 Difference]: Finished difference Result 39 states and 41 transitions. [2019-12-07 12:13:43,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 12:13:43,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 41 transitions. [2019-12-07 12:13:43,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 38 states and 40 transitions. [2019-12-07 12:13:43,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:43,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:43,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 40 transitions. [2019-12-07 12:13:43,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:43,508 INFO L688 BuchiCegarLoop]: Abstraction has 38 states and 40 transitions. [2019-12-07 12:13:43,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 40 transitions. [2019-12-07 12:13:43,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 37. [2019-12-07 12:13:43,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-12-07 12:13:43,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 39 transitions. [2019-12-07 12:13:43,510 INFO L711 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2019-12-07 12:13:43,510 INFO L591 BuchiCegarLoop]: Abstraction has 37 states and 39 transitions. [2019-12-07 12:13:43,510 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 12:13:43,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 39 transitions. [2019-12-07 12:13:43,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:43,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:43,510 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [17, 16, 1] [2019-12-07 12:13:43,511 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:43,511 INFO L794 eck$LassoCheckResult]: Stem: 2287#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2283#L12-2 assume !!(main_~i~0 < main_~j~0); 2284#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2285#L12-2 assume !!(main_~i~0 < main_~j~0); 2286#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2290#L12-2 assume !!(main_~i~0 < main_~j~0); 2319#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2318#L12-2 assume !!(main_~i~0 < main_~j~0); 2317#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2316#L12-2 assume !!(main_~i~0 < main_~j~0); 2315#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2314#L12-2 assume !!(main_~i~0 < main_~j~0); 2313#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2312#L12-2 assume !!(main_~i~0 < main_~j~0); 2311#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2310#L12-2 assume !!(main_~i~0 < main_~j~0); 2309#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2308#L12-2 assume !!(main_~i~0 < main_~j~0); 2307#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2306#L12-2 assume !!(main_~i~0 < main_~j~0); 2305#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2304#L12-2 assume !!(main_~i~0 < main_~j~0); 2303#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2302#L12-2 assume !!(main_~i~0 < main_~j~0); 2301#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2300#L12-2 assume !!(main_~i~0 < main_~j~0); 2299#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2298#L12-2 assume !!(main_~i~0 < main_~j~0); 2297#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2296#L12-2 assume !!(main_~i~0 < main_~j~0); 2294#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2293#L12-2 assume !!(main_~i~0 < main_~j~0); 2292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2291#L12-2 assume !!(main_~i~0 < main_~j~0); 2288#L12 [2019-12-07 12:13:43,511 INFO L796 eck$LassoCheckResult]: Loop: 2288#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2289#L12-2 assume !!(main_~i~0 < main_~j~0); 2292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2291#L12-2 assume !!(main_~i~0 < main_~j~0); 2288#L12 [2019-12-07 12:13:43,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,511 INFO L82 PathProgramCache]: Analyzing trace with hash 841150394, now seen corresponding path program 16 times [2019-12-07 12:13:43,511 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,511 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847297593] [2019-12-07 12:13:43,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,520 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,521 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 14 times [2019-12-07 12:13:43,521 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,521 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536445620] [2019-12-07 12:13:43,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,523 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,524 INFO L82 PathProgramCache]: Analyzing trace with hash -2091418766, now seen corresponding path program 16 times [2019-12-07 12:13:43,524 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,524 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170803547] [2019-12-07 12:13:43,524 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:43,647 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,648 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170803547] [2019-12-07 12:13:43,648 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [215210933] [2019-12-07 12:13:43,648 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:43,675 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:43,675 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:43,676 INFO L264 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 12:13:43,676 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:43,684 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 51 proven. 272 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,684 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:43,684 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2019-12-07 12:13:43,684 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407727661] [2019-12-07 12:13:43,711 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:43,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 12:13:43,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2019-12-07 12:13:43,711 INFO L87 Difference]: Start difference. First operand 37 states and 39 transitions. cyclomatic complexity: 3 Second operand 19 states. [2019-12-07 12:13:43,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:43,742 INFO L93 Difference]: Finished difference Result 41 states and 43 transitions. [2019-12-07 12:13:43,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 12:13:43,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 43 transitions. [2019-12-07 12:13:43,742 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 42 transitions. [2019-12-07 12:13:43,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:43,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:43,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 42 transitions. [2019-12-07 12:13:43,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:43,743 INFO L688 BuchiCegarLoop]: Abstraction has 40 states and 42 transitions. [2019-12-07 12:13:43,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 42 transitions. [2019-12-07 12:13:43,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2019-12-07 12:13:43,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-12-07 12:13:43,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 41 transitions. [2019-12-07 12:13:43,745 INFO L711 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2019-12-07 12:13:43,745 INFO L591 BuchiCegarLoop]: Abstraction has 39 states and 41 transitions. [2019-12-07 12:13:43,745 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 12:13:43,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 41 transitions. [2019-12-07 12:13:43,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:43,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:43,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:43,746 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [18, 17, 1] [2019-12-07 12:13:43,746 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:43,746 INFO L794 eck$LassoCheckResult]: Stem: 2500#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2496#L12-2 assume !!(main_~i~0 < main_~j~0); 2497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2498#L12-2 assume !!(main_~i~0 < main_~j~0); 2499#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2503#L12-2 assume !!(main_~i~0 < main_~j~0); 2534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2533#L12-2 assume !!(main_~i~0 < main_~j~0); 2532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2531#L12-2 assume !!(main_~i~0 < main_~j~0); 2530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2529#L12-2 assume !!(main_~i~0 < main_~j~0); 2528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2527#L12-2 assume !!(main_~i~0 < main_~j~0); 2526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2525#L12-2 assume !!(main_~i~0 < main_~j~0); 2524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2523#L12-2 assume !!(main_~i~0 < main_~j~0); 2522#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2521#L12-2 assume !!(main_~i~0 < main_~j~0); 2520#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2519#L12-2 assume !!(main_~i~0 < main_~j~0); 2518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2517#L12-2 assume !!(main_~i~0 < main_~j~0); 2516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2515#L12-2 assume !!(main_~i~0 < main_~j~0); 2514#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2513#L12-2 assume !!(main_~i~0 < main_~j~0); 2512#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2511#L12-2 assume !!(main_~i~0 < main_~j~0); 2510#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2509#L12-2 assume !!(main_~i~0 < main_~j~0); 2507#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2506#L12-2 assume !!(main_~i~0 < main_~j~0); 2505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2504#L12-2 assume !!(main_~i~0 < main_~j~0); 2501#L12 [2019-12-07 12:13:43,746 INFO L796 eck$LassoCheckResult]: Loop: 2501#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2502#L12-2 assume !!(main_~i~0 < main_~j~0); 2505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2504#L12-2 assume !!(main_~i~0 < main_~j~0); 2501#L12 [2019-12-07 12:13:43,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,746 INFO L82 PathProgramCache]: Analyzing trace with hash 891677399, now seen corresponding path program 17 times [2019-12-07 12:13:43,746 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999110765] [2019-12-07 12:13:43,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,755 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,755 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 15 times [2019-12-07 12:13:43,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417925171] [2019-12-07 12:13:43,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:43,758 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:43,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:43,758 INFO L82 PathProgramCache]: Analyzing trace with hash 134062095, now seen corresponding path program 17 times [2019-12-07 12:13:43,758 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:43,758 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323734202] [2019-12-07 12:13:43,758 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:43,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:43,898 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,898 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323734202] [2019-12-07 12:13:43,898 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1560868899] [2019-12-07 12:13:43,898 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:43,929 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2019-12-07 12:13:43,929 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:43,930 INFO L264 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 12:13:43,931 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:43,939 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 54 proven. 306 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:43,939 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:43,939 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2019-12-07 12:13:43,940 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782945268] [2019-12-07 12:13:43,966 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:43,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 12:13:43,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2019-12-07 12:13:43,967 INFO L87 Difference]: Start difference. First operand 39 states and 41 transitions. cyclomatic complexity: 3 Second operand 20 states. [2019-12-07 12:13:44,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:44,010 INFO L93 Difference]: Finished difference Result 43 states and 45 transitions. [2019-12-07 12:13:44,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 12:13:44,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 45 transitions. [2019-12-07 12:13:44,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 42 states and 44 transitions. [2019-12-07 12:13:44,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:44,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:44,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 44 transitions. [2019-12-07 12:13:44,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:44,012 INFO L688 BuchiCegarLoop]: Abstraction has 42 states and 44 transitions. [2019-12-07 12:13:44,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 44 transitions. [2019-12-07 12:13:44,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2019-12-07 12:13:44,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 12:13:44,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 43 transitions. [2019-12-07 12:13:44,014 INFO L711 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2019-12-07 12:13:44,014 INFO L591 BuchiCegarLoop]: Abstraction has 41 states and 43 transitions. [2019-12-07 12:13:44,014 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 12:13:44,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 43 transitions. [2019-12-07 12:13:44,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:44,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:44,015 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [19, 18, 1] [2019-12-07 12:13:44,016 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:44,016 INFO L794 eck$LassoCheckResult]: Stem: 2724#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2720#L12-2 assume !!(main_~i~0 < main_~j~0); 2721#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2722#L12-2 assume !!(main_~i~0 < main_~j~0); 2723#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2727#L12-2 assume !!(main_~i~0 < main_~j~0); 2760#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2759#L12-2 assume !!(main_~i~0 < main_~j~0); 2758#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2757#L12-2 assume !!(main_~i~0 < main_~j~0); 2756#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2755#L12-2 assume !!(main_~i~0 < main_~j~0); 2754#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2753#L12-2 assume !!(main_~i~0 < main_~j~0); 2752#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2751#L12-2 assume !!(main_~i~0 < main_~j~0); 2750#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2749#L12-2 assume !!(main_~i~0 < main_~j~0); 2748#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2747#L12-2 assume !!(main_~i~0 < main_~j~0); 2746#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2745#L12-2 assume !!(main_~i~0 < main_~j~0); 2744#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2743#L12-2 assume !!(main_~i~0 < main_~j~0); 2742#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2741#L12-2 assume !!(main_~i~0 < main_~j~0); 2740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2739#L12-2 assume !!(main_~i~0 < main_~j~0); 2738#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2737#L12-2 assume !!(main_~i~0 < main_~j~0); 2736#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2735#L12-2 assume !!(main_~i~0 < main_~j~0); 2734#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2733#L12-2 assume !!(main_~i~0 < main_~j~0); 2731#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2730#L12-2 assume !!(main_~i~0 < main_~j~0); 2729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2728#L12-2 assume !!(main_~i~0 < main_~j~0); 2725#L12 [2019-12-07 12:13:44,016 INFO L796 eck$LassoCheckResult]: Loop: 2725#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2726#L12-2 assume !!(main_~i~0 < main_~j~0); 2729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2728#L12-2 assume !!(main_~i~0 < main_~j~0); 2725#L12 [2019-12-07 12:13:44,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,016 INFO L82 PathProgramCache]: Analyzing trace with hash -2091478348, now seen corresponding path program 18 times [2019-12-07 12:13:44,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,016 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797549320] [2019-12-07 12:13:44,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,027 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 16 times [2019-12-07 12:13:44,027 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,027 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572640740] [2019-12-07 12:13:44,027 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,030 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,030 INFO L82 PathProgramCache]: Analyzing trace with hash -72543892, now seen corresponding path program 18 times [2019-12-07 12:13:44,030 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,030 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337797352] [2019-12-07 12:13:44,030 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:44,182 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,182 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337797352] [2019-12-07 12:13:44,182 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [373169403] [2019-12-07 12:13:44,182 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:44,212 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2019-12-07 12:13:44,212 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:44,212 INFO L264 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 12:13:44,213 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:44,219 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 57 proven. 342 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,219 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:44,219 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2019-12-07 12:13:44,219 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284002952] [2019-12-07 12:13:44,246 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:44,246 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 12:13:44,246 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2019-12-07 12:13:44,246 INFO L87 Difference]: Start difference. First operand 41 states and 43 transitions. cyclomatic complexity: 3 Second operand 21 states. [2019-12-07 12:13:44,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:44,278 INFO L93 Difference]: Finished difference Result 45 states and 47 transitions. [2019-12-07 12:13:44,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 12:13:44,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 47 transitions. [2019-12-07 12:13:44,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 46 transitions. [2019-12-07 12:13:44,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:44,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:44,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 46 transitions. [2019-12-07 12:13:44,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:44,279 INFO L688 BuchiCegarLoop]: Abstraction has 44 states and 46 transitions. [2019-12-07 12:13:44,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 46 transitions. [2019-12-07 12:13:44,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2019-12-07 12:13:44,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-12-07 12:13:44,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 45 transitions. [2019-12-07 12:13:44,280 INFO L711 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2019-12-07 12:13:44,281 INFO L591 BuchiCegarLoop]: Abstraction has 43 states and 45 transitions. [2019-12-07 12:13:44,281 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 12:13:44,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 45 transitions. [2019-12-07 12:13:44,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:44,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:44,281 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [20, 19, 1] [2019-12-07 12:13:44,281 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:44,282 INFO L794 eck$LassoCheckResult]: Stem: 2959#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 2955#L12-2 assume !!(main_~i~0 < main_~j~0); 2956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2957#L12-2 assume !!(main_~i~0 < main_~j~0); 2958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2962#L12-2 assume !!(main_~i~0 < main_~j~0); 2997#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2996#L12-2 assume !!(main_~i~0 < main_~j~0); 2995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2994#L12-2 assume !!(main_~i~0 < main_~j~0); 2993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2992#L12-2 assume !!(main_~i~0 < main_~j~0); 2991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2990#L12-2 assume !!(main_~i~0 < main_~j~0); 2989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2988#L12-2 assume !!(main_~i~0 < main_~j~0); 2987#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2986#L12-2 assume !!(main_~i~0 < main_~j~0); 2985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2984#L12-2 assume !!(main_~i~0 < main_~j~0); 2983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2982#L12-2 assume !!(main_~i~0 < main_~j~0); 2981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2980#L12-2 assume !!(main_~i~0 < main_~j~0); 2979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2978#L12-2 assume !!(main_~i~0 < main_~j~0); 2977#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2976#L12-2 assume !!(main_~i~0 < main_~j~0); 2975#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2974#L12-2 assume !!(main_~i~0 < main_~j~0); 2973#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2972#L12-2 assume !!(main_~i~0 < main_~j~0); 2971#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2970#L12-2 assume !!(main_~i~0 < main_~j~0); 2969#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2968#L12-2 assume !!(main_~i~0 < main_~j~0); 2966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2965#L12-2 assume !!(main_~i~0 < main_~j~0); 2964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2963#L12-2 assume !!(main_~i~0 < main_~j~0); 2960#L12 [2019-12-07 12:13:44,282 INFO L796 eck$LassoCheckResult]: Loop: 2960#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 2961#L12-2 assume !!(main_~i~0 < main_~j~0); 2964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 2963#L12-2 assume !!(main_~i~0 < main_~j~0); 2960#L12 [2019-12-07 12:13:44,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,282 INFO L82 PathProgramCache]: Analyzing trace with hash 134002513, now seen corresponding path program 19 times [2019-12-07 12:13:44,282 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,282 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334909792] [2019-12-07 12:13:44,282 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,292 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 17 times [2019-12-07 12:13:44,292 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,292 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911756746] [2019-12-07 12:13:44,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,294 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,294 INFO L82 PathProgramCache]: Analyzing trace with hash -1052401783, now seen corresponding path program 19 times [2019-12-07 12:13:44,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771645716] [2019-12-07 12:13:44,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:44,453 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771645716] [2019-12-07 12:13:44,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1970564528] [2019-12-07 12:13:44,453 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:44,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:44,479 INFO L264 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 12:13:44,479 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:44,490 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 60 proven. 380 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,491 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:44,491 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2019-12-07 12:13:44,491 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395078817] [2019-12-07 12:13:44,515 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:44,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 12:13:44,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2019-12-07 12:13:44,516 INFO L87 Difference]: Start difference. First operand 43 states and 45 transitions. cyclomatic complexity: 3 Second operand 22 states. [2019-12-07 12:13:44,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:44,552 INFO L93 Difference]: Finished difference Result 47 states and 49 transitions. [2019-12-07 12:13:44,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 12:13:44,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 49 transitions. [2019-12-07 12:13:44,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 46 states and 48 transitions. [2019-12-07 12:13:44,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:44,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:44,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 48 transitions. [2019-12-07 12:13:44,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:44,554 INFO L688 BuchiCegarLoop]: Abstraction has 46 states and 48 transitions. [2019-12-07 12:13:44,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 48 transitions. [2019-12-07 12:13:44,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2019-12-07 12:13:44,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-12-07 12:13:44,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2019-12-07 12:13:44,555 INFO L711 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2019-12-07 12:13:44,555 INFO L591 BuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2019-12-07 12:13:44,555 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 12:13:44,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 47 transitions. [2019-12-07 12:13:44,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:44,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:44,556 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [21, 20, 1] [2019-12-07 12:13:44,556 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:44,556 INFO L794 eck$LassoCheckResult]: Stem: 3205#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3201#L12-2 assume !!(main_~i~0 < main_~j~0); 3202#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3203#L12-2 assume !!(main_~i~0 < main_~j~0); 3204#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3208#L12-2 assume !!(main_~i~0 < main_~j~0); 3245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3244#L12-2 assume !!(main_~i~0 < main_~j~0); 3243#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3242#L12-2 assume !!(main_~i~0 < main_~j~0); 3241#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3240#L12-2 assume !!(main_~i~0 < main_~j~0); 3239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3238#L12-2 assume !!(main_~i~0 < main_~j~0); 3237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3236#L12-2 assume !!(main_~i~0 < main_~j~0); 3235#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3234#L12-2 assume !!(main_~i~0 < main_~j~0); 3233#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3232#L12-2 assume !!(main_~i~0 < main_~j~0); 3231#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3230#L12-2 assume !!(main_~i~0 < main_~j~0); 3229#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3228#L12-2 assume !!(main_~i~0 < main_~j~0); 3227#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3226#L12-2 assume !!(main_~i~0 < main_~j~0); 3225#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3224#L12-2 assume !!(main_~i~0 < main_~j~0); 3223#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3222#L12-2 assume !!(main_~i~0 < main_~j~0); 3221#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3220#L12-2 assume !!(main_~i~0 < main_~j~0); 3219#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3218#L12-2 assume !!(main_~i~0 < main_~j~0); 3217#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3216#L12-2 assume !!(main_~i~0 < main_~j~0); 3215#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3214#L12-2 assume !!(main_~i~0 < main_~j~0); 3212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3211#L12-2 assume !!(main_~i~0 < main_~j~0); 3210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3209#L12-2 assume !!(main_~i~0 < main_~j~0); 3206#L12 [2019-12-07 12:13:44,556 INFO L796 eck$LassoCheckResult]: Loop: 3206#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3207#L12-2 assume !!(main_~i~0 < main_~j~0); 3210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3209#L12-2 assume !!(main_~i~0 < main_~j~0); 3206#L12 [2019-12-07 12:13:44,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,557 INFO L82 PathProgramCache]: Analyzing trace with hash -72603474, now seen corresponding path program 20 times [2019-12-07 12:13:44,557 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,557 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317904562] [2019-12-07 12:13:44,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,570 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,570 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 18 times [2019-12-07 12:13:44,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,570 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501437229] [2019-12-07 12:13:44,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,573 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,574 INFO L82 PathProgramCache]: Analyzing trace with hash -2097997210, now seen corresponding path program 20 times [2019-12-07 12:13:44,574 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,574 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385412148] [2019-12-07 12:13:44,574 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:44,744 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,744 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385412148] [2019-12-07 12:13:44,744 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1286947882] [2019-12-07 12:13:44,744 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:44,766 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:44,766 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:44,767 INFO L264 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 12:13:44,767 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:44,776 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 63 proven. 420 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:44,776 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:44,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2019-12-07 12:13:44,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240724971] [2019-12-07 12:13:44,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:44,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 12:13:44,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2019-12-07 12:13:44,804 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. cyclomatic complexity: 3 Second operand 23 states. [2019-12-07 12:13:44,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:44,840 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2019-12-07 12:13:44,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 12:13:44,841 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 51 transitions. [2019-12-07 12:13:44,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 48 states and 50 transitions. [2019-12-07 12:13:44,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:44,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:44,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 50 transitions. [2019-12-07 12:13:44,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:44,842 INFO L688 BuchiCegarLoop]: Abstraction has 48 states and 50 transitions. [2019-12-07 12:13:44,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 50 transitions. [2019-12-07 12:13:44,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 47. [2019-12-07 12:13:44,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2019-12-07 12:13:44,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2019-12-07 12:13:44,843 INFO L711 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2019-12-07 12:13:44,843 INFO L591 BuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2019-12-07 12:13:44,843 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-12-07 12:13:44,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2019-12-07 12:13:44,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:44,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:44,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:44,844 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [22, 21, 1] [2019-12-07 12:13:44,844 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:44,845 INFO L794 eck$LassoCheckResult]: Stem: 3462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3458#L12-2 assume !!(main_~i~0 < main_~j~0); 3459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3460#L12-2 assume !!(main_~i~0 < main_~j~0); 3461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3465#L12-2 assume !!(main_~i~0 < main_~j~0); 3504#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3503#L12-2 assume !!(main_~i~0 < main_~j~0); 3502#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3501#L12-2 assume !!(main_~i~0 < main_~j~0); 3500#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3499#L12-2 assume !!(main_~i~0 < main_~j~0); 3498#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3497#L12-2 assume !!(main_~i~0 < main_~j~0); 3496#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3495#L12-2 assume !!(main_~i~0 < main_~j~0); 3494#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3493#L12-2 assume !!(main_~i~0 < main_~j~0); 3492#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3491#L12-2 assume !!(main_~i~0 < main_~j~0); 3490#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3489#L12-2 assume !!(main_~i~0 < main_~j~0); 3488#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3487#L12-2 assume !!(main_~i~0 < main_~j~0); 3486#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3485#L12-2 assume !!(main_~i~0 < main_~j~0); 3484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3483#L12-2 assume !!(main_~i~0 < main_~j~0); 3482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3481#L12-2 assume !!(main_~i~0 < main_~j~0); 3480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3479#L12-2 assume !!(main_~i~0 < main_~j~0); 3478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3477#L12-2 assume !!(main_~i~0 < main_~j~0); 3476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3475#L12-2 assume !!(main_~i~0 < main_~j~0); 3474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3473#L12-2 assume !!(main_~i~0 < main_~j~0); 3472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3471#L12-2 assume !!(main_~i~0 < main_~j~0); 3469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3468#L12-2 assume !!(main_~i~0 < main_~j~0); 3467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3466#L12-2 assume !!(main_~i~0 < main_~j~0); 3463#L12 [2019-12-07 12:13:44,845 INFO L796 eck$LassoCheckResult]: Loop: 3463#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3464#L12-2 assume !!(main_~i~0 < main_~j~0); 3467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3466#L12-2 assume !!(main_~i~0 < main_~j~0); 3463#L12 [2019-12-07 12:13:44,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,845 INFO L82 PathProgramCache]: Analyzing trace with hash -1052461365, now seen corresponding path program 21 times [2019-12-07 12:13:44,845 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,845 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559702988] [2019-12-07 12:13:44,845 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,855 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 19 times [2019-12-07 12:13:44,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94349579] [2019-12-07 12:13:44,855 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:44,857 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:44,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:44,857 INFO L82 PathProgramCache]: Analyzing trace with hash -1892855293, now seen corresponding path program 21 times [2019-12-07 12:13:44,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:44,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529832124] [2019-12-07 12:13:44,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:44,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:45,044 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529832124] [2019-12-07 12:13:45,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [550253356] [2019-12-07 12:13:45,044 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:45,075 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2019-12-07 12:13:45,075 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:45,076 INFO L264 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 12:13:45,076 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:45,085 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 66 proven. 462 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,085 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:45,086 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2019-12-07 12:13:45,086 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508334412] [2019-12-07 12:13:45,110 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:45,110 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 12:13:45,110 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2019-12-07 12:13:45,110 INFO L87 Difference]: Start difference. First operand 47 states and 49 transitions. cyclomatic complexity: 3 Second operand 24 states. [2019-12-07 12:13:45,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:45,151 INFO L93 Difference]: Finished difference Result 51 states and 53 transitions. [2019-12-07 12:13:45,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 12:13:45,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 53 transitions. [2019-12-07 12:13:45,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 52 transitions. [2019-12-07 12:13:45,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:45,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:45,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 52 transitions. [2019-12-07 12:13:45,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:45,153 INFO L688 BuchiCegarLoop]: Abstraction has 50 states and 52 transitions. [2019-12-07 12:13:45,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 52 transitions. [2019-12-07 12:13:45,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2019-12-07 12:13:45,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2019-12-07 12:13:45,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2019-12-07 12:13:45,155 INFO L711 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2019-12-07 12:13:45,155 INFO L591 BuchiCegarLoop]: Abstraction has 49 states and 51 transitions. [2019-12-07 12:13:45,155 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-12-07 12:13:45,155 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 51 transitions. [2019-12-07 12:13:45,156 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:45,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:45,157 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [23, 22, 1] [2019-12-07 12:13:45,157 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:45,157 INFO L794 eck$LassoCheckResult]: Stem: 3730#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 3726#L12-2 assume !!(main_~i~0 < main_~j~0); 3727#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3728#L12-2 assume !!(main_~i~0 < main_~j~0); 3729#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3733#L12-2 assume !!(main_~i~0 < main_~j~0); 3774#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3773#L12-2 assume !!(main_~i~0 < main_~j~0); 3772#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3771#L12-2 assume !!(main_~i~0 < main_~j~0); 3770#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3769#L12-2 assume !!(main_~i~0 < main_~j~0); 3768#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3767#L12-2 assume !!(main_~i~0 < main_~j~0); 3766#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3765#L12-2 assume !!(main_~i~0 < main_~j~0); 3764#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3763#L12-2 assume !!(main_~i~0 < main_~j~0); 3762#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3761#L12-2 assume !!(main_~i~0 < main_~j~0); 3760#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3759#L12-2 assume !!(main_~i~0 < main_~j~0); 3758#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3757#L12-2 assume !!(main_~i~0 < main_~j~0); 3756#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3755#L12-2 assume !!(main_~i~0 < main_~j~0); 3754#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3753#L12-2 assume !!(main_~i~0 < main_~j~0); 3752#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3751#L12-2 assume !!(main_~i~0 < main_~j~0); 3750#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3749#L12-2 assume !!(main_~i~0 < main_~j~0); 3748#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3747#L12-2 assume !!(main_~i~0 < main_~j~0); 3746#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3745#L12-2 assume !!(main_~i~0 < main_~j~0); 3744#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3743#L12-2 assume !!(main_~i~0 < main_~j~0); 3742#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3741#L12-2 assume !!(main_~i~0 < main_~j~0); 3740#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3739#L12-2 assume !!(main_~i~0 < main_~j~0); 3737#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3736#L12-2 assume !!(main_~i~0 < main_~j~0); 3735#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3734#L12-2 assume !!(main_~i~0 < main_~j~0); 3731#L12 [2019-12-07 12:13:45,157 INFO L796 eck$LassoCheckResult]: Loop: 3731#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 3732#L12-2 assume !!(main_~i~0 < main_~j~0); 3735#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 3734#L12-2 assume !!(main_~i~0 < main_~j~0); 3731#L12 [2019-12-07 12:13:45,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,157 INFO L82 PathProgramCache]: Analyzing trace with hash -2098056792, now seen corresponding path program 22 times [2019-12-07 12:13:45,157 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,157 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487257715] [2019-12-07 12:13:45,158 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,172 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 20 times [2019-12-07 12:13:45,173 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,173 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223290889] [2019-12-07 12:13:45,173 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,176 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1974998624, now seen corresponding path program 22 times [2019-12-07 12:13:45,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202493257] [2019-12-07 12:13:45,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:45,376 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202493257] [2019-12-07 12:13:45,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [473895022] [2019-12-07 12:13:45,376 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:45,399 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:45,399 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:45,400 INFO L264 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 12:13:45,401 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:45,407 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 69 proven. 506 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,407 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:45,407 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2019-12-07 12:13:45,407 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734737087] [2019-12-07 12:13:45,432 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:45,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 12:13:45,432 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2019-12-07 12:13:45,432 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. cyclomatic complexity: 3 Second operand 25 states. [2019-12-07 12:13:45,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:45,476 INFO L93 Difference]: Finished difference Result 53 states and 55 transitions. [2019-12-07 12:13:45,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 12:13:45,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 55 transitions. [2019-12-07 12:13:45,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 54 transitions. [2019-12-07 12:13:45,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:45,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:45,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 54 transitions. [2019-12-07 12:13:45,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:45,478 INFO L688 BuchiCegarLoop]: Abstraction has 52 states and 54 transitions. [2019-12-07 12:13:45,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 54 transitions. [2019-12-07 12:13:45,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2019-12-07 12:13:45,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2019-12-07 12:13:45,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 53 transitions. [2019-12-07 12:13:45,479 INFO L711 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2019-12-07 12:13:45,479 INFO L591 BuchiCegarLoop]: Abstraction has 51 states and 53 transitions. [2019-12-07 12:13:45,479 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-12-07 12:13:45,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 53 transitions. [2019-12-07 12:13:45,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:45,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:45,480 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 1] [2019-12-07 12:13:45,480 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:45,480 INFO L794 eck$LassoCheckResult]: Stem: 4009#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4005#L12-2 assume !!(main_~i~0 < main_~j~0); 4006#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4007#L12-2 assume !!(main_~i~0 < main_~j~0); 4008#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4012#L12-2 assume !!(main_~i~0 < main_~j~0); 4055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4054#L12-2 assume !!(main_~i~0 < main_~j~0); 4053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4052#L12-2 assume !!(main_~i~0 < main_~j~0); 4051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4050#L12-2 assume !!(main_~i~0 < main_~j~0); 4049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4048#L12-2 assume !!(main_~i~0 < main_~j~0); 4047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4046#L12-2 assume !!(main_~i~0 < main_~j~0); 4045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4044#L12-2 assume !!(main_~i~0 < main_~j~0); 4043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4042#L12-2 assume !!(main_~i~0 < main_~j~0); 4041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4040#L12-2 assume !!(main_~i~0 < main_~j~0); 4039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4038#L12-2 assume !!(main_~i~0 < main_~j~0); 4037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4036#L12-2 assume !!(main_~i~0 < main_~j~0); 4035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4034#L12-2 assume !!(main_~i~0 < main_~j~0); 4033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4032#L12-2 assume !!(main_~i~0 < main_~j~0); 4031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4030#L12-2 assume !!(main_~i~0 < main_~j~0); 4029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4028#L12-2 assume !!(main_~i~0 < main_~j~0); 4027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4026#L12-2 assume !!(main_~i~0 < main_~j~0); 4025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4024#L12-2 assume !!(main_~i~0 < main_~j~0); 4023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4022#L12-2 assume !!(main_~i~0 < main_~j~0); 4021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4020#L12-2 assume !!(main_~i~0 < main_~j~0); 4019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4018#L12-2 assume !!(main_~i~0 < main_~j~0); 4016#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4015#L12-2 assume !!(main_~i~0 < main_~j~0); 4014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4013#L12-2 assume !!(main_~i~0 < main_~j~0); 4010#L12 [2019-12-07 12:13:45,480 INFO L796 eck$LassoCheckResult]: Loop: 4010#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4011#L12-2 assume !!(main_~i~0 < main_~j~0); 4014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4013#L12-2 assume !!(main_~i~0 < main_~j~0); 4010#L12 [2019-12-07 12:13:45,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,480 INFO L82 PathProgramCache]: Analyzing trace with hash -1892914875, now seen corresponding path program 23 times [2019-12-07 12:13:45,480 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,480 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443907044] [2019-12-07 12:13:45,480 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,490 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,491 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 21 times [2019-12-07 12:13:45,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076030603] [2019-12-07 12:13:45,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,493 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,493 INFO L82 PathProgramCache]: Analyzing trace with hash -459065475, now seen corresponding path program 23 times [2019-12-07 12:13:45,494 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,494 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935696803] [2019-12-07 12:13:45,494 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:45,720 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,721 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935696803] [2019-12-07 12:13:45,721 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [652264234] [2019-12-07 12:13:45,721 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:45,756 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2019-12-07 12:13:45,756 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:45,757 INFO L264 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 12:13:45,758 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:45,765 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 72 proven. 552 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:45,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:45,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2019-12-07 12:13:45,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49848471] [2019-12-07 12:13:45,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:45,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 12:13:45,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2019-12-07 12:13:45,789 INFO L87 Difference]: Start difference. First operand 51 states and 53 transitions. cyclomatic complexity: 3 Second operand 26 states. [2019-12-07 12:13:45,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:45,833 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2019-12-07 12:13:45,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 12:13:45,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2019-12-07 12:13:45,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 54 states and 56 transitions. [2019-12-07 12:13:45,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:45,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:45,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 56 transitions. [2019-12-07 12:13:45,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:45,835 INFO L688 BuchiCegarLoop]: Abstraction has 54 states and 56 transitions. [2019-12-07 12:13:45,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 56 transitions. [2019-12-07 12:13:45,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 53. [2019-12-07 12:13:45,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2019-12-07 12:13:45,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 55 transitions. [2019-12-07 12:13:45,836 INFO L711 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2019-12-07 12:13:45,837 INFO L591 BuchiCegarLoop]: Abstraction has 53 states and 55 transitions. [2019-12-07 12:13:45,837 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-12-07 12:13:45,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 55 transitions. [2019-12-07 12:13:45,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:45,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:45,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:45,837 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [25, 24, 1] [2019-12-07 12:13:45,838 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:45,838 INFO L794 eck$LassoCheckResult]: Stem: 4299#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4295#L12-2 assume !!(main_~i~0 < main_~j~0); 4296#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4297#L12-2 assume !!(main_~i~0 < main_~j~0); 4298#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4302#L12-2 assume !!(main_~i~0 < main_~j~0); 4347#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4346#L12-2 assume !!(main_~i~0 < main_~j~0); 4345#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4344#L12-2 assume !!(main_~i~0 < main_~j~0); 4343#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4342#L12-2 assume !!(main_~i~0 < main_~j~0); 4341#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4340#L12-2 assume !!(main_~i~0 < main_~j~0); 4339#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4338#L12-2 assume !!(main_~i~0 < main_~j~0); 4337#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4336#L12-2 assume !!(main_~i~0 < main_~j~0); 4335#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4334#L12-2 assume !!(main_~i~0 < main_~j~0); 4333#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4332#L12-2 assume !!(main_~i~0 < main_~j~0); 4331#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4330#L12-2 assume !!(main_~i~0 < main_~j~0); 4329#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4328#L12-2 assume !!(main_~i~0 < main_~j~0); 4327#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4326#L12-2 assume !!(main_~i~0 < main_~j~0); 4325#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4324#L12-2 assume !!(main_~i~0 < main_~j~0); 4323#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4322#L12-2 assume !!(main_~i~0 < main_~j~0); 4321#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4320#L12-2 assume !!(main_~i~0 < main_~j~0); 4319#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4318#L12-2 assume !!(main_~i~0 < main_~j~0); 4317#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4316#L12-2 assume !!(main_~i~0 < main_~j~0); 4315#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4314#L12-2 assume !!(main_~i~0 < main_~j~0); 4313#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4312#L12-2 assume !!(main_~i~0 < main_~j~0); 4311#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4310#L12-2 assume !!(main_~i~0 < main_~j~0); 4309#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4308#L12-2 assume !!(main_~i~0 < main_~j~0); 4306#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4305#L12-2 assume !!(main_~i~0 < main_~j~0); 4304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4303#L12-2 assume !!(main_~i~0 < main_~j~0); 4300#L12 [2019-12-07 12:13:45,838 INFO L796 eck$LassoCheckResult]: Loop: 4300#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4301#L12-2 assume !!(main_~i~0 < main_~j~0); 4304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4303#L12-2 assume !!(main_~i~0 < main_~j~0); 4300#L12 [2019-12-07 12:13:45,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,838 INFO L82 PathProgramCache]: Analyzing trace with hash 1974939042, now seen corresponding path program 24 times [2019-12-07 12:13:45,838 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,838 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103263595] [2019-12-07 12:13:45,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,850 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,850 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 22 times [2019-12-07 12:13:45,850 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215979500] [2019-12-07 12:13:45,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:45,852 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:45,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:45,852 INFO L82 PathProgramCache]: Analyzing trace with hash 1162511706, now seen corresponding path program 24 times [2019-12-07 12:13:45,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:45,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956617878] [2019-12-07 12:13:45,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:45,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:46,073 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956617878] [2019-12-07 12:13:46,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [747750322] [2019-12-07 12:13:46,073 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:46,108 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 27 check-sat command(s) [2019-12-07 12:13:46,108 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:46,109 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 12:13:46,109 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:46,116 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 75 proven. 600 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,117 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:46,117 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2019-12-07 12:13:46,117 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [823140810] [2019-12-07 12:13:46,141 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:46,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 12:13:46,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2019-12-07 12:13:46,142 INFO L87 Difference]: Start difference. First operand 53 states and 55 transitions. cyclomatic complexity: 3 Second operand 27 states. [2019-12-07 12:13:46,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:46,187 INFO L93 Difference]: Finished difference Result 57 states and 59 transitions. [2019-12-07 12:13:46,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 12:13:46,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 59 transitions. [2019-12-07 12:13:46,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 56 states and 58 transitions. [2019-12-07 12:13:46,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:46,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:46,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 58 transitions. [2019-12-07 12:13:46,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:46,189 INFO L688 BuchiCegarLoop]: Abstraction has 56 states and 58 transitions. [2019-12-07 12:13:46,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 58 transitions. [2019-12-07 12:13:46,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 55. [2019-12-07 12:13:46,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2019-12-07 12:13:46,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2019-12-07 12:13:46,189 INFO L711 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2019-12-07 12:13:46,190 INFO L591 BuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2019-12-07 12:13:46,190 INFO L424 BuchiCegarLoop]: ======== Iteration 27============ [2019-12-07 12:13:46,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2019-12-07 12:13:46,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:46,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:46,190 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [26, 25, 1] [2019-12-07 12:13:46,190 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:46,191 INFO L794 eck$LassoCheckResult]: Stem: 4600#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4596#L12-2 assume !!(main_~i~0 < main_~j~0); 4597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4598#L12-2 assume !!(main_~i~0 < main_~j~0); 4599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4603#L12-2 assume !!(main_~i~0 < main_~j~0); 4650#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4649#L12-2 assume !!(main_~i~0 < main_~j~0); 4648#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4647#L12-2 assume !!(main_~i~0 < main_~j~0); 4646#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4645#L12-2 assume !!(main_~i~0 < main_~j~0); 4644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4643#L12-2 assume !!(main_~i~0 < main_~j~0); 4642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4641#L12-2 assume !!(main_~i~0 < main_~j~0); 4640#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4639#L12-2 assume !!(main_~i~0 < main_~j~0); 4638#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4637#L12-2 assume !!(main_~i~0 < main_~j~0); 4636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4635#L12-2 assume !!(main_~i~0 < main_~j~0); 4634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4633#L12-2 assume !!(main_~i~0 < main_~j~0); 4632#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4631#L12-2 assume !!(main_~i~0 < main_~j~0); 4630#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4629#L12-2 assume !!(main_~i~0 < main_~j~0); 4628#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4627#L12-2 assume !!(main_~i~0 < main_~j~0); 4626#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4625#L12-2 assume !!(main_~i~0 < main_~j~0); 4624#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4623#L12-2 assume !!(main_~i~0 < main_~j~0); 4622#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4621#L12-2 assume !!(main_~i~0 < main_~j~0); 4620#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4619#L12-2 assume !!(main_~i~0 < main_~j~0); 4618#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4617#L12-2 assume !!(main_~i~0 < main_~j~0); 4616#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4615#L12-2 assume !!(main_~i~0 < main_~j~0); 4614#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4613#L12-2 assume !!(main_~i~0 < main_~j~0); 4612#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4611#L12-2 assume !!(main_~i~0 < main_~j~0); 4610#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4609#L12-2 assume !!(main_~i~0 < main_~j~0); 4607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4606#L12-2 assume !!(main_~i~0 < main_~j~0); 4605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4604#L12-2 assume !!(main_~i~0 < main_~j~0); 4601#L12 [2019-12-07 12:13:46,191 INFO L796 eck$LassoCheckResult]: Loop: 4601#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4602#L12-2 assume !!(main_~i~0 < main_~j~0); 4605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4604#L12-2 assume !!(main_~i~0 < main_~j~0); 4601#L12 [2019-12-07 12:13:46,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,191 INFO L82 PathProgramCache]: Analyzing trace with hash -459125057, now seen corresponding path program 25 times [2019-12-07 12:13:46,191 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,191 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385747871] [2019-12-07 12:13:46,191 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,202 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,202 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 23 times [2019-12-07 12:13:46,202 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,202 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213049604] [2019-12-07 12:13:46,202 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,204 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,204 INFO L82 PathProgramCache]: Analyzing trace with hash 425054199, now seen corresponding path program 25 times [2019-12-07 12:13:46,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658100307] [2019-12-07 12:13:46,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:46,434 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,434 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658100307] [2019-12-07 12:13:46,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [72703780] [2019-12-07 12:13:46,435 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:46,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:46,460 INFO L264 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 12:13:46,461 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:46,467 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 78 proven. 650 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,468 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:46,468 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2019-12-07 12:13:46,468 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949619148] [2019-12-07 12:13:46,496 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:46,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 12:13:46,497 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2019-12-07 12:13:46,497 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 3 Second operand 28 states. [2019-12-07 12:13:46,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:46,550 INFO L93 Difference]: Finished difference Result 59 states and 61 transitions. [2019-12-07 12:13:46,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 12:13:46,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 61 transitions. [2019-12-07 12:13:46,550 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 58 states and 60 transitions. [2019-12-07 12:13:46,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:46,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:46,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 60 transitions. [2019-12-07 12:13:46,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:46,551 INFO L688 BuchiCegarLoop]: Abstraction has 58 states and 60 transitions. [2019-12-07 12:13:46,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 60 transitions. [2019-12-07 12:13:46,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2019-12-07 12:13:46,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2019-12-07 12:13:46,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 59 transitions. [2019-12-07 12:13:46,552 INFO L711 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2019-12-07 12:13:46,552 INFO L591 BuchiCegarLoop]: Abstraction has 57 states and 59 transitions. [2019-12-07 12:13:46,552 INFO L424 BuchiCegarLoop]: ======== Iteration 28============ [2019-12-07 12:13:46,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 59 transitions. [2019-12-07 12:13:46,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:46,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:46,553 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [27, 26, 1] [2019-12-07 12:13:46,553 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:46,553 INFO L794 eck$LassoCheckResult]: Stem: 4912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 4908#L12-2 assume !!(main_~i~0 < main_~j~0); 4909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4910#L12-2 assume !!(main_~i~0 < main_~j~0); 4911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4915#L12-2 assume !!(main_~i~0 < main_~j~0); 4964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4963#L12-2 assume !!(main_~i~0 < main_~j~0); 4962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4961#L12-2 assume !!(main_~i~0 < main_~j~0); 4960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4959#L12-2 assume !!(main_~i~0 < main_~j~0); 4958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4957#L12-2 assume !!(main_~i~0 < main_~j~0); 4956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4955#L12-2 assume !!(main_~i~0 < main_~j~0); 4954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4953#L12-2 assume !!(main_~i~0 < main_~j~0); 4952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4951#L12-2 assume !!(main_~i~0 < main_~j~0); 4950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4949#L12-2 assume !!(main_~i~0 < main_~j~0); 4948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4947#L12-2 assume !!(main_~i~0 < main_~j~0); 4946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4945#L12-2 assume !!(main_~i~0 < main_~j~0); 4944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4943#L12-2 assume !!(main_~i~0 < main_~j~0); 4942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4941#L12-2 assume !!(main_~i~0 < main_~j~0); 4940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4939#L12-2 assume !!(main_~i~0 < main_~j~0); 4938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4937#L12-2 assume !!(main_~i~0 < main_~j~0); 4936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4935#L12-2 assume !!(main_~i~0 < main_~j~0); 4934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4933#L12-2 assume !!(main_~i~0 < main_~j~0); 4932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4931#L12-2 assume !!(main_~i~0 < main_~j~0); 4930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4929#L12-2 assume !!(main_~i~0 < main_~j~0); 4928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4927#L12-2 assume !!(main_~i~0 < main_~j~0); 4926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4925#L12-2 assume !!(main_~i~0 < main_~j~0); 4924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4923#L12-2 assume !!(main_~i~0 < main_~j~0); 4922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4921#L12-2 assume !!(main_~i~0 < main_~j~0); 4919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4918#L12-2 assume !!(main_~i~0 < main_~j~0); 4917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4916#L12-2 assume !!(main_~i~0 < main_~j~0); 4913#L12 [2019-12-07 12:13:46,553 INFO L796 eck$LassoCheckResult]: Loop: 4913#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 4914#L12-2 assume !!(main_~i~0 < main_~j~0); 4917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 4916#L12-2 assume !!(main_~i~0 < main_~j~0); 4913#L12 [2019-12-07 12:13:46,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,553 INFO L82 PathProgramCache]: Analyzing trace with hash 1162452124, now seen corresponding path program 26 times [2019-12-07 12:13:46,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059477659] [2019-12-07 12:13:46,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,564 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,564 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 24 times [2019-12-07 12:13:46,564 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,564 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613763373] [2019-12-07 12:13:46,564 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,566 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,566 INFO L82 PathProgramCache]: Analyzing trace with hash 397993812, now seen corresponding path program 26 times [2019-12-07 12:13:46,566 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,566 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024730103] [2019-12-07 12:13:46,566 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:46,816 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,816 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024730103] [2019-12-07 12:13:46,816 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1171096166] [2019-12-07 12:13:46,816 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:46,848 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:46,848 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:46,849 INFO L264 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 28 conjunts are in the unsatisfiable core [2019-12-07 12:13:46,849 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:46,856 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 81 proven. 702 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:46,856 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:46,857 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2019-12-07 12:13:46,857 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386303240] [2019-12-07 12:13:46,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:46,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 12:13:46,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2019-12-07 12:13:46,880 INFO L87 Difference]: Start difference. First operand 57 states and 59 transitions. cyclomatic complexity: 3 Second operand 29 states. [2019-12-07 12:13:46,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:46,921 INFO L93 Difference]: Finished difference Result 61 states and 63 transitions. [2019-12-07 12:13:46,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 12:13:46,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 63 transitions. [2019-12-07 12:13:46,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 60 states and 62 transitions. [2019-12-07 12:13:46,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:46,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:46,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 62 transitions. [2019-12-07 12:13:46,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:46,923 INFO L688 BuchiCegarLoop]: Abstraction has 60 states and 62 transitions. [2019-12-07 12:13:46,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 62 transitions. [2019-12-07 12:13:46,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 59. [2019-12-07 12:13:46,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2019-12-07 12:13:46,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 61 transitions. [2019-12-07 12:13:46,924 INFO L711 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2019-12-07 12:13:46,924 INFO L591 BuchiCegarLoop]: Abstraction has 59 states and 61 transitions. [2019-12-07 12:13:46,924 INFO L424 BuchiCegarLoop]: ======== Iteration 29============ [2019-12-07 12:13:46,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 61 transitions. [2019-12-07 12:13:46,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:46,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:46,924 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:46,925 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 1] [2019-12-07 12:13:46,925 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:46,925 INFO L794 eck$LassoCheckResult]: Stem: 5235#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5231#L12-2 assume !!(main_~i~0 < main_~j~0); 5232#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5233#L12-2 assume !!(main_~i~0 < main_~j~0); 5234#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5238#L12-2 assume !!(main_~i~0 < main_~j~0); 5289#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5288#L12-2 assume !!(main_~i~0 < main_~j~0); 5287#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5286#L12-2 assume !!(main_~i~0 < main_~j~0); 5285#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5284#L12-2 assume !!(main_~i~0 < main_~j~0); 5283#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5282#L12-2 assume !!(main_~i~0 < main_~j~0); 5281#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5280#L12-2 assume !!(main_~i~0 < main_~j~0); 5279#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5278#L12-2 assume !!(main_~i~0 < main_~j~0); 5277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5276#L12-2 assume !!(main_~i~0 < main_~j~0); 5275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5274#L12-2 assume !!(main_~i~0 < main_~j~0); 5273#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5272#L12-2 assume !!(main_~i~0 < main_~j~0); 5271#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5270#L12-2 assume !!(main_~i~0 < main_~j~0); 5269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5268#L12-2 assume !!(main_~i~0 < main_~j~0); 5267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5266#L12-2 assume !!(main_~i~0 < main_~j~0); 5265#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5264#L12-2 assume !!(main_~i~0 < main_~j~0); 5263#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5262#L12-2 assume !!(main_~i~0 < main_~j~0); 5261#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5260#L12-2 assume !!(main_~i~0 < main_~j~0); 5259#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5258#L12-2 assume !!(main_~i~0 < main_~j~0); 5257#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5256#L12-2 assume !!(main_~i~0 < main_~j~0); 5255#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5254#L12-2 assume !!(main_~i~0 < main_~j~0); 5253#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5252#L12-2 assume !!(main_~i~0 < main_~j~0); 5251#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5250#L12-2 assume !!(main_~i~0 < main_~j~0); 5249#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5248#L12-2 assume !!(main_~i~0 < main_~j~0); 5247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5246#L12-2 assume !!(main_~i~0 < main_~j~0); 5245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5244#L12-2 assume !!(main_~i~0 < main_~j~0); 5242#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5241#L12-2 assume !!(main_~i~0 < main_~j~0); 5240#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5239#L12-2 assume !!(main_~i~0 < main_~j~0); 5236#L12 [2019-12-07 12:13:46,925 INFO L796 eck$LassoCheckResult]: Loop: 5236#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5237#L12-2 assume !!(main_~i~0 < main_~j~0); 5240#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5239#L12-2 assume !!(main_~i~0 < main_~j~0); 5236#L12 [2019-12-07 12:13:46,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,925 INFO L82 PathProgramCache]: Analyzing trace with hash 424994617, now seen corresponding path program 27 times [2019-12-07 12:13:46,925 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,925 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143293818] [2019-12-07 12:13:46,925 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,938 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,938 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 25 times [2019-12-07 12:13:46,938 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,938 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029268353] [2019-12-07 12:13:46,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:46,941 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:46,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:46,941 INFO L82 PathProgramCache]: Analyzing trace with hash 162765681, now seen corresponding path program 27 times [2019-12-07 12:13:46,941 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:46,941 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457025608] [2019-12-07 12:13:46,941 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:46,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:47,211 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:47,211 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457025608] [2019-12-07 12:13:47,211 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [786993329] [2019-12-07 12:13:47,211 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:47,248 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2019-12-07 12:13:47,248 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:47,249 INFO L264 TraceCheckSpWp]: Trace formula consists of 181 conjuncts, 29 conjunts are in the unsatisfiable core [2019-12-07 12:13:47,250 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:47,258 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 84 proven. 756 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:47,258 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:47,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2019-12-07 12:13:47,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707933669] [2019-12-07 12:13:47,281 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:47,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 12:13:47,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2019-12-07 12:13:47,282 INFO L87 Difference]: Start difference. First operand 59 states and 61 transitions. cyclomatic complexity: 3 Second operand 30 states. [2019-12-07 12:13:47,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:47,332 INFO L93 Difference]: Finished difference Result 63 states and 65 transitions. [2019-12-07 12:13:47,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 12:13:47,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 65 transitions. [2019-12-07 12:13:47,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:47,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 62 states and 64 transitions. [2019-12-07 12:13:47,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:47,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:47,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 64 transitions. [2019-12-07 12:13:47,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:47,333 INFO L688 BuchiCegarLoop]: Abstraction has 62 states and 64 transitions. [2019-12-07 12:13:47,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 64 transitions. [2019-12-07 12:13:47,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2019-12-07 12:13:47,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2019-12-07 12:13:47,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 63 transitions. [2019-12-07 12:13:47,334 INFO L711 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2019-12-07 12:13:47,334 INFO L591 BuchiCegarLoop]: Abstraction has 61 states and 63 transitions. [2019-12-07 12:13:47,334 INFO L424 BuchiCegarLoop]: ======== Iteration 30============ [2019-12-07 12:13:47,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 63 transitions. [2019-12-07 12:13:47,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:47,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:47,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:47,335 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [29, 28, 1] [2019-12-07 12:13:47,335 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:47,335 INFO L794 eck$LassoCheckResult]: Stem: 5569#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5565#L12-2 assume !!(main_~i~0 < main_~j~0); 5566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5567#L12-2 assume !!(main_~i~0 < main_~j~0); 5568#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5572#L12-2 assume !!(main_~i~0 < main_~j~0); 5625#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5624#L12-2 assume !!(main_~i~0 < main_~j~0); 5623#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5622#L12-2 assume !!(main_~i~0 < main_~j~0); 5621#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5620#L12-2 assume !!(main_~i~0 < main_~j~0); 5619#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5618#L12-2 assume !!(main_~i~0 < main_~j~0); 5617#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5616#L12-2 assume !!(main_~i~0 < main_~j~0); 5615#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5614#L12-2 assume !!(main_~i~0 < main_~j~0); 5613#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5612#L12-2 assume !!(main_~i~0 < main_~j~0); 5611#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5610#L12-2 assume !!(main_~i~0 < main_~j~0); 5609#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5608#L12-2 assume !!(main_~i~0 < main_~j~0); 5607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5606#L12-2 assume !!(main_~i~0 < main_~j~0); 5605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5604#L12-2 assume !!(main_~i~0 < main_~j~0); 5603#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5602#L12-2 assume !!(main_~i~0 < main_~j~0); 5601#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5600#L12-2 assume !!(main_~i~0 < main_~j~0); 5599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5598#L12-2 assume !!(main_~i~0 < main_~j~0); 5597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5596#L12-2 assume !!(main_~i~0 < main_~j~0); 5595#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5594#L12-2 assume !!(main_~i~0 < main_~j~0); 5593#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5592#L12-2 assume !!(main_~i~0 < main_~j~0); 5591#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5590#L12-2 assume !!(main_~i~0 < main_~j~0); 5589#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5588#L12-2 assume !!(main_~i~0 < main_~j~0); 5587#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5586#L12-2 assume !!(main_~i~0 < main_~j~0); 5585#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5584#L12-2 assume !!(main_~i~0 < main_~j~0); 5583#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5582#L12-2 assume !!(main_~i~0 < main_~j~0); 5581#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5580#L12-2 assume !!(main_~i~0 < main_~j~0); 5579#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5578#L12-2 assume !!(main_~i~0 < main_~j~0); 5576#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5575#L12-2 assume !!(main_~i~0 < main_~j~0); 5574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5573#L12-2 assume !!(main_~i~0 < main_~j~0); 5570#L12 [2019-12-07 12:13:47,335 INFO L796 eck$LassoCheckResult]: Loop: 5570#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5571#L12-2 assume !!(main_~i~0 < main_~j~0); 5574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5573#L12-2 assume !!(main_~i~0 < main_~j~0); 5570#L12 [2019-12-07 12:13:47,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,336 INFO L82 PathProgramCache]: Analyzing trace with hash 397934230, now seen corresponding path program 28 times [2019-12-07 12:13:47,336 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,336 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180507612] [2019-12-07 12:13:47,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,347 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:47,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,347 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 26 times [2019-12-07 12:13:47,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178336139] [2019-12-07 12:13:47,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,349 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:47,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1741798478, now seen corresponding path program 28 times [2019-12-07 12:13:47,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,350 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309698933] [2019-12-07 12:13:47,350 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:47,643 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:47,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309698933] [2019-12-07 12:13:47,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1923980521] [2019-12-07 12:13:47,643 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:47,669 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:47,669 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:47,670 INFO L264 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 12:13:47,670 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:47,679 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 87 proven. 812 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:47,679 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:47,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2019-12-07 12:13:47,680 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176145288] [2019-12-07 12:13:47,709 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:47,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 12:13:47,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2019-12-07 12:13:47,710 INFO L87 Difference]: Start difference. First operand 61 states and 63 transitions. cyclomatic complexity: 3 Second operand 31 states. [2019-12-07 12:13:47,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:47,762 INFO L93 Difference]: Finished difference Result 65 states and 67 transitions. [2019-12-07 12:13:47,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 12:13:47,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 67 transitions. [2019-12-07 12:13:47,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:47,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 64 states and 66 transitions. [2019-12-07 12:13:47,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:47,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:47,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 66 transitions. [2019-12-07 12:13:47,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:47,763 INFO L688 BuchiCegarLoop]: Abstraction has 64 states and 66 transitions. [2019-12-07 12:13:47,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 66 transitions. [2019-12-07 12:13:47,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2019-12-07 12:13:47,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2019-12-07 12:13:47,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2019-12-07 12:13:47,764 INFO L711 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2019-12-07 12:13:47,764 INFO L591 BuchiCegarLoop]: Abstraction has 63 states and 65 transitions. [2019-12-07 12:13:47,764 INFO L424 BuchiCegarLoop]: ======== Iteration 31============ [2019-12-07 12:13:47,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 65 transitions. [2019-12-07 12:13:47,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:47,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:47,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:47,765 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [30, 29, 1] [2019-12-07 12:13:47,765 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:47,765 INFO L794 eck$LassoCheckResult]: Stem: 5914#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 5910#L12-2 assume !!(main_~i~0 < main_~j~0); 5911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5912#L12-2 assume !!(main_~i~0 < main_~j~0); 5913#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5917#L12-2 assume !!(main_~i~0 < main_~j~0); 5972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5971#L12-2 assume !!(main_~i~0 < main_~j~0); 5970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5969#L12-2 assume !!(main_~i~0 < main_~j~0); 5968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5967#L12-2 assume !!(main_~i~0 < main_~j~0); 5966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5965#L12-2 assume !!(main_~i~0 < main_~j~0); 5964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5963#L12-2 assume !!(main_~i~0 < main_~j~0); 5962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5961#L12-2 assume !!(main_~i~0 < main_~j~0); 5960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5959#L12-2 assume !!(main_~i~0 < main_~j~0); 5958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5957#L12-2 assume !!(main_~i~0 < main_~j~0); 5956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5955#L12-2 assume !!(main_~i~0 < main_~j~0); 5954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5953#L12-2 assume !!(main_~i~0 < main_~j~0); 5952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5951#L12-2 assume !!(main_~i~0 < main_~j~0); 5950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5949#L12-2 assume !!(main_~i~0 < main_~j~0); 5948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5947#L12-2 assume !!(main_~i~0 < main_~j~0); 5946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5945#L12-2 assume !!(main_~i~0 < main_~j~0); 5944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5943#L12-2 assume !!(main_~i~0 < main_~j~0); 5942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5941#L12-2 assume !!(main_~i~0 < main_~j~0); 5940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5939#L12-2 assume !!(main_~i~0 < main_~j~0); 5938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5937#L12-2 assume !!(main_~i~0 < main_~j~0); 5936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5935#L12-2 assume !!(main_~i~0 < main_~j~0); 5934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5933#L12-2 assume !!(main_~i~0 < main_~j~0); 5932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5931#L12-2 assume !!(main_~i~0 < main_~j~0); 5930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5929#L12-2 assume !!(main_~i~0 < main_~j~0); 5928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5927#L12-2 assume !!(main_~i~0 < main_~j~0); 5926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5925#L12-2 assume !!(main_~i~0 < main_~j~0); 5924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5923#L12-2 assume !!(main_~i~0 < main_~j~0); 5921#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5920#L12-2 assume !!(main_~i~0 < main_~j~0); 5919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5918#L12-2 assume !!(main_~i~0 < main_~j~0); 5915#L12 [2019-12-07 12:13:47,765 INFO L796 eck$LassoCheckResult]: Loop: 5915#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 5916#L12-2 assume !!(main_~i~0 < main_~j~0); 5919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 5918#L12-2 assume !!(main_~i~0 < main_~j~0); 5915#L12 [2019-12-07 12:13:47,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,765 INFO L82 PathProgramCache]: Analyzing trace with hash 162706099, now seen corresponding path program 29 times [2019-12-07 12:13:47,765 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,765 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121722843] [2019-12-07 12:13:47,765 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,780 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:47,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 27 times [2019-12-07 12:13:47,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572432800] [2019-12-07 12:13:47,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:47,783 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:47,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:47,783 INFO L82 PathProgramCache]: Analyzing trace with hash -1226106389, now seen corresponding path program 29 times [2019-12-07 12:13:47,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:47,784 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102259244] [2019-12-07 12:13:47,784 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:47,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:48,118 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:48,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102259244] [2019-12-07 12:13:48,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1724642060] [2019-12-07 12:13:48,118 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:48,157 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 32 check-sat command(s) [2019-12-07 12:13:48,157 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:48,159 INFO L264 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 12:13:48,159 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:48,167 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 90 proven. 870 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:48,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:48,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2019-12-07 12:13:48,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969033851] [2019-12-07 12:13:48,194 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:48,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-12-07 12:13:48,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2019-12-07 12:13:48,195 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. cyclomatic complexity: 3 Second operand 32 states. [2019-12-07 12:13:48,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:48,254 INFO L93 Difference]: Finished difference Result 67 states and 69 transitions. [2019-12-07 12:13:48,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 12:13:48,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 69 transitions. [2019-12-07 12:13:48,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:48,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 66 states and 68 transitions. [2019-12-07 12:13:48,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:48,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:48,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 68 transitions. [2019-12-07 12:13:48,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:48,255 INFO L688 BuchiCegarLoop]: Abstraction has 66 states and 68 transitions. [2019-12-07 12:13:48,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 68 transitions. [2019-12-07 12:13:48,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 65. [2019-12-07 12:13:48,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2019-12-07 12:13:48,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 67 transitions. [2019-12-07 12:13:48,256 INFO L711 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2019-12-07 12:13:48,256 INFO L591 BuchiCegarLoop]: Abstraction has 65 states and 67 transitions. [2019-12-07 12:13:48,256 INFO L424 BuchiCegarLoop]: ======== Iteration 32============ [2019-12-07 12:13:48,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 67 transitions. [2019-12-07 12:13:48,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:48,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:48,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:48,257 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [31, 30, 1] [2019-12-07 12:13:48,257 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:48,257 INFO L794 eck$LassoCheckResult]: Stem: 6270#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 6266#L12-2 assume !!(main_~i~0 < main_~j~0); 6267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6268#L12-2 assume !!(main_~i~0 < main_~j~0); 6269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6273#L12-2 assume !!(main_~i~0 < main_~j~0); 6330#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6329#L12-2 assume !!(main_~i~0 < main_~j~0); 6328#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6327#L12-2 assume !!(main_~i~0 < main_~j~0); 6326#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6325#L12-2 assume !!(main_~i~0 < main_~j~0); 6324#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6323#L12-2 assume !!(main_~i~0 < main_~j~0); 6322#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6321#L12-2 assume !!(main_~i~0 < main_~j~0); 6320#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6319#L12-2 assume !!(main_~i~0 < main_~j~0); 6318#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6317#L12-2 assume !!(main_~i~0 < main_~j~0); 6316#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6315#L12-2 assume !!(main_~i~0 < main_~j~0); 6314#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6313#L12-2 assume !!(main_~i~0 < main_~j~0); 6312#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6311#L12-2 assume !!(main_~i~0 < main_~j~0); 6310#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6309#L12-2 assume !!(main_~i~0 < main_~j~0); 6308#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6307#L12-2 assume !!(main_~i~0 < main_~j~0); 6306#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6305#L12-2 assume !!(main_~i~0 < main_~j~0); 6304#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6303#L12-2 assume !!(main_~i~0 < main_~j~0); 6302#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6301#L12-2 assume !!(main_~i~0 < main_~j~0); 6300#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6299#L12-2 assume !!(main_~i~0 < main_~j~0); 6298#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6297#L12-2 assume !!(main_~i~0 < main_~j~0); 6296#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6295#L12-2 assume !!(main_~i~0 < main_~j~0); 6294#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6293#L12-2 assume !!(main_~i~0 < main_~j~0); 6292#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6291#L12-2 assume !!(main_~i~0 < main_~j~0); 6290#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6289#L12-2 assume !!(main_~i~0 < main_~j~0); 6288#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6287#L12-2 assume !!(main_~i~0 < main_~j~0); 6286#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6285#L12-2 assume !!(main_~i~0 < main_~j~0); 6284#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6283#L12-2 assume !!(main_~i~0 < main_~j~0); 6282#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6281#L12-2 assume !!(main_~i~0 < main_~j~0); 6280#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6279#L12-2 assume !!(main_~i~0 < main_~j~0); 6277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6276#L12-2 assume !!(main_~i~0 < main_~j~0); 6275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6274#L12-2 assume !!(main_~i~0 < main_~j~0); 6271#L12 [2019-12-07 12:13:48,257 INFO L796 eck$LassoCheckResult]: Loop: 6271#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 6272#L12-2 assume !!(main_~i~0 < main_~j~0); 6275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6274#L12-2 assume !!(main_~i~0 < main_~j~0); 6271#L12 [2019-12-07 12:13:48,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,257 INFO L82 PathProgramCache]: Analyzing trace with hash 1741738896, now seen corresponding path program 30 times [2019-12-07 12:13:48,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050916833] [2019-12-07 12:13:48,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,269 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:48,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,270 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 28 times [2019-12-07 12:13:48,270 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,270 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583857034] [2019-12-07 12:13:48,270 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,272 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:48,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,272 INFO L82 PathProgramCache]: Analyzing trace with hash -1524399032, now seen corresponding path program 30 times [2019-12-07 12:13:48,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,272 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524645014] [2019-12-07 12:13:48,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:48,597 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:48,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524645014] [2019-12-07 12:13:48,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1523063469] [2019-12-07 12:13:48,597 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:48,638 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 33 check-sat command(s) [2019-12-07 12:13:48,638 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:48,639 INFO L264 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 32 conjunts are in the unsatisfiable core [2019-12-07 12:13:48,640 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:48,648 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 93 proven. 930 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:48,648 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:48,648 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2019-12-07 12:13:48,648 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518245957] [2019-12-07 12:13:48,672 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:48,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 12:13:48,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 12:13:48,672 INFO L87 Difference]: Start difference. First operand 65 states and 67 transitions. cyclomatic complexity: 3 Second operand 33 states. [2019-12-07 12:13:48,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:48,732 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2019-12-07 12:13:48,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 12:13:48,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 71 transitions. [2019-12-07 12:13:48,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:48,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 68 states and 70 transitions. [2019-12-07 12:13:48,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:48,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:48,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 70 transitions. [2019-12-07 12:13:48,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:48,734 INFO L688 BuchiCegarLoop]: Abstraction has 68 states and 70 transitions. [2019-12-07 12:13:48,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 70 transitions. [2019-12-07 12:13:48,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 67. [2019-12-07 12:13:48,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2019-12-07 12:13:48,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 69 transitions. [2019-12-07 12:13:48,735 INFO L711 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2019-12-07 12:13:48,735 INFO L591 BuchiCegarLoop]: Abstraction has 67 states and 69 transitions. [2019-12-07 12:13:48,735 INFO L424 BuchiCegarLoop]: ======== Iteration 33============ [2019-12-07 12:13:48,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 69 transitions. [2019-12-07 12:13:48,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:48,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:48,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:48,736 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [32, 31, 1] [2019-12-07 12:13:48,736 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:48,736 INFO L794 eck$LassoCheckResult]: Stem: 6637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 6633#L12-2 assume !!(main_~i~0 < main_~j~0); 6634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6635#L12-2 assume !!(main_~i~0 < main_~j~0); 6636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6640#L12-2 assume !!(main_~i~0 < main_~j~0); 6699#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6698#L12-2 assume !!(main_~i~0 < main_~j~0); 6697#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6696#L12-2 assume !!(main_~i~0 < main_~j~0); 6695#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6694#L12-2 assume !!(main_~i~0 < main_~j~0); 6693#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6692#L12-2 assume !!(main_~i~0 < main_~j~0); 6691#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6690#L12-2 assume !!(main_~i~0 < main_~j~0); 6689#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6688#L12-2 assume !!(main_~i~0 < main_~j~0); 6687#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6686#L12-2 assume !!(main_~i~0 < main_~j~0); 6685#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6684#L12-2 assume !!(main_~i~0 < main_~j~0); 6683#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6682#L12-2 assume !!(main_~i~0 < main_~j~0); 6681#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6680#L12-2 assume !!(main_~i~0 < main_~j~0); 6679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6678#L12-2 assume !!(main_~i~0 < main_~j~0); 6677#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6676#L12-2 assume !!(main_~i~0 < main_~j~0); 6675#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6674#L12-2 assume !!(main_~i~0 < main_~j~0); 6673#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6672#L12-2 assume !!(main_~i~0 < main_~j~0); 6671#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6670#L12-2 assume !!(main_~i~0 < main_~j~0); 6669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6668#L12-2 assume !!(main_~i~0 < main_~j~0); 6667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6666#L12-2 assume !!(main_~i~0 < main_~j~0); 6665#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6664#L12-2 assume !!(main_~i~0 < main_~j~0); 6663#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6662#L12-2 assume !!(main_~i~0 < main_~j~0); 6661#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6660#L12-2 assume !!(main_~i~0 < main_~j~0); 6659#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6658#L12-2 assume !!(main_~i~0 < main_~j~0); 6657#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6656#L12-2 assume !!(main_~i~0 < main_~j~0); 6655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6654#L12-2 assume !!(main_~i~0 < main_~j~0); 6653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6652#L12-2 assume !!(main_~i~0 < main_~j~0); 6651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6650#L12-2 assume !!(main_~i~0 < main_~j~0); 6649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6648#L12-2 assume !!(main_~i~0 < main_~j~0); 6647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6646#L12-2 assume !!(main_~i~0 < main_~j~0); 6644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6643#L12-2 assume !!(main_~i~0 < main_~j~0); 6642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6641#L12-2 assume !!(main_~i~0 < main_~j~0); 6638#L12 [2019-12-07 12:13:48,736 INFO L796 eck$LassoCheckResult]: Loop: 6638#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 6639#L12-2 assume !!(main_~i~0 < main_~j~0); 6642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 6641#L12-2 assume !!(main_~i~0 < main_~j~0); 6638#L12 [2019-12-07 12:13:48,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,736 INFO L82 PathProgramCache]: Analyzing trace with hash -1226165971, now seen corresponding path program 31 times [2019-12-07 12:13:48,737 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,737 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056203836] [2019-12-07 12:13:48,737 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,749 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:48,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 29 times [2019-12-07 12:13:48,750 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,750 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19144756] [2019-12-07 12:13:48,750 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:48,752 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:48,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:48,752 INFO L82 PathProgramCache]: Analyzing trace with hash -420820123, now seen corresponding path program 31 times [2019-12-07 12:13:48,752 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:48,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353256958] [2019-12-07 12:13:48,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:48,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:49,092 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:49,092 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353256958] [2019-12-07 12:13:49,092 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1720809852] [2019-12-07 12:13:49,092 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:49,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:49,120 INFO L264 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 12:13:49,121 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:49,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 96 proven. 992 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:49,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:49,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2019-12-07 12:13:49,130 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426093347] [2019-12-07 12:13:49,154 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:49,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-12-07 12:13:49,155 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 12:13:49,155 INFO L87 Difference]: Start difference. First operand 67 states and 69 transitions. cyclomatic complexity: 3 Second operand 34 states. [2019-12-07 12:13:49,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:49,210 INFO L93 Difference]: Finished difference Result 71 states and 73 transitions. [2019-12-07 12:13:49,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 12:13:49,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 73 transitions. [2019-12-07 12:13:49,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:49,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 70 states and 72 transitions. [2019-12-07 12:13:49,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:49,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:49,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 72 transitions. [2019-12-07 12:13:49,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:49,212 INFO L688 BuchiCegarLoop]: Abstraction has 70 states and 72 transitions. [2019-12-07 12:13:49,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 72 transitions. [2019-12-07 12:13:49,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2019-12-07 12:13:49,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2019-12-07 12:13:49,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 71 transitions. [2019-12-07 12:13:49,217 INFO L711 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2019-12-07 12:13:49,217 INFO L591 BuchiCegarLoop]: Abstraction has 69 states and 71 transitions. [2019-12-07 12:13:49,217 INFO L424 BuchiCegarLoop]: ======== Iteration 34============ [2019-12-07 12:13:49,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 71 transitions. [2019-12-07 12:13:49,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:49,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:49,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:49,218 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [33, 32, 1] [2019-12-07 12:13:49,218 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:49,218 INFO L794 eck$LassoCheckResult]: Stem: 7015#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7011#L12-2 assume !!(main_~i~0 < main_~j~0); 7012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7013#L12-2 assume !!(main_~i~0 < main_~j~0); 7014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7018#L12-2 assume !!(main_~i~0 < main_~j~0); 7079#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7078#L12-2 assume !!(main_~i~0 < main_~j~0); 7077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7076#L12-2 assume !!(main_~i~0 < main_~j~0); 7075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7074#L12-2 assume !!(main_~i~0 < main_~j~0); 7073#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7072#L12-2 assume !!(main_~i~0 < main_~j~0); 7071#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7070#L12-2 assume !!(main_~i~0 < main_~j~0); 7069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7068#L12-2 assume !!(main_~i~0 < main_~j~0); 7067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7066#L12-2 assume !!(main_~i~0 < main_~j~0); 7065#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7064#L12-2 assume !!(main_~i~0 < main_~j~0); 7063#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7062#L12-2 assume !!(main_~i~0 < main_~j~0); 7061#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7060#L12-2 assume !!(main_~i~0 < main_~j~0); 7059#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7058#L12-2 assume !!(main_~i~0 < main_~j~0); 7057#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7056#L12-2 assume !!(main_~i~0 < main_~j~0); 7055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7054#L12-2 assume !!(main_~i~0 < main_~j~0); 7053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7052#L12-2 assume !!(main_~i~0 < main_~j~0); 7051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7050#L12-2 assume !!(main_~i~0 < main_~j~0); 7049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7048#L12-2 assume !!(main_~i~0 < main_~j~0); 7047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7046#L12-2 assume !!(main_~i~0 < main_~j~0); 7045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7044#L12-2 assume !!(main_~i~0 < main_~j~0); 7043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7042#L12-2 assume !!(main_~i~0 < main_~j~0); 7041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7040#L12-2 assume !!(main_~i~0 < main_~j~0); 7039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7038#L12-2 assume !!(main_~i~0 < main_~j~0); 7037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7036#L12-2 assume !!(main_~i~0 < main_~j~0); 7035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7034#L12-2 assume !!(main_~i~0 < main_~j~0); 7033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7032#L12-2 assume !!(main_~i~0 < main_~j~0); 7031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7030#L12-2 assume !!(main_~i~0 < main_~j~0); 7029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7028#L12-2 assume !!(main_~i~0 < main_~j~0); 7027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7026#L12-2 assume !!(main_~i~0 < main_~j~0); 7025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7024#L12-2 assume !!(main_~i~0 < main_~j~0); 7022#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7021#L12-2 assume !!(main_~i~0 < main_~j~0); 7020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7019#L12-2 assume !!(main_~i~0 < main_~j~0); 7016#L12 [2019-12-07 12:13:49,218 INFO L796 eck$LassoCheckResult]: Loop: 7016#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7017#L12-2 assume !!(main_~i~0 < main_~j~0); 7020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7019#L12-2 assume !!(main_~i~0 < main_~j~0); 7016#L12 [2019-12-07 12:13:49,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1524458614, now seen corresponding path program 32 times [2019-12-07 12:13:49,218 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,218 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461116873] [2019-12-07 12:13:49,219 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,238 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:49,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 30 times [2019-12-07 12:13:49,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,239 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160337391] [2019-12-07 12:13:49,239 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,241 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:49,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,241 INFO L82 PathProgramCache]: Analyzing trace with hash -738410686, now seen corresponding path program 32 times [2019-12-07 12:13:49,242 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,242 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556903614] [2019-12-07 12:13:49,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:49,595 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:49,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556903614] [2019-12-07 12:13:49,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1269070723] [2019-12-07 12:13:49,595 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:49,623 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:49,623 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:49,624 INFO L264 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 34 conjunts are in the unsatisfiable core [2019-12-07 12:13:49,625 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:49,635 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 99 proven. 1056 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:49,635 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:49,635 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2019-12-07 12:13:49,635 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609046325] [2019-12-07 12:13:49,659 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:49,659 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-12-07 12:13:49,659 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 12:13:49,659 INFO L87 Difference]: Start difference. First operand 69 states and 71 transitions. cyclomatic complexity: 3 Second operand 35 states. [2019-12-07 12:13:49,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:49,722 INFO L93 Difference]: Finished difference Result 73 states and 75 transitions. [2019-12-07 12:13:49,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 12:13:49,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 75 transitions. [2019-12-07 12:13:49,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:49,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 72 states and 74 transitions. [2019-12-07 12:13:49,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:49,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:49,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 74 transitions. [2019-12-07 12:13:49,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:49,723 INFO L688 BuchiCegarLoop]: Abstraction has 72 states and 74 transitions. [2019-12-07 12:13:49,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 74 transitions. [2019-12-07 12:13:49,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 71. [2019-12-07 12:13:49,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2019-12-07 12:13:49,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 73 transitions. [2019-12-07 12:13:49,724 INFO L711 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2019-12-07 12:13:49,724 INFO L591 BuchiCegarLoop]: Abstraction has 71 states and 73 transitions. [2019-12-07 12:13:49,724 INFO L424 BuchiCegarLoop]: ======== Iteration 35============ [2019-12-07 12:13:49,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 73 transitions. [2019-12-07 12:13:49,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:49,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:49,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:49,725 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [34, 33, 1] [2019-12-07 12:13:49,725 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:49,725 INFO L794 eck$LassoCheckResult]: Stem: 7404#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7400#L12-2 assume !!(main_~i~0 < main_~j~0); 7401#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7402#L12-2 assume !!(main_~i~0 < main_~j~0); 7403#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7407#L12-2 assume !!(main_~i~0 < main_~j~0); 7470#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7469#L12-2 assume !!(main_~i~0 < main_~j~0); 7468#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7467#L12-2 assume !!(main_~i~0 < main_~j~0); 7466#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7465#L12-2 assume !!(main_~i~0 < main_~j~0); 7464#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7463#L12-2 assume !!(main_~i~0 < main_~j~0); 7462#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7461#L12-2 assume !!(main_~i~0 < main_~j~0); 7460#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7459#L12-2 assume !!(main_~i~0 < main_~j~0); 7458#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7457#L12-2 assume !!(main_~i~0 < main_~j~0); 7456#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7455#L12-2 assume !!(main_~i~0 < main_~j~0); 7454#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7453#L12-2 assume !!(main_~i~0 < main_~j~0); 7452#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7451#L12-2 assume !!(main_~i~0 < main_~j~0); 7450#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7449#L12-2 assume !!(main_~i~0 < main_~j~0); 7448#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7447#L12-2 assume !!(main_~i~0 < main_~j~0); 7446#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7445#L12-2 assume !!(main_~i~0 < main_~j~0); 7444#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7443#L12-2 assume !!(main_~i~0 < main_~j~0); 7442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7441#L12-2 assume !!(main_~i~0 < main_~j~0); 7440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7439#L12-2 assume !!(main_~i~0 < main_~j~0); 7438#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7437#L12-2 assume !!(main_~i~0 < main_~j~0); 7436#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7435#L12-2 assume !!(main_~i~0 < main_~j~0); 7434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7433#L12-2 assume !!(main_~i~0 < main_~j~0); 7432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7431#L12-2 assume !!(main_~i~0 < main_~j~0); 7430#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7429#L12-2 assume !!(main_~i~0 < main_~j~0); 7428#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7427#L12-2 assume !!(main_~i~0 < main_~j~0); 7426#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7425#L12-2 assume !!(main_~i~0 < main_~j~0); 7424#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7423#L12-2 assume !!(main_~i~0 < main_~j~0); 7422#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7421#L12-2 assume !!(main_~i~0 < main_~j~0); 7420#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7419#L12-2 assume !!(main_~i~0 < main_~j~0); 7418#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7417#L12-2 assume !!(main_~i~0 < main_~j~0); 7416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7415#L12-2 assume !!(main_~i~0 < main_~j~0); 7414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7413#L12-2 assume !!(main_~i~0 < main_~j~0); 7411#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7410#L12-2 assume !!(main_~i~0 < main_~j~0); 7409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7408#L12-2 assume !!(main_~i~0 < main_~j~0); 7405#L12 [2019-12-07 12:13:49,725 INFO L796 eck$LassoCheckResult]: Loop: 7405#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7406#L12-2 assume !!(main_~i~0 < main_~j~0); 7409#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7408#L12-2 assume !!(main_~i~0 < main_~j~0); 7405#L12 [2019-12-07 12:13:49,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,725 INFO L82 PathProgramCache]: Analyzing trace with hash -420879705, now seen corresponding path program 33 times [2019-12-07 12:13:49,726 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,726 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980902936] [2019-12-07 12:13:49,726 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,739 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:49,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 31 times [2019-12-07 12:13:49,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098996505] [2019-12-07 12:13:49,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:49,741 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:49,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:49,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1000263713, now seen corresponding path program 33 times [2019-12-07 12:13:49,741 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:49,741 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642819289] [2019-12-07 12:13:49,741 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:49,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:50,110 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:50,110 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642819289] [2019-12-07 12:13:50,110 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1111984668] [2019-12-07 12:13:50,110 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:50,154 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2019-12-07 12:13:50,154 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:50,155 INFO L264 TraceCheckSpWp]: Trace formula consists of 217 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 12:13:50,156 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:50,166 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 102 proven. 1122 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:50,166 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:50,166 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2019-12-07 12:13:50,166 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130140360] [2019-12-07 12:13:50,189 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:50,189 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-12-07 12:13:50,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 12:13:50,190 INFO L87 Difference]: Start difference. First operand 71 states and 73 transitions. cyclomatic complexity: 3 Second operand 36 states. [2019-12-07 12:13:50,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:50,247 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2019-12-07 12:13:50,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 12:13:50,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2019-12-07 12:13:50,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:50,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 74 states and 76 transitions. [2019-12-07 12:13:50,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:50,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:50,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 76 transitions. [2019-12-07 12:13:50,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:50,249 INFO L688 BuchiCegarLoop]: Abstraction has 74 states and 76 transitions. [2019-12-07 12:13:50,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 76 transitions. [2019-12-07 12:13:50,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 73. [2019-12-07 12:13:50,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2019-12-07 12:13:50,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 75 transitions. [2019-12-07 12:13:50,250 INFO L711 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2019-12-07 12:13:50,250 INFO L591 BuchiCegarLoop]: Abstraction has 73 states and 75 transitions. [2019-12-07 12:13:50,250 INFO L424 BuchiCegarLoop]: ======== Iteration 36============ [2019-12-07 12:13:50,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 75 transitions. [2019-12-07 12:13:50,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:50,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:50,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:50,251 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [35, 34, 1] [2019-12-07 12:13:50,251 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:50,251 INFO L794 eck$LassoCheckResult]: Stem: 7804#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 7800#L12-2 assume !!(main_~i~0 < main_~j~0); 7801#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7802#L12-2 assume !!(main_~i~0 < main_~j~0); 7803#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7807#L12-2 assume !!(main_~i~0 < main_~j~0); 7872#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7871#L12-2 assume !!(main_~i~0 < main_~j~0); 7870#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7869#L12-2 assume !!(main_~i~0 < main_~j~0); 7868#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7867#L12-2 assume !!(main_~i~0 < main_~j~0); 7866#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7865#L12-2 assume !!(main_~i~0 < main_~j~0); 7864#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7863#L12-2 assume !!(main_~i~0 < main_~j~0); 7862#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7861#L12-2 assume !!(main_~i~0 < main_~j~0); 7860#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7859#L12-2 assume !!(main_~i~0 < main_~j~0); 7858#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7857#L12-2 assume !!(main_~i~0 < main_~j~0); 7856#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7855#L12-2 assume !!(main_~i~0 < main_~j~0); 7854#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7853#L12-2 assume !!(main_~i~0 < main_~j~0); 7852#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7851#L12-2 assume !!(main_~i~0 < main_~j~0); 7850#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7849#L12-2 assume !!(main_~i~0 < main_~j~0); 7848#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7847#L12-2 assume !!(main_~i~0 < main_~j~0); 7846#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7845#L12-2 assume !!(main_~i~0 < main_~j~0); 7844#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7843#L12-2 assume !!(main_~i~0 < main_~j~0); 7842#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7841#L12-2 assume !!(main_~i~0 < main_~j~0); 7840#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7839#L12-2 assume !!(main_~i~0 < main_~j~0); 7838#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7837#L12-2 assume !!(main_~i~0 < main_~j~0); 7836#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7835#L12-2 assume !!(main_~i~0 < main_~j~0); 7834#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7833#L12-2 assume !!(main_~i~0 < main_~j~0); 7832#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7831#L12-2 assume !!(main_~i~0 < main_~j~0); 7830#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7829#L12-2 assume !!(main_~i~0 < main_~j~0); 7828#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7827#L12-2 assume !!(main_~i~0 < main_~j~0); 7826#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7825#L12-2 assume !!(main_~i~0 < main_~j~0); 7824#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7823#L12-2 assume !!(main_~i~0 < main_~j~0); 7822#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7821#L12-2 assume !!(main_~i~0 < main_~j~0); 7820#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7819#L12-2 assume !!(main_~i~0 < main_~j~0); 7818#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7817#L12-2 assume !!(main_~i~0 < main_~j~0); 7816#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7815#L12-2 assume !!(main_~i~0 < main_~j~0); 7814#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7813#L12-2 assume !!(main_~i~0 < main_~j~0); 7811#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7810#L12-2 assume !!(main_~i~0 < main_~j~0); 7809#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7808#L12-2 assume !!(main_~i~0 < main_~j~0); 7805#L12 [2019-12-07 12:13:50,251 INFO L796 eck$LassoCheckResult]: Loop: 7805#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 7806#L12-2 assume !!(main_~i~0 < main_~j~0); 7809#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 7808#L12-2 assume !!(main_~i~0 < main_~j~0); 7805#L12 [2019-12-07 12:13:50,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,251 INFO L82 PathProgramCache]: Analyzing trace with hash -738470268, now seen corresponding path program 34 times [2019-12-07 12:13:50,251 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,251 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235168641] [2019-12-07 12:13:50,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,265 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:50,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 32 times [2019-12-07 12:13:50,265 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,265 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616591736] [2019-12-07 12:13:50,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,267 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:50,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,267 INFO L82 PathProgramCache]: Analyzing trace with hash 762047804, now seen corresponding path program 34 times [2019-12-07 12:13:50,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249868414] [2019-12-07 12:13:50,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:50,667 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:50,667 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249868414] [2019-12-07 12:13:50,667 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1655389757] [2019-12-07 12:13:50,667 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:50,696 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:50,697 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:50,698 INFO L264 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 36 conjunts are in the unsatisfiable core [2019-12-07 12:13:50,698 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:50,707 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 105 proven. 1190 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:50,708 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:50,708 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2019-12-07 12:13:50,708 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902967245] [2019-12-07 12:13:50,735 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:50,735 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 12:13:50,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 12:13:50,736 INFO L87 Difference]: Start difference. First operand 73 states and 75 transitions. cyclomatic complexity: 3 Second operand 37 states. [2019-12-07 12:13:50,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:50,805 INFO L93 Difference]: Finished difference Result 77 states and 79 transitions. [2019-12-07 12:13:50,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 12:13:50,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 79 transitions. [2019-12-07 12:13:50,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:50,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 76 states and 78 transitions. [2019-12-07 12:13:50,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:50,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:50,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 78 transitions. [2019-12-07 12:13:50,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:50,806 INFO L688 BuchiCegarLoop]: Abstraction has 76 states and 78 transitions. [2019-12-07 12:13:50,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 78 transitions. [2019-12-07 12:13:50,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2019-12-07 12:13:50,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2019-12-07 12:13:50,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2019-12-07 12:13:50,807 INFO L711 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2019-12-07 12:13:50,807 INFO L591 BuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2019-12-07 12:13:50,808 INFO L424 BuchiCegarLoop]: ======== Iteration 37============ [2019-12-07 12:13:50,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2019-12-07 12:13:50,808 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:50,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:50,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:50,808 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [36, 35, 1] [2019-12-07 12:13:50,808 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:50,808 INFO L794 eck$LassoCheckResult]: Stem: 8215#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 8211#L12-2 assume !!(main_~i~0 < main_~j~0); 8212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8213#L12-2 assume !!(main_~i~0 < main_~j~0); 8214#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8218#L12-2 assume !!(main_~i~0 < main_~j~0); 8285#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8284#L12-2 assume !!(main_~i~0 < main_~j~0); 8283#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8282#L12-2 assume !!(main_~i~0 < main_~j~0); 8281#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8280#L12-2 assume !!(main_~i~0 < main_~j~0); 8279#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8278#L12-2 assume !!(main_~i~0 < main_~j~0); 8277#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8276#L12-2 assume !!(main_~i~0 < main_~j~0); 8275#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8274#L12-2 assume !!(main_~i~0 < main_~j~0); 8273#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8272#L12-2 assume !!(main_~i~0 < main_~j~0); 8271#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8270#L12-2 assume !!(main_~i~0 < main_~j~0); 8269#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8268#L12-2 assume !!(main_~i~0 < main_~j~0); 8267#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8266#L12-2 assume !!(main_~i~0 < main_~j~0); 8265#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8264#L12-2 assume !!(main_~i~0 < main_~j~0); 8263#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8262#L12-2 assume !!(main_~i~0 < main_~j~0); 8261#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8260#L12-2 assume !!(main_~i~0 < main_~j~0); 8259#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8258#L12-2 assume !!(main_~i~0 < main_~j~0); 8257#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8256#L12-2 assume !!(main_~i~0 < main_~j~0); 8255#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8254#L12-2 assume !!(main_~i~0 < main_~j~0); 8253#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8252#L12-2 assume !!(main_~i~0 < main_~j~0); 8251#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8250#L12-2 assume !!(main_~i~0 < main_~j~0); 8249#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8248#L12-2 assume !!(main_~i~0 < main_~j~0); 8247#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8246#L12-2 assume !!(main_~i~0 < main_~j~0); 8245#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8244#L12-2 assume !!(main_~i~0 < main_~j~0); 8243#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8242#L12-2 assume !!(main_~i~0 < main_~j~0); 8241#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8240#L12-2 assume !!(main_~i~0 < main_~j~0); 8239#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8238#L12-2 assume !!(main_~i~0 < main_~j~0); 8237#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8236#L12-2 assume !!(main_~i~0 < main_~j~0); 8235#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8234#L12-2 assume !!(main_~i~0 < main_~j~0); 8233#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8232#L12-2 assume !!(main_~i~0 < main_~j~0); 8231#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8230#L12-2 assume !!(main_~i~0 < main_~j~0); 8229#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8228#L12-2 assume !!(main_~i~0 < main_~j~0); 8227#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8226#L12-2 assume !!(main_~i~0 < main_~j~0); 8225#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8224#L12-2 assume !!(main_~i~0 < main_~j~0); 8222#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8221#L12-2 assume !!(main_~i~0 < main_~j~0); 8220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8219#L12-2 assume !!(main_~i~0 < main_~j~0); 8216#L12 [2019-12-07 12:13:50,809 INFO L796 eck$LassoCheckResult]: Loop: 8216#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 8217#L12-2 assume !!(main_~i~0 < main_~j~0); 8220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8219#L12-2 assume !!(main_~i~0 < main_~j~0); 8216#L12 [2019-12-07 12:13:50,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,809 INFO L82 PathProgramCache]: Analyzing trace with hash -1000323295, now seen corresponding path program 35 times [2019-12-07 12:13:50,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,809 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031143421] [2019-12-07 12:13:50,809 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,823 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:50,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,823 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 33 times [2019-12-07 12:13:50,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845404306] [2019-12-07 12:13:50,824 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:50,825 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:50,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:50,825 INFO L82 PathProgramCache]: Analyzing trace with hash 2126301017, now seen corresponding path program 35 times [2019-12-07 12:13:50,825 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:50,825 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669302026] [2019-12-07 12:13:50,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:50,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:51,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:51,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669302026] [2019-12-07 12:13:51,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1934317833] [2019-12-07 12:13:51,236 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:51,283 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 38 check-sat command(s) [2019-12-07 12:13:51,283 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:51,284 INFO L264 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 37 conjunts are in the unsatisfiable core [2019-12-07 12:13:51,285 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:51,297 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 108 proven. 1260 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:51,297 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:51,297 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2019-12-07 12:13:51,297 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489976181] [2019-12-07 12:13:51,321 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:51,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-12-07 12:13:51,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 12:13:51,322 INFO L87 Difference]: Start difference. First operand 75 states and 77 transitions. cyclomatic complexity: 3 Second operand 38 states. [2019-12-07 12:13:51,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:51,383 INFO L93 Difference]: Finished difference Result 79 states and 81 transitions. [2019-12-07 12:13:51,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 12:13:51,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 81 transitions. [2019-12-07 12:13:51,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:51,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 78 states and 80 transitions. [2019-12-07 12:13:51,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:51,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:51,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 80 transitions. [2019-12-07 12:13:51,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:51,384 INFO L688 BuchiCegarLoop]: Abstraction has 78 states and 80 transitions. [2019-12-07 12:13:51,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 80 transitions. [2019-12-07 12:13:51,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 77. [2019-12-07 12:13:51,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2019-12-07 12:13:51,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 79 transitions. [2019-12-07 12:13:51,385 INFO L711 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2019-12-07 12:13:51,385 INFO L591 BuchiCegarLoop]: Abstraction has 77 states and 79 transitions. [2019-12-07 12:13:51,385 INFO L424 BuchiCegarLoop]: ======== Iteration 38============ [2019-12-07 12:13:51,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 79 transitions. [2019-12-07 12:13:51,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:51,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:51,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:51,386 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [37, 36, 1] [2019-12-07 12:13:51,386 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:51,386 INFO L794 eck$LassoCheckResult]: Stem: 8637#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 8633#L12-2 assume !!(main_~i~0 < main_~j~0); 8634#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8635#L12-2 assume !!(main_~i~0 < main_~j~0); 8636#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8640#L12-2 assume !!(main_~i~0 < main_~j~0); 8709#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8708#L12-2 assume !!(main_~i~0 < main_~j~0); 8707#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8706#L12-2 assume !!(main_~i~0 < main_~j~0); 8705#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8704#L12-2 assume !!(main_~i~0 < main_~j~0); 8703#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8702#L12-2 assume !!(main_~i~0 < main_~j~0); 8701#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8700#L12-2 assume !!(main_~i~0 < main_~j~0); 8699#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8698#L12-2 assume !!(main_~i~0 < main_~j~0); 8697#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8696#L12-2 assume !!(main_~i~0 < main_~j~0); 8695#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8694#L12-2 assume !!(main_~i~0 < main_~j~0); 8693#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8692#L12-2 assume !!(main_~i~0 < main_~j~0); 8691#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8690#L12-2 assume !!(main_~i~0 < main_~j~0); 8689#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8688#L12-2 assume !!(main_~i~0 < main_~j~0); 8687#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8686#L12-2 assume !!(main_~i~0 < main_~j~0); 8685#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8684#L12-2 assume !!(main_~i~0 < main_~j~0); 8683#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8682#L12-2 assume !!(main_~i~0 < main_~j~0); 8681#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8680#L12-2 assume !!(main_~i~0 < main_~j~0); 8679#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8678#L12-2 assume !!(main_~i~0 < main_~j~0); 8677#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8676#L12-2 assume !!(main_~i~0 < main_~j~0); 8675#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8674#L12-2 assume !!(main_~i~0 < main_~j~0); 8673#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8672#L12-2 assume !!(main_~i~0 < main_~j~0); 8671#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8670#L12-2 assume !!(main_~i~0 < main_~j~0); 8669#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8668#L12-2 assume !!(main_~i~0 < main_~j~0); 8667#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8666#L12-2 assume !!(main_~i~0 < main_~j~0); 8665#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8664#L12-2 assume !!(main_~i~0 < main_~j~0); 8663#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8662#L12-2 assume !!(main_~i~0 < main_~j~0); 8661#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8660#L12-2 assume !!(main_~i~0 < main_~j~0); 8659#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8658#L12-2 assume !!(main_~i~0 < main_~j~0); 8657#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8656#L12-2 assume !!(main_~i~0 < main_~j~0); 8655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8654#L12-2 assume !!(main_~i~0 < main_~j~0); 8653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8652#L12-2 assume !!(main_~i~0 < main_~j~0); 8651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8650#L12-2 assume !!(main_~i~0 < main_~j~0); 8649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8648#L12-2 assume !!(main_~i~0 < main_~j~0); 8647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8646#L12-2 assume !!(main_~i~0 < main_~j~0); 8644#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8643#L12-2 assume !!(main_~i~0 < main_~j~0); 8642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8641#L12-2 assume !!(main_~i~0 < main_~j~0); 8638#L12 [2019-12-07 12:13:51,386 INFO L796 eck$LassoCheckResult]: Loop: 8638#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 8639#L12-2 assume !!(main_~i~0 < main_~j~0); 8642#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 8641#L12-2 assume !!(main_~i~0 < main_~j~0); 8638#L12 [2019-12-07 12:13:51,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:51,386 INFO L82 PathProgramCache]: Analyzing trace with hash 761988222, now seen corresponding path program 36 times [2019-12-07 12:13:51,386 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:51,386 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278111337] [2019-12-07 12:13:51,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:51,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:51,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:51,401 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:51,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:51,401 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 34 times [2019-12-07 12:13:51,401 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:51,401 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216008995] [2019-12-07 12:13:51,401 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:51,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:51,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:51,403 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:51,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:51,403 INFO L82 PathProgramCache]: Analyzing trace with hash -1086353866, now seen corresponding path program 36 times [2019-12-07 12:13:51,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:51,403 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793543557] [2019-12-07 12:13:51,403 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:51,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:51,840 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:51,840 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793543557] [2019-12-07 12:13:51,840 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [864470380] [2019-12-07 12:13:51,840 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:51,887 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2019-12-07 12:13:51,887 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:51,888 INFO L264 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 12:13:51,889 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:51,899 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 111 proven. 1332 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:51,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:51,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2019-12-07 12:13:51,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241702962] [2019-12-07 12:13:51,923 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:51,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-12-07 12:13:51,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 12:13:51,923 INFO L87 Difference]: Start difference. First operand 77 states and 79 transitions. cyclomatic complexity: 3 Second operand 39 states. [2019-12-07 12:13:51,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:51,992 INFO L93 Difference]: Finished difference Result 81 states and 83 transitions. [2019-12-07 12:13:51,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 12:13:51,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 83 transitions. [2019-12-07 12:13:51,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:51,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 80 states and 82 transitions. [2019-12-07 12:13:51,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:51,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:51,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 82 transitions. [2019-12-07 12:13:51,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:51,993 INFO L688 BuchiCegarLoop]: Abstraction has 80 states and 82 transitions. [2019-12-07 12:13:51,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 82 transitions. [2019-12-07 12:13:51,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 79. [2019-12-07 12:13:51,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2019-12-07 12:13:51,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 81 transitions. [2019-12-07 12:13:51,994 INFO L711 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2019-12-07 12:13:51,994 INFO L591 BuchiCegarLoop]: Abstraction has 79 states and 81 transitions. [2019-12-07 12:13:51,994 INFO L424 BuchiCegarLoop]: ======== Iteration 39============ [2019-12-07 12:13:51,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 81 transitions. [2019-12-07 12:13:51,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:51,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:51,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:51,995 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [38, 37, 1] [2019-12-07 12:13:51,995 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:51,995 INFO L794 eck$LassoCheckResult]: Stem: 9070#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9066#L12-2 assume !!(main_~i~0 < main_~j~0); 9067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9068#L12-2 assume !!(main_~i~0 < main_~j~0); 9069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9073#L12-2 assume !!(main_~i~0 < main_~j~0); 9144#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9143#L12-2 assume !!(main_~i~0 < main_~j~0); 9142#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9141#L12-2 assume !!(main_~i~0 < main_~j~0); 9140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9139#L12-2 assume !!(main_~i~0 < main_~j~0); 9138#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9137#L12-2 assume !!(main_~i~0 < main_~j~0); 9136#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9135#L12-2 assume !!(main_~i~0 < main_~j~0); 9134#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9133#L12-2 assume !!(main_~i~0 < main_~j~0); 9132#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9131#L12-2 assume !!(main_~i~0 < main_~j~0); 9130#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9129#L12-2 assume !!(main_~i~0 < main_~j~0); 9128#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9127#L12-2 assume !!(main_~i~0 < main_~j~0); 9126#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9125#L12-2 assume !!(main_~i~0 < main_~j~0); 9124#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9123#L12-2 assume !!(main_~i~0 < main_~j~0); 9122#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9121#L12-2 assume !!(main_~i~0 < main_~j~0); 9120#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9119#L12-2 assume !!(main_~i~0 < main_~j~0); 9118#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9117#L12-2 assume !!(main_~i~0 < main_~j~0); 9116#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9115#L12-2 assume !!(main_~i~0 < main_~j~0); 9114#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9113#L12-2 assume !!(main_~i~0 < main_~j~0); 9112#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9111#L12-2 assume !!(main_~i~0 < main_~j~0); 9110#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9109#L12-2 assume !!(main_~i~0 < main_~j~0); 9108#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9107#L12-2 assume !!(main_~i~0 < main_~j~0); 9106#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9105#L12-2 assume !!(main_~i~0 < main_~j~0); 9104#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9103#L12-2 assume !!(main_~i~0 < main_~j~0); 9102#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9101#L12-2 assume !!(main_~i~0 < main_~j~0); 9100#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9099#L12-2 assume !!(main_~i~0 < main_~j~0); 9098#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9097#L12-2 assume !!(main_~i~0 < main_~j~0); 9096#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9095#L12-2 assume !!(main_~i~0 < main_~j~0); 9094#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9093#L12-2 assume !!(main_~i~0 < main_~j~0); 9092#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9091#L12-2 assume !!(main_~i~0 < main_~j~0); 9090#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9089#L12-2 assume !!(main_~i~0 < main_~j~0); 9088#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9087#L12-2 assume !!(main_~i~0 < main_~j~0); 9086#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9085#L12-2 assume !!(main_~i~0 < main_~j~0); 9084#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9083#L12-2 assume !!(main_~i~0 < main_~j~0); 9082#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9081#L12-2 assume !!(main_~i~0 < main_~j~0); 9080#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9079#L12-2 assume !!(main_~i~0 < main_~j~0); 9077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9076#L12-2 assume !!(main_~i~0 < main_~j~0); 9075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9074#L12-2 assume !!(main_~i~0 < main_~j~0); 9071#L12 [2019-12-07 12:13:51,995 INFO L796 eck$LassoCheckResult]: Loop: 9071#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9072#L12-2 assume !!(main_~i~0 < main_~j~0); 9075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9074#L12-2 assume !!(main_~i~0 < main_~j~0); 9071#L12 [2019-12-07 12:13:51,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:51,996 INFO L82 PathProgramCache]: Analyzing trace with hash 2126241435, now seen corresponding path program 37 times [2019-12-07 12:13:51,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:51,996 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745738445] [2019-12-07 12:13:51,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,011 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:52,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:52,011 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 35 times [2019-12-07 12:13:52,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:52,012 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506451860] [2019-12-07 12:13:52,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,013 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:52,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:52,013 INFO L82 PathProgramCache]: Analyzing trace with hash -366210605, now seen corresponding path program 37 times [2019-12-07 12:13:52,013 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:52,013 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398507884] [2019-12-07 12:13:52,013 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:52,503 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:52,504 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398507884] [2019-12-07 12:13:52,504 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [812993121] [2019-12-07 12:13:52,504 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:52,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:52,537 INFO L264 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 39 conjunts are in the unsatisfiable core [2019-12-07 12:13:52,538 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:52,552 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 114 proven. 1406 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:52,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:52,553 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2019-12-07 12:13:52,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293449039] [2019-12-07 12:13:52,579 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:52,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 12:13:52,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 12:13:52,580 INFO L87 Difference]: Start difference. First operand 79 states and 81 transitions. cyclomatic complexity: 3 Second operand 40 states. [2019-12-07 12:13:52,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:52,664 INFO L93 Difference]: Finished difference Result 83 states and 85 transitions. [2019-12-07 12:13:52,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 12:13:52,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 85 transitions. [2019-12-07 12:13:52,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:52,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 82 states and 84 transitions. [2019-12-07 12:13:52,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:52,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:52,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 84 transitions. [2019-12-07 12:13:52,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:52,666 INFO L688 BuchiCegarLoop]: Abstraction has 82 states and 84 transitions. [2019-12-07 12:13:52,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 84 transitions. [2019-12-07 12:13:52,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2019-12-07 12:13:52,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2019-12-07 12:13:52,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 83 transitions. [2019-12-07 12:13:52,667 INFO L711 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2019-12-07 12:13:52,667 INFO L591 BuchiCegarLoop]: Abstraction has 81 states and 83 transitions. [2019-12-07 12:13:52,667 INFO L424 BuchiCegarLoop]: ======== Iteration 40============ [2019-12-07 12:13:52,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 83 transitions. [2019-12-07 12:13:52,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:52,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:52,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:52,668 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [39, 38, 1] [2019-12-07 12:13:52,668 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:52,668 INFO L794 eck$LassoCheckResult]: Stem: 9514#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9510#L12-2 assume !!(main_~i~0 < main_~j~0); 9511#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9512#L12-2 assume !!(main_~i~0 < main_~j~0); 9513#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9517#L12-2 assume !!(main_~i~0 < main_~j~0); 9590#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9589#L12-2 assume !!(main_~i~0 < main_~j~0); 9588#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9587#L12-2 assume !!(main_~i~0 < main_~j~0); 9586#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9585#L12-2 assume !!(main_~i~0 < main_~j~0); 9584#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9583#L12-2 assume !!(main_~i~0 < main_~j~0); 9582#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9581#L12-2 assume !!(main_~i~0 < main_~j~0); 9580#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9579#L12-2 assume !!(main_~i~0 < main_~j~0); 9578#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9577#L12-2 assume !!(main_~i~0 < main_~j~0); 9576#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9575#L12-2 assume !!(main_~i~0 < main_~j~0); 9574#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9573#L12-2 assume !!(main_~i~0 < main_~j~0); 9572#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9571#L12-2 assume !!(main_~i~0 < main_~j~0); 9570#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9569#L12-2 assume !!(main_~i~0 < main_~j~0); 9568#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9567#L12-2 assume !!(main_~i~0 < main_~j~0); 9566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9565#L12-2 assume !!(main_~i~0 < main_~j~0); 9564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9563#L12-2 assume !!(main_~i~0 < main_~j~0); 9562#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9561#L12-2 assume !!(main_~i~0 < main_~j~0); 9560#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9559#L12-2 assume !!(main_~i~0 < main_~j~0); 9558#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9557#L12-2 assume !!(main_~i~0 < main_~j~0); 9556#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9555#L12-2 assume !!(main_~i~0 < main_~j~0); 9554#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9553#L12-2 assume !!(main_~i~0 < main_~j~0); 9552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9551#L12-2 assume !!(main_~i~0 < main_~j~0); 9550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9549#L12-2 assume !!(main_~i~0 < main_~j~0); 9548#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9547#L12-2 assume !!(main_~i~0 < main_~j~0); 9546#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9545#L12-2 assume !!(main_~i~0 < main_~j~0); 9544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9543#L12-2 assume !!(main_~i~0 < main_~j~0); 9542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9541#L12-2 assume !!(main_~i~0 < main_~j~0); 9540#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9539#L12-2 assume !!(main_~i~0 < main_~j~0); 9538#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9537#L12-2 assume !!(main_~i~0 < main_~j~0); 9536#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9535#L12-2 assume !!(main_~i~0 < main_~j~0); 9534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9533#L12-2 assume !!(main_~i~0 < main_~j~0); 9532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9531#L12-2 assume !!(main_~i~0 < main_~j~0); 9530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9529#L12-2 assume !!(main_~i~0 < main_~j~0); 9528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9527#L12-2 assume !!(main_~i~0 < main_~j~0); 9526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9525#L12-2 assume !!(main_~i~0 < main_~j~0); 9524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9523#L12-2 assume !!(main_~i~0 < main_~j~0); 9521#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9520#L12-2 assume !!(main_~i~0 < main_~j~0); 9519#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9518#L12-2 assume !!(main_~i~0 < main_~j~0); 9515#L12 [2019-12-07 12:13:52,668 INFO L796 eck$LassoCheckResult]: Loop: 9515#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9516#L12-2 assume !!(main_~i~0 < main_~j~0); 9519#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9518#L12-2 assume !!(main_~i~0 < main_~j~0); 9515#L12 [2019-12-07 12:13:52,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:52,668 INFO L82 PathProgramCache]: Analyzing trace with hash -1086413448, now seen corresponding path program 38 times [2019-12-07 12:13:52,668 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:52,668 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751533250] [2019-12-07 12:13:52,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,685 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:52,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:52,685 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 36 times [2019-12-07 12:13:52,685 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:52,685 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051898949] [2019-12-07 12:13:52,685 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:52,687 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:52,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:52,687 INFO L82 PathProgramCache]: Analyzing trace with hash 201728560, now seen corresponding path program 38 times [2019-12-07 12:13:52,687 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:52,687 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841304640] [2019-12-07 12:13:52,687 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:52,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:53,294 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:53,294 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841304640] [2019-12-07 12:13:53,294 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1463387329] [2019-12-07 12:13:53,294 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:53,334 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:53,334 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:53,335 INFO L264 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 40 conjunts are in the unsatisfiable core [2019-12-07 12:13:53,337 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:53,348 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 117 proven. 1482 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:53,348 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:53,348 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2019-12-07 12:13:53,348 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495441828] [2019-12-07 12:13:53,376 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:53,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 12:13:53,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 12:13:53,376 INFO L87 Difference]: Start difference. First operand 81 states and 83 transitions. cyclomatic complexity: 3 Second operand 41 states. [2019-12-07 12:13:53,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:53,463 INFO L93 Difference]: Finished difference Result 85 states and 87 transitions. [2019-12-07 12:13:53,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 12:13:53,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 87 transitions. [2019-12-07 12:13:53,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:53,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 84 states and 86 transitions. [2019-12-07 12:13:53,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:53,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:53,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 86 transitions. [2019-12-07 12:13:53,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:53,465 INFO L688 BuchiCegarLoop]: Abstraction has 84 states and 86 transitions. [2019-12-07 12:13:53,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 86 transitions. [2019-12-07 12:13:53,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 83. [2019-12-07 12:13:53,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-12-07 12:13:53,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 85 transitions. [2019-12-07 12:13:53,466 INFO L711 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2019-12-07 12:13:53,466 INFO L591 BuchiCegarLoop]: Abstraction has 83 states and 85 transitions. [2019-12-07 12:13:53,466 INFO L424 BuchiCegarLoop]: ======== Iteration 41============ [2019-12-07 12:13:53,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 85 transitions. [2019-12-07 12:13:53,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:53,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:53,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:53,467 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [40, 39, 1] [2019-12-07 12:13:53,467 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:53,467 INFO L794 eck$LassoCheckResult]: Stem: 9969#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 9965#L12-2 assume !!(main_~i~0 < main_~j~0); 9966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9967#L12-2 assume !!(main_~i~0 < main_~j~0); 9968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9972#L12-2 assume !!(main_~i~0 < main_~j~0); 10047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10046#L12-2 assume !!(main_~i~0 < main_~j~0); 10045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10044#L12-2 assume !!(main_~i~0 < main_~j~0); 10043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10042#L12-2 assume !!(main_~i~0 < main_~j~0); 10041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10040#L12-2 assume !!(main_~i~0 < main_~j~0); 10039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10038#L12-2 assume !!(main_~i~0 < main_~j~0); 10037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10036#L12-2 assume !!(main_~i~0 < main_~j~0); 10035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10034#L12-2 assume !!(main_~i~0 < main_~j~0); 10033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10032#L12-2 assume !!(main_~i~0 < main_~j~0); 10031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10030#L12-2 assume !!(main_~i~0 < main_~j~0); 10029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10028#L12-2 assume !!(main_~i~0 < main_~j~0); 10027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10026#L12-2 assume !!(main_~i~0 < main_~j~0); 10025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10024#L12-2 assume !!(main_~i~0 < main_~j~0); 10023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10022#L12-2 assume !!(main_~i~0 < main_~j~0); 10021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10020#L12-2 assume !!(main_~i~0 < main_~j~0); 10019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10018#L12-2 assume !!(main_~i~0 < main_~j~0); 10017#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10016#L12-2 assume !!(main_~i~0 < main_~j~0); 10015#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10014#L12-2 assume !!(main_~i~0 < main_~j~0); 10013#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10012#L12-2 assume !!(main_~i~0 < main_~j~0); 10011#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10010#L12-2 assume !!(main_~i~0 < main_~j~0); 10009#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10008#L12-2 assume !!(main_~i~0 < main_~j~0); 10007#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10006#L12-2 assume !!(main_~i~0 < main_~j~0); 10005#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10004#L12-2 assume !!(main_~i~0 < main_~j~0); 10003#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10002#L12-2 assume !!(main_~i~0 < main_~j~0); 10001#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10000#L12-2 assume !!(main_~i~0 < main_~j~0); 9999#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9998#L12-2 assume !!(main_~i~0 < main_~j~0); 9997#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9996#L12-2 assume !!(main_~i~0 < main_~j~0); 9995#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9994#L12-2 assume !!(main_~i~0 < main_~j~0); 9993#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9992#L12-2 assume !!(main_~i~0 < main_~j~0); 9991#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9990#L12-2 assume !!(main_~i~0 < main_~j~0); 9989#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9988#L12-2 assume !!(main_~i~0 < main_~j~0); 9987#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9986#L12-2 assume !!(main_~i~0 < main_~j~0); 9985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9984#L12-2 assume !!(main_~i~0 < main_~j~0); 9983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9982#L12-2 assume !!(main_~i~0 < main_~j~0); 9981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9980#L12-2 assume !!(main_~i~0 < main_~j~0); 9979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9978#L12-2 assume !!(main_~i~0 < main_~j~0); 9976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9975#L12-2 assume !!(main_~i~0 < main_~j~0); 9974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9973#L12-2 assume !!(main_~i~0 < main_~j~0); 9970#L12 [2019-12-07 12:13:53,467 INFO L796 eck$LassoCheckResult]: Loop: 9970#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 9971#L12-2 assume !!(main_~i~0 < main_~j~0); 9974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 9973#L12-2 assume !!(main_~i~0 < main_~j~0); 9970#L12 [2019-12-07 12:13:53,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:53,467 INFO L82 PathProgramCache]: Analyzing trace with hash -366270187, now seen corresponding path program 39 times [2019-12-07 12:13:53,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:53,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040831166] [2019-12-07 12:13:53,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:53,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:53,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:53,484 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:53,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:53,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 37 times [2019-12-07 12:13:53,485 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:53,485 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425521527] [2019-12-07 12:13:53,485 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:53,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:53,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:53,486 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:53,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:53,486 INFO L82 PathProgramCache]: Analyzing trace with hash 530419533, now seen corresponding path program 39 times [2019-12-07 12:13:53,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:53,487 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028938132] [2019-12-07 12:13:53,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:53,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:53,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:53,991 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028938132] [2019-12-07 12:13:53,991 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1971872673] [2019-12-07 12:13:53,991 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:54,089 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2019-12-07 12:13:54,090 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:54,091 INFO L264 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 41 conjunts are in the unsatisfiable core [2019-12-07 12:13:54,092 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:54,107 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 120 proven. 1560 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:54,107 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:54,107 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2019-12-07 12:13:54,107 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595338497] [2019-12-07 12:13:54,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:54,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2019-12-07 12:13:54,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 12:13:54,132 INFO L87 Difference]: Start difference. First operand 83 states and 85 transitions. cyclomatic complexity: 3 Second operand 42 states. [2019-12-07 12:13:54,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:54,205 INFO L93 Difference]: Finished difference Result 87 states and 89 transitions. [2019-12-07 12:13:54,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 12:13:54,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 89 transitions. [2019-12-07 12:13:54,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:54,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 86 states and 88 transitions. [2019-12-07 12:13:54,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:54,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:54,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 88 transitions. [2019-12-07 12:13:54,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:54,207 INFO L688 BuchiCegarLoop]: Abstraction has 86 states and 88 transitions. [2019-12-07 12:13:54,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 88 transitions. [2019-12-07 12:13:54,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 85. [2019-12-07 12:13:54,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2019-12-07 12:13:54,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 87 transitions. [2019-12-07 12:13:54,208 INFO L711 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2019-12-07 12:13:54,208 INFO L591 BuchiCegarLoop]: Abstraction has 85 states and 87 transitions. [2019-12-07 12:13:54,208 INFO L424 BuchiCegarLoop]: ======== Iteration 42============ [2019-12-07 12:13:54,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 87 transitions. [2019-12-07 12:13:54,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:54,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:54,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:54,208 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [41, 40, 1] [2019-12-07 12:13:54,208 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:54,209 INFO L794 eck$LassoCheckResult]: Stem: 10435#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 10431#L12-2 assume !!(main_~i~0 < main_~j~0); 10432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10433#L12-2 assume !!(main_~i~0 < main_~j~0); 10434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10438#L12-2 assume !!(main_~i~0 < main_~j~0); 10515#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10514#L12-2 assume !!(main_~i~0 < main_~j~0); 10513#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10512#L12-2 assume !!(main_~i~0 < main_~j~0); 10511#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10510#L12-2 assume !!(main_~i~0 < main_~j~0); 10509#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10508#L12-2 assume !!(main_~i~0 < main_~j~0); 10507#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10506#L12-2 assume !!(main_~i~0 < main_~j~0); 10505#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10504#L12-2 assume !!(main_~i~0 < main_~j~0); 10503#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10502#L12-2 assume !!(main_~i~0 < main_~j~0); 10501#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10500#L12-2 assume !!(main_~i~0 < main_~j~0); 10499#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10498#L12-2 assume !!(main_~i~0 < main_~j~0); 10497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10496#L12-2 assume !!(main_~i~0 < main_~j~0); 10495#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10494#L12-2 assume !!(main_~i~0 < main_~j~0); 10493#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10492#L12-2 assume !!(main_~i~0 < main_~j~0); 10491#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10490#L12-2 assume !!(main_~i~0 < main_~j~0); 10489#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10488#L12-2 assume !!(main_~i~0 < main_~j~0); 10487#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10486#L12-2 assume !!(main_~i~0 < main_~j~0); 10485#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10484#L12-2 assume !!(main_~i~0 < main_~j~0); 10483#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10482#L12-2 assume !!(main_~i~0 < main_~j~0); 10481#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10480#L12-2 assume !!(main_~i~0 < main_~j~0); 10479#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10478#L12-2 assume !!(main_~i~0 < main_~j~0); 10477#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10476#L12-2 assume !!(main_~i~0 < main_~j~0); 10475#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10474#L12-2 assume !!(main_~i~0 < main_~j~0); 10473#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10472#L12-2 assume !!(main_~i~0 < main_~j~0); 10471#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10470#L12-2 assume !!(main_~i~0 < main_~j~0); 10469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10468#L12-2 assume !!(main_~i~0 < main_~j~0); 10467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10466#L12-2 assume !!(main_~i~0 < main_~j~0); 10465#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10464#L12-2 assume !!(main_~i~0 < main_~j~0); 10463#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10462#L12-2 assume !!(main_~i~0 < main_~j~0); 10461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10460#L12-2 assume !!(main_~i~0 < main_~j~0); 10459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10458#L12-2 assume !!(main_~i~0 < main_~j~0); 10457#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10456#L12-2 assume !!(main_~i~0 < main_~j~0); 10455#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10454#L12-2 assume !!(main_~i~0 < main_~j~0); 10453#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10452#L12-2 assume !!(main_~i~0 < main_~j~0); 10451#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10450#L12-2 assume !!(main_~i~0 < main_~j~0); 10449#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10448#L12-2 assume !!(main_~i~0 < main_~j~0); 10447#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10446#L12-2 assume !!(main_~i~0 < main_~j~0); 10445#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10444#L12-2 assume !!(main_~i~0 < main_~j~0); 10442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10441#L12-2 assume !!(main_~i~0 < main_~j~0); 10440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10439#L12-2 assume !!(main_~i~0 < main_~j~0); 10436#L12 [2019-12-07 12:13:54,209 INFO L796 eck$LassoCheckResult]: Loop: 10436#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 10437#L12-2 assume !!(main_~i~0 < main_~j~0); 10440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10439#L12-2 assume !!(main_~i~0 < main_~j~0); 10436#L12 [2019-12-07 12:13:54,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,209 INFO L82 PathProgramCache]: Analyzing trace with hash 201668978, now seen corresponding path program 40 times [2019-12-07 12:13:54,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,209 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552168414] [2019-12-07 12:13:54,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,226 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:54,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,227 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 38 times [2019-12-07 12:13:54,227 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,227 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438267454] [2019-12-07 12:13:54,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,228 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:54,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,228 INFO L82 PathProgramCache]: Analyzing trace with hash -1425135318, now seen corresponding path program 40 times [2019-12-07 12:13:54,229 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,229 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223426873] [2019-12-07 12:13:54,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:54,750 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:54,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223426873] [2019-12-07 12:13:54,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1368618173] [2019-12-07 12:13:54,750 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:54,781 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:54,782 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:54,783 INFO L264 TraceCheckSpWp]: Trace formula consists of 259 conjuncts, 42 conjunts are in the unsatisfiable core [2019-12-07 12:13:54,784 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:54,794 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 123 proven. 1640 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:54,794 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:54,794 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2019-12-07 12:13:54,795 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424126525] [2019-12-07 12:13:54,817 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:54,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-12-07 12:13:54,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 12:13:54,818 INFO L87 Difference]: Start difference. First operand 85 states and 87 transitions. cyclomatic complexity: 3 Second operand 43 states. [2019-12-07 12:13:54,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:54,879 INFO L93 Difference]: Finished difference Result 89 states and 91 transitions. [2019-12-07 12:13:54,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-12-07 12:13:54,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 91 transitions. [2019-12-07 12:13:54,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:54,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 88 states and 90 transitions. [2019-12-07 12:13:54,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:54,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:54,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 90 transitions. [2019-12-07 12:13:54,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:54,881 INFO L688 BuchiCegarLoop]: Abstraction has 88 states and 90 transitions. [2019-12-07 12:13:54,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 90 transitions. [2019-12-07 12:13:54,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2019-12-07 12:13:54,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-12-07 12:13:54,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 89 transitions. [2019-12-07 12:13:54,882 INFO L711 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2019-12-07 12:13:54,882 INFO L591 BuchiCegarLoop]: Abstraction has 87 states and 89 transitions. [2019-12-07 12:13:54,882 INFO L424 BuchiCegarLoop]: ======== Iteration 43============ [2019-12-07 12:13:54,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 89 transitions. [2019-12-07 12:13:54,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:54,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:54,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:54,883 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [42, 41, 1] [2019-12-07 12:13:54,883 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:54,883 INFO L794 eck$LassoCheckResult]: Stem: 10912#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 10908#L12-2 assume !!(main_~i~0 < main_~j~0); 10909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10910#L12-2 assume !!(main_~i~0 < main_~j~0); 10911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10915#L12-2 assume !!(main_~i~0 < main_~j~0); 10994#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10993#L12-2 assume !!(main_~i~0 < main_~j~0); 10992#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10991#L12-2 assume !!(main_~i~0 < main_~j~0); 10990#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10989#L12-2 assume !!(main_~i~0 < main_~j~0); 10988#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10987#L12-2 assume !!(main_~i~0 < main_~j~0); 10986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10985#L12-2 assume !!(main_~i~0 < main_~j~0); 10984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10983#L12-2 assume !!(main_~i~0 < main_~j~0); 10982#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10981#L12-2 assume !!(main_~i~0 < main_~j~0); 10980#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10979#L12-2 assume !!(main_~i~0 < main_~j~0); 10978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10977#L12-2 assume !!(main_~i~0 < main_~j~0); 10976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10975#L12-2 assume !!(main_~i~0 < main_~j~0); 10974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10973#L12-2 assume !!(main_~i~0 < main_~j~0); 10972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10971#L12-2 assume !!(main_~i~0 < main_~j~0); 10970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10969#L12-2 assume !!(main_~i~0 < main_~j~0); 10968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10967#L12-2 assume !!(main_~i~0 < main_~j~0); 10966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10965#L12-2 assume !!(main_~i~0 < main_~j~0); 10964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10963#L12-2 assume !!(main_~i~0 < main_~j~0); 10962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10961#L12-2 assume !!(main_~i~0 < main_~j~0); 10960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10959#L12-2 assume !!(main_~i~0 < main_~j~0); 10958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10957#L12-2 assume !!(main_~i~0 < main_~j~0); 10956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10955#L12-2 assume !!(main_~i~0 < main_~j~0); 10954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10953#L12-2 assume !!(main_~i~0 < main_~j~0); 10952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10951#L12-2 assume !!(main_~i~0 < main_~j~0); 10950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10949#L12-2 assume !!(main_~i~0 < main_~j~0); 10948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10947#L12-2 assume !!(main_~i~0 < main_~j~0); 10946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10945#L12-2 assume !!(main_~i~0 < main_~j~0); 10944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10943#L12-2 assume !!(main_~i~0 < main_~j~0); 10942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10941#L12-2 assume !!(main_~i~0 < main_~j~0); 10940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10939#L12-2 assume !!(main_~i~0 < main_~j~0); 10938#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10937#L12-2 assume !!(main_~i~0 < main_~j~0); 10936#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10935#L12-2 assume !!(main_~i~0 < main_~j~0); 10934#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10933#L12-2 assume !!(main_~i~0 < main_~j~0); 10932#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10931#L12-2 assume !!(main_~i~0 < main_~j~0); 10930#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10929#L12-2 assume !!(main_~i~0 < main_~j~0); 10928#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10927#L12-2 assume !!(main_~i~0 < main_~j~0); 10926#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10925#L12-2 assume !!(main_~i~0 < main_~j~0); 10924#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10923#L12-2 assume !!(main_~i~0 < main_~j~0); 10922#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10921#L12-2 assume !!(main_~i~0 < main_~j~0); 10919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10918#L12-2 assume !!(main_~i~0 < main_~j~0); 10917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10916#L12-2 assume !!(main_~i~0 < main_~j~0); 10913#L12 [2019-12-07 12:13:54,883 INFO L796 eck$LassoCheckResult]: Loop: 10913#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 10914#L12-2 assume !!(main_~i~0 < main_~j~0); 10917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 10916#L12-2 assume !!(main_~i~0 < main_~j~0); 10913#L12 [2019-12-07 12:13:54,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,883 INFO L82 PathProgramCache]: Analyzing trace with hash 530359951, now seen corresponding path program 41 times [2019-12-07 12:13:54,883 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,883 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925782987] [2019-12-07 12:13:54,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,901 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:54,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,901 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 39 times [2019-12-07 12:13:54,902 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125884614] [2019-12-07 12:13:54,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:54,903 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:54,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:54,903 INFO L82 PathProgramCache]: Analyzing trace with hash 482328519, now seen corresponding path program 41 times [2019-12-07 12:13:54,903 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:54,904 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210850667] [2019-12-07 12:13:54,904 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:54,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:55,444 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:55,444 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210850667] [2019-12-07 12:13:55,444 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1682240309] [2019-12-07 12:13:55,445 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:55,499 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 44 check-sat command(s) [2019-12-07 12:13:55,499 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:55,501 INFO L264 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 43 conjunts are in the unsatisfiable core [2019-12-07 12:13:55,502 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:55,513 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 126 proven. 1722 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:55,513 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:55,513 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2019-12-07 12:13:55,513 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227040289] [2019-12-07 12:13:55,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:55,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-12-07 12:13:55,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 12:13:55,538 INFO L87 Difference]: Start difference. First operand 87 states and 89 transitions. cyclomatic complexity: 3 Second operand 44 states. [2019-12-07 12:13:55,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:55,614 INFO L93 Difference]: Finished difference Result 91 states and 93 transitions. [2019-12-07 12:13:55,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 12:13:55,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 93 transitions. [2019-12-07 12:13:55,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:55,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 90 states and 92 transitions. [2019-12-07 12:13:55,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:55,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:55,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 92 transitions. [2019-12-07 12:13:55,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:55,616 INFO L688 BuchiCegarLoop]: Abstraction has 90 states and 92 transitions. [2019-12-07 12:13:55,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 92 transitions. [2019-12-07 12:13:55,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 89. [2019-12-07 12:13:55,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2019-12-07 12:13:55,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 91 transitions. [2019-12-07 12:13:55,617 INFO L711 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2019-12-07 12:13:55,617 INFO L591 BuchiCegarLoop]: Abstraction has 89 states and 91 transitions. [2019-12-07 12:13:55,617 INFO L424 BuchiCegarLoop]: ======== Iteration 44============ [2019-12-07 12:13:55,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 91 transitions. [2019-12-07 12:13:55,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:55,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:55,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:55,618 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [43, 42, 1] [2019-12-07 12:13:55,618 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:55,618 INFO L794 eck$LassoCheckResult]: Stem: 11400#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 11396#L12-2 assume !!(main_~i~0 < main_~j~0); 11397#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11398#L12-2 assume !!(main_~i~0 < main_~j~0); 11399#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11403#L12-2 assume !!(main_~i~0 < main_~j~0); 11484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11483#L12-2 assume !!(main_~i~0 < main_~j~0); 11482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11481#L12-2 assume !!(main_~i~0 < main_~j~0); 11480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11479#L12-2 assume !!(main_~i~0 < main_~j~0); 11478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11477#L12-2 assume !!(main_~i~0 < main_~j~0); 11476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11475#L12-2 assume !!(main_~i~0 < main_~j~0); 11474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11473#L12-2 assume !!(main_~i~0 < main_~j~0); 11472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11471#L12-2 assume !!(main_~i~0 < main_~j~0); 11470#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11469#L12-2 assume !!(main_~i~0 < main_~j~0); 11468#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11467#L12-2 assume !!(main_~i~0 < main_~j~0); 11466#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11465#L12-2 assume !!(main_~i~0 < main_~j~0); 11464#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11463#L12-2 assume !!(main_~i~0 < main_~j~0); 11462#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11461#L12-2 assume !!(main_~i~0 < main_~j~0); 11460#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11459#L12-2 assume !!(main_~i~0 < main_~j~0); 11458#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11457#L12-2 assume !!(main_~i~0 < main_~j~0); 11456#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11455#L12-2 assume !!(main_~i~0 < main_~j~0); 11454#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11453#L12-2 assume !!(main_~i~0 < main_~j~0); 11452#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11451#L12-2 assume !!(main_~i~0 < main_~j~0); 11450#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11449#L12-2 assume !!(main_~i~0 < main_~j~0); 11448#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11447#L12-2 assume !!(main_~i~0 < main_~j~0); 11446#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11445#L12-2 assume !!(main_~i~0 < main_~j~0); 11444#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11443#L12-2 assume !!(main_~i~0 < main_~j~0); 11442#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11441#L12-2 assume !!(main_~i~0 < main_~j~0); 11440#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11439#L12-2 assume !!(main_~i~0 < main_~j~0); 11438#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11437#L12-2 assume !!(main_~i~0 < main_~j~0); 11436#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11435#L12-2 assume !!(main_~i~0 < main_~j~0); 11434#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11433#L12-2 assume !!(main_~i~0 < main_~j~0); 11432#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11431#L12-2 assume !!(main_~i~0 < main_~j~0); 11430#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11429#L12-2 assume !!(main_~i~0 < main_~j~0); 11428#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11427#L12-2 assume !!(main_~i~0 < main_~j~0); 11426#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11425#L12-2 assume !!(main_~i~0 < main_~j~0); 11424#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11423#L12-2 assume !!(main_~i~0 < main_~j~0); 11422#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11421#L12-2 assume !!(main_~i~0 < main_~j~0); 11420#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11419#L12-2 assume !!(main_~i~0 < main_~j~0); 11418#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11417#L12-2 assume !!(main_~i~0 < main_~j~0); 11416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11415#L12-2 assume !!(main_~i~0 < main_~j~0); 11414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11413#L12-2 assume !!(main_~i~0 < main_~j~0); 11412#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11411#L12-2 assume !!(main_~i~0 < main_~j~0); 11410#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11409#L12-2 assume !!(main_~i~0 < main_~j~0); 11407#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11406#L12-2 assume !!(main_~i~0 < main_~j~0); 11405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11404#L12-2 assume !!(main_~i~0 < main_~j~0); 11401#L12 [2019-12-07 12:13:55,618 INFO L796 eck$LassoCheckResult]: Loop: 11401#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 11402#L12-2 assume !!(main_~i~0 < main_~j~0); 11405#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11404#L12-2 assume !!(main_~i~0 < main_~j~0); 11401#L12 [2019-12-07 12:13:55,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:55,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1425194900, now seen corresponding path program 42 times [2019-12-07 12:13:55,618 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:55,618 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182280313] [2019-12-07 12:13:55,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:55,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:55,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:55,637 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:55,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:55,637 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 40 times [2019-12-07 12:13:55,637 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:55,637 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037263161] [2019-12-07 12:13:55,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:55,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:55,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:55,639 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:55,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:55,639 INFO L82 PathProgramCache]: Analyzing trace with hash -395959516, now seen corresponding path program 42 times [2019-12-07 12:13:55,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:55,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110709598] [2019-12-07 12:13:55,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:55,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:56,214 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:56,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110709598] [2019-12-07 12:13:56,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [214047316] [2019-12-07 12:13:56,215 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:56,270 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2019-12-07 12:13:56,270 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:56,272 INFO L264 TraceCheckSpWp]: Trace formula consists of 271 conjuncts, 44 conjunts are in the unsatisfiable core [2019-12-07 12:13:56,273 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:56,284 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 129 proven. 1806 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:56,284 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:56,284 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2019-12-07 12:13:56,284 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322089456] [2019-12-07 12:13:56,308 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:56,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2019-12-07 12:13:56,308 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 12:13:56,308 INFO L87 Difference]: Start difference. First operand 89 states and 91 transitions. cyclomatic complexity: 3 Second operand 45 states. [2019-12-07 12:13:56,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:56,384 INFO L93 Difference]: Finished difference Result 93 states and 95 transitions. [2019-12-07 12:13:56,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 12:13:56,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 95 transitions. [2019-12-07 12:13:56,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:56,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 92 states and 94 transitions. [2019-12-07 12:13:56,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:56,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:56,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 94 transitions. [2019-12-07 12:13:56,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:56,385 INFO L688 BuchiCegarLoop]: Abstraction has 92 states and 94 transitions. [2019-12-07 12:13:56,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 94 transitions. [2019-12-07 12:13:56,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 91. [2019-12-07 12:13:56,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2019-12-07 12:13:56,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 93 transitions. [2019-12-07 12:13:56,386 INFO L711 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2019-12-07 12:13:56,386 INFO L591 BuchiCegarLoop]: Abstraction has 91 states and 93 transitions. [2019-12-07 12:13:56,387 INFO L424 BuchiCegarLoop]: ======== Iteration 45============ [2019-12-07 12:13:56,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 93 transitions. [2019-12-07 12:13:56,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:56,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:56,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:56,387 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [44, 43, 1] [2019-12-07 12:13:56,387 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:56,388 INFO L794 eck$LassoCheckResult]: Stem: 11899#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 11895#L12-2 assume !!(main_~i~0 < main_~j~0); 11896#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11897#L12-2 assume !!(main_~i~0 < main_~j~0); 11898#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11902#L12-2 assume !!(main_~i~0 < main_~j~0); 11985#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11984#L12-2 assume !!(main_~i~0 < main_~j~0); 11983#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11982#L12-2 assume !!(main_~i~0 < main_~j~0); 11981#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11980#L12-2 assume !!(main_~i~0 < main_~j~0); 11979#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11978#L12-2 assume !!(main_~i~0 < main_~j~0); 11977#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11976#L12-2 assume !!(main_~i~0 < main_~j~0); 11975#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11974#L12-2 assume !!(main_~i~0 < main_~j~0); 11973#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11972#L12-2 assume !!(main_~i~0 < main_~j~0); 11971#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11970#L12-2 assume !!(main_~i~0 < main_~j~0); 11969#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11968#L12-2 assume !!(main_~i~0 < main_~j~0); 11967#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11966#L12-2 assume !!(main_~i~0 < main_~j~0); 11965#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11964#L12-2 assume !!(main_~i~0 < main_~j~0); 11963#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11962#L12-2 assume !!(main_~i~0 < main_~j~0); 11961#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11960#L12-2 assume !!(main_~i~0 < main_~j~0); 11959#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11958#L12-2 assume !!(main_~i~0 < main_~j~0); 11957#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11956#L12-2 assume !!(main_~i~0 < main_~j~0); 11955#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11954#L12-2 assume !!(main_~i~0 < main_~j~0); 11953#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11952#L12-2 assume !!(main_~i~0 < main_~j~0); 11951#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11950#L12-2 assume !!(main_~i~0 < main_~j~0); 11949#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11948#L12-2 assume !!(main_~i~0 < main_~j~0); 11947#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11946#L12-2 assume !!(main_~i~0 < main_~j~0); 11945#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11944#L12-2 assume !!(main_~i~0 < main_~j~0); 11943#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11942#L12-2 assume !!(main_~i~0 < main_~j~0); 11941#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11940#L12-2 assume !!(main_~i~0 < main_~j~0); 11939#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11938#L12-2 assume !!(main_~i~0 < main_~j~0); 11937#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11936#L12-2 assume !!(main_~i~0 < main_~j~0); 11935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11934#L12-2 assume !!(main_~i~0 < main_~j~0); 11933#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11932#L12-2 assume !!(main_~i~0 < main_~j~0); 11931#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11930#L12-2 assume !!(main_~i~0 < main_~j~0); 11929#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11928#L12-2 assume !!(main_~i~0 < main_~j~0); 11927#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11926#L12-2 assume !!(main_~i~0 < main_~j~0); 11925#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11924#L12-2 assume !!(main_~i~0 < main_~j~0); 11923#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11922#L12-2 assume !!(main_~i~0 < main_~j~0); 11921#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11920#L12-2 assume !!(main_~i~0 < main_~j~0); 11919#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11918#L12-2 assume !!(main_~i~0 < main_~j~0); 11917#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11916#L12-2 assume !!(main_~i~0 < main_~j~0); 11915#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11914#L12-2 assume !!(main_~i~0 < main_~j~0); 11913#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11912#L12-2 assume !!(main_~i~0 < main_~j~0); 11911#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11910#L12-2 assume !!(main_~i~0 < main_~j~0); 11909#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11908#L12-2 assume !!(main_~i~0 < main_~j~0); 11906#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11905#L12-2 assume !!(main_~i~0 < main_~j~0); 11904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11903#L12-2 assume !!(main_~i~0 < main_~j~0); 11900#L12 [2019-12-07 12:13:56,388 INFO L796 eck$LassoCheckResult]: Loop: 11900#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 11901#L12-2 assume !!(main_~i~0 < main_~j~0); 11904#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 11903#L12-2 assume !!(main_~i~0 < main_~j~0); 11900#L12 [2019-12-07 12:13:56,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:56,388 INFO L82 PathProgramCache]: Analyzing trace with hash 482268937, now seen corresponding path program 43 times [2019-12-07 12:13:56,388 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:56,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146453853] [2019-12-07 12:13:56,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:56,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:56,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:56,407 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:56,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:56,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 41 times [2019-12-07 12:13:56,407 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:56,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2375639] [2019-12-07 12:13:56,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:56,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:56,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:56,409 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:56,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:56,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1677796161, now seen corresponding path program 43 times [2019-12-07 12:13:56,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:56,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034278738] [2019-12-07 12:13:56,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:56,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:57,006 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:57,006 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034278738] [2019-12-07 12:13:57,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [764252956] [2019-12-07 12:13:57,007 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:57,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:57,044 INFO L264 TraceCheckSpWp]: Trace formula consists of 277 conjuncts, 45 conjunts are in the unsatisfiable core [2019-12-07 12:13:57,045 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:57,055 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 132 proven. 1892 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:57,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:57,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2019-12-07 12:13:57,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190420044] [2019-12-07 12:13:57,081 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:57,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-12-07 12:13:57,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 12:13:57,082 INFO L87 Difference]: Start difference. First operand 91 states and 93 transitions. cyclomatic complexity: 3 Second operand 46 states. [2019-12-07 12:13:57,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:57,148 INFO L93 Difference]: Finished difference Result 95 states and 97 transitions. [2019-12-07 12:13:57,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2019-12-07 12:13:57,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 97 transitions. [2019-12-07 12:13:57,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:57,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 94 states and 96 transitions. [2019-12-07 12:13:57,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:57,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:57,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 96 transitions. [2019-12-07 12:13:57,149 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:57,149 INFO L688 BuchiCegarLoop]: Abstraction has 94 states and 96 transitions. [2019-12-07 12:13:57,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 96 transitions. [2019-12-07 12:13:57,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2019-12-07 12:13:57,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2019-12-07 12:13:57,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 95 transitions. [2019-12-07 12:13:57,150 INFO L711 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2019-12-07 12:13:57,150 INFO L591 BuchiCegarLoop]: Abstraction has 93 states and 95 transitions. [2019-12-07 12:13:57,150 INFO L424 BuchiCegarLoop]: ======== Iteration 46============ [2019-12-07 12:13:57,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 95 transitions. [2019-12-07 12:13:57,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:57,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:57,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:57,151 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [45, 44, 1] [2019-12-07 12:13:57,151 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:57,152 INFO L794 eck$LassoCheckResult]: Stem: 12409#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 12405#L12-2 assume !!(main_~i~0 < main_~j~0); 12406#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12407#L12-2 assume !!(main_~i~0 < main_~j~0); 12408#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12412#L12-2 assume !!(main_~i~0 < main_~j~0); 12497#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12496#L12-2 assume !!(main_~i~0 < main_~j~0); 12495#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12494#L12-2 assume !!(main_~i~0 < main_~j~0); 12493#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12492#L12-2 assume !!(main_~i~0 < main_~j~0); 12491#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12490#L12-2 assume !!(main_~i~0 < main_~j~0); 12489#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12488#L12-2 assume !!(main_~i~0 < main_~j~0); 12487#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12486#L12-2 assume !!(main_~i~0 < main_~j~0); 12485#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12484#L12-2 assume !!(main_~i~0 < main_~j~0); 12483#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12482#L12-2 assume !!(main_~i~0 < main_~j~0); 12481#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12480#L12-2 assume !!(main_~i~0 < main_~j~0); 12479#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12478#L12-2 assume !!(main_~i~0 < main_~j~0); 12477#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12476#L12-2 assume !!(main_~i~0 < main_~j~0); 12475#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12474#L12-2 assume !!(main_~i~0 < main_~j~0); 12473#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12472#L12-2 assume !!(main_~i~0 < main_~j~0); 12471#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12470#L12-2 assume !!(main_~i~0 < main_~j~0); 12469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12468#L12-2 assume !!(main_~i~0 < main_~j~0); 12467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12466#L12-2 assume !!(main_~i~0 < main_~j~0); 12465#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12464#L12-2 assume !!(main_~i~0 < main_~j~0); 12463#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12462#L12-2 assume !!(main_~i~0 < main_~j~0); 12461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12460#L12-2 assume !!(main_~i~0 < main_~j~0); 12459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12458#L12-2 assume !!(main_~i~0 < main_~j~0); 12457#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12456#L12-2 assume !!(main_~i~0 < main_~j~0); 12455#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12454#L12-2 assume !!(main_~i~0 < main_~j~0); 12453#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12452#L12-2 assume !!(main_~i~0 < main_~j~0); 12451#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12450#L12-2 assume !!(main_~i~0 < main_~j~0); 12449#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12448#L12-2 assume !!(main_~i~0 < main_~j~0); 12447#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12446#L12-2 assume !!(main_~i~0 < main_~j~0); 12445#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12444#L12-2 assume !!(main_~i~0 < main_~j~0); 12443#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12442#L12-2 assume !!(main_~i~0 < main_~j~0); 12441#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12440#L12-2 assume !!(main_~i~0 < main_~j~0); 12439#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12438#L12-2 assume !!(main_~i~0 < main_~j~0); 12437#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12436#L12-2 assume !!(main_~i~0 < main_~j~0); 12435#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12434#L12-2 assume !!(main_~i~0 < main_~j~0); 12433#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12432#L12-2 assume !!(main_~i~0 < main_~j~0); 12431#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12430#L12-2 assume !!(main_~i~0 < main_~j~0); 12429#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12428#L12-2 assume !!(main_~i~0 < main_~j~0); 12427#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12426#L12-2 assume !!(main_~i~0 < main_~j~0); 12425#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12424#L12-2 assume !!(main_~i~0 < main_~j~0); 12423#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12422#L12-2 assume !!(main_~i~0 < main_~j~0); 12421#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12420#L12-2 assume !!(main_~i~0 < main_~j~0); 12419#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12418#L12-2 assume !!(main_~i~0 < main_~j~0); 12416#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12415#L12-2 assume !!(main_~i~0 < main_~j~0); 12414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12413#L12-2 assume !!(main_~i~0 < main_~j~0); 12410#L12 [2019-12-07 12:13:57,152 INFO L796 eck$LassoCheckResult]: Loop: 12410#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 12411#L12-2 assume !!(main_~i~0 < main_~j~0); 12414#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12413#L12-2 assume !!(main_~i~0 < main_~j~0); 12410#L12 [2019-12-07 12:13:57,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,152 INFO L82 PathProgramCache]: Analyzing trace with hash -396019098, now seen corresponding path program 44 times [2019-12-07 12:13:57,152 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,152 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889724389] [2019-12-07 12:13:57,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,172 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:57,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,172 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 42 times [2019-12-07 12:13:57,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397302847] [2019-12-07 12:13:57,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,173 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:57,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1692176414, now seen corresponding path program 44 times [2019-12-07 12:13:57,174 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,174 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336752375] [2019-12-07 12:13:57,174 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:57,794 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:57,794 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336752375] [2019-12-07 12:13:57,794 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2102619905] [2019-12-07 12:13:57,795 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:57,827 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 12:13:57,827 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:57,828 INFO L264 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 46 conjunts are in the unsatisfiable core [2019-12-07 12:13:57,829 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 135 proven. 1980 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:57,840 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:57,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2019-12-07 12:13:57,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872987785] [2019-12-07 12:13:57,865 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:57,865 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2019-12-07 12:13:57,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 12:13:57,866 INFO L87 Difference]: Start difference. First operand 93 states and 95 transitions. cyclomatic complexity: 3 Second operand 47 states. [2019-12-07 12:13:57,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:57,933 INFO L93 Difference]: Finished difference Result 97 states and 99 transitions. [2019-12-07 12:13:57,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2019-12-07 12:13:57,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 99 transitions. [2019-12-07 12:13:57,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:57,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 96 states and 98 transitions. [2019-12-07 12:13:57,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:57,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:57,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 98 transitions. [2019-12-07 12:13:57,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:57,935 INFO L688 BuchiCegarLoop]: Abstraction has 96 states and 98 transitions. [2019-12-07 12:13:57,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 98 transitions. [2019-12-07 12:13:57,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 95. [2019-12-07 12:13:57,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2019-12-07 12:13:57,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 97 transitions. [2019-12-07 12:13:57,936 INFO L711 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2019-12-07 12:13:57,936 INFO L591 BuchiCegarLoop]: Abstraction has 95 states and 97 transitions. [2019-12-07 12:13:57,936 INFO L424 BuchiCegarLoop]: ======== Iteration 47============ [2019-12-07 12:13:57,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 97 transitions. [2019-12-07 12:13:57,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:57,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:57,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:57,937 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [46, 45, 1] [2019-12-07 12:13:57,937 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:57,937 INFO L794 eck$LassoCheckResult]: Stem: 12930#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 12926#L12-2 assume !!(main_~i~0 < main_~j~0); 12927#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12928#L12-2 assume !!(main_~i~0 < main_~j~0); 12929#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12933#L12-2 assume !!(main_~i~0 < main_~j~0); 13020#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13019#L12-2 assume !!(main_~i~0 < main_~j~0); 13018#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13017#L12-2 assume !!(main_~i~0 < main_~j~0); 13016#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13015#L12-2 assume !!(main_~i~0 < main_~j~0); 13014#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13013#L12-2 assume !!(main_~i~0 < main_~j~0); 13012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13011#L12-2 assume !!(main_~i~0 < main_~j~0); 13010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13009#L12-2 assume !!(main_~i~0 < main_~j~0); 13008#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13007#L12-2 assume !!(main_~i~0 < main_~j~0); 13006#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13005#L12-2 assume !!(main_~i~0 < main_~j~0); 13004#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13003#L12-2 assume !!(main_~i~0 < main_~j~0); 13002#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13001#L12-2 assume !!(main_~i~0 < main_~j~0); 13000#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12999#L12-2 assume !!(main_~i~0 < main_~j~0); 12998#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12997#L12-2 assume !!(main_~i~0 < main_~j~0); 12996#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12995#L12-2 assume !!(main_~i~0 < main_~j~0); 12994#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12993#L12-2 assume !!(main_~i~0 < main_~j~0); 12992#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12991#L12-2 assume !!(main_~i~0 < main_~j~0); 12990#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12989#L12-2 assume !!(main_~i~0 < main_~j~0); 12988#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12987#L12-2 assume !!(main_~i~0 < main_~j~0); 12986#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12985#L12-2 assume !!(main_~i~0 < main_~j~0); 12984#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12983#L12-2 assume !!(main_~i~0 < main_~j~0); 12982#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12981#L12-2 assume !!(main_~i~0 < main_~j~0); 12980#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12979#L12-2 assume !!(main_~i~0 < main_~j~0); 12978#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12977#L12-2 assume !!(main_~i~0 < main_~j~0); 12976#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12975#L12-2 assume !!(main_~i~0 < main_~j~0); 12974#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12973#L12-2 assume !!(main_~i~0 < main_~j~0); 12972#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12971#L12-2 assume !!(main_~i~0 < main_~j~0); 12970#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12969#L12-2 assume !!(main_~i~0 < main_~j~0); 12968#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12967#L12-2 assume !!(main_~i~0 < main_~j~0); 12966#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12965#L12-2 assume !!(main_~i~0 < main_~j~0); 12964#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12963#L12-2 assume !!(main_~i~0 < main_~j~0); 12962#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12961#L12-2 assume !!(main_~i~0 < main_~j~0); 12960#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12959#L12-2 assume !!(main_~i~0 < main_~j~0); 12958#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12957#L12-2 assume !!(main_~i~0 < main_~j~0); 12956#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12955#L12-2 assume !!(main_~i~0 < main_~j~0); 12954#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12953#L12-2 assume !!(main_~i~0 < main_~j~0); 12952#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12951#L12-2 assume !!(main_~i~0 < main_~j~0); 12950#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12949#L12-2 assume !!(main_~i~0 < main_~j~0); 12948#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12947#L12-2 assume !!(main_~i~0 < main_~j~0); 12946#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12945#L12-2 assume !!(main_~i~0 < main_~j~0); 12944#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12943#L12-2 assume !!(main_~i~0 < main_~j~0); 12942#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12941#L12-2 assume !!(main_~i~0 < main_~j~0); 12940#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12939#L12-2 assume !!(main_~i~0 < main_~j~0); 12937#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12936#L12-2 assume !!(main_~i~0 < main_~j~0); 12935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12934#L12-2 assume !!(main_~i~0 < main_~j~0); 12931#L12 [2019-12-07 12:13:57,937 INFO L796 eck$LassoCheckResult]: Loop: 12931#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 12932#L12-2 assume !!(main_~i~0 < main_~j~0); 12935#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 12934#L12-2 assume !!(main_~i~0 < main_~j~0); 12931#L12 [2019-12-07 12:13:57,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,937 INFO L82 PathProgramCache]: Analyzing trace with hash 1677736579, now seen corresponding path program 45 times [2019-12-07 12:13:57,937 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018779040] [2019-12-07 12:13:57,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,958 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:57,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,958 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 43 times [2019-12-07 12:13:57,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,959 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056974979] [2019-12-07 12:13:57,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:57,960 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:57,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:57,960 INFO L82 PathProgramCache]: Analyzing trace with hash -1668269637, now seen corresponding path program 45 times [2019-12-07 12:13:57,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:57,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182210686] [2019-12-07 12:13:57,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:57,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:58,596 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:58,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182210686] [2019-12-07 12:13:58,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1216132601] [2019-12-07 12:13:58,597 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:58,656 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2019-12-07 12:13:58,656 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:58,658 INFO L264 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 47 conjunts are in the unsatisfiable core [2019-12-07 12:13:58,658 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:58,670 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 138 proven. 2070 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:58,670 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:58,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2019-12-07 12:13:58,670 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246008104] [2019-12-07 12:13:58,695 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:58,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2019-12-07 12:13:58,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 12:13:58,696 INFO L87 Difference]: Start difference. First operand 95 states and 97 transitions. cyclomatic complexity: 3 Second operand 48 states. [2019-12-07 12:13:58,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:58,768 INFO L93 Difference]: Finished difference Result 99 states and 101 transitions. [2019-12-07 12:13:58,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2019-12-07 12:13:58,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 101 transitions. [2019-12-07 12:13:58,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:58,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 98 states and 100 transitions. [2019-12-07 12:13:58,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:58,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:58,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 100 transitions. [2019-12-07 12:13:58,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:58,769 INFO L688 BuchiCegarLoop]: Abstraction has 98 states and 100 transitions. [2019-12-07 12:13:58,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 100 transitions. [2019-12-07 12:13:58,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 97. [2019-12-07 12:13:58,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2019-12-07 12:13:58,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 99 transitions. [2019-12-07 12:13:58,770 INFO L711 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2019-12-07 12:13:58,770 INFO L591 BuchiCegarLoop]: Abstraction has 97 states and 99 transitions. [2019-12-07 12:13:58,770 INFO L424 BuchiCegarLoop]: ======== Iteration 48============ [2019-12-07 12:13:58,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 99 transitions. [2019-12-07 12:13:58,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:58,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:58,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:58,771 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [47, 46, 1] [2019-12-07 12:13:58,771 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:58,772 INFO L794 eck$LassoCheckResult]: Stem: 13462#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 13458#L12-2 assume !!(main_~i~0 < main_~j~0); 13459#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13460#L12-2 assume !!(main_~i~0 < main_~j~0); 13461#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13465#L12-2 assume !!(main_~i~0 < main_~j~0); 13554#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13553#L12-2 assume !!(main_~i~0 < main_~j~0); 13552#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13551#L12-2 assume !!(main_~i~0 < main_~j~0); 13550#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13549#L12-2 assume !!(main_~i~0 < main_~j~0); 13548#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13547#L12-2 assume !!(main_~i~0 < main_~j~0); 13546#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13545#L12-2 assume !!(main_~i~0 < main_~j~0); 13544#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13543#L12-2 assume !!(main_~i~0 < main_~j~0); 13542#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13541#L12-2 assume !!(main_~i~0 < main_~j~0); 13540#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13539#L12-2 assume !!(main_~i~0 < main_~j~0); 13538#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13537#L12-2 assume !!(main_~i~0 < main_~j~0); 13536#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13535#L12-2 assume !!(main_~i~0 < main_~j~0); 13534#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13533#L12-2 assume !!(main_~i~0 < main_~j~0); 13532#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13531#L12-2 assume !!(main_~i~0 < main_~j~0); 13530#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13529#L12-2 assume !!(main_~i~0 < main_~j~0); 13528#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13527#L12-2 assume !!(main_~i~0 < main_~j~0); 13526#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13525#L12-2 assume !!(main_~i~0 < main_~j~0); 13524#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13523#L12-2 assume !!(main_~i~0 < main_~j~0); 13522#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13521#L12-2 assume !!(main_~i~0 < main_~j~0); 13520#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13519#L12-2 assume !!(main_~i~0 < main_~j~0); 13518#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13517#L12-2 assume !!(main_~i~0 < main_~j~0); 13516#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13515#L12-2 assume !!(main_~i~0 < main_~j~0); 13514#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13513#L12-2 assume !!(main_~i~0 < main_~j~0); 13512#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13511#L12-2 assume !!(main_~i~0 < main_~j~0); 13510#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13509#L12-2 assume !!(main_~i~0 < main_~j~0); 13508#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13507#L12-2 assume !!(main_~i~0 < main_~j~0); 13506#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13505#L12-2 assume !!(main_~i~0 < main_~j~0); 13504#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13503#L12-2 assume !!(main_~i~0 < main_~j~0); 13502#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13501#L12-2 assume !!(main_~i~0 < main_~j~0); 13500#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13499#L12-2 assume !!(main_~i~0 < main_~j~0); 13498#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13497#L12-2 assume !!(main_~i~0 < main_~j~0); 13496#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13495#L12-2 assume !!(main_~i~0 < main_~j~0); 13494#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13493#L12-2 assume !!(main_~i~0 < main_~j~0); 13492#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13491#L12-2 assume !!(main_~i~0 < main_~j~0); 13490#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13489#L12-2 assume !!(main_~i~0 < main_~j~0); 13488#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13487#L12-2 assume !!(main_~i~0 < main_~j~0); 13486#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13485#L12-2 assume !!(main_~i~0 < main_~j~0); 13484#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13483#L12-2 assume !!(main_~i~0 < main_~j~0); 13482#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13481#L12-2 assume !!(main_~i~0 < main_~j~0); 13480#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13479#L12-2 assume !!(main_~i~0 < main_~j~0); 13478#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13477#L12-2 assume !!(main_~i~0 < main_~j~0); 13476#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13475#L12-2 assume !!(main_~i~0 < main_~j~0); 13474#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13473#L12-2 assume !!(main_~i~0 < main_~j~0); 13472#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13471#L12-2 assume !!(main_~i~0 < main_~j~0); 13469#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13468#L12-2 assume !!(main_~i~0 < main_~j~0); 13467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13466#L12-2 assume !!(main_~i~0 < main_~j~0); 13463#L12 [2019-12-07 12:13:58,772 INFO L796 eck$LassoCheckResult]: Loop: 13463#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 13464#L12-2 assume !!(main_~i~0 < main_~j~0); 13467#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 13466#L12-2 assume !!(main_~i~0 < main_~j~0); 13463#L12 [2019-12-07 12:13:58,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:58,772 INFO L82 PathProgramCache]: Analyzing trace with hash 1692116832, now seen corresponding path program 46 times [2019-12-07 12:13:58,772 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:58,772 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589550283] [2019-12-07 12:13:58,772 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:58,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:58,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:58,794 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:58,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:58,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 44 times [2019-12-07 12:13:58,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:58,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309573864] [2019-12-07 12:13:58,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:58,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:58,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:58,796 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:58,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:58,796 INFO L82 PathProgramCache]: Analyzing trace with hash -1241518056, now seen corresponding path program 46 times [2019-12-07 12:13:58,796 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:58,796 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925590454] [2019-12-07 12:13:58,796 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:58,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:13:59,470 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:59,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925590454] [2019-12-07 12:13:59,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [860941963] [2019-12-07 12:13:59,471 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:13:59,504 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 12:13:59,504 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:13:59,506 INFO L264 TraceCheckSpWp]: Trace formula consists of 295 conjuncts, 48 conjunts are in the unsatisfiable core [2019-12-07 12:13:59,507 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:13:59,518 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 141 proven. 2162 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:13:59,519 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:13:59,519 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2019-12-07 12:13:59,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943276724] [2019-12-07 12:13:59,543 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:13:59,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2019-12-07 12:13:59,544 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 12:13:59,544 INFO L87 Difference]: Start difference. First operand 97 states and 99 transitions. cyclomatic complexity: 3 Second operand 49 states. [2019-12-07 12:13:59,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:13:59,632 INFO L93 Difference]: Finished difference Result 101 states and 103 transitions. [2019-12-07 12:13:59,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2019-12-07 12:13:59,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 103 transitions. [2019-12-07 12:13:59,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:59,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 100 states and 102 transitions. [2019-12-07 12:13:59,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:13:59,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:13:59,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 102 transitions. [2019-12-07 12:13:59,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:13:59,634 INFO L688 BuchiCegarLoop]: Abstraction has 100 states and 102 transitions. [2019-12-07 12:13:59,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 102 transitions. [2019-12-07 12:13:59,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2019-12-07 12:13:59,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2019-12-07 12:13:59,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 101 transitions. [2019-12-07 12:13:59,635 INFO L711 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2019-12-07 12:13:59,635 INFO L591 BuchiCegarLoop]: Abstraction has 99 states and 101 transitions. [2019-12-07 12:13:59,635 INFO L424 BuchiCegarLoop]: ======== Iteration 49============ [2019-12-07 12:13:59,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 101 transitions. [2019-12-07 12:13:59,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:13:59,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:13:59,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:13:59,636 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [48, 47, 1] [2019-12-07 12:13:59,636 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:13:59,636 INFO L794 eck$LassoCheckResult]: Stem: 14005#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 14001#L12-2 assume !!(main_~i~0 < main_~j~0); 14002#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14003#L12-2 assume !!(main_~i~0 < main_~j~0); 14004#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14008#L12-2 assume !!(main_~i~0 < main_~j~0); 14099#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14098#L12-2 assume !!(main_~i~0 < main_~j~0); 14097#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14096#L12-2 assume !!(main_~i~0 < main_~j~0); 14095#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14094#L12-2 assume !!(main_~i~0 < main_~j~0); 14093#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14092#L12-2 assume !!(main_~i~0 < main_~j~0); 14091#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14090#L12-2 assume !!(main_~i~0 < main_~j~0); 14089#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14088#L12-2 assume !!(main_~i~0 < main_~j~0); 14087#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14086#L12-2 assume !!(main_~i~0 < main_~j~0); 14085#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14084#L12-2 assume !!(main_~i~0 < main_~j~0); 14083#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14082#L12-2 assume !!(main_~i~0 < main_~j~0); 14081#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14080#L12-2 assume !!(main_~i~0 < main_~j~0); 14079#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14078#L12-2 assume !!(main_~i~0 < main_~j~0); 14077#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14076#L12-2 assume !!(main_~i~0 < main_~j~0); 14075#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14074#L12-2 assume !!(main_~i~0 < main_~j~0); 14073#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14072#L12-2 assume !!(main_~i~0 < main_~j~0); 14071#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14070#L12-2 assume !!(main_~i~0 < main_~j~0); 14069#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14068#L12-2 assume !!(main_~i~0 < main_~j~0); 14067#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14066#L12-2 assume !!(main_~i~0 < main_~j~0); 14065#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14064#L12-2 assume !!(main_~i~0 < main_~j~0); 14063#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14062#L12-2 assume !!(main_~i~0 < main_~j~0); 14061#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14060#L12-2 assume !!(main_~i~0 < main_~j~0); 14059#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14058#L12-2 assume !!(main_~i~0 < main_~j~0); 14057#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14056#L12-2 assume !!(main_~i~0 < main_~j~0); 14055#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14054#L12-2 assume !!(main_~i~0 < main_~j~0); 14053#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14052#L12-2 assume !!(main_~i~0 < main_~j~0); 14051#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14050#L12-2 assume !!(main_~i~0 < main_~j~0); 14049#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14048#L12-2 assume !!(main_~i~0 < main_~j~0); 14047#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14046#L12-2 assume !!(main_~i~0 < main_~j~0); 14045#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14044#L12-2 assume !!(main_~i~0 < main_~j~0); 14043#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14042#L12-2 assume !!(main_~i~0 < main_~j~0); 14041#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14040#L12-2 assume !!(main_~i~0 < main_~j~0); 14039#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14038#L12-2 assume !!(main_~i~0 < main_~j~0); 14037#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14036#L12-2 assume !!(main_~i~0 < main_~j~0); 14035#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14034#L12-2 assume !!(main_~i~0 < main_~j~0); 14033#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14032#L12-2 assume !!(main_~i~0 < main_~j~0); 14031#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14030#L12-2 assume !!(main_~i~0 < main_~j~0); 14029#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14028#L12-2 assume !!(main_~i~0 < main_~j~0); 14027#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14026#L12-2 assume !!(main_~i~0 < main_~j~0); 14025#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14024#L12-2 assume !!(main_~i~0 < main_~j~0); 14023#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14022#L12-2 assume !!(main_~i~0 < main_~j~0); 14021#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14020#L12-2 assume !!(main_~i~0 < main_~j~0); 14019#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14018#L12-2 assume !!(main_~i~0 < main_~j~0); 14017#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14016#L12-2 assume !!(main_~i~0 < main_~j~0); 14015#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14014#L12-2 assume !!(main_~i~0 < main_~j~0); 14012#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14011#L12-2 assume !!(main_~i~0 < main_~j~0); 14010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14009#L12-2 assume !!(main_~i~0 < main_~j~0); 14006#L12 [2019-12-07 12:13:59,636 INFO L796 eck$LassoCheckResult]: Loop: 14006#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 14007#L12-2 assume !!(main_~i~0 < main_~j~0); 14010#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14009#L12-2 assume !!(main_~i~0 < main_~j~0); 14006#L12 [2019-12-07 12:13:59,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:59,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1668329219, now seen corresponding path program 47 times [2019-12-07 12:13:59,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:59,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444908697] [2019-12-07 12:13:59,636 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:59,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:59,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:59,659 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:59,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:59,659 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 45 times [2019-12-07 12:13:59,659 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:59,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737877545] [2019-12-07 12:13:59,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:59,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:59,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:13:59,661 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:13:59,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:13:59,661 INFO L82 PathProgramCache]: Analyzing trace with hash 844858165, now seen corresponding path program 47 times [2019-12-07 12:13:59,661 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:13:59,661 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070279823] [2019-12-07 12:13:59,661 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:13:59,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:14:00,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:14:00,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070279823] [2019-12-07 12:14:00,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [575822570] [2019-12-07 12:14:00,357 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:14:00,426 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 50 check-sat command(s) [2019-12-07 12:14:00,427 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:14:00,429 INFO L264 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 49 conjunts are in the unsatisfiable core [2019-12-07 12:14:00,430 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:14:00,442 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 144 proven. 2256 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:14:00,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:14:00,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2019-12-07 12:14:00,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812148377] [2019-12-07 12:14:00,466 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:14:00,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2019-12-07 12:14:00,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 12:14:00,467 INFO L87 Difference]: Start difference. First operand 99 states and 101 transitions. cyclomatic complexity: 3 Second operand 50 states. [2019-12-07 12:14:00,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:14:00,540 INFO L93 Difference]: Finished difference Result 103 states and 105 transitions. [2019-12-07 12:14:00,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 12:14:00,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 105 transitions. [2019-12-07 12:14:00,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:14:00,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 102 states and 104 transitions. [2019-12-07 12:14:00,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:14:00,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:14:00,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 104 transitions. [2019-12-07 12:14:00,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:14:00,542 INFO L688 BuchiCegarLoop]: Abstraction has 102 states and 104 transitions. [2019-12-07 12:14:00,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 104 transitions. [2019-12-07 12:14:00,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 101. [2019-12-07 12:14:00,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2019-12-07 12:14:00,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 103 transitions. [2019-12-07 12:14:00,543 INFO L711 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2019-12-07 12:14:00,543 INFO L591 BuchiCegarLoop]: Abstraction has 101 states and 103 transitions. [2019-12-07 12:14:00,543 INFO L424 BuchiCegarLoop]: ======== Iteration 50============ [2019-12-07 12:14:00,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 103 transitions. [2019-12-07 12:14:00,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:14:00,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:14:00,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:14:00,544 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [49, 48, 1] [2019-12-07 12:14:00,544 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:14:00,544 INFO L794 eck$LassoCheckResult]: Stem: 14559#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 14555#L12-2 assume !!(main_~i~0 < main_~j~0); 14556#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14557#L12-2 assume !!(main_~i~0 < main_~j~0); 14558#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14562#L12-2 assume !!(main_~i~0 < main_~j~0); 14655#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14654#L12-2 assume !!(main_~i~0 < main_~j~0); 14653#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14652#L12-2 assume !!(main_~i~0 < main_~j~0); 14651#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14650#L12-2 assume !!(main_~i~0 < main_~j~0); 14649#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14648#L12-2 assume !!(main_~i~0 < main_~j~0); 14647#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14646#L12-2 assume !!(main_~i~0 < main_~j~0); 14645#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14644#L12-2 assume !!(main_~i~0 < main_~j~0); 14643#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14642#L12-2 assume !!(main_~i~0 < main_~j~0); 14641#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14640#L12-2 assume !!(main_~i~0 < main_~j~0); 14639#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14638#L12-2 assume !!(main_~i~0 < main_~j~0); 14637#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14636#L12-2 assume !!(main_~i~0 < main_~j~0); 14635#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14634#L12-2 assume !!(main_~i~0 < main_~j~0); 14633#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14632#L12-2 assume !!(main_~i~0 < main_~j~0); 14631#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14630#L12-2 assume !!(main_~i~0 < main_~j~0); 14629#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14628#L12-2 assume !!(main_~i~0 < main_~j~0); 14627#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14626#L12-2 assume !!(main_~i~0 < main_~j~0); 14625#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14624#L12-2 assume !!(main_~i~0 < main_~j~0); 14623#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14622#L12-2 assume !!(main_~i~0 < main_~j~0); 14621#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14620#L12-2 assume !!(main_~i~0 < main_~j~0); 14619#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14618#L12-2 assume !!(main_~i~0 < main_~j~0); 14617#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14616#L12-2 assume !!(main_~i~0 < main_~j~0); 14615#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14614#L12-2 assume !!(main_~i~0 < main_~j~0); 14613#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14612#L12-2 assume !!(main_~i~0 < main_~j~0); 14611#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14610#L12-2 assume !!(main_~i~0 < main_~j~0); 14609#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14608#L12-2 assume !!(main_~i~0 < main_~j~0); 14607#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14606#L12-2 assume !!(main_~i~0 < main_~j~0); 14605#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14604#L12-2 assume !!(main_~i~0 < main_~j~0); 14603#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14602#L12-2 assume !!(main_~i~0 < main_~j~0); 14601#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14600#L12-2 assume !!(main_~i~0 < main_~j~0); 14599#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14598#L12-2 assume !!(main_~i~0 < main_~j~0); 14597#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14596#L12-2 assume !!(main_~i~0 < main_~j~0); 14595#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14594#L12-2 assume !!(main_~i~0 < main_~j~0); 14593#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14592#L12-2 assume !!(main_~i~0 < main_~j~0); 14591#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14590#L12-2 assume !!(main_~i~0 < main_~j~0); 14589#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14588#L12-2 assume !!(main_~i~0 < main_~j~0); 14587#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14586#L12-2 assume !!(main_~i~0 < main_~j~0); 14585#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14584#L12-2 assume !!(main_~i~0 < main_~j~0); 14583#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14582#L12-2 assume !!(main_~i~0 < main_~j~0); 14581#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14580#L12-2 assume !!(main_~i~0 < main_~j~0); 14579#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14578#L12-2 assume !!(main_~i~0 < main_~j~0); 14577#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14576#L12-2 assume !!(main_~i~0 < main_~j~0); 14575#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14574#L12-2 assume !!(main_~i~0 < main_~j~0); 14573#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14572#L12-2 assume !!(main_~i~0 < main_~j~0); 14571#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14570#L12-2 assume !!(main_~i~0 < main_~j~0); 14569#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14568#L12-2 assume !!(main_~i~0 < main_~j~0); 14566#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14565#L12-2 assume !!(main_~i~0 < main_~j~0); 14564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14563#L12-2 assume !!(main_~i~0 < main_~j~0); 14560#L12 [2019-12-07 12:14:00,544 INFO L796 eck$LassoCheckResult]: Loop: 14560#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 14561#L12-2 assume !!(main_~i~0 < main_~j~0); 14564#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 14563#L12-2 assume !!(main_~i~0 < main_~j~0); 14560#L12 [2019-12-07 12:14:00,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:00,544 INFO L82 PathProgramCache]: Analyzing trace with hash -1241577638, now seen corresponding path program 48 times [2019-12-07 12:14:00,544 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:00,544 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170956717] [2019-12-07 12:14:00,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:00,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:00,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:00,568 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:14:00,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:00,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 46 times [2019-12-07 12:14:00,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:00,568 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660427927] [2019-12-07 12:14:00,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:00,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:00,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:00,569 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:14:00,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:00,570 INFO L82 PathProgramCache]: Analyzing trace with hash 102679314, now seen corresponding path program 48 times [2019-12-07 12:14:00,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:00,570 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951487510] [2019-12-07 12:14:00,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:00,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:14:01,290 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:14:01,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951487510] [2019-12-07 12:14:01,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [355460843] [2019-12-07 12:14:01,290 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 12:14:01,353 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2019-12-07 12:14:01,353 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 12:14:01,355 INFO L264 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 50 conjunts are in the unsatisfiable core [2019-12-07 12:14:01,355 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 12:14:01,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 147 proven. 2352 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 12:14:01,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 12:14:01,368 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2019-12-07 12:14:01,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837199732] [2019-12-07 12:14:01,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:14:01,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2019-12-07 12:14:01,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 12:14:01,393 INFO L87 Difference]: Start difference. First operand 101 states and 103 transitions. cyclomatic complexity: 3 Second operand 51 states. [2019-12-07 12:14:01,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:14:01,486 INFO L93 Difference]: Finished difference Result 105 states and 107 transitions. [2019-12-07 12:14:01,486 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 12:14:01,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 107 transitions. [2019-12-07 12:14:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:14:01,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 104 states and 106 transitions. [2019-12-07 12:14:01,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3 [2019-12-07 12:14:01,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3 [2019-12-07 12:14:01,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 106 transitions. [2019-12-07 12:14:01,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 12:14:01,487 INFO L688 BuchiCegarLoop]: Abstraction has 104 states and 106 transitions. [2019-12-07 12:14:01,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 106 transitions. [2019-12-07 12:14:01,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 103. [2019-12-07 12:14:01,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2019-12-07 12:14:01,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 105 transitions. [2019-12-07 12:14:01,489 INFO L711 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2019-12-07 12:14:01,489 INFO L591 BuchiCegarLoop]: Abstraction has 103 states and 105 transitions. [2019-12-07 12:14:01,489 INFO L424 BuchiCegarLoop]: ======== Iteration 51============ [2019-12-07 12:14:01,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 105 transitions. [2019-12-07 12:14:01,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 12:14:01,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:14:01,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:14:01,490 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [50, 49, 1] [2019-12-07 12:14:01,490 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1] [2019-12-07 12:14:01,490 INFO L794 eck$LassoCheckResult]: Stem: 15124#ULTIMATE.startENTRY havoc main_#res;havoc main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0;main_~j~0 := 100;main_~i~0 := 0; 15120#L12-2 assume !!(main_~i~0 < main_~j~0); 15121#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15122#L12-2 assume !!(main_~i~0 < main_~j~0); 15123#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15127#L12-2 assume !!(main_~i~0 < main_~j~0); 15222#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15221#L12-2 assume !!(main_~i~0 < main_~j~0); 15220#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15219#L12-2 assume !!(main_~i~0 < main_~j~0); 15218#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15217#L12-2 assume !!(main_~i~0 < main_~j~0); 15216#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15215#L12-2 assume !!(main_~i~0 < main_~j~0); 15214#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15213#L12-2 assume !!(main_~i~0 < main_~j~0); 15212#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15211#L12-2 assume !!(main_~i~0 < main_~j~0); 15210#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15209#L12-2 assume !!(main_~i~0 < main_~j~0); 15208#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15207#L12-2 assume !!(main_~i~0 < main_~j~0); 15206#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15205#L12-2 assume !!(main_~i~0 < main_~j~0); 15204#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15203#L12-2 assume !!(main_~i~0 < main_~j~0); 15202#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15201#L12-2 assume !!(main_~i~0 < main_~j~0); 15200#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15199#L12-2 assume !!(main_~i~0 < main_~j~0); 15198#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15197#L12-2 assume !!(main_~i~0 < main_~j~0); 15196#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15195#L12-2 assume !!(main_~i~0 < main_~j~0); 15194#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15193#L12-2 assume !!(main_~i~0 < main_~j~0); 15192#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15191#L12-2 assume !!(main_~i~0 < main_~j~0); 15190#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15189#L12-2 assume !!(main_~i~0 < main_~j~0); 15188#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15187#L12-2 assume !!(main_~i~0 < main_~j~0); 15186#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15185#L12-2 assume !!(main_~i~0 < main_~j~0); 15184#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15183#L12-2 assume !!(main_~i~0 < main_~j~0); 15182#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15181#L12-2 assume !!(main_~i~0 < main_~j~0); 15180#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15179#L12-2 assume !!(main_~i~0 < main_~j~0); 15178#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15177#L12-2 assume !!(main_~i~0 < main_~j~0); 15176#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15175#L12-2 assume !!(main_~i~0 < main_~j~0); 15174#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15173#L12-2 assume !!(main_~i~0 < main_~j~0); 15172#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15171#L12-2 assume !!(main_~i~0 < main_~j~0); 15170#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15169#L12-2 assume !!(main_~i~0 < main_~j~0); 15168#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15167#L12-2 assume !!(main_~i~0 < main_~j~0); 15166#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15165#L12-2 assume !!(main_~i~0 < main_~j~0); 15164#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15163#L12-2 assume !!(main_~i~0 < main_~j~0); 15162#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15161#L12-2 assume !!(main_~i~0 < main_~j~0); 15160#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15159#L12-2 assume !!(main_~i~0 < main_~j~0); 15158#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15157#L12-2 assume !!(main_~i~0 < main_~j~0); 15156#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15155#L12-2 assume !!(main_~i~0 < main_~j~0); 15154#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15153#L12-2 assume !!(main_~i~0 < main_~j~0); 15152#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15151#L12-2 assume !!(main_~i~0 < main_~j~0); 15150#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15149#L12-2 assume !!(main_~i~0 < main_~j~0); 15148#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15147#L12-2 assume !!(main_~i~0 < main_~j~0); 15146#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15145#L12-2 assume !!(main_~i~0 < main_~j~0); 15144#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15143#L12-2 assume !!(main_~i~0 < main_~j~0); 15142#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15141#L12-2 assume !!(main_~i~0 < main_~j~0); 15140#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15139#L12-2 assume !!(main_~i~0 < main_~j~0); 15138#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15137#L12-2 assume !!(main_~i~0 < main_~j~0); 15136#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15135#L12-2 assume !!(main_~i~0 < main_~j~0); 15134#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15133#L12-2 assume !!(main_~i~0 < main_~j~0); 15131#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15130#L12-2 assume !!(main_~i~0 < main_~j~0); 15129#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15128#L12-2 assume !!(main_~i~0 < main_~j~0); 15125#L12 [2019-12-07 12:14:01,490 INFO L796 eck$LassoCheckResult]: Loop: 15125#L12 assume !(51 < main_~j~0);main_~i~0 := main_~i~0 - 1;main_~j~0 := 1 + main_~j~0; 15126#L12-2 assume !!(main_~i~0 < main_~j~0); 15129#L12 assume 51 < main_~j~0;main_~i~0 := 1 + main_~i~0;main_~j~0 := main_~j~0 - 1; 15128#L12-2 assume !!(main_~i~0 < main_~j~0); 15125#L12 [2019-12-07 12:14:01,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:01,490 INFO L82 PathProgramCache]: Analyzing trace with hash 844798583, now seen corresponding path program 49 times [2019-12-07 12:14:01,490 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:01,490 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184612890] [2019-12-07 12:14:01,490 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:01,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,518 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:14:01,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:01,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1380409, now seen corresponding path program 47 times [2019-12-07 12:14:01,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:01,518 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427499073] [2019-12-07 12:14:01,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:01,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,520 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:14:01,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:14:01,520 INFO L82 PathProgramCache]: Analyzing trace with hash -166625361, now seen corresponding path program 49 times [2019-12-07 12:14:01,520 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:14:01,520 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974811002] [2019-12-07 12:14:01,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:14:01,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:14:01,547 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:14:03,344 WARN L192 SmtUtils]: Spent 1.77 s on a formula simplification. DAG size of input: 403 DAG size of output: 303 [2019-12-07 12:14:03,386 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 12:14:03 BoogieIcfgContainer [2019-12-07 12:14:03,387 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 12:14:03,387 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:14:03,387 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:14:03,387 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:14:03,387 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:13:39" (3/4) ... [2019-12-07 12:14:03,390 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 12:14:03,435 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_9714d39f-3f88-4a91-950c-b18dd149095e/bin/uautomizer/witness.graphml [2019-12-07 12:14:03,435 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:14:03,436 INFO L168 Benchmark]: Toolchain (without parser) took 23816.53 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 382.2 MB). Free memory was 946.3 MB in the beginning and 871.5 MB in the end (delta: 74.7 MB). Peak memory consumption was 457.0 MB. Max. memory is 11.5 GB. [2019-12-07 12:14:03,437 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:14:03,437 INFO L168 Benchmark]: CACSL2BoogieTranslator took 171.22 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -151.8 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:14:03,437 INFO L168 Benchmark]: Boogie Procedure Inliner took 21.94 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:14:03,437 INFO L168 Benchmark]: Boogie Preprocessor took 11.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:14:03,437 INFO L168 Benchmark]: RCFGBuilder took 120.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. [2019-12-07 12:14:03,438 INFO L168 Benchmark]: BuchiAutomizer took 23439.54 ms. Allocated memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: 280.5 MB). Free memory was 1.1 GB in the beginning and 886.7 MB in the end (delta: 191.7 MB). Peak memory consumption was 554.5 MB. Max. memory is 11.5 GB. [2019-12-07 12:14:03,438 INFO L168 Benchmark]: Witness Printer took 48.49 ms. Allocated memory is still 1.4 GB. Free memory was 886.7 MB in the beginning and 871.5 MB in the end (delta: 15.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. [2019-12-07 12:14:03,440 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 171.22 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -151.8 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 21.94 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 11.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 120.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 23439.54 ms. Allocated memory was 1.1 GB in the beginning and 1.4 GB in the end (delta: 280.5 MB). Free memory was 1.1 GB in the beginning and 886.7 MB in the end (delta: 191.7 MB). Peak memory consumption was 554.5 MB. Max. memory is 11.5 GB. * Witness Printer took 48.49 ms. Allocated memory is still 1.4 GB. Free memory was 886.7 MB in the beginning and 871.5 MB in the end (delta: 15.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 53 terminating modules (49 trivial, 2 deterministic, 2 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function j and consists of 4 locations. One deterministic module has affine ranking function j and consists of 3 locations. One nondeterministic module has affine ranking function j and consists of 3 locations. One nondeterministic module has affine ranking function -2 * j + 103 and consists of 3 locations. 49 modules have a trivial ranking function, the largest among these consists of 51 locations. The remainder module has 103 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 23.3s and 51 iterations. TraceHistogramMax:50. Analysis of lassos took 20.5s. Construction of modules took 1.7s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 53. Automata minimization 0.0s AutomataMinimizationTime, 53 MinimizatonAttempts, 57 StatesRemovedByMinimization, 51 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 103 states and ocurred in iteration 50. Nontrivial modules had stage [2, 0, 2, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 126 SDtfs, 29 SDslu, 3 SDs, 0 SdLazy, 3392 SolverSat, 82 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.7s Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc46 concLT1 SILN0 SILU0 SILI0 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital18 mio100 ax165 hnf99 lsp59 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq166 hnf93 smp100 dnf100 smp100 tf107 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 14ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 5 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 12]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, i=49, j=51} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 12]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int j; [L8] j = 100 [L9] i = 0 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j Loop: [L12] COND FALSE !(51 < j) [L13] i = i-1 [L13] j = j+1 [L11] COND TRUE i < j [L12] COND TRUE 51 < j [L12] i = i+1 [L12] j = j-1 [L11] COND TRUE i < j End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...