./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 446a3f39420f718ff3d1f0852398f1e5da972fdc .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:48:56,931 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:48:56,932 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:48:56,940 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:48:56,940 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:48:56,941 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:48:56,942 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:48:56,943 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:48:56,944 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:48:56,945 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:48:56,945 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:48:56,946 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:48:56,946 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:48:56,947 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:48:56,948 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:48:56,949 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:48:56,949 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:48:56,950 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:48:56,951 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:48:56,953 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:48:56,954 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:48:56,955 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:48:56,956 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:48:56,956 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:48:56,958 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:48:56,958 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:48:56,958 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:48:56,959 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:48:56,959 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:48:56,960 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:48:56,960 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:48:56,960 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:48:56,961 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:48:56,961 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:48:56,962 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:48:56,962 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:48:56,962 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:48:56,962 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:48:56,962 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:48:56,963 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:48:56,963 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:48:56,964 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/config/svcomp-Termination-64bit-Automizer_Default.epf [2019-12-07 18:48:56,975 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:48:56,976 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:48:56,976 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:48:56,976 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:48:56,976 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:48:56,977 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:48:56,977 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:48:56,977 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:48:56,978 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:48:56,979 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:48:56,979 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:48:56,979 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:48:56,979 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:48:56,979 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:48:56,979 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:48:56,979 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:48:56,980 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:48:56,980 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:48:56,980 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 446a3f39420f718ff3d1f0852398f1e5da972fdc [2019-12-07 18:48:57,084 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:48:57,093 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:48:57,096 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:48:57,097 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:48:57,097 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:48:57,098 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2019-12-07 18:48:57,136 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/data/d522e4c56/39c3886795c442adaabc17c122929d00/FLAGcd2fa34bd [2019-12-07 18:48:57,527 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:48:57,528 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2019-12-07 18:48:57,532 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/data/d522e4c56/39c3886795c442adaabc17c122929d00/FLAGcd2fa34bd [2019-12-07 18:48:57,907 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/data/d522e4c56/39c3886795c442adaabc17c122929d00 [2019-12-07 18:48:57,910 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:48:57,911 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:48:57,911 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:48:57,912 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:48:57,914 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:48:57,914 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:48:57" (1/1) ... [2019-12-07 18:48:57,916 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ca783c9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:57, skipping insertion in model container [2019-12-07 18:48:57,916 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:48:57" (1/1) ... [2019-12-07 18:48:57,921 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:48:57,931 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:48:58,039 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:48:58,042 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:48:58,052 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:48:58,092 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:48:58,092 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58 WrapperNode [2019-12-07 18:48:58,092 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:48:58,093 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:48:58,093 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:48:58,093 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:48:58,098 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,102 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,112 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:48:58,113 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:48:58,113 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:48:58,113 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:48:58,118 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,118 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,119 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,119 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,120 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,123 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,123 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... [2019-12-07 18:48:58,124 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:48:58,124 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:48:58,124 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:48:58,124 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:48:58,125 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,163 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:48:58,164 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:48:58,248 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:48:58,248 INFO L287 CfgBuilder]: Removed 5 assume(true) statements. [2019-12-07 18:48:58,249 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:48:58 BoogieIcfgContainer [2019-12-07 18:48:58,249 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:48:58,249 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:48:58,249 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:48:58,252 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:48:58,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:48:58,252 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:48:57" (1/3) ... [2019-12-07 18:48:58,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1209cd78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:48:58, skipping insertion in model container [2019-12-07 18:48:58,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:48:58,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:48:58" (2/3) ... [2019-12-07 18:48:58,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1209cd78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:48:58, skipping insertion in model container [2019-12-07 18:48:58,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:48:58,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:48:58" (3/3) ... [2019-12-07 18:48:58,254 INFO L371 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2019-12-07 18:48:58,283 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:48:58,283 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:48:58,283 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:48:58,283 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:48:58,283 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:48:58,283 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:48:58,283 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:48:58,283 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:48:58,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states. [2019-12-07 18:48:58,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:58,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:58,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:58,309 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1] [2019-12-07 18:48:58,309 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:48:58,309 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:48:58,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states. [2019-12-07 18:48:58,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:58,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:58,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:58,310 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1] [2019-12-07 18:48:58,310 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:48:58,315 INFO L794 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 4#L12-1true [2019-12-07 18:48:58,315 INFO L796 eck$LassoCheckResult]: Loop: 4#L12-1true assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6#L12true assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4#L12-1true [2019-12-07 18:48:58,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,319 INFO L82 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2019-12-07 18:48:58,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720163722] [2019-12-07 18:48:58,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,387 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,388 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 1 times [2019-12-07 18:48:58,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195056556] [2019-12-07 18:48:58,389 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,397 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,398 INFO L82 PathProgramCache]: Analyzing trace with hash 31083, now seen corresponding path program 1 times [2019-12-07 18:48:58,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705714335] [2019-12-07 18:48:58,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:58,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:58,434 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705714335] [2019-12-07 18:48:58,434 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:48:58,435 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:48:58,435 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808324792] [2019-12-07 18:48:58,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:58,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:48:58,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:48:58,472 INFO L87 Difference]: Start difference. First operand 8 states. Second operand 3 states. [2019-12-07 18:48:58,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:58,499 INFO L93 Difference]: Finished difference Result 15 states and 18 transitions. [2019-12-07 18:48:58,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:48:58,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 18 transitions. [2019-12-07 18:48:58,502 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2019-12-07 18:48:58,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 7 states and 10 transitions. [2019-12-07 18:48:58,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2019-12-07 18:48:58,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2019-12-07 18:48:58,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 10 transitions. [2019-12-07 18:48:58,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:48:58,507 INFO L688 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 18:48:58,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 10 transitions. [2019-12-07 18:48:58,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2019-12-07 18:48:58,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7 states. [2019-12-07 18:48:58,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 10 transitions. [2019-12-07 18:48:58,529 INFO L711 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 18:48:58,529 INFO L591 BuchiCegarLoop]: Abstraction has 7 states and 10 transitions. [2019-12-07 18:48:58,530 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:48:58,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 10 transitions. [2019-12-07 18:48:58,530 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2019-12-07 18:48:58,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:58,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:58,531 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1] [2019-12-07 18:48:58,531 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2019-12-07 18:48:58,531 INFO L794 eck$LassoCheckResult]: Stem: 34#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 35#L12-1 [2019-12-07 18:48:58,531 INFO L796 eck$LassoCheckResult]: Loop: 35#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 35#L12-1 [2019-12-07 18:48:58,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,531 INFO L82 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 2 times [2019-12-07 18:48:58,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500580940] [2019-12-07 18:48:58,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,536 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,537 INFO L82 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 1 times [2019-12-07 18:48:58,537 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,537 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367887808] [2019-12-07 18:48:58,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,545 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,545 INFO L82 PathProgramCache]: Analyzing trace with hash 963343, now seen corresponding path program 1 times [2019-12-07 18:48:58,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925529158] [2019-12-07 18:48:58,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,554 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,585 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:58,585 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:58,586 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:58,586 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:58,586 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 18:48:58,586 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,586 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:58,586 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:58,586 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2019-12-07 18:48:58,586 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:58,586 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:58,600 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,608 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,673 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:58,674 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,678 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:58,678 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:58,684 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 18:48:58,684 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,688 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:58,688 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:58,692 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 18:48:58,692 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,696 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:58,696 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,703 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 18:48:58,703 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:58,723 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 18:48:58,724 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:58,724 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:58,724 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:58,724 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:58,724 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 18:48:58,724 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,725 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:58,725 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:58,725 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2019-12-07 18:48:58,725 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:58,725 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:58,726 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,729 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,731 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:58,777 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:58,781 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,785 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:58,787 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:58,787 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:58,787 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:58,787 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:58,792 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 18:48:58,792 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 18:48:58,796 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,803 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:58,804 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:58,805 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:58,805 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:58,805 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:58,808 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 18:48:58,808 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 18:48:58,812 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,816 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:58,817 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:58,817 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 18:48:58,818 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:58,818 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:58,818 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:58,819 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 18:48:58,819 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 18:48:58,821 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 18:48:58,826 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2019-12-07 18:48:58,826 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:58,830 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 18:48:58,830 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 18:48:58,830 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 18:48:58,831 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, ULTIMATE.start_main_~range~0) = -1*ULTIMATE.start_main_~i~0 + 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2019-12-07 18:48:58,834 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 18:48:58,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:58,857 INFO L264 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:48:58,858 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:58,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:58,863 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:58,864 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:58,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:58,874 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 18:48:58,874 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5 Second operand 3 states. [2019-12-07 18:48:58,898 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 7 states and 10 transitions. cyclomatic complexity: 5. Second operand 3 states. Result 10 states and 14 transitions. Complement of second has 5 states. [2019-12-07 18:48:58,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:48:58,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 18:48:58,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 4 transitions. [2019-12-07 18:48:58,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 1 letters. Loop has 3 letters. [2019-12-07 18:48:58,900 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:58,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 4 letters. Loop has 3 letters. [2019-12-07 18:48:58,900 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:58,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 4 transitions. Stem has 1 letters. Loop has 6 letters. [2019-12-07 18:48:58,901 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:58,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 14 transitions. [2019-12-07 18:48:58,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:58,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 10 states and 14 transitions. [2019-12-07 18:48:58,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:48:58,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2019-12-07 18:48:58,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 14 transitions. [2019-12-07 18:48:58,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:48:58,902 INFO L688 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2019-12-07 18:48:58,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 14 transitions. [2019-12-07 18:48:58,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2019-12-07 18:48:58,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-12-07 18:48:58,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 14 transitions. [2019-12-07 18:48:58,903 INFO L711 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2019-12-07 18:48:58,903 INFO L591 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2019-12-07 18:48:58,903 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:48:58,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 14 transitions. [2019-12-07 18:48:58,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:58,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:58,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:58,904 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2019-12-07 18:48:58,904 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:48:58,905 INFO L794 eck$LassoCheckResult]: Stem: 84#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 85#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 90#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 91#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 86#L12-1 [2019-12-07 18:48:58,905 INFO L796 eck$LassoCheckResult]: Loop: 86#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 87#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 86#L12-1 [2019-12-07 18:48:58,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,905 INFO L82 PathProgramCache]: Analyzing trace with hash 963341, now seen corresponding path program 1 times [2019-12-07 18:48:58,905 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708149832] [2019-12-07 18:48:58,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,912 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 2 times [2019-12-07 18:48:58,913 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,913 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423689299] [2019-12-07 18:48:58,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:58,917 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:58,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:58,917 INFO L82 PathProgramCache]: Analyzing trace with hash 925771032, now seen corresponding path program 1 times [2019-12-07 18:48:58,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:58,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137617985] [2019-12-07 18:48:58,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:58,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:58,936 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:58,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137617985] [2019-12-07 18:48:58,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [673761760] [2019-12-07 18:48:58,936 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:48:58,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:58,953 INFO L264 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:58,953 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:58,969 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:58,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:48:58,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2] total 3 [2019-12-07 18:48:58,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193052548] [2019-12-07 18:48:58,980 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:58,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:48:58,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:48:58,981 INFO L87 Difference]: Start difference. First operand 10 states and 14 transitions. cyclomatic complexity: 6 Second operand 5 states. [2019-12-07 18:48:58,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:58,998 INFO L93 Difference]: Finished difference Result 13 states and 17 transitions. [2019-12-07 18:48:58,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:48:58,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 17 transitions. [2019-12-07 18:48:58,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:59,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 17 transitions. [2019-12-07 18:48:59,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:48:59,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:48:59,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 17 transitions. [2019-12-07 18:48:59,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:48:59,000 INFO L688 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2019-12-07 18:48:59,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 17 transitions. [2019-12-07 18:48:59,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2019-12-07 18:48:59,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-12-07 18:48:59,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 17 transitions. [2019-12-07 18:48:59,002 INFO L711 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2019-12-07 18:48:59,002 INFO L591 BuchiCegarLoop]: Abstraction has 13 states and 17 transitions. [2019-12-07 18:48:59,003 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:48:59,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 17 transitions. [2019-12-07 18:48:59,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2019-12-07 18:48:59,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:59,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:59,004 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1] [2019-12-07 18:48:59,004 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:48:59,004 INFO L794 eck$LassoCheckResult]: Stem: 132#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 138#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 142#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 134#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 139#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 141#L12-1 [2019-12-07 18:48:59,004 INFO L796 eck$LassoCheckResult]: Loop: 141#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 144#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 141#L12-1 [2019-12-07 18:48:59,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1365869310, now seen corresponding path program 1 times [2019-12-07 18:48:59,005 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,005 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394696119] [2019-12-07 18:48:59,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,018 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,018 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 3 times [2019-12-07 18:48:59,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840643064] [2019-12-07 18:48:59,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,024 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,024 INFO L82 PathProgramCache]: Analyzing trace with hash 1659585997, now seen corresponding path program 1 times [2019-12-07 18:48:59,024 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,024 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032316560] [2019-12-07 18:48:59,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,050 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032316560] [2019-12-07 18:48:59,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1758343039] [2019-12-07 18:48:59,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:48:59,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,067 INFO L264 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 3 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,067 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,069 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,069 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 18:48:59,069 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 4 [2019-12-07 18:48:59,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902456932] [2019-12-07 18:48:59,080 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:48:59,080 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:48:59,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:48:59,080 INFO L87 Difference]: Start difference. First operand 13 states and 17 transitions. cyclomatic complexity: 6 Second operand 4 states. [2019-12-07 18:48:59,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:48:59,096 INFO L93 Difference]: Finished difference Result 20 states and 25 transitions. [2019-12-07 18:48:59,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:48:59,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 25 transitions. [2019-12-07 18:48:59,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2019-12-07 18:48:59,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 20 states and 25 transitions. [2019-12-07 18:48:59,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2019-12-07 18:48:59,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2019-12-07 18:48:59,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 25 transitions. [2019-12-07 18:48:59,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:48:59,099 INFO L688 BuchiCegarLoop]: Abstraction has 20 states and 25 transitions. [2019-12-07 18:48:59,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 25 transitions. [2019-12-07 18:48:59,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 15. [2019-12-07 18:48:59,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-12-07 18:48:59,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 19 transitions. [2019-12-07 18:48:59,102 INFO L711 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2019-12-07 18:48:59,102 INFO L591 BuchiCegarLoop]: Abstraction has 15 states and 19 transitions. [2019-12-07 18:48:59,102 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:48:59,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 19 transitions. [2019-12-07 18:48:59,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 18:48:59,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:59,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:59,103 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1] [2019-12-07 18:48:59,104 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2019-12-07 18:48:59,104 INFO L794 eck$LassoCheckResult]: Stem: 199#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 205#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 206#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 209#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 213#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 208#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 201#L12-1 [2019-12-07 18:48:59,104 INFO L796 eck$LassoCheckResult]: Loop: 201#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 202#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 210#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 201#L12-1 [2019-12-07 18:48:59,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,104 INFO L82 PathProgramCache]: Analyzing trace with hash -1365869310, now seen corresponding path program 2 times [2019-12-07 18:48:59,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539369875] [2019-12-07 18:48:59,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,116 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,116 INFO L82 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 2 times [2019-12-07 18:48:59,116 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,117 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095037174] [2019-12-07 18:48:59,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,122 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,123 INFO L82 PathProgramCache]: Analyzing trace with hash -92441875, now seen corresponding path program 3 times [2019-12-07 18:48:59,123 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,123 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224932479] [2019-12-07 18:48:59,124 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,137 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,158 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,158 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,158 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,158 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,159 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 18:48:59,159 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,159 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,159 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,159 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2019-12-07 18:48:59,159 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,159 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,160 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,163 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,165 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,214 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:59,215 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,217 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:59,217 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:59,220 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 18:48:59,221 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,224 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:59,224 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:59,227 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 18:48:59,227 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,231 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:59,231 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,238 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 18:48:59,238 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:59,267 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 18:48:59,268 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,268 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,268 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,269 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,269 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 18:48:59,269 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,269 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,269 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,269 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2019-12-07 18:48:59,269 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,269 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,270 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,274 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,327 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:59,327 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,330 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:59,331 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:59,332 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:59,332 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:59,332 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:59,334 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 18:48:59,334 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 18:48:59,338 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,343 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:59,344 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:59,344 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:59,344 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:59,344 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:59,347 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2019-12-07 18:48:59,347 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2019-12-07 18:48:59,351 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,356 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:59,357 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:59,357 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 18:48:59,357 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:59,357 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:59,357 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:59,358 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 18:48:59,359 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 18:48:59,360 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 18:48:59,364 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 18:48:59,364 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,367 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 18:48:59,367 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 18:48:59,367 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 18:48:59,367 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0, ULTIMATE.start_main_~i~0) = 1*ULTIMATE.start_main_~range~0 - 1*ULTIMATE.start_main_~i~0 Supporting invariants [] [2019-12-07 18:48:59,369 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 18:48:59,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,384 INFO L264 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,384 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,387 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,388 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,395 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 18:48:59,395 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 15 states and 19 transitions. cyclomatic complexity: 6 Second operand 3 states. [2019-12-07 18:48:59,405 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 15 states and 19 transitions. cyclomatic complexity: 6. Second operand 3 states. Result 32 states and 38 transitions. Complement of second has 5 states. [2019-12-07 18:48:59,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:48:59,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 18:48:59,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2019-12-07 18:48:59,406 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 7 letters. Loop has 3 letters. [2019-12-07 18:48:59,407 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,407 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 10 letters. Loop has 3 letters. [2019-12-07 18:48:59,407 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,407 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 7 letters. Loop has 6 letters. [2019-12-07 18:48:59,407 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 38 transitions. [2019-12-07 18:48:59,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 18:48:59,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 28 states and 34 transitions. [2019-12-07 18:48:59,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2019-12-07 18:48:59,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2019-12-07 18:48:59,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2019-12-07 18:48:59,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:48:59,411 INFO L688 BuchiCegarLoop]: Abstraction has 28 states and 34 transitions. [2019-12-07 18:48:59,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2019-12-07 18:48:59,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2019-12-07 18:48:59,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-12-07 18:48:59,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 32 transitions. [2019-12-07 18:48:59,413 INFO L711 BuchiCegarLoop]: Abstraction has 26 states and 32 transitions. [2019-12-07 18:48:59,413 INFO L591 BuchiCegarLoop]: Abstraction has 26 states and 32 transitions. [2019-12-07 18:48:59,413 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:48:59,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 32 transitions. [2019-12-07 18:48:59,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2019-12-07 18:48:59,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:59,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:59,415 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1] [2019-12-07 18:48:59,415 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2019-12-07 18:48:59,415 INFO L794 eck$LassoCheckResult]: Stem: 297#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 298#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 305#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 322#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 321#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 320#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 318#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 307#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 299#L12-1 [2019-12-07 18:48:59,415 INFO L796 eck$LassoCheckResult]: Loop: 299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 300#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 316#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 299#L12-1 [2019-12-07 18:48:59,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,415 INFO L82 PathProgramCache]: Analyzing trace with hash 1682505905, now seen corresponding path program 4 times [2019-12-07 18:48:59,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640552033] [2019-12-07 18:48:59,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,426 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,426 INFO L82 PathProgramCache]: Analyzing trace with hash 39822, now seen corresponding path program 3 times [2019-12-07 18:48:59,427 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,427 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611000916] [2019-12-07 18:48:59,427 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,432 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,432 INFO L82 PathProgramCache]: Analyzing trace with hash 1265081566, now seen corresponding path program 5 times [2019-12-07 18:48:59,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075705616] [2019-12-07 18:48:59,433 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,443 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,463 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,463 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,463 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,463 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,463 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 18:48:59,463 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,464 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,464 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,464 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2019-12-07 18:48:59,464 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,464 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,511 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:59,511 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,515 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:59,516 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,522 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 18:48:59,522 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:59,540 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 18:48:59,542 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,542 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,542 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,542 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,542 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 18:48:59,542 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,542 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,542 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,542 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2019-12-07 18:48:59,543 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,543 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,550 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,551 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,580 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:59,580 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,583 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:48:59,584 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:48:59,584 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 18:48:59,584 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:48:59,584 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:48:59,584 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:48:59,585 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 18:48:59,585 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 18:48:59,586 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 18:48:59,589 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2019-12-07 18:48:59,589 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,591 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 18:48:59,591 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 18:48:59,592 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 18:48:59,592 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, ULTIMATE.start_main_~range~0) = -1*ULTIMATE.start_main_~i~0 + 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2019-12-07 18:48:59,593 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 18:48:59,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,605 INFO L264 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,605 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,608 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,608 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,614 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 18:48:59,615 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9 Second operand 3 states. [2019-12-07 18:48:59,623 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9. Second operand 3 states. Result 36 states and 44 transitions. Complement of second has 5 states. [2019-12-07 18:48:59,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:48:59,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 18:48:59,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2019-12-07 18:48:59,624 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 10 letters. Loop has 3 letters. [2019-12-07 18:48:59,624 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,624 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 18:48:59,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,636 INFO L264 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,636 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,639 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,639 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,646 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 18:48:59,646 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9 Second operand 3 states. [2019-12-07 18:48:59,654 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9. Second operand 3 states. Result 36 states and 44 transitions. Complement of second has 5 states. [2019-12-07 18:48:59,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:48:59,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 18:48:59,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 8 transitions. [2019-12-07 18:48:59,655 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 8 transitions. Stem has 10 letters. Loop has 3 letters. [2019-12-07 18:48:59,655 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,655 INFO L639 RefineBuchi]: Bad chosen interpolant automaton: word not accepted [2019-12-07 18:48:59,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,667 INFO L264 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,668 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,672 WARN L262 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,672 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,685 INFO L152 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2019-12-07 18:48:59,685 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9 Second operand 3 states. [2019-12-07 18:48:59,695 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 26 states and 32 transitions. cyclomatic complexity: 9. Second operand 3 states. Result 40 states and 50 transitions. Complement of second has 4 states. [2019-12-07 18:48:59,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:48:59,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2019-12-07 18:48:59,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 10 transitions. [2019-12-07 18:48:59,695 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 10 letters. Loop has 3 letters. [2019-12-07 18:48:59,696 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,696 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 13 letters. Loop has 3 letters. [2019-12-07 18:48:59,696 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,696 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 10 transitions. Stem has 10 letters. Loop has 6 letters. [2019-12-07 18:48:59,696 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:48:59,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 50 transitions. [2019-12-07 18:48:59,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2019-12-07 18:48:59,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 32 states and 40 transitions. [2019-12-07 18:48:59,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2019-12-07 18:48:59,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2019-12-07 18:48:59,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 40 transitions. [2019-12-07 18:48:59,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:48:59,699 INFO L688 BuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2019-12-07 18:48:59,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 40 transitions. [2019-12-07 18:48:59,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 19. [2019-12-07 18:48:59,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-12-07 18:48:59,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 25 transitions. [2019-12-07 18:48:59,700 INFO L711 BuchiCegarLoop]: Abstraction has 19 states and 25 transitions. [2019-12-07 18:48:59,700 INFO L591 BuchiCegarLoop]: Abstraction has 19 states and 25 transitions. [2019-12-07 18:48:59,700 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:48:59,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 25 transitions. [2019-12-07 18:48:59,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2019-12-07 18:48:59,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:48:59,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:48:59,701 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1] [2019-12-07 18:48:59,701 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2019-12-07 18:48:59,701 INFO L794 eck$LassoCheckResult]: Stem: 584#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 591#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 587#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 595#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 596#L12-1 [2019-12-07 18:48:59,701 INFO L796 eck$LassoCheckResult]: Loop: 596#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 601#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 600#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 599#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 596#L12-1 [2019-12-07 18:48:59,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,702 INFO L82 PathProgramCache]: Analyzing trace with hash -1365869310, now seen corresponding path program 6 times [2019-12-07 18:48:59,702 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,702 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124308702] [2019-12-07 18:48:59,702 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,708 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,708 INFO L82 PathProgramCache]: Analyzing trace with hash 1186287651, now seen corresponding path program 1 times [2019-12-07 18:48:59,708 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,708 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45672586] [2019-12-07 18:48:59,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:48:59,713 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:48:59,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:48:59,713 INFO L82 PathProgramCache]: Analyzing trace with hash -861910940, now seen corresponding path program 7 times [2019-12-07 18:48:59,713 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:48:59,713 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776135712] [2019-12-07 18:48:59,713 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:48:59,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,789 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776135712] [2019-12-07 18:48:59,790 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [374741549] [2019-12-07 18:48:59,790 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:48:59,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:48:59,807 INFO L264 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:48:59,808 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:48:59,828 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:48:59,829 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:48:59,829 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 4] total 11 [2019-12-07 18:48:59,829 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521749778] [2019-12-07 18:48:59,861 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,861 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,861 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,861 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,861 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 18:48:59,861 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,861 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,861 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,861 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2019-12-07 18:48:59,862 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,862 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,862 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,870 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,872 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:48:59,914 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:48:59,914 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,917 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:48:59,917 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,923 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 18:48:59,924 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:48:59,993 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 18:48:59,995 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:48:59,995 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:48:59,995 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:48:59,996 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:48:59,996 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 18:48:59,996 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:48:59,996 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:48:59,996 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:48:59,996 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2019-12-07 18:48:59,996 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:48:59,996 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:48:59,997 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:49:00,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:49:00,007 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:49:00,044 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:49:00,044 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:49:00,047 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:49:00,048 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:49:00,048 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 18:49:00,049 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:49:00,049 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:49:00,049 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:49:00,049 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 18:49:00,049 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 18:49:00,052 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 18:49:00,054 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 18:49:00,054 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:49:00,056 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 18:49:00,057 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 18:49:00,057 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 18:49:00,057 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0) = 1*ULTIMATE.start_main_~range~0 Supporting invariants [] [2019-12-07 18:49:00,059 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 18:49:00,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,069 INFO L264 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,070 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:00,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,073 INFO L264 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,073 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:00,085 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,085 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-12-07 18:49:00,085 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 19 states and 25 transitions. cyclomatic complexity: 8 Second operand 4 states. [2019-12-07 18:49:00,095 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 19 states and 25 transitions. cyclomatic complexity: 8. Second operand 4 states. Result 48 states and 65 transitions. Complement of second has 4 states. [2019-12-07 18:49:00,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:49:00,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2019-12-07 18:49:00,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 11 transitions. [2019-12-07 18:49:00,096 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 7 letters. Loop has 6 letters. [2019-12-07 18:49:00,096 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:49:00,096 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 13 letters. Loop has 6 letters. [2019-12-07 18:49:00,096 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:49:00,096 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 7 letters. Loop has 12 letters. [2019-12-07 18:49:00,097 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:49:00,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 65 transitions. [2019-12-07 18:49:00,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 32 states and 41 transitions. [2019-12-07 18:49:00,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:00,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2019-12-07 18:49:00,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 41 transitions. [2019-12-07 18:49:00,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:00,099 INFO L688 BuchiCegarLoop]: Abstraction has 32 states and 41 transitions. [2019-12-07 18:49:00,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 41 transitions. [2019-12-07 18:49:00,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 25. [2019-12-07 18:49:00,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-12-07 18:49:00,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 32 transitions. [2019-12-07 18:49:00,101 INFO L711 BuchiCegarLoop]: Abstraction has 25 states and 32 transitions. [2019-12-07 18:49:00,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:00,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:49:00,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:49:00,101 INFO L87 Difference]: Start difference. First operand 25 states and 32 transitions. Second operand 12 states. [2019-12-07 18:49:00,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:00,160 INFO L93 Difference]: Finished difference Result 40 states and 47 transitions. [2019-12-07 18:49:00,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:49:00,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 47 transitions. [2019-12-07 18:49:00,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 33 states and 38 transitions. [2019-12-07 18:49:00,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2019-12-07 18:49:00,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2019-12-07 18:49:00,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 38 transitions. [2019-12-07 18:49:00,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:00,162 INFO L688 BuchiCegarLoop]: Abstraction has 33 states and 38 transitions. [2019-12-07 18:49:00,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 38 transitions. [2019-12-07 18:49:00,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 30. [2019-12-07 18:49:00,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-12-07 18:49:00,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 35 transitions. [2019-12-07 18:49:00,165 INFO L711 BuchiCegarLoop]: Abstraction has 30 states and 35 transitions. [2019-12-07 18:49:00,165 INFO L591 BuchiCegarLoop]: Abstraction has 30 states and 35 transitions. [2019-12-07 18:49:00,165 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:49:00,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 35 transitions. [2019-12-07 18:49:00,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:00,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:00,166 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [6, 5, 3, 2, 1] [2019-12-07 18:49:00,166 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:00,166 INFO L794 eck$LassoCheckResult]: Stem: 823#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 824#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 841#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 840#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 835#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 834#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 832#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 826#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 852#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 851#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 848#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 850#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 847#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 849#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 844#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 838#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 837#L12 [2019-12-07 18:49:00,167 INFO L796 eck$LassoCheckResult]: Loop: 837#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 836#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 837#L12 [2019-12-07 18:49:00,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,167 INFO L82 PathProgramCache]: Analyzing trace with hash 1216646815, now seen corresponding path program 8 times [2019-12-07 18:49:00,167 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,167 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060221882] [2019-12-07 18:49:00,167 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,215 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 5 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060221882] [2019-12-07 18:49:00,216 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1918471540] [2019-12-07 18:49:00,216 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:00,234 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:49:00,234 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:00,234 INFO L264 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 7 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,235 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:00,265 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 5 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,265 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:00,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6] total 12 [2019-12-07 18:49:00,265 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140572246] [2019-12-07 18:49:00,265 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:00,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 4 times [2019-12-07 18:49:00,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391018213] [2019-12-07 18:49:00,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,268 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:00,277 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:00,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:49:00,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:49:00,277 INFO L87 Difference]: Start difference. First operand 30 states and 35 transitions. cyclomatic complexity: 8 Second operand 13 states. [2019-12-07 18:49:00,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:00,319 INFO L93 Difference]: Finished difference Result 42 states and 47 transitions. [2019-12-07 18:49:00,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:49:00,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 47 transitions. [2019-12-07 18:49:00,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 38 states and 43 transitions. [2019-12-07 18:49:00,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:00,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:00,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 43 transitions. [2019-12-07 18:49:00,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:00,321 INFO L688 BuchiCegarLoop]: Abstraction has 38 states and 43 transitions. [2019-12-07 18:49:00,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 43 transitions. [2019-12-07 18:49:00,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 36. [2019-12-07 18:49:00,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-12-07 18:49:00,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 41 transitions. [2019-12-07 18:49:00,323 INFO L711 BuchiCegarLoop]: Abstraction has 36 states and 41 transitions. [2019-12-07 18:49:00,323 INFO L591 BuchiCegarLoop]: Abstraction has 36 states and 41 transitions. [2019-12-07 18:49:00,323 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:49:00,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 41 transitions. [2019-12-07 18:49:00,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:00,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:00,324 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [8, 7, 5, 2, 1] [2019-12-07 18:49:00,324 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:00,324 INFO L794 eck$LassoCheckResult]: Stem: 959#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 976#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 969#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 968#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 962#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 993#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 990#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 989#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 987#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 986#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 984#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 980#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 973#L12 [2019-12-07 18:49:00,324 INFO L796 eck$LassoCheckResult]: Loop: 973#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 973#L12 [2019-12-07 18:49:00,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,324 INFO L82 PathProgramCache]: Analyzing trace with hash 1280613055, now seen corresponding path program 9 times [2019-12-07 18:49:00,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934715728] [2019-12-07 18:49:00,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,391 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 7 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934715728] [2019-12-07 18:49:00,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [716403470] [2019-12-07 18:49:00,392 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:00,411 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2019-12-07 18:49:00,411 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:00,411 INFO L264 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,412 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:00,461 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 7 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,461 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:00,461 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 16 [2019-12-07 18:49:00,461 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506449609] [2019-12-07 18:49:00,461 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:00,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,462 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 5 times [2019-12-07 18:49:00,462 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,462 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137831432] [2019-12-07 18:49:00,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,464 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:00,472 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:00,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:49:00,473 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=165, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:49:00,473 INFO L87 Difference]: Start difference. First operand 36 states and 41 transitions. cyclomatic complexity: 8 Second operand 17 states. [2019-12-07 18:49:00,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:00,531 INFO L93 Difference]: Finished difference Result 48 states and 53 transitions. [2019-12-07 18:49:00,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:49:00,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 53 transitions. [2019-12-07 18:49:00,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 44 states and 49 transitions. [2019-12-07 18:49:00,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:00,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:00,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 49 transitions. [2019-12-07 18:49:00,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:00,533 INFO L688 BuchiCegarLoop]: Abstraction has 44 states and 49 transitions. [2019-12-07 18:49:00,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 49 transitions. [2019-12-07 18:49:00,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 42. [2019-12-07 18:49:00,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2019-12-07 18:49:00,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 47 transitions. [2019-12-07 18:49:00,535 INFO L711 BuchiCegarLoop]: Abstraction has 42 states and 47 transitions. [2019-12-07 18:49:00,535 INFO L591 BuchiCegarLoop]: Abstraction has 42 states and 47 transitions. [2019-12-07 18:49:00,535 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:49:00,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 47 transitions. [2019-12-07 18:49:00,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:00,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:00,536 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [10, 9, 7, 2, 1] [2019-12-07 18:49:00,537 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:00,537 INFO L794 eck$LassoCheckResult]: Stem: 1129#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1140#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1146#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1147#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1139#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1138#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1131#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1169#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1168#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1167#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1166#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1165#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1164#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1163#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1162#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1160#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1159#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1158#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1157#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1156#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1155#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1152#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1154#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1150#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1143#L12 [2019-12-07 18:49:00,537 INFO L796 eck$LassoCheckResult]: Loop: 1143#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1143#L12 [2019-12-07 18:49:00,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1682764065, now seen corresponding path program 10 times [2019-12-07 18:49:00,537 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,537 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991315560] [2019-12-07 18:49:00,537 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,628 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 9 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991315560] [2019-12-07 18:49:00,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [395829787] [2019-12-07 18:49:00,629 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:00,652 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:49:00,652 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:00,653 INFO L264 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,653 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:00,722 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 9 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:00,722 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 20 [2019-12-07 18:49:00,722 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567976202] [2019-12-07 18:49:00,722 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:00,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,723 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 6 times [2019-12-07 18:49:00,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746488997] [2019-12-07 18:49:00,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:00,725 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:00,734 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:00,734 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:49:00,734 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=164, Invalid=256, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:49:00,734 INFO L87 Difference]: Start difference. First operand 42 states and 47 transitions. cyclomatic complexity: 8 Second operand 21 states. [2019-12-07 18:49:00,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:00,785 INFO L93 Difference]: Finished difference Result 54 states and 59 transitions. [2019-12-07 18:49:00,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:49:00,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 59 transitions. [2019-12-07 18:49:00,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 50 states and 55 transitions. [2019-12-07 18:49:00,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:00,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:00,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 55 transitions. [2019-12-07 18:49:00,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:00,787 INFO L688 BuchiCegarLoop]: Abstraction has 50 states and 55 transitions. [2019-12-07 18:49:00,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 55 transitions. [2019-12-07 18:49:00,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 48. [2019-12-07 18:49:00,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-12-07 18:49:00,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 53 transitions. [2019-12-07 18:49:00,790 INFO L711 BuchiCegarLoop]: Abstraction has 48 states and 53 transitions. [2019-12-07 18:49:00,790 INFO L591 BuchiCegarLoop]: Abstraction has 48 states and 53 transitions. [2019-12-07 18:49:00,791 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:49:00,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 53 transitions. [2019-12-07 18:49:00,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:00,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:00,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:00,792 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1] [2019-12-07 18:49:00,792 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:00,793 INFO L794 eck$LassoCheckResult]: Stem: 1333#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1334#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1344#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1350#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1351#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1342#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1379#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1378#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1377#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1374#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1373#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1371#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1368#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1366#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1365#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1363#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1362#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1361#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1360#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1357#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1359#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1358#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1354#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1346#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1347#L12 [2019-12-07 18:49:00,793 INFO L796 eck$LassoCheckResult]: Loop: 1347#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1347#L12 [2019-12-07 18:49:00,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:00,793 INFO L82 PathProgramCache]: Analyzing trace with hash 1546775295, now seen corresponding path program 11 times [2019-12-07 18:49:00,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:00,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367998843] [2019-12-07 18:49:00,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:00,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:00,893 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 11 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:00,893 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367998843] [2019-12-07 18:49:00,894 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1810413550] [2019-12-07 18:49:00,894 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:00,917 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2019-12-07 18:49:00,917 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:00,918 INFO L264 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 18:49:00,919 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:01,008 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 11 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:01,008 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:01,008 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 12] total 24 [2019-12-07 18:49:01,008 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181049645] [2019-12-07 18:49:01,009 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:01,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 7 times [2019-12-07 18:49:01,009 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15709525] [2019-12-07 18:49:01,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,011 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:01,020 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:01,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:49:01,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=367, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:49:01,020 INFO L87 Difference]: Start difference. First operand 48 states and 53 transitions. cyclomatic complexity: 8 Second operand 25 states. [2019-12-07 18:49:01,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:01,094 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2019-12-07 18:49:01,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:49:01,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 65 transitions. [2019-12-07 18:49:01,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 56 states and 61 transitions. [2019-12-07 18:49:01,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:01,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:01,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 61 transitions. [2019-12-07 18:49:01,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:01,096 INFO L688 BuchiCegarLoop]: Abstraction has 56 states and 61 transitions. [2019-12-07 18:49:01,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 61 transitions. [2019-12-07 18:49:01,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 54. [2019-12-07 18:49:01,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-12-07 18:49:01,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 59 transitions. [2019-12-07 18:49:01,098 INFO L711 BuchiCegarLoop]: Abstraction has 54 states and 59 transitions. [2019-12-07 18:49:01,098 INFO L591 BuchiCegarLoop]: Abstraction has 54 states and 59 transitions. [2019-12-07 18:49:01,098 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:49:01,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 59 transitions. [2019-12-07 18:49:01,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:01,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:01,100 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [14, 13, 11, 2, 1] [2019-12-07 18:49:01,100 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:01,100 INFO L794 eck$LassoCheckResult]: Stem: 1571#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1572#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1588#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1587#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1581#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1580#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1574#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1617#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1611#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1597#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1596#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1591#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1584#L12 [2019-12-07 18:49:01,100 INFO L796 eck$LassoCheckResult]: Loop: 1584#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1584#L12 [2019-12-07 18:49:01,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,100 INFO L82 PathProgramCache]: Analyzing trace with hash -1109184737, now seen corresponding path program 12 times [2019-12-07 18:49:01,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,100 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988867975] [2019-12-07 18:49:01,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:01,214 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 13 proven. 234 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:01,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988867975] [2019-12-07 18:49:01,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1827186208] [2019-12-07 18:49:01,214 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:01,237 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2019-12-07 18:49:01,237 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:01,238 INFO L264 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 18:49:01,239 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:01,362 INFO L134 CoverageAnalysis]: Checked inductivity of 247 backedges. 13 proven. 234 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:01,362 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:01,362 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14] total 28 [2019-12-07 18:49:01,362 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802667240] [2019-12-07 18:49:01,362 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:01,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,363 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 8 times [2019-12-07 18:49:01,363 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,363 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980106531] [2019-12-07 18:49:01,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,365 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:01,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:01,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 18:49:01,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=314, Invalid=498, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:49:01,375 INFO L87 Difference]: Start difference. First operand 54 states and 59 transitions. cyclomatic complexity: 8 Second operand 29 states. [2019-12-07 18:49:01,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:01,473 INFO L93 Difference]: Finished difference Result 66 states and 71 transitions. [2019-12-07 18:49:01,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:49:01,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 71 transitions. [2019-12-07 18:49:01,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 62 states and 67 transitions. [2019-12-07 18:49:01,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:01,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:01,475 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 67 transitions. [2019-12-07 18:49:01,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:01,475 INFO L688 BuchiCegarLoop]: Abstraction has 62 states and 67 transitions. [2019-12-07 18:49:01,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 67 transitions. [2019-12-07 18:49:01,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2019-12-07 18:49:01,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-12-07 18:49:01,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 65 transitions. [2019-12-07 18:49:01,477 INFO L711 BuchiCegarLoop]: Abstraction has 60 states and 65 transitions. [2019-12-07 18:49:01,477 INFO L591 BuchiCegarLoop]: Abstraction has 60 states and 65 transitions. [2019-12-07 18:49:01,477 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:49:01,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 65 transitions. [2019-12-07 18:49:01,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:01,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:01,479 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [16, 15, 13, 2, 1] [2019-12-07 18:49:01,479 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:01,479 INFO L794 eck$LassoCheckResult]: Stem: 1843#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 1844#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1860#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1859#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1854#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1853#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1852#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1845#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1846#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1884#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1880#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1878#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1877#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1875#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1874#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1872#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1871#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1867#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1869#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 1866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 1863#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 1857#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1856#L12 [2019-12-07 18:49:01,479 INFO L796 eck$LassoCheckResult]: Loop: 1856#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 1855#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 1856#L12 [2019-12-07 18:49:01,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,479 INFO L82 PathProgramCache]: Analyzing trace with hash 458808127, now seen corresponding path program 13 times [2019-12-07 18:49:01,479 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,480 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061432010] [2019-12-07 18:49:01,480 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:01,617 INFO L134 CoverageAnalysis]: Checked inductivity of 330 backedges. 15 proven. 315 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:01,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061432010] [2019-12-07 18:49:01,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [30079968] [2019-12-07 18:49:01,617 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:01,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:01,639 INFO L264 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 18:49:01,641 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:01,805 INFO L134 CoverageAnalysis]: Checked inductivity of 330 backedges. 15 proven. 315 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:01,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:01,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 16] total 32 [2019-12-07 18:49:01,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272876515] [2019-12-07 18:49:01,806 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:01,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 9 times [2019-12-07 18:49:01,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106386380] [2019-12-07 18:49:01,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:01,809 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:01,822 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:01,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 18:49:01,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=407, Invalid=649, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:49:01,823 INFO L87 Difference]: Start difference. First operand 60 states and 65 transitions. cyclomatic complexity: 8 Second operand 33 states. [2019-12-07 18:49:01,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:01,894 INFO L93 Difference]: Finished difference Result 72 states and 77 transitions. [2019-12-07 18:49:01,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:49:01,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 77 transitions. [2019-12-07 18:49:01,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 68 states and 73 transitions. [2019-12-07 18:49:01,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:01,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:01,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 73 transitions. [2019-12-07 18:49:01,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:01,895 INFO L688 BuchiCegarLoop]: Abstraction has 68 states and 73 transitions. [2019-12-07 18:49:01,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 73 transitions. [2019-12-07 18:49:01,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 66. [2019-12-07 18:49:01,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2019-12-07 18:49:01,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 71 transitions. [2019-12-07 18:49:01,898 INFO L711 BuchiCegarLoop]: Abstraction has 66 states and 71 transitions. [2019-12-07 18:49:01,898 INFO L591 BuchiCegarLoop]: Abstraction has 66 states and 71 transitions. [2019-12-07 18:49:01,898 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:49:01,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 71 transitions. [2019-12-07 18:49:01,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:01,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:01,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:01,899 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [18, 17, 15, 2, 1] [2019-12-07 18:49:01,899 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:01,899 INFO L794 eck$LassoCheckResult]: Stem: 2149#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 2150#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2160#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2166#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2167#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2151#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2152#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2213#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2212#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2211#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2210#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2209#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2208#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2206#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2205#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2204#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2203#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2202#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2201#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2200#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2199#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2198#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2197#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2196#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2195#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2194#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2193#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2192#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2191#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2190#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2189#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2188#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2187#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2186#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2184#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2183#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2181#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2179#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2178#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2177#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2176#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2173#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2175#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2170#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2162#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2163#L12 [2019-12-07 18:49:01,899 INFO L796 eck$LassoCheckResult]: Loop: 2163#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 2165#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2163#L12 [2019-12-07 18:49:01,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:01,899 INFO L82 PathProgramCache]: Analyzing trace with hash 430239583, now seen corresponding path program 14 times [2019-12-07 18:49:01,899 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:01,899 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004228933] [2019-12-07 18:49:01,899 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:01,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:02,061 INFO L134 CoverageAnalysis]: Checked inductivity of 425 backedges. 17 proven. 408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:02,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004228933] [2019-12-07 18:49:02,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1949430615] [2019-12-07 18:49:02,061 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:02,082 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:49:02,082 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:02,083 INFO L264 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 18:49:02,084 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:02,253 INFO L134 CoverageAnalysis]: Checked inductivity of 425 backedges. 17 proven. 408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:02,253 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:02,253 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18] total 36 [2019-12-07 18:49:02,253 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899514476] [2019-12-07 18:49:02,254 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:02,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,254 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 10 times [2019-12-07 18:49:02,254 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,254 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014689763] [2019-12-07 18:49:02,254 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,256 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:02,264 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:02,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 18:49:02,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=512, Invalid=820, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:49:02,265 INFO L87 Difference]: Start difference. First operand 66 states and 71 transitions. cyclomatic complexity: 8 Second operand 37 states. [2019-12-07 18:49:02,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:02,378 INFO L93 Difference]: Finished difference Result 78 states and 83 transitions. [2019-12-07 18:49:02,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:49:02,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 83 transitions. [2019-12-07 18:49:02,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:02,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 74 states and 79 transitions. [2019-12-07 18:49:02,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:02,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:02,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 79 transitions. [2019-12-07 18:49:02,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:02,380 INFO L688 BuchiCegarLoop]: Abstraction has 74 states and 79 transitions. [2019-12-07 18:49:02,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 79 transitions. [2019-12-07 18:49:02,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 72. [2019-12-07 18:49:02,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2019-12-07 18:49:02,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2019-12-07 18:49:02,383 INFO L711 BuchiCegarLoop]: Abstraction has 72 states and 77 transitions. [2019-12-07 18:49:02,383 INFO L591 BuchiCegarLoop]: Abstraction has 72 states and 77 transitions. [2019-12-07 18:49:02,383 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:49:02,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 77 transitions. [2019-12-07 18:49:02,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:02,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:02,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:02,384 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [20, 19, 17, 2, 1] [2019-12-07 18:49:02,384 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:02,384 INFO L794 eck$LassoCheckResult]: Stem: 2489#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 2490#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2506#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2507#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2499#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2498#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2559#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2558#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2557#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2554#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2553#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2552#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2551#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2550#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2548#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2547#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2546#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2545#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2544#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2541#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2540#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2539#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2538#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2536#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2535#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2534#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2533#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2532#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2530#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2529#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2528#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2526#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2524#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2523#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2522#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2520#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2518#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2517#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2516#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2513#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2515#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2514#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2510#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2502#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2503#L12 [2019-12-07 18:49:02,384 INFO L796 eck$LassoCheckResult]: Loop: 2503#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 2505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2503#L12 [2019-12-07 18:49:02,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,384 INFO L82 PathProgramCache]: Analyzing trace with hash -933663873, now seen corresponding path program 15 times [2019-12-07 18:49:02,385 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,385 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947939014] [2019-12-07 18:49:02,385 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:02,576 INFO L134 CoverageAnalysis]: Checked inductivity of 532 backedges. 19 proven. 513 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:02,576 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947939014] [2019-12-07 18:49:02,576 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1725506861] [2019-12-07 18:49:02,576 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:02,605 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2019-12-07 18:49:02,605 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:02,606 INFO L264 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 18:49:02,607 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:02,807 INFO L134 CoverageAnalysis]: Checked inductivity of 532 backedges. 19 proven. 513 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:02,807 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:02,807 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 20] total 40 [2019-12-07 18:49:02,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12294840] [2019-12-07 18:49:02,808 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:02,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,808 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 11 times [2019-12-07 18:49:02,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984574760] [2019-12-07 18:49:02,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,810 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:02,820 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:02,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 18:49:02,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=629, Invalid=1011, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 18:49:02,821 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. cyclomatic complexity: 8 Second operand 41 states. [2019-12-07 18:49:02,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:02,931 INFO L93 Difference]: Finished difference Result 84 states and 89 transitions. [2019-12-07 18:49:02,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:49:02,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 89 transitions. [2019-12-07 18:49:02,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:02,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 80 states and 85 transitions. [2019-12-07 18:49:02,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:02,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:02,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 85 transitions. [2019-12-07 18:49:02,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:02,933 INFO L688 BuchiCegarLoop]: Abstraction has 80 states and 85 transitions. [2019-12-07 18:49:02,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 85 transitions. [2019-12-07 18:49:02,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 78. [2019-12-07 18:49:02,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-12-07 18:49:02,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 83 transitions. [2019-12-07 18:49:02,935 INFO L711 BuchiCegarLoop]: Abstraction has 78 states and 83 transitions. [2019-12-07 18:49:02,935 INFO L591 BuchiCegarLoop]: Abstraction has 78 states and 83 transitions. [2019-12-07 18:49:02,935 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 18:49:02,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 83 transitions. [2019-12-07 18:49:02,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:02,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:02,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:02,936 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [22, 21, 19, 2, 1] [2019-12-07 18:49:02,936 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:02,936 INFO L794 eck$LassoCheckResult]: Stem: 2863#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 2864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2880#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2873#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2865#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2866#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2937#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2935#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2934#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2932#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2930#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2928#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2926#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2924#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2923#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2922#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2920#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2918#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2917#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2914#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2913#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2912#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2911#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2908#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2906#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2902#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2901#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2900#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2899#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2894#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2893#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2890#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 2886#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 2884#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 2876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2877#L12 [2019-12-07 18:49:02,936 INFO L796 eck$LassoCheckResult]: Loop: 2877#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 2879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 2877#L12 [2019-12-07 18:49:02,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,936 INFO L82 PathProgramCache]: Analyzing trace with hash -1048031329, now seen corresponding path program 16 times [2019-12-07 18:49:02,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,940 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569675580] [2019-12-07 18:49:02,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,956 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:02,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,957 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 12 times [2019-12-07 18:49:02,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580247637] [2019-12-07 18:49:02,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:02,959 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:02,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:02,959 INFO L82 PathProgramCache]: Analyzing trace with hash -2135759244, now seen corresponding path program 2 times [2019-12-07 18:49:02,959 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:02,959 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061449764] [2019-12-07 18:49:02,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:02,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:02,991 INFO L134 CoverageAnalysis]: Checked inductivity of 694 backedges. 22 proven. 102 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2019-12-07 18:49:02,991 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061449764] [2019-12-07 18:49:02,991 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1312958726] [2019-12-07 18:49:02,991 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:03,017 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:49:03,017 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:03,018 INFO L264 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:49:03,019 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:03,031 INFO L134 CoverageAnalysis]: Checked inductivity of 694 backedges. 22 proven. 102 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2019-12-07 18:49:03,031 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:03,031 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2019-12-07 18:49:03,031 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919194377] [2019-12-07 18:49:03,041 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:03,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:49:03,041 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:49:03,041 INFO L87 Difference]: Start difference. First operand 78 states and 83 transitions. cyclomatic complexity: 8 Second operand 6 states. [2019-12-07 18:49:03,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:03,065 INFO L93 Difference]: Finished difference Result 87 states and 93 transitions. [2019-12-07 18:49:03,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:49:03,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 93 transitions. [2019-12-07 18:49:03,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:03,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 86 states and 92 transitions. [2019-12-07 18:49:03,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:49:03,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:49:03,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 92 transitions. [2019-12-07 18:49:03,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:03,067 INFO L688 BuchiCegarLoop]: Abstraction has 86 states and 92 transitions. [2019-12-07 18:49:03,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 92 transitions. [2019-12-07 18:49:03,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 84. [2019-12-07 18:49:03,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2019-12-07 18:49:03,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2019-12-07 18:49:03,069 INFO L711 BuchiCegarLoop]: Abstraction has 84 states and 90 transitions. [2019-12-07 18:49:03,069 INFO L591 BuchiCegarLoop]: Abstraction has 84 states and 90 transitions. [2019-12-07 18:49:03,069 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 18:49:03,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 90 transitions. [2019-12-07 18:49:03,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:03,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:03,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:03,070 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [24, 23, 20, 3, 1] [2019-12-07 18:49:03,070 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:03,070 INFO L794 eck$LassoCheckResult]: Stem: 3239#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 3240#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3250#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3256#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3257#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3249#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3241#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3242#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3319#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3318#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3317#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3316#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3315#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3312#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3310#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3300#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3292#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3291#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3288#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3285#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3284#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3283#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3282#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3281#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3280#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3279#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3278#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3277#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3276#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3275#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3274#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3273#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3272#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3270#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3271#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3269#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3268#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3267#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3266#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3263#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3265#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 3262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 3260#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 3252#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3253#L12 [2019-12-07 18:49:03,071 INFO L796 eck$LassoCheckResult]: Loop: 3253#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 3255#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 3253#L12 [2019-12-07 18:49:03,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:03,071 INFO L82 PathProgramCache]: Analyzing trace with hash 2046902785, now seen corresponding path program 17 times [2019-12-07 18:49:03,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:03,071 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482589553] [2019-12-07 18:49:03,071 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:03,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:03,343 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 448 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:03,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482589553] [2019-12-07 18:49:03,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2091032183] [2019-12-07 18:49:03,344 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:03,376 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2019-12-07 18:49:03,376 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:03,377 INFO L264 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 18:49:03,378 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:03,769 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 622 proven. 159 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 18:49:03,770 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:03,770 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 25] total 51 [2019-12-07 18:49:03,770 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047979240] [2019-12-07 18:49:03,770 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:03,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:03,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 13 times [2019-12-07 18:49:03,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:03,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980813090] [2019-12-07 18:49:03,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:03,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:03,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:03,773 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:03,781 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:03,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2019-12-07 18:49:03,782 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=470, Invalid=2080, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 18:49:03,782 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. cyclomatic complexity: 10 Second operand 51 states. [2019-12-07 18:49:05,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:05,268 INFO L93 Difference]: Finished difference Result 481 states and 556 transitions. [2019-12-07 18:49:05,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2019-12-07 18:49:05,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 481 states and 556 transitions. [2019-12-07 18:49:05,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:05,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 481 states to 465 states and 540 transitions. [2019-12-07 18:49:05,273 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2019-12-07 18:49:05,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2019-12-07 18:49:05,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 465 states and 540 transitions. [2019-12-07 18:49:05,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:05,274 INFO L688 BuchiCegarLoop]: Abstraction has 465 states and 540 transitions. [2019-12-07 18:49:05,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 465 states and 540 transitions. [2019-12-07 18:49:05,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 465 to 255. [2019-12-07 18:49:05,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 255 states. [2019-12-07 18:49:05,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 255 states to 255 states and 309 transitions. [2019-12-07 18:49:05,278 INFO L711 BuchiCegarLoop]: Abstraction has 255 states and 309 transitions. [2019-12-07 18:49:05,278 INFO L591 BuchiCegarLoop]: Abstraction has 255 states and 309 transitions. [2019-12-07 18:49:05,278 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 18:49:05,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 255 states and 309 transitions. [2019-12-07 18:49:05,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:05,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:05,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:05,280 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [28, 27, 23, 4, 1] [2019-12-07 18:49:05,280 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:05,281 INFO L794 eck$LassoCheckResult]: Stem: 4283#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 4284#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4293#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4294#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4297#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4298#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4285#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4533#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4532#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4531#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4530#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4527#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4525#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4523#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4521#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4519#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4517#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4515#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4513#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4511#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4509#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4507#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4505#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4503#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4501#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4499#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4495#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4493#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4491#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4489#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4487#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4485#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4483#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4481#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4479#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4477#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4475#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4471#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4469#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4463#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4459#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4457#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4445#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4441#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4435#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4436#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4434#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4428#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4427#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4352#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4349#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4344#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4339#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4330#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4331#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4421#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4415#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4316#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4313#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4312#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4311#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4310#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 4307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4308#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 4305#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 4303#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4301#L12 [2019-12-07 18:49:05,281 INFO L796 eck$LassoCheckResult]: Loop: 4301#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 4302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 4301#L12 [2019-12-07 18:49:05,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:05,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1893636733, now seen corresponding path program 18 times [2019-12-07 18:49:05,281 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:05,281 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894394271] [2019-12-07 18:49:05,281 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:05,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:05,644 INFO L134 CoverageAnalysis]: Checked inductivity of 1080 backedges. 494 proven. 586 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:49:05,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894394271] [2019-12-07 18:49:05,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2050324119] [2019-12-07 18:49:05,645 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:05,676 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2019-12-07 18:49:05,677 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:05,677 INFO L264 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:49:05,678 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:05,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1080 backedges. 404 proven. 25 refuted. 0 times theorem prover too weak. 651 trivial. 0 not checked. [2019-12-07 18:49:05,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:05,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 8] total 41 [2019-12-07 18:49:05,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709085927] [2019-12-07 18:49:05,780 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:05,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:05,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 14 times [2019-12-07 18:49:05,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:05,780 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882047139] [2019-12-07 18:49:05,780 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:05,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:05,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:05,782 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:05,790 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:05,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 18:49:05,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1329, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 18:49:05,791 INFO L87 Difference]: Start difference. First operand 255 states and 309 transitions. cyclomatic complexity: 57 Second operand 41 states. [2019-12-07 18:49:08,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:08,431 INFO L93 Difference]: Finished difference Result 1233 states and 1490 transitions. [2019-12-07 18:49:08,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-12-07 18:49:08,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1233 states and 1490 transitions. [2019-12-07 18:49:08,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:08,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1233 states to 1201 states and 1457 transitions. [2019-12-07 18:49:08,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2019-12-07 18:49:08,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2019-12-07 18:49:08,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1201 states and 1457 transitions. [2019-12-07 18:49:08,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:08,442 INFO L688 BuchiCegarLoop]: Abstraction has 1201 states and 1457 transitions. [2019-12-07 18:49:08,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1201 states and 1457 transitions. [2019-12-07 18:49:08,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1201 to 621. [2019-12-07 18:49:08,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 621 states. [2019-12-07 18:49:08,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 621 states to 621 states and 764 transitions. [2019-12-07 18:49:08,453 INFO L711 BuchiCegarLoop]: Abstraction has 621 states and 764 transitions. [2019-12-07 18:49:08,453 INFO L591 BuchiCegarLoop]: Abstraction has 621 states and 764 transitions. [2019-12-07 18:49:08,453 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 18:49:08,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 621 states and 764 transitions. [2019-12-07 18:49:08,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:08,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:08,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:08,456 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [32, 31, 26, 5, 1] [2019-12-07 18:49:08,456 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:08,456 INFO L794 eck$LassoCheckResult]: Stem: 6232#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 6233#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6247#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6242#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6243#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6245#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6246#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6234#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6739#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6734#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6730#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6728#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6723#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6722#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6720#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6625#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6721#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6729#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6717#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6609#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6610#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6715#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6605#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6725#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6718#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6716#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6584#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6733#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6580#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6738#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6575#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6737#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6732#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6529#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6528#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6527#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6526#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6344#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6343#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6341#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6340#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6339#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6338#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6337#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6335#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6333#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6570#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6569#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6272#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6270#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6269#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6268#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6267#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6266#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6256#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6265#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6263#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6262#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6261#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6260#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6259#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6257#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 6255#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6254#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 6253#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 6251#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6249#L12 [2019-12-07 18:49:08,456 INFO L796 eck$LassoCheckResult]: Loop: 6249#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 6250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 6249#L12 [2019-12-07 18:49:08,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:08,456 INFO L82 PathProgramCache]: Analyzing trace with hash 715015873, now seen corresponding path program 19 times [2019-12-07 18:49:08,456 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:08,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712200876] [2019-12-07 18:49:08,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:08,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:08,826 INFO L134 CoverageAnalysis]: Checked inductivity of 1426 backedges. 504 proven. 892 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2019-12-07 18:49:08,826 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [712200876] [2019-12-07 18:49:08,826 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1462828883] [2019-12-07 18:49:08,826 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:08,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:08,853 INFO L264 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:49:08,854 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:08,946 INFO L134 CoverageAnalysis]: Checked inductivity of 1426 backedges. 416 proven. 405 refuted. 0 times theorem prover too weak. 605 trivial. 0 not checked. [2019-12-07 18:49:08,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:08,947 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 8] total 39 [2019-12-07 18:49:08,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248039678] [2019-12-07 18:49:08,947 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:08,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:08,947 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 15 times [2019-12-07 18:49:08,947 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:08,947 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262849812] [2019-12-07 18:49:08,947 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:08,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:08,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:08,949 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:08,962 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:08,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 18:49:08,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=332, Invalid=1228, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 18:49:08,963 INFO L87 Difference]: Start difference. First operand 621 states and 764 transitions. cyclomatic complexity: 148 Second operand 40 states. [2019-12-07 18:49:10,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:10,539 INFO L93 Difference]: Finished difference Result 1124 states and 1332 transitions. [2019-12-07 18:49:10,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2019-12-07 18:49:10,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1124 states and 1332 transitions. [2019-12-07 18:49:10,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:10,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1124 states to 1080 states and 1284 transitions. [2019-12-07 18:49:10,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2019-12-07 18:49:10,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2019-12-07 18:49:10,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1080 states and 1284 transitions. [2019-12-07 18:49:10,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:10,548 INFO L688 BuchiCegarLoop]: Abstraction has 1080 states and 1284 transitions. [2019-12-07 18:49:10,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1080 states and 1284 transitions. [2019-12-07 18:49:10,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1080 to 723. [2019-12-07 18:49:10,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 723 states. [2019-12-07 18:49:10,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 723 states to 723 states and 884 transitions. [2019-12-07 18:49:10,559 INFO L711 BuchiCegarLoop]: Abstraction has 723 states and 884 transitions. [2019-12-07 18:49:10,559 INFO L591 BuchiCegarLoop]: Abstraction has 723 states and 884 transitions. [2019-12-07 18:49:10,559 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 18:49:10,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 723 states and 884 transitions. [2019-12-07 18:49:10,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:10,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:10,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:10,561 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [38, 37, 31, 6, 1] [2019-12-07 18:49:10,561 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:10,562 INFO L794 eck$LassoCheckResult]: Stem: 8450#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 8451#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8466#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8460#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 8461#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8465#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8452#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8453#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8802#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8800#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8799#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8797#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8796#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8795#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8794#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8793#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8791#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8789#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8788#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8787#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8785#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8784#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8783#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8782#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8781#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8780#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8779#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8778#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8777#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8776#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8774#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8773#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8772#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8771#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8770#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8768#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8767#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8766#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8765#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8764#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8762#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8761#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8760#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8759#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8758#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8756#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8755#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8754#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8752#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9117#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9116#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9115#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9114#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9113#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9112#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9111#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9110#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9109#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9108#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9107#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9106#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9105#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9104#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9103#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9102#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9099#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9048#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 9047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 9043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 9042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 9041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8483#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8587#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8498#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8489#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 8488#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8487#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8486#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8485#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8475#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8481#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8480#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 8479#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8478#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8476#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 8474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 8472#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 8470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8468#L12 [2019-12-07 18:49:10,562 INFO L796 eck$LassoCheckResult]: Loop: 8468#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 8469#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 8468#L12 [2019-12-07 18:49:10,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:10,562 INFO L82 PathProgramCache]: Analyzing trace with hash 513598879, now seen corresponding path program 20 times [2019-12-07 18:49:10,562 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:10,562 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851841991] [2019-12-07 18:49:10,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:10,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:11,055 INFO L134 CoverageAnalysis]: Checked inductivity of 2035 backedges. 977 proven. 1023 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2019-12-07 18:49:11,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851841991] [2019-12-07 18:49:11,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1475564153] [2019-12-07 18:49:11,055 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:11,086 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:49:11,086 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:11,087 INFO L264 TraceCheckSpWp]: Trace formula consists of 248 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 18:49:11,088 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:11,237 INFO L134 CoverageAnalysis]: Checked inductivity of 2035 backedges. 784 proven. 564 refuted. 0 times theorem prover too weak. 687 trivial. 0 not checked. [2019-12-07 18:49:11,237 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:11,237 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 10] total 46 [2019-12-07 18:49:11,237 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133875905] [2019-12-07 18:49:11,237 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:11,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:11,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 16 times [2019-12-07 18:49:11,238 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:11,238 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624109737] [2019-12-07 18:49:11,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:11,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:11,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:11,240 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:11,249 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:11,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2019-12-07 18:49:11,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=1781, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 18:49:11,249 INFO L87 Difference]: Start difference. First operand 723 states and 884 transitions. cyclomatic complexity: 168 Second operand 47 states. [2019-12-07 18:49:13,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:13,533 INFO L93 Difference]: Finished difference Result 894 states and 1056 transitions. [2019-12-07 18:49:13,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2019-12-07 18:49:13,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 894 states and 1056 transitions. [2019-12-07 18:49:13,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:13,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 894 states to 860 states and 1015 transitions. [2019-12-07 18:49:13,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2019-12-07 18:49:13,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2019-12-07 18:49:13,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 860 states and 1015 transitions. [2019-12-07 18:49:13,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:13,543 INFO L688 BuchiCegarLoop]: Abstraction has 860 states and 1015 transitions. [2019-12-07 18:49:13,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 860 states and 1015 transitions. [2019-12-07 18:49:13,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 860 to 657. [2019-12-07 18:49:13,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 657 states. [2019-12-07 18:49:13,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 657 states and 787 transitions. [2019-12-07 18:49:13,554 INFO L711 BuchiCegarLoop]: Abstraction has 657 states and 787 transitions. [2019-12-07 18:49:13,554 INFO L591 BuchiCegarLoop]: Abstraction has 657 states and 787 transitions. [2019-12-07 18:49:13,554 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 18:49:13,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 657 states and 787 transitions. [2019-12-07 18:49:13,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:13,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:13,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:13,558 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [44, 43, 37, 6, 1] [2019-12-07 18:49:13,558 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:13,559 INFO L794 eck$LassoCheckResult]: Stem: 10581#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 10582#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10591#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10595#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10934#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10933#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10932#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10931#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10930#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10928#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10925#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10921#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10920#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10919#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10914#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10913#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10910#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10909#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10908#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10907#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10818#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10882#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10881#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10879#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10878#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10876#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10873#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10872#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10871#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10870#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10869#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10867#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10864#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10863#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10861#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10860#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10859#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10858#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10857#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10855#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10854#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10853#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10852#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10851#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10849#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10848#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10940#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10939#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10884#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10825#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10822#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10819#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10801#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10798#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10795#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10792#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10790#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10628#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10620#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10617#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10615#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10611#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10607#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 10605#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 10603#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 10601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10599#L12 [2019-12-07 18:49:13,559 INFO L796 eck$LassoCheckResult]: Loop: 10599#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 10600#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 10599#L12 [2019-12-07 18:49:13,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:13,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1091788543, now seen corresponding path program 21 times [2019-12-07 18:49:13,559 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:13,560 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985883950] [2019-12-07 18:49:13,560 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:13,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:14,343 INFO L134 CoverageAnalysis]: Checked inductivity of 2752 backedges. 688 proven. 2062 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-12-07 18:49:14,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985883950] [2019-12-07 18:49:14,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [325231397] [2019-12-07 18:49:14,344 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:14,371 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2019-12-07 18:49:14,371 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:14,371 INFO L264 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 18:49:14,372 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:14,559 INFO L134 CoverageAnalysis]: Checked inductivity of 2752 backedges. 1035 proven. 91 refuted. 0 times theorem prover too weak. 1626 trivial. 0 not checked. [2019-12-07 18:49:14,559 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:14,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 10] total 62 [2019-12-07 18:49:14,560 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630851644] [2019-12-07 18:49:14,560 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:14,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:14,560 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 17 times [2019-12-07 18:49:14,560 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:14,560 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681433645] [2019-12-07 18:49:14,560 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:14,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:14,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:14,562 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:14,570 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:14,570 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2019-12-07 18:49:14,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=501, Invalid=3281, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 18:49:14,571 INFO L87 Difference]: Start difference. First operand 657 states and 787 transitions. cyclomatic complexity: 137 Second operand 62 states. [2019-12-07 18:49:22,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:22,569 INFO L93 Difference]: Finished difference Result 2238 states and 2639 transitions. [2019-12-07 18:49:22,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 181 states. [2019-12-07 18:49:22,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2238 states and 2639 transitions. [2019-12-07 18:49:22,576 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:22,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2238 states to 2216 states and 2617 transitions. [2019-12-07 18:49:22,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2019-12-07 18:49:22,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2019-12-07 18:49:22,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2216 states and 2617 transitions. [2019-12-07 18:49:22,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:22,586 INFO L688 BuchiCegarLoop]: Abstraction has 2216 states and 2617 transitions. [2019-12-07 18:49:22,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2216 states and 2617 transitions. [2019-12-07 18:49:22,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2216 to 897. [2019-12-07 18:49:22,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 897 states. [2019-12-07 18:49:22,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 897 states to 897 states and 1073 transitions. [2019-12-07 18:49:22,604 INFO L711 BuchiCegarLoop]: Abstraction has 897 states and 1073 transitions. [2019-12-07 18:49:22,604 INFO L591 BuchiCegarLoop]: Abstraction has 897 states and 1073 transitions. [2019-12-07 18:49:22,604 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 18:49:22,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 897 states and 1073 transitions. [2019-12-07 18:49:22,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:22,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:22,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:22,608 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [52, 51, 44, 7, 1] [2019-12-07 18:49:22,608 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:22,608 INFO L794 eck$LassoCheckResult]: Stem: 14272#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 14273#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14287#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14282#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14286#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14274#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14275#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14643#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14642#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14640#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14613#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14612#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14611#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14610#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14609#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14607#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14603#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14604#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14765#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14599#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14598#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14594#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14593#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14592#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14591#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14589#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14584#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14585#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14581#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14579#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14578#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14577#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14573#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14572#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14571#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14570#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14568#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14567#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14566#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14565#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14564#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14562#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14561#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14560#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14558#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14556#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14553#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14547#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14545#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14541#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14542#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14999#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14997#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14996#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14995#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14993#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14380#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14379#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14377#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14378#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14370#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14369#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14367#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14365#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14364#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14363#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14362#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14358#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14356#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14357#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14352#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14323#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14322#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14321#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14320#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14319#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14318#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14317#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14316#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14315#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14314#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14312#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14311#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14310#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14309#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14308#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14307#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14306#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14296#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14305#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14303#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14302#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14301#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14300#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 14295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14294#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 14293#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 14291#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14289#L12 [2019-12-07 18:49:22,608 INFO L796 eck$LassoCheckResult]: Loop: 14289#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 14290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 14289#L12 [2019-12-07 18:49:22,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:22,608 INFO L82 PathProgramCache]: Analyzing trace with hash -1559636355, now seen corresponding path program 22 times [2019-12-07 18:49:22,608 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:22,608 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598842401] [2019-12-07 18:49:22,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:22,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:23,142 INFO L134 CoverageAnalysis]: Checked inductivity of 3876 backedges. 395 proven. 3181 refuted. 0 times theorem prover too weak. 300 trivial. 0 not checked. [2019-12-07 18:49:23,142 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598842401] [2019-12-07 18:49:23,143 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1918979041] [2019-12-07 18:49:23,143 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:23,184 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:49:23,184 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:23,185 INFO L264 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 18:49:23,187 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:23,869 INFO L134 CoverageAnalysis]: Checked inductivity of 3876 backedges. 2426 proven. 916 refuted. 0 times theorem prover too weak. 534 trivial. 0 not checked. [2019-12-07 18:49:23,869 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:23,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 33] total 74 [2019-12-07 18:49:23,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016468226] [2019-12-07 18:49:23,870 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:23,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:23,871 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 18 times [2019-12-07 18:49:23,871 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:23,871 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378745430] [2019-12-07 18:49:23,871 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:23,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:23,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:23,873 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:23,882 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:23,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-12-07 18:49:23,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=717, Invalid=4685, Unknown=0, NotChecked=0, Total=5402 [2019-12-07 18:49:23,883 INFO L87 Difference]: Start difference. First operand 897 states and 1073 transitions. cyclomatic complexity: 182 Second operand 74 states. [2019-12-07 18:49:30,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:30,962 INFO L93 Difference]: Finished difference Result 3762 states and 4349 transitions. [2019-12-07 18:49:30,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 167 states. [2019-12-07 18:49:30,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3762 states and 4349 transitions. [2019-12-07 18:49:30,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:30,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3762 states to 3528 states and 4047 transitions. [2019-12-07 18:49:30,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2019-12-07 18:49:30,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2019-12-07 18:49:30,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3528 states and 4047 transitions. [2019-12-07 18:49:30,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:30,990 INFO L688 BuchiCegarLoop]: Abstraction has 3528 states and 4047 transitions. [2019-12-07 18:49:30,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3528 states and 4047 transitions. [2019-12-07 18:49:31,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3528 to 2061. [2019-12-07 18:49:31,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2061 states. [2019-12-07 18:49:31,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2061 states to 2061 states and 2452 transitions. [2019-12-07 18:49:31,015 INFO L711 BuchiCegarLoop]: Abstraction has 2061 states and 2452 transitions. [2019-12-07 18:49:31,015 INFO L591 BuchiCegarLoop]: Abstraction has 2061 states and 2452 transitions. [2019-12-07 18:49:31,015 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-12-07 18:49:31,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2061 states and 2452 transitions. [2019-12-07 18:49:31,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:31,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:31,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:31,021 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [85, 84, 74, 10, 1] [2019-12-07 18:49:31,021 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:31,022 INFO L794 eck$LassoCheckResult]: Stem: 19876#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 19877#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19894#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19887#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19891#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19878#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19879#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21502#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21501#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21500#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21499#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21498#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21497#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21495#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21494#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21493#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21492#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21491#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21490#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21489#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21487#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21486#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21485#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21483#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21482#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21481#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21480#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21479#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21478#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21477#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21476#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21475#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21455#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21456#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21935#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21452#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21450#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21449#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21447#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21445#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21444#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21443#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21442#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21441#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21440#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21439#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21438#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21437#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21436#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21435#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21434#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21433#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21432#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21431#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21430#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21429#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21428#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21427#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21426#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21425#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21424#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21423#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21422#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21420#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21419#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21418#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21417#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21416#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21415#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21414#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21413#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21412#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21411#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21409#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21406#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21397#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21398#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21410#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21331#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21329#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21328#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21327#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21326#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21325#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21324#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21323#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21322#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21319#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21318#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21317#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21316#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21315#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21312#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21310#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21300#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21293#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21292#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21291#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21290#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21289#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21288#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21287#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21285#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21284#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21281#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20290#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 20291#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20286#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20282#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20283#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20278#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20279#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20274#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20243#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20244#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20248#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20235#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20230#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20232#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20226#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20227#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20222#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20223#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20217#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20219#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20213#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20214#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20209#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20210#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20205#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20185#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21748#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 21747#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21746#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21745#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21741#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21740#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21739#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21738#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21737#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21736#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21734#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 21735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 21730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 21731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20062#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19967#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19968#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20052#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20048#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 20043#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 20041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 20040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19931#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19928#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19927#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19926#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19925#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19922#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19921#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19910#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19920#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19916#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19914#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19913#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19903#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19909#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19908#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19907#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 19901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 19899#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 19897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19895#L12 [2019-12-07 18:49:31,022 INFO L796 eck$LassoCheckResult]: Loop: 19895#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 19896#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 19895#L12 [2019-12-07 18:49:31,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:31,022 INFO L82 PathProgramCache]: Analyzing trace with hash 364188958, now seen corresponding path program 23 times [2019-12-07 18:49:31,022 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:31,022 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905469044] [2019-12-07 18:49:31,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:31,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:33,390 INFO L134 CoverageAnalysis]: Checked inductivity of 10542 backedges. 1566 proven. 8974 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-12-07 18:49:33,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905469044] [2019-12-07 18:49:33,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [458820528] [2019-12-07 18:49:33,391 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:33,439 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2019-12-07 18:49:33,439 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:33,440 INFO L264 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 18:49:33,442 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:34,702 INFO L134 CoverageAnalysis]: Checked inductivity of 10542 backedges. 7316 proven. 1076 refuted. 0 times theorem prover too weak. 2150 trivial. 0 not checked. [2019-12-07 18:49:34,702 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:34,703 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [102, 35] total 136 [2019-12-07 18:49:34,703 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207744679] [2019-12-07 18:49:34,703 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:34,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:34,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1622, now seen corresponding path program 19 times [2019-12-07 18:49:34,703 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:34,703 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899738818] [2019-12-07 18:49:34,703 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:34,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:34,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:34,705 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:34,717 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:34,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 136 interpolants. [2019-12-07 18:49:34,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1647, Invalid=16713, Unknown=0, NotChecked=0, Total=18360 [2019-12-07 18:49:34,721 INFO L87 Difference]: Start difference. First operand 2061 states and 2452 transitions. cyclomatic complexity: 396 Second operand 136 states. [2019-12-07 18:49:49,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:49:49,376 INFO L93 Difference]: Finished difference Result 2151 states and 2308 transitions. [2019-12-07 18:49:49,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2019-12-07 18:49:49,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2151 states and 2308 transitions. [2019-12-07 18:49:49,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:49,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2151 states to 1660 states and 1748 transitions. [2019-12-07 18:49:49,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2019-12-07 18:49:49,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2019-12-07 18:49:49,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1660 states and 1748 transitions. [2019-12-07 18:49:49,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:49:49,400 INFO L688 BuchiCegarLoop]: Abstraction has 1660 states and 1748 transitions. [2019-12-07 18:49:49,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1660 states and 1748 transitions. [2019-12-07 18:49:49,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1660 to 732. [2019-12-07 18:49:49,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 732 states. [2019-12-07 18:49:49,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 732 states to 732 states and 771 transitions. [2019-12-07 18:49:49,414 INFO L711 BuchiCegarLoop]: Abstraction has 732 states and 771 transitions. [2019-12-07 18:49:49,414 INFO L591 BuchiCegarLoop]: Abstraction has 732 states and 771 transitions. [2019-12-07 18:49:49,414 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-12-07 18:49:49,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 732 states and 771 transitions. [2019-12-07 18:49:49,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:49:49,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:49:49,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:49:49,424 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [133, 133, 121, 12, 1] [2019-12-07 18:49:49,424 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:49:49,424 INFO L794 eck$LassoCheckResult]: Stem: 25375#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 25376#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25417#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25416#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26102#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26101#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26100#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26099#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26098#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26097#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26096#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26094#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26093#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26092#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26091#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26090#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26089#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26088#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26087#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26086#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26085#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26084#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26083#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26082#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26081#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26079#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26078#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26077#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26076#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26074#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26073#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26072#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26070#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26069#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26068#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26067#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26066#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26065#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26064#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26063#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26062#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26060#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26059#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26058#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26057#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26056#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26054#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26053#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25995#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26050#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26048#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 26047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26046#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26045#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26044#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26042#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26041#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26040#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26039#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26038#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26036#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26035#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26034#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26033#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26032#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26030#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26029#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26028#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26024#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26023#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26022#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26021#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26020#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26018#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26017#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26016#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26015#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26014#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26011#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26010#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26009#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26006#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 26002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 26001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25998#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 26051#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25993#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25992#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25991#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25990#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25989#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25988#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25987#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25986#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25985#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25984#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25983#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25982#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25981#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25980#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25979#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25978#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25977#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25976#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25975#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25974#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25973#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25972#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25971#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25970#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25969#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25968#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25966#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25965#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25964#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25963#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25961#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25960#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25959#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25958#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25957#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25956#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25955#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25954#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25953#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25952#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25949#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25948#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25947#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25946#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25945#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25944#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25940#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25938#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25939#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25921#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25914#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25912#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25906#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25905#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25904#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25903#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25902#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25900#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25899#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25898#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25897#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25896#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25895#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25894#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25893#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25892#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25891#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25890#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25889#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25888#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25887#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25886#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25885#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25883#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25882#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25881#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25880#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25879#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25877#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25876#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25875#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25874#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25873#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25871#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25869#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25866#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25865#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25863#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25746#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25745#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25744#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25743#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25741#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25740#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25739#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25738#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25737#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25736#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25735#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25734#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25733#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25732#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25730#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25729#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25728#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25727#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25726#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25725#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25724#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25723#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25722#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25721#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25720#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25719#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25718#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25717#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25716#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25715#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25714#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25713#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25712#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25711#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25710#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25709#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25708#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25707#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25706#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25705#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25704#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25703#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25702#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25701#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25700#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25699#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25698#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25697#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25696#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25695#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25694#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25693#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25692#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25691#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25690#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25689#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25688#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25687#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25686#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25685#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25684#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25683#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25682#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25681#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25680#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25679#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25678#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25677#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25676#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25675#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25674#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25673#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25672#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25671#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25670#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25669#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25668#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25667#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25666#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25665#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25664#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25663#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25662#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25661#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25660#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25659#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25658#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25657#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25651#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25650#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25649#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25648#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25647#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25645#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25642#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25641#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25639#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25638#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25637#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25636#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25635#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25633#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25632#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25631#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25630#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25629#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25627#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25626#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25625#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25624#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25623#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25621#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25620#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25619#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25618#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25617#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25616#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25422#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25478#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25472#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25468#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25466#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25462#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25460#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25456#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25454#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25450#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25426#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25406#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25423#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25424#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25420#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25415#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25410#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25408#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25397#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25407#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25405#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25404#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25403#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25402#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25401#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25399#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25398#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25395#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25394#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 25387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 25386#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 25418#L12-1 [2019-12-07 18:49:49,425 INFO L796 eck$LassoCheckResult]: Loop: 25418#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 25419#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 25418#L12-1 [2019-12-07 18:49:49,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:49,425 INFO L82 PathProgramCache]: Analyzing trace with hash -901810105, now seen corresponding path program 24 times [2019-12-07 18:49:49,425 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:49,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256334005] [2019-12-07 18:49:49,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:49,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:49:54,608 INFO L134 CoverageAnalysis]: Checked inductivity of 26334 backedges. 2849 proven. 23439 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2019-12-07 18:49:54,608 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256334005] [2019-12-07 18:49:54,608 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1124017997] [2019-12-07 18:49:54,608 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:49:54,696 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2019-12-07 18:49:54,697 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:49:54,698 INFO L264 TraceCheckSpWp]: Trace formula consists of 396 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 18:49:54,700 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:49:55,136 INFO L134 CoverageAnalysis]: Checked inductivity of 26334 backedges. 7021 proven. 496 refuted. 0 times theorem prover too weak. 18817 trivial. 0 not checked. [2019-12-07 18:49:55,136 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:49:55,136 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [137, 13] total 146 [2019-12-07 18:49:55,136 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432932710] [2019-12-07 18:49:55,137 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:49:55,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:49:55,137 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 20 times [2019-12-07 18:49:55,137 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:49:55,137 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240530213] [2019-12-07 18:49:55,137 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:49:55,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:55,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:49:55,139 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:49:55,154 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:49:55,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 146 interpolants. [2019-12-07 18:49:55,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=19367, Unknown=0, NotChecked=0, Total=21170 [2019-12-07 18:49:55,160 INFO L87 Difference]: Start difference. First operand 732 states and 771 transitions. cyclomatic complexity: 43 Second operand 146 states. [2019-12-07 18:50:35,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:35,922 INFO L93 Difference]: Finished difference Result 2470 states and 2615 transitions. [2019-12-07 18:50:35,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 487 states. [2019-12-07 18:50:35,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2470 states and 2615 transitions. [2019-12-07 18:50:35,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:35,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2470 states to 2212 states and 2351 transitions. [2019-12-07 18:50:35,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2019-12-07 18:50:35,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2019-12-07 18:50:35,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2212 states and 2351 transitions. [2019-12-07 18:50:35,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:50:35,937 INFO L688 BuchiCegarLoop]: Abstraction has 2212 states and 2351 transitions. [2019-12-07 18:50:35,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2212 states and 2351 transitions. [2019-12-07 18:50:35,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2212 to 1042. [2019-12-07 18:50:35,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1042 states. [2019-12-07 18:50:35,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1042 states to 1042 states and 1115 transitions. [2019-12-07 18:50:35,955 INFO L711 BuchiCegarLoop]: Abstraction has 1042 states and 1115 transitions. [2019-12-07 18:50:35,955 INFO L591 BuchiCegarLoop]: Abstraction has 1042 states and 1115 transitions. [2019-12-07 18:50:35,955 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-12-07 18:50:35,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1042 states and 1115 transitions. [2019-12-07 18:50:35,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:35,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:35,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:35,983 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [191, 191, 173, 18, 1] [2019-12-07 18:50:35,983 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:50:35,984 INFO L794 eck$LassoCheckResult]: Stem: 30882#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 30883#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30901#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30898#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30891#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30884#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30885#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31919#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31918#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31916#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31914#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31913#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31910#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31909#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31908#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31907#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31906#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31904#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31902#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31901#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31898#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31897#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31896#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31895#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31892#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31890#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31889#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31887#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31886#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31885#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31884#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31883#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31881#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31880#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31878#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31877#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31875#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31874#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31872#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31871#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31812#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31869#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31868#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31867#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31866#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31865#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31864#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31863#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31862#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31861#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31859#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31858#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31857#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31856#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31855#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31854#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31853#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31852#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31851#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31850#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31849#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31848#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31847#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31846#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31845#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31844#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31843#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31842#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31841#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31840#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31839#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31838#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31837#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31836#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31835#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31834#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31833#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31832#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31831#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31830#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31829#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31828#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31827#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31826#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31825#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31824#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31823#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31822#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31821#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31820#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31819#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31818#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31817#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31816#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31815#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31814#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31758#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31813#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31811#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31810#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31809#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31808#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31807#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31806#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31805#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31804#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31803#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31802#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31801#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31800#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31799#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31798#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31797#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31796#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31795#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31794#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31792#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31791#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31790#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31789#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31788#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31787#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31786#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31785#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31784#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31782#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31781#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31780#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31779#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31778#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31776#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31775#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31774#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31773#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31772#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31770#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31769#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31768#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31767#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31766#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31764#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31763#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31762#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31761#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31760#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31707#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31759#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31757#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31756#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31755#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31754#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31752#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31751#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31750#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31749#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31748#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31746#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31745#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31744#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31743#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31742#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31740#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31739#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31738#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31737#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31736#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31734#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31733#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31732#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31731#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31730#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31729#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31728#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31726#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31725#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31724#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31722#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31721#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31720#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31719#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31717#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31716#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31715#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31714#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31713#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31712#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31711#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31710#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31709#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31658#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31708#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31704#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31702#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31701#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31700#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31698#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31697#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31696#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31695#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31692#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31690#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31689#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31688#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31686#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31685#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31684#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31683#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31681#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31680#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31679#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31678#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31677#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31675#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31674#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31673#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31672#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31671#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31669#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31668#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31667#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31665#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31663#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31662#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31661#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31657#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31656#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31655#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31654#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31653#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31652#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31651#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31650#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31649#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31648#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31647#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31646#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31645#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31644#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31643#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31642#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31640#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31639#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31637#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31636#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31635#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31634#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31633#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31631#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31630#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31628#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31615#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31405#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31614#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31613#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31612#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31611#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31609#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31608#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31607#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31606#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31605#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31603#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31602#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31601#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31600#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31599#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31597#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31596#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31595#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31594#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31593#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31591#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31590#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31589#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31588#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31587#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31586#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31585#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31584#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31583#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31582#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31581#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31580#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31579#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31578#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31577#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31576#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31574#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31564#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31400#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31399#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31398#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31397#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31396#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31395#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31394#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31393#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31392#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31391#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31390#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31389#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31388#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31387#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31386#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31385#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31384#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31383#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31382#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31381#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31380#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31379#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31378#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31377#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31375#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31374#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31373#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31372#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31371#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31369#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31368#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31367#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31365#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31440#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31439#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31438#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31437#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31435#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31434#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31433#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31431#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31430#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31428#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31427#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31426#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31425#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31424#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31422#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31421#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31420#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31419#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31418#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31416#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31415#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31414#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31413#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31412#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31411#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31410#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31409#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31407#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31561#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31559#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31555#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31475#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31474#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31473#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31471#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31470#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31469#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31468#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31467#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31465#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31464#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31463#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31462#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31461#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31459#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31458#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31457#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31456#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31453#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31452#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31451#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31450#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31449#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31226#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31225#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31224#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31223#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31222#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31221#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31220#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31219#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31218#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31217#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31216#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31215#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31214#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31213#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31212#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31211#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31210#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31209#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31208#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31207#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31206#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31205#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31204#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31202#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31203#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31317#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31315#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31309#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31253#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31252#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31251#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31250#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31249#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31248#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31247#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31246#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31245#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31244#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31243#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31242#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31241#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31240#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31239#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31238#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31237#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31236#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31235#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31232#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31065#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31061#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31060#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31059#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31058#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31056#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31055#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31054#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31053#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31052#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31050#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31049#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31047#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31048#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31100#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31099#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31098#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31097#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31095#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31092#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31081#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31075#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31072#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31067#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30972#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30973#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 31090#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31089#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31088#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31087#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31086#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31082#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31080#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 31077#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 31074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 31071#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30951#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30946#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30945#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30941#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30938#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30936#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30910#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30909#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30906#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30905#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30899#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 30900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30893#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 30894#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 30907#L12-1 [2019-12-07 18:50:35,984 INFO L796 eck$LassoCheckResult]: Loop: 30907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 30908#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 30907#L12-1 [2019-12-07 18:50:35,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:35,984 INFO L82 PathProgramCache]: Analyzing trace with hash -694193177, now seen corresponding path program 25 times [2019-12-07 18:50:35,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:35,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272279036] [2019-12-07 18:50:35,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:36,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:37,437 INFO L134 CoverageAnalysis]: Checked inductivity of 54435 backedges. 470 proven. 50621 refuted. 0 times theorem prover too weak. 3344 trivial. 0 not checked. [2019-12-07 18:50:37,437 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272279036] [2019-12-07 18:50:37,438 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1956639891] [2019-12-07 18:50:37,438 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:50:37,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:37,541 INFO L264 TraceCheckSpWp]: Trace formula consists of 1206 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 18:50:37,545 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:50:37,951 INFO L134 CoverageAnalysis]: Checked inductivity of 54435 backedges. 16740 proven. 32475 refuted. 0 times theorem prover too weak. 5220 trivial. 0 not checked. [2019-12-07 18:50:37,952 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:50:37,952 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 21] total 76 [2019-12-07 18:50:37,952 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247979290] [2019-12-07 18:50:37,953 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:37,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:37,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 21 times [2019-12-07 18:50:37,953 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:37,953 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825746906] [2019-12-07 18:50:37,953 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:37,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:37,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:37,955 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:37,965 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:37,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2019-12-07 18:50:37,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1153, Invalid=4699, Unknown=0, NotChecked=0, Total=5852 [2019-12-07 18:50:37,966 INFO L87 Difference]: Start difference. First operand 1042 states and 1115 transitions. cyclomatic complexity: 77 Second operand 77 states. [2019-12-07 18:50:47,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:47,146 INFO L93 Difference]: Finished difference Result 4409 states and 4548 transitions. [2019-12-07 18:50:47,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 166 states. [2019-12-07 18:50:47,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4409 states and 4548 transitions. [2019-12-07 18:50:47,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:47,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4409 states to 4407 states and 4546 transitions. [2019-12-07 18:50:47,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2019-12-07 18:50:47,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2019-12-07 18:50:47,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4407 states and 4546 transitions. [2019-12-07 18:50:47,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:50:47,185 INFO L688 BuchiCegarLoop]: Abstraction has 4407 states and 4546 transitions. [2019-12-07 18:50:47,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4407 states and 4546 transitions. [2019-12-07 18:50:47,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4407 to 1503. [2019-12-07 18:50:47,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1503 states. [2019-12-07 18:50:47,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1503 states to 1503 states and 1583 transitions. [2019-12-07 18:50:47,203 INFO L711 BuchiCegarLoop]: Abstraction has 1503 states and 1583 transitions. [2019-12-07 18:50:47,203 INFO L591 BuchiCegarLoop]: Abstraction has 1503 states and 1583 transitions. [2019-12-07 18:50:47,203 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-12-07 18:50:47,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1503 states and 1583 transitions. [2019-12-07 18:50:47,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:47,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:47,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:47,208 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [202, 202, 183, 19, 1] [2019-12-07 18:50:47,208 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:50:47,208 INFO L794 eck$LassoCheckResult]: Stem: 38430#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 38431#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38455#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38440#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38441#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38448#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38432#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38433#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39402#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39401#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39400#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39399#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39398#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39397#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39396#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39395#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39394#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39393#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39391#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39390#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39389#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39388#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39387#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39385#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39384#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39383#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39382#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39381#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39379#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39378#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39377#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39376#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39375#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39373#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39372#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39371#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39370#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39369#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39367#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39366#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39365#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39364#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39363#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39361#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39360#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39359#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39358#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39357#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39355#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39354#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39353#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39352#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39351#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39349#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39348#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39347#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39346#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39345#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39344#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39343#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39342#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39341#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39340#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39339#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39337#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39336#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39335#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39334#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39333#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39332#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39331#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39330#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39329#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39328#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39327#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39326#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39325#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39324#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39323#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39322#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39320#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39319#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39318#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39317#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39316#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39315#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39314#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39313#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39312#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39311#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39310#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39308#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39307#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39306#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39305#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39304#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39302#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39301#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39300#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39299#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39298#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39296#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39295#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39294#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39292#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39291#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39290#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39288#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39287#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39286#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39285#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39284#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39282#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39281#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39280#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39279#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39278#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39276#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39275#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39274#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39273#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39272#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39270#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39269#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39268#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39267#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39266#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39265#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39264#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39263#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39262#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39261#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39260#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39259#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39258#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39257#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39256#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39255#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39254#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39253#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39252#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39251#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39250#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39249#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39247#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39246#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39245#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39244#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39243#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39242#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39241#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39240#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39239#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39237#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39236#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39235#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39234#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39233#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39232#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39231#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39230#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39229#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39228#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39227#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39226#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39225#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39224#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39223#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39222#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39221#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39220#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39219#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39218#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39217#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39216#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39215#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39214#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39213#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39212#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39211#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39210#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39209#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39208#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39207#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39206#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39205#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39204#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39203#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39202#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39201#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39200#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39199#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39198#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39197#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39196#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39195#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39194#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39193#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39192#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39191#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39190#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39189#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39188#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39187#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39185#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39184#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39183#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39182#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39181#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39180#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39179#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39178#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39177#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39176#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39175#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39174#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39173#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39172#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39171#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39170#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39169#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39168#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39167#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39166#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39165#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39164#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39163#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39161#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39160#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39159#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39158#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39157#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39156#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39155#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39154#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39153#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39152#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39151#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39150#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39149#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39148#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39147#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39146#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39145#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39144#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39143#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39142#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39141#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39140#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39139#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39138#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39136#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39135#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39134#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39132#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39131#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39129#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39128#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39127#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39125#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39123#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39122#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39119#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39107#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39101#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39098#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39097#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39096#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39095#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39094#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39093#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39092#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39091#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39090#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39089#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39088#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39068#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39065#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39064#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39063#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39062#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39061#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39060#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39059#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39058#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39057#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39056#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39055#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39054#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39052#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39051#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39050#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39048#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39047#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39046#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39044#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39043#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39042#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39041#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39040#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39038#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39037#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39036#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39035#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39034#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39032#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39031#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39030#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39029#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39028#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39026#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39025#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39024#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39022#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39018#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39013#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39012#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39011#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39010#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39007#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39006#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 39005#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39004#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39003#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 39002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 39001#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 39000#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38999#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38998#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38997#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38995#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38994#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38993#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38992#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38991#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38989#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38988#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38987#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38986#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38985#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38983#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38982#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38981#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38980#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38979#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38977#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38976#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38975#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38974#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38973#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38971#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38970#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38969#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38967#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38965#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38964#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38963#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38962#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38961#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38959#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38958#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38957#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38956#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38955#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38953#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38952#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38951#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38950#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38949#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38947#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38946#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38945#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38944#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38943#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38942#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38780#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38929#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38925#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38923#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38924#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38919#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38920#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38915#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38916#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38911#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38912#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38907#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38908#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38903#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38904#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38899#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38900#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38895#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38896#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38891#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38887#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38883#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38879#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38749#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38750#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38742#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38734#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38735#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38730#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38731#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38726#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38727#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38722#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38723#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38718#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38719#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38714#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38715#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38710#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38711#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38706#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38707#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38702#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38703#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38698#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38699#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38694#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38695#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38690#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38691#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38754#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38816#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38814#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38807#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38806#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38805#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38804#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38803#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38802#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38801#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38800#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38799#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38798#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38797#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38796#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38795#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38794#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38793#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38792#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38791#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38790#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38789#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38788#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38786#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38629#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38628#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38627#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38625#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38624#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38623#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38622#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38621#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38618#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38617#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38616#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38614#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38615#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38676#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38668#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38666#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38664#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38662#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38660#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38658#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38656#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38654#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38652#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38650#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38647#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38644#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38641#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38678#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38674#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38667#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38665#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38663#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38661#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38659#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38657#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38655#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38653#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38651#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38649#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38646#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38643#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38501#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38500#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38499#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38489#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38487#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38488#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38498#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38495#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38494#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38493#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38491#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38490#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38456#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 38457#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38444#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 38445#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 38449#L12-1 [2019-12-07 18:50:47,208 INFO L796 eck$LassoCheckResult]: Loop: 38449#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 38450#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 38449#L12-1 [2019-12-07 18:50:47,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:47,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1123607934, now seen corresponding path program 26 times [2019-12-07 18:50:47,209 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:47,209 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140634412] [2019-12-07 18:50:47,209 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:47,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:48,203 INFO L134 CoverageAnalysis]: Checked inductivity of 60903 backedges. 124 proven. 57031 refuted. 0 times theorem prover too weak. 3748 trivial. 0 not checked. [2019-12-07 18:50:48,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140634412] [2019-12-07 18:50:48,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1616163527] [2019-12-07 18:50:48,203 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:50:48,301 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:50:48,301 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:50:48,303 INFO L264 TraceCheckSpWp]: Trace formula consists of 1275 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 18:50:48,307 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:50:48,689 INFO L134 CoverageAnalysis]: Checked inductivity of 60903 backedges. 10920 proven. 45675 refuted. 0 times theorem prover too weak. 4308 trivial. 0 not checked. [2019-12-07 18:50:48,689 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:50:48,689 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 21] total 55 [2019-12-07 18:50:48,689 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874461864] [2019-12-07 18:50:48,690 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:48,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:48,690 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 22 times [2019-12-07 18:50:48,690 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:48,690 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139755647] [2019-12-07 18:50:48,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:48,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:48,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:48,692 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:48,718 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:48,718 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2019-12-07 18:50:48,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=637, Invalid=2443, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:50:48,718 INFO L87 Difference]: Start difference. First operand 1503 states and 1583 transitions. cyclomatic complexity: 84 Second operand 56 states. [2019-12-07 18:50:57,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:57,956 INFO L93 Difference]: Finished difference Result 5699 states and 5872 transitions. [2019-12-07 18:50:57,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2019-12-07 18:50:57,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5699 states and 5872 transitions. [2019-12-07 18:50:57,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:57,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5699 states to 5697 states and 5870 transitions. [2019-12-07 18:50:57,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2019-12-07 18:50:57,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2019-12-07 18:50:57,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5697 states and 5870 transitions. [2019-12-07 18:50:57,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:50:57,987 INFO L688 BuchiCegarLoop]: Abstraction has 5697 states and 5870 transitions. [2019-12-07 18:50:57,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5697 states and 5870 transitions. [2019-12-07 18:50:58,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5697 to 2052. [2019-12-07 18:50:58,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2052 states. [2019-12-07 18:50:58,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2052 states to 2052 states and 2143 transitions. [2019-12-07 18:50:58,008 INFO L711 BuchiCegarLoop]: Abstraction has 2052 states and 2143 transitions. [2019-12-07 18:50:58,009 INFO L591 BuchiCegarLoop]: Abstraction has 2052 states and 2143 transitions. [2019-12-07 18:50:58,009 INFO L424 BuchiCegarLoop]: ======== Iteration 27============ [2019-12-07 18:50:58,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2052 states and 2143 transitions. [2019-12-07 18:50:58,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2019-12-07 18:50:58,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:58,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:58,014 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [210, 210, 190, 20, 1] [2019-12-07 18:50:58,014 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2019-12-07 18:50:58,015 INFO L794 eck$LassoCheckResult]: Stem: 47805#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_~i~0, main_~range~0;havoc main_~i~0;havoc main_~range~0;main_~i~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~range~0 := 20; 47806#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47817#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47815#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 47816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47827#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47826#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47807#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47808#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49089#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49088#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49087#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49086#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49085#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49084#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49083#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49082#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49081#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49080#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49079#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49078#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49077#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49076#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49075#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49074#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49073#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49072#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49071#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49070#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49069#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49068#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49067#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49066#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49065#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49063#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49061#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49059#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49057#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49055#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49053#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49051#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49047#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49045#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49043#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49041#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49039#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49037#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49035#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49033#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49031#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49029#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49027#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49025#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49023#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49019#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49017#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49013#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49011#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49008#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49006#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49004#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 49002#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49000#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48996#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48994#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48992#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48988#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48986#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48984#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48980#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48978#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48976#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48974#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48972#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48968#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48966#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48964#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48962#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48960#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48958#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48956#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48954#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48952#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48950#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48948#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48946#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48945#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48943#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48941#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48939#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48937#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48935#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48933#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48931#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48929#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48927#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48925#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48923#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48921#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48919#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48917#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48915#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48913#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48911#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48909#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48907#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48905#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48903#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48901#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48899#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48897#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48894#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48892#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48890#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48888#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48886#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48884#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48882#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48880#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48878#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48876#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48874#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48872#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48870#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48866#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48864#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48862#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48860#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48858#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48856#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48854#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48852#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48850#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48848#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48846#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48844#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48842#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48840#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48838#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48836#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48834#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48832#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48831#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48829#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48826#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48824#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48822#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48818#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48816#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48814#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48812#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48810#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48808#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48806#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48804#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48802#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48800#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48798#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48796#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48794#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48792#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48790#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48788#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48785#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48783#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48781#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48779#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48777#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48775#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48773#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48771#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48769#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48767#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48765#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48763#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48761#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48759#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48757#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48755#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48753#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48751#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48749#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48747#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48745#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48743#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48741#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48739#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48737#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48735#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48733#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48731#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48729#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48727#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48725#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48723#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48722#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48720#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48717#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48715#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48713#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48711#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48709#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48707#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48705#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48703#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48701#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48699#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48697#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48695#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48693#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48691#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48689#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48687#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48685#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48682#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48680#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48678#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48676#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48674#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48672#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48670#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48668#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48666#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48664#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48662#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48660#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48658#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48656#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48654#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48652#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48650#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48648#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48646#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48644#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48642#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48640#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48638#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48636#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48634#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48632#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48630#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48628#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48626#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48624#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48622#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48620#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48619#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48617#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48614#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48612#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48610#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48608#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48606#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48604#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48602#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48600#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48598#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48596#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48594#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48592#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48590#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48588#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48585#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48583#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48581#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48579#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48577#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48575#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48573#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48571#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48569#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48567#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48565#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48563#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48561#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48559#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48557#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48555#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48553#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48551#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48549#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48547#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48545#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48543#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48541#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48539#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48537#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48535#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48533#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48531#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48529#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48527#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48525#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48523#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48521#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48519#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48516#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48514#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48512#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48510#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48508#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48506#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48504#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48502#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48500#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48498#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48496#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48494#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48492#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48490#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48488#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48486#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48484#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48482#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48480#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48478#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48476#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48474#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48472#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48470#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48468#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48466#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48464#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48462#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48460#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48458#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48456#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48454#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48452#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48450#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48448#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48446#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48444#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48442#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48440#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48438#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48436#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48434#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48432#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48431#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48429#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48427#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48425#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48423#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48421#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48419#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48417#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48415#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48413#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48410#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48408#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48406#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48404#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48402#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48400#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48398#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48396#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48394#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48392#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48390#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48388#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48386#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48384#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48382#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48380#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48378#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48376#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48374#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48372#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48370#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48368#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48366#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48364#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48362#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48360#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48358#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48356#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48354#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48352#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48350#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48348#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48347#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48345#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48342#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48340#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48338#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48336#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48334#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48331#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48329#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48327#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48325#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48323#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48321#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48319#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48317#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48315#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48313#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48311#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48309#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48307#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48305#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48303#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48301#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48299#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48297#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48295#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48293#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48291#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48289#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48287#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48285#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48283#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48281#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48279#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48277#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48275#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48273#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48271#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48269#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48267#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48265#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48262#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48260#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48258#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48256#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48254#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48252#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48250#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48248#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48246#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48244#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48242#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48240#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48238#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48236#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48234#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48232#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48230#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48228#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48226#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48224#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48222#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48220#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48218#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48216#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48214#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48212#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48210#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48208#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48206#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48204#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48202#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48200#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48198#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48197#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48196#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48195#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48185#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48186#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48181#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48182#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48177#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48178#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48173#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48174#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48170#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48165#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48161#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48162#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48158#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48153#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48149#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48150#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48145#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48146#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48141#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48142#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48137#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48138#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48133#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48134#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48129#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48130#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48126#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48125#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48124#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48123#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48122#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48121#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48120#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48119#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48118#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48117#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48116#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48114#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48113#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48112#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48111#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48110#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48109#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48108#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48107#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48106#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48105#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48104#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48103#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48102#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48101#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48100#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48099#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48095#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48096#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49174#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49173#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49172#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49171#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49170#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49169#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49168#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49167#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49166#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49165#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49164#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49163#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49162#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49161#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49160#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49159#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49158#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49157#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49153#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49152#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49115#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48049#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48050#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 49192#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49191#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49190#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49189#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49188#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49187#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49186#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49185#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49184#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49183#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49182#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49181#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49180#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49179#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49178#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49177#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 49176#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 49175#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 49154#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47982#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47981#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 47980#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47979#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47978#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47977#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47976#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47975#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47974#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47973#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47972#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47971#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47970#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47969#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47967#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47968#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48027#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48026#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48023#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48022#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48021#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48020#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48019#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48018#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48017#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48016#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48015#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48014#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48013#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47992#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47991#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48012#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48007#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48005#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48004#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 48003#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 48002#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 48001#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 48000#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47999#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47998#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47997#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47996#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47994#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47990#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47877#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47876#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 47875#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47868#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47865#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47863#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47864#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47874#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47873#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47870#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47869#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 47867#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47866#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47829#L13 assume !(main_~i~0 == main_~range~0);main_~i~0 := 1 + main_~i~0; 47830#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47820#L12 assume !(0 == main_~i~0 && main_~i~0 == main_~range~0); 47825#L13 assume main_~i~0 == main_~range~0;main_~i~0 := 0;main_~range~0 := main_~range~0 - 1; 47823#L12-1 [2019-12-07 18:50:58,015 INFO L796 eck$LassoCheckResult]: Loop: 47823#L12-1 assume !!(0 <= main_~i~0 && main_~i~0 <= main_~range~0); 47824#L12 assume !!(0 == main_~i~0 && main_~i~0 == main_~range~0); 47823#L12-1 [2019-12-07 18:50:58,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:58,015 INFO L82 PathProgramCache]: Analyzing trace with hash -397192768, now seen corresponding path program 27 times [2019-12-07 18:50:58,015 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:58,015 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509158135] [2019-12-07 18:50:58,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:58,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,146 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:58,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:58,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1292, now seen corresponding path program 23 times [2019-12-07 18:50:58,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:58,146 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095613378] [2019-12-07 18:50:58,146 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:58,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,148 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:58,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:58,148 INFO L82 PathProgramCache]: Analyzing trace with hash 549839627, now seen corresponding path program 3 times [2019-12-07 18:50:58,148 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:58,148 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371766414] [2019-12-07 18:50:58,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:58,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:58,293 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:51:28,329 WARN L192 SmtUtils]: Spent 29.96 s on a formula simplification. DAG size of input: 2131 DAG size of output: 674 [2019-12-07 18:51:28,454 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:51:28 BoogieIcfgContainer [2019-12-07 18:51:28,455 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:51:28,455 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:51:28,455 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:51:28,455 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:51:28,455 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:48:58" (3/4) ... [2019-12-07 18:51:28,457 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:51:28,556 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_7915347a-6eec-4166-82fd-9007c6d90abc/bin/uautomizer/witness.graphml [2019-12-07 18:51:28,556 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:51:28,558 INFO L168 Benchmark]: Toolchain (without parser) took 150646.80 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 176.2 MB). Free memory was 944.7 MB in the beginning and 877.4 MB in the end (delta: 67.3 MB). Peak memory consumption was 243.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:51:28,558 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:51:28,558 INFO L168 Benchmark]: CACSL2BoogieTranslator took 181.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.0 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -149.8 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:51:28,558 INFO L168 Benchmark]: Boogie Procedure Inliner took 19.58 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:51:28,558 INFO L168 Benchmark]: Boogie Preprocessor took 11.21 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:51:28,558 INFO L168 Benchmark]: RCFGBuilder took 125.12 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 21.0 MB). Peak memory consumption was 21.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:51:28,559 INFO L168 Benchmark]: BuchiAutomizer took 150205.28 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 79.2 MB). Free memory was 1.1 GB in the beginning and 903.1 MB in the end (delta: 170.4 MB). Peak memory consumption was 718.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:51:28,559 INFO L168 Benchmark]: Witness Printer took 101.58 ms. Allocated memory is still 1.2 GB. Free memory was 903.1 MB in the beginning and 877.4 MB in the end (delta: 25.7 MB). Peak memory consumption was 25.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:51:28,560 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 181.12 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.0 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -149.8 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 19.58 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 11.21 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 125.12 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 21.0 MB). Peak memory consumption was 21.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 150205.28 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 79.2 MB). Free memory was 1.1 GB in the beginning and 903.1 MB in the end (delta: 170.4 MB). Peak memory consumption was 718.4 MB. Max. memory is 11.5 GB. * Witness Printer took 101.58 ms. Allocated memory is still 1.2 GB. Free memory was 903.1 MB in the beginning and 877.4 MB in the end (delta: 25.7 MB). Peak memory consumption was 25.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 27 terminating modules (23 trivial, 3 deterministic, 1 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * i + range and consists of 3 locations. One deterministic module has affine ranking function range + -1 * i and consists of 3 locations. One deterministic module has affine ranking function range and consists of 3 locations. One nondeterministic module has affine ranking function -1 * i + range and consists of 3 locations. 23 modules have a trivial ranking function, the largest among these consists of 146 locations. The remainder module has 2052 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 150.1s and 27 iterations. TraceHistogramMax:210. Analysis of lassos took 51.6s. Construction of modules took 19.5s. Büchi inclusion checks took 78.3s. Highest rank in rank-based complementation 3. Minimization of det autom 1. Minimization of nondet autom 26. Automata minimization 0.1s AutomataMinimizationTime, 27 MinimizatonAttempts, 12831 StatesRemovedByMinimization, 24 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 2061 states and ocurred in iteration 22. Nontrivial modules had stage [3, 0, 1, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 1/3 HoareTripleCheckerStatistics: 70 SDtfs, 11855 SDslu, 3 SDs, 0 SdLazy, 27644 SolverSat, 8270 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 19.5s Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT3 conc4 concLT1 SILN18 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital17 mio100 ax167 hnf100 lsp59 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq166 hnf95 smp74 dnf100 smp100 tf109 neg95 sie109 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 14ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 11]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {range=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@673fa68c=0, \result=0, i=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 11]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND FALSE !(i == range) [L17] i = i+1 [L11] COND TRUE 0 <= i && i <= range [L12] COND TRUE !(0 == i && i == range) [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 Loop: [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...