./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9f3cf63c7adaf3e2c576343bf7deb0d4236e103c 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:22:55,000 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:22:55,002 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:22:55,009 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:22:55,009 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:22:55,010 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:22:55,011 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:22:55,012 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:22:55,013 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:22:55,014 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:22:55,014 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:22:55,015 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:22:55,015 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:22:55,016 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:22:55,017 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:22:55,018 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:22:55,018 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:22:55,019 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:22:55,020 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:22:55,021 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:22:55,022 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:22:55,023 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:22:55,024 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:22:55,024 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:22:55,026 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:22:55,026 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:22:55,026 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:22:55,027 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:22:55,027 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:22:55,028 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:22:55,028 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:22:55,028 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:22:55,029 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:22:55,029 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:22:55,030 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:22:55,030 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:22:55,030 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:22:55,030 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:22:55,030 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:22:55,031 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:22:55,031 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:22:55,032 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 18:22:55,043 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:22:55,043 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:22:55,044 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:22:55,044 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:22:55,044 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:22:55,044 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:22:55,044 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:22:55,044 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:22:55,045 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:22:55,045 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:22:55,046 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:22:55,047 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:22:55,047 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:22:55,047 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:22:55,048 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:22:55,048 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:22:55,048 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:22:55,048 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9f3cf63c7adaf3e2c576343bf7deb0d4236e103c [2019-12-07 18:22:55,145 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:22:55,152 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:22:55,154 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:22:55,155 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:22:55,156 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:22:55,156 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2019-12-07 18:22:55,193 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/data/8aec97ead/3093c491fcc04df8855efc072e1c60f9/FLAGce72cc0c5 [2019-12-07 18:22:55,522 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:22:55,523 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2019-12-07 18:22:55,526 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/data/8aec97ead/3093c491fcc04df8855efc072e1c60f9/FLAGce72cc0c5 [2019-12-07 18:22:55,535 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/data/8aec97ead/3093c491fcc04df8855efc072e1c60f9 [2019-12-07 18:22:55,537 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:22:55,537 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:22:55,538 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:22:55,538 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:22:55,540 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:22:55,541 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,543 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@446e037f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55, skipping insertion in model container [2019-12-07 18:22:55,543 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,547 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:22:55,557 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:22:55,653 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:22:55,655 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:22:55,698 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:22:55,708 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:22:55,708 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55 WrapperNode [2019-12-07 18:22:55,709 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:22:55,709 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:22:55,709 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:22:55,709 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:22:55,715 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,719 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,731 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:22:55,731 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:22:55,732 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:22:55,732 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:22:55,737 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,738 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,738 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,738 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,739 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,742 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,743 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... [2019-12-07 18:22:55,744 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:22:55,744 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:22:55,744 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:22:55,744 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:22:55,745 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:55,792 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:22:55,792 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:22:55,912 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:22:55,912 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:22:55,913 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:22:55 BoogieIcfgContainer [2019-12-07 18:22:55,913 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:22:55,914 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:22:55,914 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:22:55,916 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:22:55,916 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:22:55,916 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:22:55" (1/3) ... [2019-12-07 18:22:55,917 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53123ad2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:22:55, skipping insertion in model container [2019-12-07 18:22:55,917 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:22:55,917 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:22:55" (2/3) ... [2019-12-07 18:22:55,917 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53123ad2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:22:55, skipping insertion in model container [2019-12-07 18:22:55,917 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:22:55,917 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:22:55" (3/3) ... [2019-12-07 18:22:55,918 INFO L371 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2019-12-07 18:22:55,947 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:22:55,947 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:22:55,947 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:22:55,947 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:22:55,947 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:22:55,947 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:22:55,947 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:22:55,948 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:22:55,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states. [2019-12-07 18:22:55,969 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:55,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:55,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:55,973 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2019-12-07 18:22:55,973 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:55,973 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:22:55,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states. [2019-12-07 18:22:55,974 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:55,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:55,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:55,975 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2019-12-07 18:22:55,975 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:55,980 INFO L794 eck$LassoCheckResult]: Stem: 7#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 8#L12true main_~i~0 := 0; 13#L15-1true [2019-12-07 18:22:55,980 INFO L796 eck$LassoCheckResult]: Loop: 13#L15-1true assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13#L15-1true [2019-12-07 18:22:55,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:55,984 INFO L82 PathProgramCache]: Analyzing trace with hash 995, now seen corresponding path program 1 times [2019-12-07 18:22:55,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:55,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634627592] [2019-12-07 18:22:55,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,049 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,050 INFO L82 PathProgramCache]: Analyzing trace with hash 43, now seen corresponding path program 1 times [2019-12-07 18:22:56,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,051 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433298651] [2019-12-07 18:22:56,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,058 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,060 INFO L82 PathProgramCache]: Analyzing trace with hash 30857, now seen corresponding path program 1 times [2019-12-07 18:22:56,060 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,060 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591374196] [2019-12-07 18:22:56,060 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,068 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,098 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:22:56,099 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:22:56,099 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:22:56,099 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:22:56,099 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 18:22:56,099 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,099 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:22:56,100 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:22:56,100 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2019-12-07 18:22:56,100 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:22:56,100 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:22:56,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,125 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,127 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,164 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:22:56,164 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,169 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 18:22:56,169 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,176 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 18:22:56,176 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 18:22:56,184 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 18:22:56,185 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 18:22:56,185 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 18:22:56,185 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 18:22:56,185 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 18:22:56,185 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 18:22:56,185 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,185 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 18:22:56,185 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 18:22:56,186 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2019-12-07 18:22:56,186 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 18:22:56,186 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 18:22:56,187 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,198 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 18:22:56,225 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 18:22:56,228 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,233 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 18:22:56,235 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 18:22:56,235 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 18:22:56,235 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 18:22:56,235 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 18:22:56,235 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 18:22:56,238 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 18:22:56,238 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 18:22:56,240 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 18:22:56,244 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 18:22:56,245 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:22:56,248 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 18:22:56,248 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 18:22:56,249 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 18:22:56,249 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0) = -2*ULTIMATE.start_main_~i~0 + 1999999 Supporting invariants [] [2019-12-07 18:22:56,252 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 18:22:56,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,277 INFO L264 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,278 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,286 WARN L262 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,287 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,302 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2019-12-07 18:22:56,303 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 13 states. Second operand 2 states. [2019-12-07 18:22:56,345 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 13 states.. Second operand 2 states. Result 36 states and 55 transitions. Complement of second has 5 states. [2019-12-07 18:22:56,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 18:22:56,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2019-12-07 18:22:56,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 36 transitions. [2019-12-07 18:22:56,348 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 36 transitions. Stem has 2 letters. Loop has 1 letters. [2019-12-07 18:22:56,349 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:22:56,349 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 36 transitions. Stem has 3 letters. Loop has 1 letters. [2019-12-07 18:22:56,349 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:22:56,349 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 36 transitions. Stem has 2 letters. Loop has 2 letters. [2019-12-07 18:22:56,349 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 18:22:56,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 55 transitions. [2019-12-07 18:22:56,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 12 states and 18 transitions. [2019-12-07 18:22:56,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:56,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2019-12-07 18:22:56,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 18 transitions. [2019-12-07 18:22:56,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,358 INFO L688 BuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2019-12-07 18:22:56,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 18 transitions. [2019-12-07 18:22:56,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2019-12-07 18:22:56,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-12-07 18:22:56,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 17 transitions. [2019-12-07 18:22:56,376 INFO L711 BuchiCegarLoop]: Abstraction has 11 states and 17 transitions. [2019-12-07 18:22:56,376 INFO L591 BuchiCegarLoop]: Abstraction has 11 states and 17 transitions. [2019-12-07 18:22:56,376 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:22:56,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 17 transitions. [2019-12-07 18:22:56,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,377 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2019-12-07 18:22:56,377 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,377 INFO L794 eck$LassoCheckResult]: Stem: 81#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 82#L12 main_~i~0 := 0; 83#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 84#L15-2 assume main_~i~0 >= 100; 85#L25 [2019-12-07 18:22:56,377 INFO L796 eck$LassoCheckResult]: Loop: 85#L25 assume true; 85#L25 [2019-12-07 18:22:56,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,378 INFO L82 PathProgramCache]: Analyzing trace with hash 956523, now seen corresponding path program 1 times [2019-12-07 18:22:56,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095771449] [2019-12-07 18:22:56,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,398 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095771449] [2019-12-07 18:22:56,399 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:22:56,399 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:22:56,400 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623487601] [2019-12-07 18:22:56,402 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,402 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 1 times [2019-12-07 18:22:56,402 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,402 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137163339] [2019-12-07 18:22:56,402 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,404 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,407 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,408 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:22:56,409 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:22:56,409 INFO L87 Difference]: Start difference. First operand 11 states and 17 transitions. cyclomatic complexity: 9 Second operand 3 states. [2019-12-07 18:22:56,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,428 INFO L93 Difference]: Finished difference Result 17 states and 23 transitions. [2019-12-07 18:22:56,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:22:56,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 23 transitions. [2019-12-07 18:22:56,430 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2019-12-07 18:22:56,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 17 states and 23 transitions. [2019-12-07 18:22:56,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2019-12-07 18:22:56,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2019-12-07 18:22:56,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 23 transitions. [2019-12-07 18:22:56,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,431 INFO L688 BuchiCegarLoop]: Abstraction has 17 states and 23 transitions. [2019-12-07 18:22:56,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 23 transitions. [2019-12-07 18:22:56,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 12. [2019-12-07 18:22:56,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-12-07 18:22:56,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 18 transitions. [2019-12-07 18:22:56,433 INFO L711 BuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2019-12-07 18:22:56,433 INFO L591 BuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2019-12-07 18:22:56,433 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:22:56,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 18 transitions. [2019-12-07 18:22:56,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,434 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2019-12-07 18:22:56,434 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,435 INFO L794 eck$LassoCheckResult]: Stem: 115#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 116#L12 main_~i~0 := 0; 117#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 124#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 125#L15-2 assume main_~i~0 >= 100; 123#L25 [2019-12-07 18:22:56,435 INFO L796 eck$LassoCheckResult]: Loop: 123#L25 assume true; 123#L25 [2019-12-07 18:22:56,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,435 INFO L82 PathProgramCache]: Analyzing trace with hash 29653905, now seen corresponding path program 1 times [2019-12-07 18:22:56,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585057568] [2019-12-07 18:22:56,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,449 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585057568] [2019-12-07 18:22:56,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1342608045] [2019-12-07 18:22:56,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,466 INFO L264 TraceCheckSpWp]: Trace formula consists of 11 conjuncts, 3 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,466 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,473 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,473 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2019-12-07 18:22:56,473 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297962818] [2019-12-07 18:22:56,474 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,474 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 2 times [2019-12-07 18:22:56,474 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,474 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026524278] [2019-12-07 18:22:56,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,477 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,479 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:22:56,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:22:56,480 INFO L87 Difference]: Start difference. First operand 12 states and 18 transitions. cyclomatic complexity: 9 Second operand 4 states. [2019-12-07 18:22:56,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,503 INFO L93 Difference]: Finished difference Result 25 states and 34 transitions. [2019-12-07 18:22:56,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:22:56,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 34 transitions. [2019-12-07 18:22:56,504 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:56,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 34 transitions. [2019-12-07 18:22:56,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2019-12-07 18:22:56,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2019-12-07 18:22:56,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 34 transitions. [2019-12-07 18:22:56,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,505 INFO L688 BuchiCegarLoop]: Abstraction has 25 states and 34 transitions. [2019-12-07 18:22:56,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 34 transitions. [2019-12-07 18:22:56,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 13. [2019-12-07 18:22:56,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-12-07 18:22:56,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 21 transitions. [2019-12-07 18:22:56,507 INFO L711 BuchiCegarLoop]: Abstraction has 13 states and 21 transitions. [2019-12-07 18:22:56,507 INFO L591 BuchiCegarLoop]: Abstraction has 13 states and 21 transitions. [2019-12-07 18:22:56,507 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:22:56,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 21 transitions. [2019-12-07 18:22:56,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,508 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2019-12-07 18:22:56,508 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,508 INFO L794 eck$LassoCheckResult]: Stem: 171#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 172#L12 main_~i~0 := 0; 173#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 174#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 175#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 178#L21-2 assume main_~j~0 >= 100; 179#L25 [2019-12-07 18:22:56,508 INFO L796 eck$LassoCheckResult]: Loop: 179#L25 assume true; 179#L25 [2019-12-07 18:22:56,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,508 INFO L82 PathProgramCache]: Analyzing trace with hash 919222390, now seen corresponding path program 1 times [2019-12-07 18:22:56,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843830174] [2019-12-07 18:22:56,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843830174] [2019-12-07 18:22:56,518 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:22:56,518 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:22:56,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568841202] [2019-12-07 18:22:56,519 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,519 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 3 times [2019-12-07 18:22:56,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236696144] [2019-12-07 18:22:56,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,521 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:22:56,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:22:56,523 INFO L87 Difference]: Start difference. First operand 13 states and 21 transitions. cyclomatic complexity: 11 Second operand 3 states. [2019-12-07 18:22:56,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,527 INFO L93 Difference]: Finished difference Result 14 states and 21 transitions. [2019-12-07 18:22:56,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:22:56,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 21 transitions. [2019-12-07 18:22:56,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 11 states and 16 transitions. [2019-12-07 18:22:56,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:56,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:56,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 16 transitions. [2019-12-07 18:22:56,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,529 INFO L688 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2019-12-07 18:22:56,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 16 transitions. [2019-12-07 18:22:56,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-12-07 18:22:56,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-12-07 18:22:56,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 16 transitions. [2019-12-07 18:22:56,530 INFO L711 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2019-12-07 18:22:56,530 INFO L591 BuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2019-12-07 18:22:56,530 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:22:56,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 16 transitions. [2019-12-07 18:22:56,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,531 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1] [2019-12-07 18:22:56,531 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,531 INFO L794 eck$LassoCheckResult]: Stem: 204#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 205#L12 main_~i~0 := 0; 206#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 212#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 213#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 207#L15-2 assume main_~i~0 >= 100; 208#L25 [2019-12-07 18:22:56,531 INFO L796 eck$LassoCheckResult]: Loop: 208#L25 assume true; 208#L25 [2019-12-07 18:22:56,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,531 INFO L82 PathProgramCache]: Analyzing trace with hash 919272747, now seen corresponding path program 2 times [2019-12-07 18:22:56,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572868908] [2019-12-07 18:22:56,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,550 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572868908] [2019-12-07 18:22:56,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1896263066] [2019-12-07 18:22:56,551 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,575 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:56,575 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:56,576 INFO L264 TraceCheckSpWp]: Trace formula consists of 15 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,576 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,579 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,579 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,579 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2019-12-07 18:22:56,579 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406880929] [2019-12-07 18:22:56,580 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,580 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 4 times [2019-12-07 18:22:56,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759094204] [2019-12-07 18:22:56,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,582 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:22:56,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:22:56,585 INFO L87 Difference]: Start difference. First operand 11 states and 16 transitions. cyclomatic complexity: 8 Second operand 5 states. [2019-12-07 18:22:56,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,610 INFO L93 Difference]: Finished difference Result 25 states and 33 transitions. [2019-12-07 18:22:56,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:22:56,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 33 transitions. [2019-12-07 18:22:56,612 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:56,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 24 states and 32 transitions. [2019-12-07 18:22:56,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:56,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:56,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 32 transitions. [2019-12-07 18:22:56,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,613 INFO L688 BuchiCegarLoop]: Abstraction has 24 states and 32 transitions. [2019-12-07 18:22:56,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 32 transitions. [2019-12-07 18:22:56,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 12. [2019-12-07 18:22:56,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-12-07 18:22:56,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 18 transitions. [2019-12-07 18:22:56,615 INFO L711 BuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2019-12-07 18:22:56,615 INFO L591 BuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2019-12-07 18:22:56,615 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:22:56,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 18 transitions. [2019-12-07 18:22:56,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,616 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:56,616 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,616 INFO L794 eck$LassoCheckResult]: Stem: 263#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 264#L12 main_~i~0 := 0; 265#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 268#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 269#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 273#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 270#L21-2 assume main_~j~0 >= 100; 267#L25 [2019-12-07 18:22:56,616 INFO L796 eck$LassoCheckResult]: Loop: 267#L25 assume true; 267#L25 [2019-12-07 18:22:56,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,617 INFO L82 PathProgramCache]: Analyzing trace with hash -1568875272, now seen corresponding path program 1 times [2019-12-07 18:22:56,617 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,617 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276779321] [2019-12-07 18:22:56,617 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,632 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276779321] [2019-12-07 18:22:56,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [150447653] [2019-12-07 18:22:56,632 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,648 INFO L264 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 3 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,648 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,650 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2019-12-07 18:22:56,651 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655739802] [2019-12-07 18:22:56,651 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,651 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 5 times [2019-12-07 18:22:56,651 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362679674] [2019-12-07 18:22:56,652 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,654 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,656 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:22:56,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:22:56,656 INFO L87 Difference]: Start difference. First operand 12 states and 18 transitions. cyclomatic complexity: 9 Second operand 4 states. [2019-12-07 18:22:56,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,663 INFO L93 Difference]: Finished difference Result 14 states and 20 transitions. [2019-12-07 18:22:56,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:22:56,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 20 transitions. [2019-12-07 18:22:56,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 13 states and 19 transitions. [2019-12-07 18:22:56,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:56,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:56,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 19 transitions. [2019-12-07 18:22:56,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,665 INFO L688 BuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2019-12-07 18:22:56,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 19 transitions. [2019-12-07 18:22:56,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2019-12-07 18:22:56,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-12-07 18:22:56,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 19 transitions. [2019-12-07 18:22:56,667 INFO L711 BuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2019-12-07 18:22:56,667 INFO L591 BuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2019-12-07 18:22:56,667 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:22:56,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 19 transitions. [2019-12-07 18:22:56,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,668 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [3, 1, 1, 1, 1] [2019-12-07 18:22:56,668 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,668 INFO L794 eck$LassoCheckResult]: Stem: 314#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 315#L12 main_~i~0 := 0; 316#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 322#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 323#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 326#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 317#L15-2 assume main_~i~0 >= 100; 318#L25 [2019-12-07 18:22:56,668 INFO L796 eck$LassoCheckResult]: Loop: 318#L25 assume true; 318#L25 [2019-12-07 18:22:56,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1567314223, now seen corresponding path program 3 times [2019-12-07 18:22:56,669 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,669 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595165531] [2019-12-07 18:22:56,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,703 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595165531] [2019-12-07 18:22:56,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [320375539] [2019-12-07 18:22:56,704 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,720 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-12-07 18:22:56,720 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:56,721 INFO L264 TraceCheckSpWp]: Trace formula consists of 19 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,721 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,724 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,724 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,724 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-12-07 18:22:56,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145314287] [2019-12-07 18:22:56,725 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,725 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 6 times [2019-12-07 18:22:56,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868788556] [2019-12-07 18:22:56,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,727 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,729 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:22:56,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:22:56,729 INFO L87 Difference]: Start difference. First operand 13 states and 19 transitions. cyclomatic complexity: 9 Second operand 6 states. [2019-12-07 18:22:56,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,761 INFO L93 Difference]: Finished difference Result 32 states and 41 transitions. [2019-12-07 18:22:56,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:22:56,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 41 transitions. [2019-12-07 18:22:56,763 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:56,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 31 states and 40 transitions. [2019-12-07 18:22:56,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:56,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:56,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 40 transitions. [2019-12-07 18:22:56,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,764 INFO L688 BuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2019-12-07 18:22:56,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 40 transitions. [2019-12-07 18:22:56,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 14. [2019-12-07 18:22:56,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-12-07 18:22:56,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 21 transitions. [2019-12-07 18:22:56,766 INFO L711 BuchiCegarLoop]: Abstraction has 14 states and 21 transitions. [2019-12-07 18:22:56,766 INFO L591 BuchiCegarLoop]: Abstraction has 14 states and 21 transitions. [2019-12-07 18:22:56,766 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:22:56,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 21 transitions. [2019-12-07 18:22:56,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,768 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:56,768 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,768 INFO L794 eck$LassoCheckResult]: Stem: 386#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 387#L12 main_~i~0 := 0; 388#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 391#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 392#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 396#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 399#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 393#L21-2 assume main_~j~0 >= 100; 390#L25 [2019-12-07 18:22:56,768 INFO L796 eck$LassoCheckResult]: Loop: 390#L25 assume true; 390#L25 [2019-12-07 18:22:56,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,768 INFO L82 PathProgramCache]: Analyzing trace with hash -1390491466, now seen corresponding path program 2 times [2019-12-07 18:22:56,768 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,769 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444500216] [2019-12-07 18:22:56,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,789 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444500216] [2019-12-07 18:22:56,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [73506179] [2019-12-07 18:22:56,789 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,805 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:56,806 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:56,806 INFO L264 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,806 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,808 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,808 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2019-12-07 18:22:56,809 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265935931] [2019-12-07 18:22:56,809 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,809 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 7 times [2019-12-07 18:22:56,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,809 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101983274] [2019-12-07 18:22:56,809 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,811 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,812 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:22:56,813 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:22:56,813 INFO L87 Difference]: Start difference. First operand 14 states and 21 transitions. cyclomatic complexity: 10 Second operand 5 states. [2019-12-07 18:22:56,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,821 INFO L93 Difference]: Finished difference Result 16 states and 23 transitions. [2019-12-07 18:22:56,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:22:56,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 23 transitions. [2019-12-07 18:22:56,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 15 states and 22 transitions. [2019-12-07 18:22:56,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:56,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:56,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 22 transitions. [2019-12-07 18:22:56,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,822 INFO L688 BuchiCegarLoop]: Abstraction has 15 states and 22 transitions. [2019-12-07 18:22:56,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 22 transitions. [2019-12-07 18:22:56,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2019-12-07 18:22:56,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-12-07 18:22:56,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 22 transitions. [2019-12-07 18:22:56,823 INFO L711 BuchiCegarLoop]: Abstraction has 15 states and 22 transitions. [2019-12-07 18:22:56,824 INFO L591 BuchiCegarLoop]: Abstraction has 15 states and 22 transitions. [2019-12-07 18:22:56,824 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:22:56,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 22 transitions. [2019-12-07 18:22:56,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,824 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1] [2019-12-07 18:22:56,824 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,824 INFO L794 eck$LassoCheckResult]: Stem: 445#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 446#L12 main_~i~0 := 0; 447#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 453#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 454#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 459#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 457#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 448#L15-2 assume main_~i~0 >= 100; 449#L25 [2019-12-07 18:22:56,824 INFO L796 eck$LassoCheckResult]: Loop: 449#L25 assume true; 449#L25 [2019-12-07 18:22:56,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1342098965, now seen corresponding path program 4 times [2019-12-07 18:22:56,825 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,825 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505535641] [2019-12-07 18:22:56,825 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,851 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,851 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505535641] [2019-12-07 18:22:56,852 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1761287750] [2019-12-07 18:22:56,852 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,868 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:22:56,868 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:56,869 INFO L264 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 6 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,869 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,872 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,873 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,873 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2019-12-07 18:22:56,873 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969507395] [2019-12-07 18:22:56,873 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,874 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 8 times [2019-12-07 18:22:56,874 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,874 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165577994] [2019-12-07 18:22:56,874 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,875 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:22:56,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:22:56,878 INFO L87 Difference]: Start difference. First operand 15 states and 22 transitions. cyclomatic complexity: 10 Second operand 7 states. [2019-12-07 18:22:56,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,913 INFO L93 Difference]: Finished difference Result 40 states and 50 transitions. [2019-12-07 18:22:56,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:22:56,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 50 transitions. [2019-12-07 18:22:56,914 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:56,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 39 states and 49 transitions. [2019-12-07 18:22:56,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:56,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:56,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 49 transitions. [2019-12-07 18:22:56,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,915 INFO L688 BuchiCegarLoop]: Abstraction has 39 states and 49 transitions. [2019-12-07 18:22:56,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 49 transitions. [2019-12-07 18:22:56,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 16. [2019-12-07 18:22:56,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-12-07 18:22:56,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 24 transitions. [2019-12-07 18:22:56,917 INFO L711 BuchiCegarLoop]: Abstraction has 16 states and 24 transitions. [2019-12-07 18:22:56,917 INFO L591 BuchiCegarLoop]: Abstraction has 16 states and 24 transitions. [2019-12-07 18:22:56,917 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:22:56,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 24 transitions. [2019-12-07 18:22:56,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,918 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [3, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:56,918 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,919 INFO L794 eck$LassoCheckResult]: Stem: 531#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 532#L12 main_~i~0 := 0; 533#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 536#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 537#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 541#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 546#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 545#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 538#L21-2 assume main_~j~0 >= 100; 535#L25 [2019-12-07 18:22:56,919 INFO L796 eck$LassoCheckResult]: Loop: 535#L25 assume true; 535#L25 [2019-12-07 18:22:56,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,919 INFO L82 PathProgramCache]: Analyzing trace with hash -155560776, now seen corresponding path program 3 times [2019-12-07 18:22:56,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359869144] [2019-12-07 18:22:56,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:56,944 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359869144] [2019-12-07 18:22:56,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [997078790] [2019-12-07 18:22:56,945 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:56,963 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-12-07 18:22:56,963 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:56,964 INFO L264 TraceCheckSpWp]: Trace formula consists of 29 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 18:22:56,964 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:56,967 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:56,967 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:56,967 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-12-07 18:22:56,967 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176685166] [2019-12-07 18:22:56,968 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:56,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,968 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 9 times [2019-12-07 18:22:56,968 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,968 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943065293] [2019-12-07 18:22:56,968 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:56,970 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:56,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:56,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:22:56,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:22:56,972 INFO L87 Difference]: Start difference. First operand 16 states and 24 transitions. cyclomatic complexity: 11 Second operand 6 states. [2019-12-07 18:22:56,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:56,983 INFO L93 Difference]: Finished difference Result 18 states and 26 transitions. [2019-12-07 18:22:56,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:22:56,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 26 transitions. [2019-12-07 18:22:56,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 17 states and 25 transitions. [2019-12-07 18:22:56,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:56,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:56,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 25 transitions. [2019-12-07 18:22:56,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:56,985 INFO L688 BuchiCegarLoop]: Abstraction has 17 states and 25 transitions. [2019-12-07 18:22:56,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 25 transitions. [2019-12-07 18:22:56,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2019-12-07 18:22:56,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-12-07 18:22:56,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 25 transitions. [2019-12-07 18:22:56,987 INFO L711 BuchiCegarLoop]: Abstraction has 17 states and 25 transitions. [2019-12-07 18:22:56,987 INFO L591 BuchiCegarLoop]: Abstraction has 17 states and 25 transitions. [2019-12-07 18:22:56,987 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:22:56,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 25 transitions. [2019-12-07 18:22:56,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:56,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:56,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:56,988 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [5, 1, 1, 1, 1] [2019-12-07 18:22:56,989 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:56,989 INFO L794 eck$LassoCheckResult]: Stem: 598#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 599#L12 main_~i~0 := 0; 600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 607#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 610#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 601#L15-2 assume main_~i~0 >= 100; 602#L25 [2019-12-07 18:22:56,989 INFO L796 eck$LassoCheckResult]: Loop: 602#L25 assume true; 602#L25 [2019-12-07 18:22:56,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:56,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1344606737, now seen corresponding path program 5 times [2019-12-07 18:22:56,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:56,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127109321] [2019-12-07 18:22:56,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:56,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,026 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127109321] [2019-12-07 18:22:57,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [801645325] [2019-12-07 18:22:57,027 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,048 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2019-12-07 18:22:57,048 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,049 INFO L264 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 7 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,050 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,053 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-12-07 18:22:57,054 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14680189] [2019-12-07 18:22:57,054 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,054 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 10 times [2019-12-07 18:22:57,054 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,054 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967080008] [2019-12-07 18:22:57,054 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,056 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,058 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:22:57,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:22:57,058 INFO L87 Difference]: Start difference. First operand 17 states and 25 transitions. cyclomatic complexity: 11 Second operand 8 states. [2019-12-07 18:22:57,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,098 INFO L93 Difference]: Finished difference Result 49 states and 60 transitions. [2019-12-07 18:22:57,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:22:57,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 60 transitions. [2019-12-07 18:22:57,099 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:57,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 48 states and 59 transitions. [2019-12-07 18:22:57,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:57,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:57,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 59 transitions. [2019-12-07 18:22:57,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,100 INFO L688 BuchiCegarLoop]: Abstraction has 48 states and 59 transitions. [2019-12-07 18:22:57,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 59 transitions. [2019-12-07 18:22:57,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 18. [2019-12-07 18:22:57,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-12-07 18:22:57,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 27 transitions. [2019-12-07 18:22:57,102 INFO L711 BuchiCegarLoop]: Abstraction has 18 states and 27 transitions. [2019-12-07 18:22:57,102 INFO L591 BuchiCegarLoop]: Abstraction has 18 states and 27 transitions. [2019-12-07 18:22:57,103 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:22:57,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 27 transitions. [2019-12-07 18:22:57,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,103 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:57,103 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,104 INFO L794 eck$LassoCheckResult]: Stem: 699#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 700#L12 main_~i~0 := 0; 701#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 704#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 709#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 716#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 715#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 714#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 706#L21-2 assume main_~j~0 >= 100; 703#L25 [2019-12-07 18:22:57,104 INFO L796 eck$LassoCheckResult]: Loop: 703#L25 assume true; 703#L25 [2019-12-07 18:22:57,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,104 INFO L82 PathProgramCache]: Analyzing trace with hash -527415050, now seen corresponding path program 4 times [2019-12-07 18:22:57,104 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,104 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439283095] [2019-12-07 18:22:57,104 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,134 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439283095] [2019-12-07 18:22:57,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1518270142] [2019-12-07 18:22:57,134 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,153 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:22:57,153 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,154 INFO L264 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 6 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,155 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,158 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2019-12-07 18:22:57,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555702413] [2019-12-07 18:22:57,159 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,160 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 11 times [2019-12-07 18:22:57,160 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,160 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813809178] [2019-12-07 18:22:57,160 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,162 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,165 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,165 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:22:57,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:22:57,166 INFO L87 Difference]: Start difference. First operand 18 states and 27 transitions. cyclomatic complexity: 12 Second operand 7 states. [2019-12-07 18:22:57,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,177 INFO L93 Difference]: Finished difference Result 20 states and 29 transitions. [2019-12-07 18:22:57,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:22:57,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 29 transitions. [2019-12-07 18:22:57,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 19 states and 28 transitions. [2019-12-07 18:22:57,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:57,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:57,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 28 transitions. [2019-12-07 18:22:57,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,179 INFO L688 BuchiCegarLoop]: Abstraction has 19 states and 28 transitions. [2019-12-07 18:22:57,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 28 transitions. [2019-12-07 18:22:57,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2019-12-07 18:22:57,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-12-07 18:22:57,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 28 transitions. [2019-12-07 18:22:57,181 INFO L711 BuchiCegarLoop]: Abstraction has 19 states and 28 transitions. [2019-12-07 18:22:57,181 INFO L591 BuchiCegarLoop]: Abstraction has 19 states and 28 transitions. [2019-12-07 18:22:57,181 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:22:57,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 28 transitions. [2019-12-07 18:22:57,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,182 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [6, 1, 1, 1, 1] [2019-12-07 18:22:57,182 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,182 INFO L794 eck$LassoCheckResult]: Stem: 774#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 775#L12 main_~i~0 := 0; 776#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 782#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 783#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 792#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 790#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 788#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 786#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 777#L15-2 assume main_~i~0 >= 100; 778#L25 [2019-12-07 18:22:57,182 INFO L796 eck$LassoCheckResult]: Loop: 778#L25 assume true; 778#L25 [2019-12-07 18:22:57,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,183 INFO L82 PathProgramCache]: Analyzing trace with hash -1266862421, now seen corresponding path program 6 times [2019-12-07 18:22:57,183 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,183 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126519795] [2019-12-07 18:22:57,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,231 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,231 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126519795] [2019-12-07 18:22:57,232 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1729764052] [2019-12-07 18:22:57,232 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,254 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2019-12-07 18:22:57,254 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,254 INFO L264 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,255 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,258 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,258 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,258 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2019-12-07 18:22:57,259 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159837891] [2019-12-07 18:22:57,259 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,259 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 12 times [2019-12-07 18:22:57,259 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,259 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457845714] [2019-12-07 18:22:57,259 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,261 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,262 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:22:57,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:22:57,263 INFO L87 Difference]: Start difference. First operand 19 states and 28 transitions. cyclomatic complexity: 12 Second operand 9 states. [2019-12-07 18:22:57,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,298 INFO L93 Difference]: Finished difference Result 59 states and 71 transitions. [2019-12-07 18:22:57,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:22:57,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 71 transitions. [2019-12-07 18:22:57,300 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:57,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 58 states and 70 transitions. [2019-12-07 18:22:57,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:57,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:57,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 70 transitions. [2019-12-07 18:22:57,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,301 INFO L688 BuchiCegarLoop]: Abstraction has 58 states and 70 transitions. [2019-12-07 18:22:57,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 70 transitions. [2019-12-07 18:22:57,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 20. [2019-12-07 18:22:57,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-12-07 18:22:57,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 30 transitions. [2019-12-07 18:22:57,302 INFO L711 BuchiCegarLoop]: Abstraction has 20 states and 30 transitions. [2019-12-07 18:22:57,302 INFO L591 BuchiCegarLoop]: Abstraction has 20 states and 30 transitions. [2019-12-07 18:22:57,302 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:22:57,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 30 transitions. [2019-12-07 18:22:57,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,303 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [5, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:57,303 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,303 INFO L794 eck$LassoCheckResult]: Stem: 891#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 892#L12 main_~i~0 := 0; 893#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 896#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 897#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 901#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 910#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 909#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 908#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 907#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 898#L21-2 assume main_~j~0 >= 100; 895#L25 [2019-12-07 18:22:57,303 INFO L796 eck$LassoCheckResult]: Loop: 895#L25 assume true; 895#L25 [2019-12-07 18:22:57,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,303 INFO L82 PathProgramCache]: Analyzing trace with hash 830004344, now seen corresponding path program 5 times [2019-12-07 18:22:57,303 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230483214] [2019-12-07 18:22:57,304 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,335 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230483214] [2019-12-07 18:22:57,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [598617176] [2019-12-07 18:22:57,336 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,354 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2019-12-07 18:22:57,354 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,354 INFO L264 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 7 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,355 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,358 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,359 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,359 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2019-12-07 18:22:57,359 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740798005] [2019-12-07 18:22:57,359 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,359 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 13 times [2019-12-07 18:22:57,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310360080] [2019-12-07 18:22:57,360 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,361 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,363 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 18:22:57,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:22:57,363 INFO L87 Difference]: Start difference. First operand 20 states and 30 transitions. cyclomatic complexity: 13 Second operand 8 states. [2019-12-07 18:22:57,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,375 INFO L93 Difference]: Finished difference Result 22 states and 32 transitions. [2019-12-07 18:22:57,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:22:57,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 32 transitions. [2019-12-07 18:22:57,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 21 states and 31 transitions. [2019-12-07 18:22:57,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:57,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:57,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 31 transitions. [2019-12-07 18:22:57,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,376 INFO L688 BuchiCegarLoop]: Abstraction has 21 states and 31 transitions. [2019-12-07 18:22:57,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 31 transitions. [2019-12-07 18:22:57,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2019-12-07 18:22:57,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-12-07 18:22:57,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 31 transitions. [2019-12-07 18:22:57,377 INFO L711 BuchiCegarLoop]: Abstraction has 21 states and 31 transitions. [2019-12-07 18:22:57,377 INFO L591 BuchiCegarLoop]: Abstraction has 21 states and 31 transitions. [2019-12-07 18:22:57,377 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:22:57,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 31 transitions. [2019-12-07 18:22:57,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,378 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [7, 1, 1, 1, 1] [2019-12-07 18:22:57,378 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,378 INFO L794 eck$LassoCheckResult]: Stem: 974#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 975#L12 main_~i~0 := 0; 976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 983#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 994#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 992#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 990#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 988#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 986#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 977#L15-2 assume main_~i~0 >= 100; 978#L25 [2019-12-07 18:22:57,378 INFO L796 eck$LassoCheckResult]: Loop: 978#L25 assume true; 978#L25 [2019-12-07 18:22:57,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,378 INFO L82 PathProgramCache]: Analyzing trace with hash -618027695, now seen corresponding path program 7 times [2019-12-07 18:22:57,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355963040] [2019-12-07 18:22:57,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,418 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355963040] [2019-12-07 18:22:57,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [506968585] [2019-12-07 18:22:57,419 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,440 INFO L264 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,441 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,445 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2019-12-07 18:22:57,446 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494289166] [2019-12-07 18:22:57,446 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,447 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 14 times [2019-12-07 18:22:57,447 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,447 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147293047] [2019-12-07 18:22:57,447 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,449 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,451 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:22:57,451 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:22:57,451 INFO L87 Difference]: Start difference. First operand 21 states and 31 transitions. cyclomatic complexity: 13 Second operand 10 states. [2019-12-07 18:22:57,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,503 INFO L93 Difference]: Finished difference Result 70 states and 83 transitions. [2019-12-07 18:22:57,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:22:57,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 83 transitions. [2019-12-07 18:22:57,504 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:57,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 69 states and 82 transitions. [2019-12-07 18:22:57,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:57,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:57,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 82 transitions. [2019-12-07 18:22:57,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,506 INFO L688 BuchiCegarLoop]: Abstraction has 69 states and 82 transitions. [2019-12-07 18:22:57,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 82 transitions. [2019-12-07 18:22:57,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 22. [2019-12-07 18:22:57,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2019-12-07 18:22:57,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 33 transitions. [2019-12-07 18:22:57,507 INFO L711 BuchiCegarLoop]: Abstraction has 22 states and 33 transitions. [2019-12-07 18:22:57,508 INFO L591 BuchiCegarLoop]: Abstraction has 22 states and 33 transitions. [2019-12-07 18:22:57,508 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 18:22:57,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 33 transitions. [2019-12-07 18:22:57,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,509 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [6, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:57,509 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,509 INFO L794 eck$LassoCheckResult]: Stem: 1108#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1109#L12 main_~i~0 := 0; 1110#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1113#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 1114#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1118#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1129#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1128#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1127#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1126#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1125#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 1115#L21-2 assume main_~j~0 >= 100; 1112#L25 [2019-12-07 18:22:57,509 INFO L796 eck$LassoCheckResult]: Loop: 1112#L25 assume true; 1112#L25 [2019-12-07 18:22:57,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,509 INFO L82 PathProgramCache]: Analyzing trace with hash -39667402, now seen corresponding path program 6 times [2019-12-07 18:22:57,509 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,509 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782378624] [2019-12-07 18:22:57,509 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,545 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782378624] [2019-12-07 18:22:57,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1834124447] [2019-12-07 18:22:57,545 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,563 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2019-12-07 18:22:57,563 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,564 INFO L264 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,564 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,567 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,567 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,567 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2019-12-07 18:22:57,567 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326183450] [2019-12-07 18:22:57,568 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,568 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 15 times [2019-12-07 18:22:57,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,568 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534960571] [2019-12-07 18:22:57,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,569 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,571 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 18:22:57,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:22:57,571 INFO L87 Difference]: Start difference. First operand 22 states and 33 transitions. cyclomatic complexity: 14 Second operand 9 states. [2019-12-07 18:22:57,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,586 INFO L93 Difference]: Finished difference Result 24 states and 35 transitions. [2019-12-07 18:22:57,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:22:57,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24 states and 35 transitions. [2019-12-07 18:22:57,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24 states to 23 states and 34 transitions. [2019-12-07 18:22:57,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:57,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:57,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 34 transitions. [2019-12-07 18:22:57,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,588 INFO L688 BuchiCegarLoop]: Abstraction has 23 states and 34 transitions. [2019-12-07 18:22:57,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 34 transitions. [2019-12-07 18:22:57,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2019-12-07 18:22:57,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2019-12-07 18:22:57,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 34 transitions. [2019-12-07 18:22:57,589 INFO L711 BuchiCegarLoop]: Abstraction has 23 states and 34 transitions. [2019-12-07 18:22:57,589 INFO L591 BuchiCegarLoop]: Abstraction has 23 states and 34 transitions. [2019-12-07 18:22:57,589 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 18:22:57,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 34 transitions. [2019-12-07 18:22:57,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,590 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [8, 1, 1, 1, 1] [2019-12-07 18:22:57,590 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,590 INFO L794 eck$LassoCheckResult]: Stem: 1199#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1200#L12 main_~i~0 := 0; 1201#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1207#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1208#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1221#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1219#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1217#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1215#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1213#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1211#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1202#L15-2 assume main_~i~0 >= 100; 1203#L25 [2019-12-07 18:22:57,590 INFO L796 eck$LassoCheckResult]: Loop: 1203#L25 assume true; 1203#L25 [2019-12-07 18:22:57,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,590 INFO L82 PathProgramCache]: Analyzing trace with hash -1978987669, now seen corresponding path program 8 times [2019-12-07 18:22:57,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395204611] [2019-12-07 18:22:57,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,642 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395204611] [2019-12-07 18:22:57,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1622208899] [2019-12-07 18:22:57,642 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,659 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:57,659 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,660 INFO L264 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,661 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,665 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,666 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-12-07 18:22:57,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152115203] [2019-12-07 18:22:57,666 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,667 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 16 times [2019-12-07 18:22:57,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,667 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263876470] [2019-12-07 18:22:57,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,669 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:22:57,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:22:57,671 INFO L87 Difference]: Start difference. First operand 23 states and 34 transitions. cyclomatic complexity: 14 Second operand 11 states. [2019-12-07 18:22:57,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,711 INFO L93 Difference]: Finished difference Result 82 states and 96 transitions. [2019-12-07 18:22:57,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:22:57,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 96 transitions. [2019-12-07 18:22:57,712 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:57,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 81 states and 95 transitions. [2019-12-07 18:22:57,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:57,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:57,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 95 transitions. [2019-12-07 18:22:57,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,713 INFO L688 BuchiCegarLoop]: Abstraction has 81 states and 95 transitions. [2019-12-07 18:22:57,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 95 transitions. [2019-12-07 18:22:57,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 24. [2019-12-07 18:22:57,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-12-07 18:22:57,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 36 transitions. [2019-12-07 18:22:57,715 INFO L711 BuchiCegarLoop]: Abstraction has 24 states and 36 transitions. [2019-12-07 18:22:57,715 INFO L591 BuchiCegarLoop]: Abstraction has 24 states and 36 transitions. [2019-12-07 18:22:57,715 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 18:22:57,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 36 transitions. [2019-12-07 18:22:57,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,715 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [7, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:57,715 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,715 INFO L794 eck$LassoCheckResult]: Stem: 1351#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1352#L12 main_~i~0 := 0; 1353#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1356#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 1357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1374#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1373#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1372#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1371#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1369#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 1358#L21-2 assume main_~j~0 >= 100; 1355#L25 [2019-12-07 18:22:57,716 INFO L796 eck$LassoCheckResult]: Loop: 1355#L25 assume true; 1355#L25 [2019-12-07 18:22:57,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1229687752, now seen corresponding path program 7 times [2019-12-07 18:22:57,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,716 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464974385] [2019-12-07 18:22:57,716 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,753 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464974385] [2019-12-07 18:22:57,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1747703618] [2019-12-07 18:22:57,754 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,773 INFO L264 TraceCheckSpWp]: Trace formula consists of 53 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,774 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,777 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,777 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,777 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2019-12-07 18:22:57,777 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162777936] [2019-12-07 18:22:57,777 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,778 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 17 times [2019-12-07 18:22:57,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085573142] [2019-12-07 18:22:57,778 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,779 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:22:57,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:22:57,780 INFO L87 Difference]: Start difference. First operand 24 states and 36 transitions. cyclomatic complexity: 15 Second operand 10 states. [2019-12-07 18:22:57,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,792 INFO L93 Difference]: Finished difference Result 26 states and 38 transitions. [2019-12-07 18:22:57,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 18:22:57,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 38 transitions. [2019-12-07 18:22:57,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 25 states and 37 transitions. [2019-12-07 18:22:57,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:57,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:57,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 37 transitions. [2019-12-07 18:22:57,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,793 INFO L688 BuchiCegarLoop]: Abstraction has 25 states and 37 transitions. [2019-12-07 18:22:57,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 37 transitions. [2019-12-07 18:22:57,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-12-07 18:22:57,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-12-07 18:22:57,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 37 transitions. [2019-12-07 18:22:57,795 INFO L711 BuchiCegarLoop]: Abstraction has 25 states and 37 transitions. [2019-12-07 18:22:57,795 INFO L591 BuchiCegarLoop]: Abstraction has 25 states and 37 transitions. [2019-12-07 18:22:57,795 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 18:22:57,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 37 transitions. [2019-12-07 18:22:57,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,796 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [9, 1, 1, 1, 1] [2019-12-07 18:22:57,796 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,796 INFO L794 eck$LassoCheckResult]: Stem: 1450#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1451#L12 main_~i~0 := 0; 1452#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1458#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1459#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1474#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1472#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1470#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1468#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1466#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1464#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1462#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1453#L15-2 assume main_~i~0 >= 100; 1454#L25 [2019-12-07 18:22:57,796 INFO L796 eck$LassoCheckResult]: Loop: 1454#L25 assume true; 1454#L25 [2019-12-07 18:22:57,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,797 INFO L82 PathProgramCache]: Analyzing trace with hash -1219073903, now seen corresponding path program 9 times [2019-12-07 18:22:57,797 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,797 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103245428] [2019-12-07 18:22:57,797 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,847 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103245428] [2019-12-07 18:22:57,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1131683856] [2019-12-07 18:22:57,847 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,866 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2019-12-07 18:22:57,866 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,866 INFO L264 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,867 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:57,870 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,870 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:57,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2019-12-07 18:22:57,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131619770] [2019-12-07 18:22:57,870 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:57,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,871 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 18 times [2019-12-07 18:22:57,871 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,871 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292733439] [2019-12-07 18:22:57,871 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:57,872 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:57,874 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:57,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:22:57,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:22:57,874 INFO L87 Difference]: Start difference. First operand 25 states and 37 transitions. cyclomatic complexity: 15 Second operand 12 states. [2019-12-07 18:22:57,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:57,922 INFO L93 Difference]: Finished difference Result 95 states and 110 transitions. [2019-12-07 18:22:57,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:22:57,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 110 transitions. [2019-12-07 18:22:57,923 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:57,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 94 states and 109 transitions. [2019-12-07 18:22:57,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:57,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:57,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 109 transitions. [2019-12-07 18:22:57,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:57,924 INFO L688 BuchiCegarLoop]: Abstraction has 94 states and 109 transitions. [2019-12-07 18:22:57,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 109 transitions. [2019-12-07 18:22:57,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 26. [2019-12-07 18:22:57,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2019-12-07 18:22:57,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 39 transitions. [2019-12-07 18:22:57,926 INFO L711 BuchiCegarLoop]: Abstraction has 26 states and 39 transitions. [2019-12-07 18:22:57,926 INFO L591 BuchiCegarLoop]: Abstraction has 26 states and 39 transitions. [2019-12-07 18:22:57,926 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 18:22:57,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 39 transitions. [2019-12-07 18:22:57,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:57,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:57,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:57,927 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [8, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:57,927 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:57,927 INFO L794 eck$LassoCheckResult]: Stem: 1621#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1622#L12 main_~i~0 := 0; 1623#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1626#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 1627#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1631#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1646#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1645#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1644#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1643#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1642#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1641#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1640#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 1628#L21-2 assume main_~j~0 >= 100; 1625#L25 [2019-12-07 18:22:57,927 INFO L796 eck$LassoCheckResult]: Loop: 1625#L25 assume true; 1625#L25 [2019-12-07 18:22:57,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:57,927 INFO L82 PathProgramCache]: Analyzing trace with hash 534387062, now seen corresponding path program 8 times [2019-12-07 18:22:57,927 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:57,927 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842136016] [2019-12-07 18:22:57,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:57,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:57,971 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:57,971 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842136016] [2019-12-07 18:22:57,971 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [386587680] [2019-12-07 18:22:57,971 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:57,995 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:57,995 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:57,996 INFO L264 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 18:22:57,996 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,000 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,001 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,001 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-12-07 18:22:58,001 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134215942] [2019-12-07 18:22:58,001 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,001 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 19 times [2019-12-07 18:22:58,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131811048] [2019-12-07 18:22:58,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,003 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,004 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:22:58,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:22:58,004 INFO L87 Difference]: Start difference. First operand 26 states and 39 transitions. cyclomatic complexity: 16 Second operand 11 states. [2019-12-07 18:22:58,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,017 INFO L93 Difference]: Finished difference Result 28 states and 41 transitions. [2019-12-07 18:22:58,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 18:22:58,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 41 transitions. [2019-12-07 18:22:58,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 27 states and 40 transitions. [2019-12-07 18:22:58,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:58,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:58,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 40 transitions. [2019-12-07 18:22:58,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,018 INFO L688 BuchiCegarLoop]: Abstraction has 27 states and 40 transitions. [2019-12-07 18:22:58,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 40 transitions. [2019-12-07 18:22:58,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2019-12-07 18:22:58,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-12-07 18:22:58,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 40 transitions. [2019-12-07 18:22:58,020 INFO L711 BuchiCegarLoop]: Abstraction has 27 states and 40 transitions. [2019-12-07 18:22:58,020 INFO L591 BuchiCegarLoop]: Abstraction has 27 states and 40 transitions. [2019-12-07 18:22:58,020 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 18:22:58,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 40 transitions. [2019-12-07 18:22:58,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,020 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1] [2019-12-07 18:22:58,020 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,021 INFO L794 eck$LassoCheckResult]: Stem: 1728#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1729#L12 main_~i~0 := 0; 1730#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1736#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1737#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1754#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1752#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1750#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1748#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1746#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1744#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1742#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1740#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1731#L15-2 assume main_~i~0 >= 100; 1732#L25 [2019-12-07 18:22:58,021 INFO L796 eck$LassoCheckResult]: Loop: 1732#L25 assume true; 1732#L25 [2019-12-07 18:22:58,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,021 INFO L82 PathProgramCache]: Analyzing trace with hash 863416363, now seen corresponding path program 10 times [2019-12-07 18:22:58,021 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,021 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079868844] [2019-12-07 18:22:58,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,078 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,078 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079868844] [2019-12-07 18:22:58,079 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1283883722] [2019-12-07 18:22:58,079 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,096 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:22:58,096 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,096 INFO L264 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,097 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,101 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,101 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,101 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2019-12-07 18:22:58,101 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297986172] [2019-12-07 18:22:58,101 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,101 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 20 times [2019-12-07 18:22:58,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563998763] [2019-12-07 18:22:58,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,103 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,104 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:22:58,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:22:58,105 INFO L87 Difference]: Start difference. First operand 27 states and 40 transitions. cyclomatic complexity: 16 Second operand 13 states. [2019-12-07 18:22:58,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,152 INFO L93 Difference]: Finished difference Result 109 states and 125 transitions. [2019-12-07 18:22:58,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:22:58,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 125 transitions. [2019-12-07 18:22:58,153 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:58,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 108 states and 124 transitions. [2019-12-07 18:22:58,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:58,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:58,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 124 transitions. [2019-12-07 18:22:58,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,155 INFO L688 BuchiCegarLoop]: Abstraction has 108 states and 124 transitions. [2019-12-07 18:22:58,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 124 transitions. [2019-12-07 18:22:58,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 28. [2019-12-07 18:22:58,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2019-12-07 18:22:58,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 42 transitions. [2019-12-07 18:22:58,157 INFO L711 BuchiCegarLoop]: Abstraction has 28 states and 42 transitions. [2019-12-07 18:22:58,157 INFO L591 BuchiCegarLoop]: Abstraction has 28 states and 42 transitions. [2019-12-07 18:22:58,157 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 18:22:58,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 42 transitions. [2019-12-07 18:22:58,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,158 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [9, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:58,158 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,158 INFO L794 eck$LassoCheckResult]: Stem: 1919#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 1920#L12 main_~i~0 := 0; 1921#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 1924#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 1925#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1929#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1946#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1945#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1944#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1943#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1942#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1941#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1940#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 1939#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 1926#L21-2 assume main_~j~0 >= 100; 1923#L25 [2019-12-07 18:22:58,159 INFO L796 eck$LassoCheckResult]: Loop: 1923#L25 assume true; 1923#L25 [2019-12-07 18:22:58,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,159 INFO L82 PathProgramCache]: Analyzing trace with hash -613868552, now seen corresponding path program 9 times [2019-12-07 18:22:58,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497603312] [2019-12-07 18:22:58,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,214 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497603312] [2019-12-07 18:22:58,214 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [154718186] [2019-12-07 18:22:58,214 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,238 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2019-12-07 18:22:58,238 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,238 INFO L264 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,239 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,242 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,242 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,243 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2019-12-07 18:22:58,243 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709499161] [2019-12-07 18:22:58,243 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,243 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 21 times [2019-12-07 18:22:58,243 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,243 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808390059] [2019-12-07 18:22:58,243 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,245 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 18:22:58,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:22:58,248 INFO L87 Difference]: Start difference. First operand 28 states and 42 transitions. cyclomatic complexity: 17 Second operand 12 states. [2019-12-07 18:22:58,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,264 INFO L93 Difference]: Finished difference Result 30 states and 44 transitions. [2019-12-07 18:22:58,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:22:58,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 44 transitions. [2019-12-07 18:22:58,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 43 transitions. [2019-12-07 18:22:58,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:58,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:58,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 43 transitions. [2019-12-07 18:22:58,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,265 INFO L688 BuchiCegarLoop]: Abstraction has 29 states and 43 transitions. [2019-12-07 18:22:58,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 43 transitions. [2019-12-07 18:22:58,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2019-12-07 18:22:58,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-12-07 18:22:58,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 43 transitions. [2019-12-07 18:22:58,267 INFO L711 BuchiCegarLoop]: Abstraction has 29 states and 43 transitions. [2019-12-07 18:22:58,267 INFO L591 BuchiCegarLoop]: Abstraction has 29 states and 43 transitions. [2019-12-07 18:22:58,267 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-12-07 18:22:58,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 43 transitions. [2019-12-07 18:22:58,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,268 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [11, 1, 1, 1, 1] [2019-12-07 18:22:58,268 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,268 INFO L794 eck$LassoCheckResult]: Stem: 2034#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2035#L12 main_~i~0 := 0; 2036#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2042#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2043#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2050#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2048#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2046#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2037#L15-2 assume main_~i~0 >= 100; 2038#L25 [2019-12-07 18:22:58,268 INFO L796 eck$LassoCheckResult]: Loop: 2038#L25 assume true; 2038#L25 [2019-12-07 18:22:58,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,268 INFO L82 PathProgramCache]: Analyzing trace with hash 996105169, now seen corresponding path program 11 times [2019-12-07 18:22:58,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297517740] [2019-12-07 18:22:58,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,331 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297517740] [2019-12-07 18:22:58,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1291540082] [2019-12-07 18:22:58,331 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,351 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2019-12-07 18:22:58,351 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,352 INFO L264 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,352 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,358 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,358 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2019-12-07 18:22:58,358 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642691945] [2019-12-07 18:22:58,358 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,359 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 22 times [2019-12-07 18:22:58,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080861728] [2019-12-07 18:22:58,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,360 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,362 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:22:58,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:22:58,363 INFO L87 Difference]: Start difference. First operand 29 states and 43 transitions. cyclomatic complexity: 17 Second operand 14 states. [2019-12-07 18:22:58,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,420 INFO L93 Difference]: Finished difference Result 124 states and 141 transitions. [2019-12-07 18:22:58,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:22:58,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 141 transitions. [2019-12-07 18:22:58,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:58,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 123 states and 140 transitions. [2019-12-07 18:22:58,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:58,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:58,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 140 transitions. [2019-12-07 18:22:58,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,422 INFO L688 BuchiCegarLoop]: Abstraction has 123 states and 140 transitions. [2019-12-07 18:22:58,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 140 transitions. [2019-12-07 18:22:58,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 30. [2019-12-07 18:22:58,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-12-07 18:22:58,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 45 transitions. [2019-12-07 18:22:58,424 INFO L711 BuchiCegarLoop]: Abstraction has 30 states and 45 transitions. [2019-12-07 18:22:58,424 INFO L591 BuchiCegarLoop]: Abstraction has 30 states and 45 transitions. [2019-12-07 18:22:58,424 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-12-07 18:22:58,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 45 transitions. [2019-12-07 18:22:58,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,424 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:58,424 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,425 INFO L794 eck$LassoCheckResult]: Stem: 2246#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2247#L12 main_~i~0 := 0; 2248#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2251#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 2252#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2256#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2275#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2274#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2273#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2272#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2271#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2270#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2269#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2268#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2267#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 2253#L21-2 assume main_~j~0 >= 100; 2250#L25 [2019-12-07 18:22:58,425 INFO L796 eck$LassoCheckResult]: Loop: 2250#L25 assume true; 2250#L25 [2019-12-07 18:22:58,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,425 INFO L82 PathProgramCache]: Analyzing trace with hash -1850054218, now seen corresponding path program 10 times [2019-12-07 18:22:58,425 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509027204] [2019-12-07 18:22:58,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,481 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,481 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509027204] [2019-12-07 18:22:58,481 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1274453517] [2019-12-07 18:22:58,481 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,501 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:22:58,501 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,502 INFO L264 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,502 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,506 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,506 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2019-12-07 18:22:58,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047520254] [2019-12-07 18:22:58,506 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,506 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 23 times [2019-12-07 18:22:58,506 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,507 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279976075] [2019-12-07 18:22:58,507 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,508 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,509 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:22:58,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:22:58,510 INFO L87 Difference]: Start difference. First operand 30 states and 45 transitions. cyclomatic complexity: 18 Second operand 13 states. [2019-12-07 18:22:58,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,519 INFO L93 Difference]: Finished difference Result 32 states and 47 transitions. [2019-12-07 18:22:58,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:22:58,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 47 transitions. [2019-12-07 18:22:58,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 31 states and 46 transitions. [2019-12-07 18:22:58,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:58,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:58,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 46 transitions. [2019-12-07 18:22:58,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,520 INFO L688 BuchiCegarLoop]: Abstraction has 31 states and 46 transitions. [2019-12-07 18:22:58,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 46 transitions. [2019-12-07 18:22:58,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2019-12-07 18:22:58,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-12-07 18:22:58,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 46 transitions. [2019-12-07 18:22:58,521 INFO L711 BuchiCegarLoop]: Abstraction has 31 states and 46 transitions. [2019-12-07 18:22:58,521 INFO L591 BuchiCegarLoop]: Abstraction has 31 states and 46 transitions. [2019-12-07 18:22:58,521 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-12-07 18:22:58,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 46 transitions. [2019-12-07 18:22:58,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,522 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [12, 1, 1, 1, 1] [2019-12-07 18:22:58,522 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,522 INFO L794 eck$LassoCheckResult]: Stem: 2369#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2370#L12 main_~i~0 := 0; 2371#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2377#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2378#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2399#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2397#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2395#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2393#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2391#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2389#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2387#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2385#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2383#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2381#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2372#L15-2 assume main_~i~0 >= 100; 2373#L25 [2019-12-07 18:22:58,522 INFO L796 eck$LassoCheckResult]: Loop: 2373#L25 assume true; 2373#L25 [2019-12-07 18:22:58,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,522 INFO L82 PathProgramCache]: Analyzing trace with hash 814490859, now seen corresponding path program 12 times [2019-12-07 18:22:58,522 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,522 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557977838] [2019-12-07 18:22:58,522 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,595 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557977838] [2019-12-07 18:22:58,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [114929773] [2019-12-07 18:22:58,595 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,615 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2019-12-07 18:22:58,615 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,616 INFO L264 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,617 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,623 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,623 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,623 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2019-12-07 18:22:58,623 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464018054] [2019-12-07 18:22:58,623 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,624 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 24 times [2019-12-07 18:22:58,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452658523] [2019-12-07 18:22:58,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,625 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:22:58,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:22:58,628 INFO L87 Difference]: Start difference. First operand 31 states and 46 transitions. cyclomatic complexity: 18 Second operand 15 states. [2019-12-07 18:22:58,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,695 INFO L93 Difference]: Finished difference Result 140 states and 158 transitions. [2019-12-07 18:22:58,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:22:58,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 158 transitions. [2019-12-07 18:22:58,696 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:58,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 139 states and 157 transitions. [2019-12-07 18:22:58,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:58,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:58,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 157 transitions. [2019-12-07 18:22:58,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,697 INFO L688 BuchiCegarLoop]: Abstraction has 139 states and 157 transitions. [2019-12-07 18:22:58,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 157 transitions. [2019-12-07 18:22:58,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 32. [2019-12-07 18:22:58,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2019-12-07 18:22:58,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 48 transitions. [2019-12-07 18:22:58,699 INFO L711 BuchiCegarLoop]: Abstraction has 32 states and 48 transitions. [2019-12-07 18:22:58,699 INFO L591 BuchiCegarLoop]: Abstraction has 32 states and 48 transitions. [2019-12-07 18:22:58,699 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-12-07 18:22:58,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 48 transitions. [2019-12-07 18:22:58,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,700 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [11, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:58,700 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,701 INFO L794 eck$LassoCheckResult]: Stem: 2603#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2604#L12 main_~i~0 := 0; 2605#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2608#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 2609#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2613#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2634#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2633#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2632#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2631#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2630#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2629#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2628#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2627#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2626#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 2625#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 2610#L21-2 assume main_~j~0 >= 100; 2607#L25 [2019-12-07 18:22:58,701 INFO L796 eck$LassoCheckResult]: Loop: 2607#L25 assume true; 2607#L25 [2019-12-07 18:22:58,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,701 INFO L82 PathProgramCache]: Analyzing trace with hash -1517104200, now seen corresponding path program 11 times [2019-12-07 18:22:58,701 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,701 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344989166] [2019-12-07 18:22:58,701 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,769 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344989166] [2019-12-07 18:22:58,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [667703060] [2019-12-07 18:22:58,769 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,791 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2019-12-07 18:22:58,791 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:58,791 INFO L264 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,792 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,795 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,795 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,796 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2019-12-07 18:22:58,796 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202652747] [2019-12-07 18:22:58,796 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,796 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 25 times [2019-12-07 18:22:58,796 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,796 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339382858] [2019-12-07 18:22:58,796 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,797 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,800 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:22:58,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:22:58,801 INFO L87 Difference]: Start difference. First operand 32 states and 48 transitions. cyclomatic complexity: 19 Second operand 14 states. [2019-12-07 18:22:58,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,815 INFO L93 Difference]: Finished difference Result 34 states and 50 transitions. [2019-12-07 18:22:58,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 18:22:58,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 50 transitions. [2019-12-07 18:22:58,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 33 states and 49 transitions. [2019-12-07 18:22:58,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:58,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:58,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 49 transitions. [2019-12-07 18:22:58,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,817 INFO L688 BuchiCegarLoop]: Abstraction has 33 states and 49 transitions. [2019-12-07 18:22:58,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 49 transitions. [2019-12-07 18:22:58,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2019-12-07 18:22:58,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2019-12-07 18:22:58,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 49 transitions. [2019-12-07 18:22:58,818 INFO L711 BuchiCegarLoop]: Abstraction has 33 states and 49 transitions. [2019-12-07 18:22:58,818 INFO L591 BuchiCegarLoop]: Abstraction has 33 states and 49 transitions. [2019-12-07 18:22:58,818 INFO L424 BuchiCegarLoop]: ======== Iteration 27============ [2019-12-07 18:22:58,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 49 transitions. [2019-12-07 18:22:58,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:58,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:58,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:58,819 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [13, 1, 1, 1, 1] [2019-12-07 18:22:58,819 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:58,819 INFO L794 eck$LassoCheckResult]: Stem: 2734#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2735#L12 main_~i~0 := 0; 2736#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2742#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2743#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2766#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2764#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2762#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2760#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2758#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2756#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2754#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2752#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2750#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2748#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2746#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2737#L15-2 assume main_~i~0 >= 100; 2738#L25 [2019-12-07 18:22:58,819 INFO L796 eck$LassoCheckResult]: Loop: 2738#L25 assume true; 2738#L25 [2019-12-07 18:22:58,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,819 INFO L82 PathProgramCache]: Analyzing trace with hash -520585455, now seen corresponding path program 13 times [2019-12-07 18:22:58,819 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,819 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671355568] [2019-12-07 18:22:58,819 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,894 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,894 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671355568] [2019-12-07 18:22:58,894 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1825580633] [2019-12-07 18:22:58,894 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:58,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:58,914 INFO L264 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 18:22:58,915 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:58,919 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:58,919 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:58,919 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2019-12-07 18:22:58,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777584277] [2019-12-07 18:22:58,920 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:58,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:58,920 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 26 times [2019-12-07 18:22:58,920 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:58,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905240574] [2019-12-07 18:22:58,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:58,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:58,922 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:58,928 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:58,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:22:58,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:22:58,929 INFO L87 Difference]: Start difference. First operand 33 states and 49 transitions. cyclomatic complexity: 19 Second operand 16 states. [2019-12-07 18:22:58,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:58,996 INFO L93 Difference]: Finished difference Result 157 states and 176 transitions. [2019-12-07 18:22:58,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:22:58,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157 states and 176 transitions. [2019-12-07 18:22:58,997 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:58,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157 states to 156 states and 175 transitions. [2019-12-07 18:22:58,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:58,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:58,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156 states and 175 transitions. [2019-12-07 18:22:58,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:58,998 INFO L688 BuchiCegarLoop]: Abstraction has 156 states and 175 transitions. [2019-12-07 18:22:58,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states and 175 transitions. [2019-12-07 18:22:58,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 34. [2019-12-07 18:22:58,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2019-12-07 18:22:58,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 51 transitions. [2019-12-07 18:22:58,999 INFO L711 BuchiCegarLoop]: Abstraction has 34 states and 51 transitions. [2019-12-07 18:22:58,999 INFO L591 BuchiCegarLoop]: Abstraction has 34 states and 51 transitions. [2019-12-07 18:22:58,999 INFO L424 BuchiCegarLoop]: ======== Iteration 28============ [2019-12-07 18:22:58,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 51 transitions. [2019-12-07 18:22:59,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,000 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [12, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:59,000 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,000 INFO L794 eck$LassoCheckResult]: Stem: 2991#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 2992#L12 main_~i~0 := 0; 2993#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 2996#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 2997#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3001#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3024#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3023#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3022#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3021#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3020#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3019#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3018#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3017#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3016#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3015#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3014#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 2998#L21-2 assume main_~j~0 >= 100; 2995#L25 [2019-12-07 18:22:59,000 INFO L796 eck$LassoCheckResult]: Loop: 2995#L25 assume true; 2995#L25 [2019-12-07 18:22:59,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,000 INFO L82 PathProgramCache]: Analyzing trace with hash 214411766, now seen corresponding path program 12 times [2019-12-07 18:22:59,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777216463] [2019-12-07 18:22:59,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,069 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,069 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777216463] [2019-12-07 18:22:59,069 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [624059732] [2019-12-07 18:22:59,069 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,096 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2019-12-07 18:22:59,096 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:59,097 INFO L264 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 14 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,097 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,101 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,101 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2019-12-07 18:22:59,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644465845] [2019-12-07 18:22:59,102 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,102 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 27 times [2019-12-07 18:22:59,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999110765] [2019-12-07 18:22:59,103 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,104 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,106 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:22:59,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:22:59,106 INFO L87 Difference]: Start difference. First operand 34 states and 51 transitions. cyclomatic complexity: 20 Second operand 15 states. [2019-12-07 18:22:59,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:59,117 INFO L93 Difference]: Finished difference Result 36 states and 53 transitions. [2019-12-07 18:22:59,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 18:22:59,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 53 transitions. [2019-12-07 18:22:59,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 35 states and 52 transitions. [2019-12-07 18:22:59,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:59,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:59,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 52 transitions. [2019-12-07 18:22:59,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:59,118 INFO L688 BuchiCegarLoop]: Abstraction has 35 states and 52 transitions. [2019-12-07 18:22:59,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 52 transitions. [2019-12-07 18:22:59,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 35. [2019-12-07 18:22:59,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2019-12-07 18:22:59,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 52 transitions. [2019-12-07 18:22:59,119 INFO L711 BuchiCegarLoop]: Abstraction has 35 states and 52 transitions. [2019-12-07 18:22:59,119 INFO L591 BuchiCegarLoop]: Abstraction has 35 states and 52 transitions. [2019-12-07 18:22:59,119 INFO L424 BuchiCegarLoop]: ======== Iteration 29============ [2019-12-07 18:22:59,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 52 transitions. [2019-12-07 18:22:59,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,119 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [14, 1, 1, 1, 1] [2019-12-07 18:22:59,119 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,120 INFO L794 eck$LassoCheckResult]: Stem: 3130#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 3131#L12 main_~i~0 := 0; 3132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3139#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3142#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 3133#L15-2 assume main_~i~0 >= 100; 3134#L25 [2019-12-07 18:22:59,120 INFO L796 eck$LassoCheckResult]: Loop: 3134#L25 assume true; 3134#L25 [2019-12-07 18:22:59,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1041721771, now seen corresponding path program 14 times [2019-12-07 18:22:59,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,120 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413186659] [2019-12-07 18:22:59,120 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,208 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413186659] [2019-12-07 18:22:59,208 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1767723728] [2019-12-07 18:22:59,208 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,227 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:59,227 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:59,227 INFO L264 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 16 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,228 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,232 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,232 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,232 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2019-12-07 18:22:59,232 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151232597] [2019-12-07 18:22:59,232 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,232 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 28 times [2019-12-07 18:22:59,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889848314] [2019-12-07 18:22:59,233 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,234 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,235 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,235 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:22:59,235 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:22:59,236 INFO L87 Difference]: Start difference. First operand 35 states and 52 transitions. cyclomatic complexity: 20 Second operand 17 states. [2019-12-07 18:22:59,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:59,306 INFO L93 Difference]: Finished difference Result 175 states and 195 transitions. [2019-12-07 18:22:59,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:22:59,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175 states and 195 transitions. [2019-12-07 18:22:59,308 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:59,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175 states to 174 states and 194 transitions. [2019-12-07 18:22:59,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:59,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:59,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 194 transitions. [2019-12-07 18:22:59,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:59,309 INFO L688 BuchiCegarLoop]: Abstraction has 174 states and 194 transitions. [2019-12-07 18:22:59,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 194 transitions. [2019-12-07 18:22:59,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 36. [2019-12-07 18:22:59,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-12-07 18:22:59,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 54 transitions. [2019-12-07 18:22:59,311 INFO L711 BuchiCegarLoop]: Abstraction has 36 states and 54 transitions. [2019-12-07 18:22:59,311 INFO L591 BuchiCegarLoop]: Abstraction has 36 states and 54 transitions. [2019-12-07 18:22:59,311 INFO L424 BuchiCegarLoop]: ======== Iteration 30============ [2019-12-07 18:22:59,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 54 transitions. [2019-12-07 18:22:59,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,312 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [13, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:59,312 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,312 INFO L794 eck$LassoCheckResult]: Stem: 3411#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 3412#L12 main_~i~0 := 0; 3413#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 3416#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 3417#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3421#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3446#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3445#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3444#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3443#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3442#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3440#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3439#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3438#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3437#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3436#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3435#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 3418#L21-2 assume main_~j~0 >= 100; 3415#L25 [2019-12-07 18:22:59,312 INFO L796 eck$LassoCheckResult]: Loop: 3415#L25 assume true; 3415#L25 [2019-12-07 18:22:59,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1943168136, now seen corresponding path program 13 times [2019-12-07 18:22:59,312 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,312 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245724763] [2019-12-07 18:22:59,313 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,406 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245724763] [2019-12-07 18:22:59,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [664001996] [2019-12-07 18:22:59,406 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,431 INFO L264 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,432 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,436 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,437 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,437 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2019-12-07 18:22:59,437 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071980715] [2019-12-07 18:22:59,437 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,437 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 29 times [2019-12-07 18:22:59,438 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,438 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488442558] [2019-12-07 18:22:59,438 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,439 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,441 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 18:22:59,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2019-12-07 18:22:59,441 INFO L87 Difference]: Start difference. First operand 36 states and 54 transitions. cyclomatic complexity: 21 Second operand 16 states. [2019-12-07 18:22:59,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:59,471 INFO L93 Difference]: Finished difference Result 38 states and 56 transitions. [2019-12-07 18:22:59,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:22:59,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 56 transitions. [2019-12-07 18:22:59,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 37 states and 55 transitions. [2019-12-07 18:22:59,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:59,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:59,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 55 transitions. [2019-12-07 18:22:59,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:59,472 INFO L688 BuchiCegarLoop]: Abstraction has 37 states and 55 transitions. [2019-12-07 18:22:59,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 55 transitions. [2019-12-07 18:22:59,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2019-12-07 18:22:59,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-12-07 18:22:59,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 55 transitions. [2019-12-07 18:22:59,473 INFO L711 BuchiCegarLoop]: Abstraction has 37 states and 55 transitions. [2019-12-07 18:22:59,473 INFO L591 BuchiCegarLoop]: Abstraction has 37 states and 55 transitions. [2019-12-07 18:22:59,473 INFO L424 BuchiCegarLoop]: ======== Iteration 31============ [2019-12-07 18:22:59,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 55 transitions. [2019-12-07 18:22:59,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,473 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [15, 1, 1, 1, 1] [2019-12-07 18:22:59,473 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,474 INFO L794 eck$LassoCheckResult]: Stem: 3558#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 3559#L12 main_~i~0 := 0; 3560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3567#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3570#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 3561#L15-2 assume main_~i~0 >= 100; 3562#L25 [2019-12-07 18:22:59,474 INFO L796 eck$LassoCheckResult]: Loop: 3562#L25 assume true; 3562#L25 [2019-12-07 18:22:59,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,474 INFO L82 PathProgramCache]: Analyzing trace with hash -2066361775, now seen corresponding path program 15 times [2019-12-07 18:22:59,474 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,474 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295746559] [2019-12-07 18:22:59,474 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,567 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295746559] [2019-12-07 18:22:59,568 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1425107681] [2019-12-07 18:22:59,568 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,588 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-12-07 18:22:59,588 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:59,589 INFO L264 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,589 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,593 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,593 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,593 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2019-12-07 18:22:59,593 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786482765] [2019-12-07 18:22:59,593 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,593 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 30 times [2019-12-07 18:22:59,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101219918] [2019-12-07 18:22:59,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,594 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,596 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,596 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:22:59,596 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:22:59,596 INFO L87 Difference]: Start difference. First operand 37 states and 55 transitions. cyclomatic complexity: 21 Second operand 18 states. [2019-12-07 18:22:59,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:59,667 INFO L93 Difference]: Finished difference Result 194 states and 215 transitions. [2019-12-07 18:22:59,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:22:59,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 215 transitions. [2019-12-07 18:22:59,668 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:22:59,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 193 states and 214 transitions. [2019-12-07 18:22:59,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:22:59,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:22:59,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 214 transitions. [2019-12-07 18:22:59,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:59,670 INFO L688 BuchiCegarLoop]: Abstraction has 193 states and 214 transitions. [2019-12-07 18:22:59,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 214 transitions. [2019-12-07 18:22:59,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 38. [2019-12-07 18:22:59,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-12-07 18:22:59,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 57 transitions. [2019-12-07 18:22:59,671 INFO L711 BuchiCegarLoop]: Abstraction has 38 states and 57 transitions. [2019-12-07 18:22:59,671 INFO L591 BuchiCegarLoop]: Abstraction has 38 states and 57 transitions. [2019-12-07 18:22:59,671 INFO L424 BuchiCegarLoop]: ======== Iteration 32============ [2019-12-07 18:22:59,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 57 transitions. [2019-12-07 18:22:59,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,672 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [14, 1, 1, 1, 1, 1, 1] [2019-12-07 18:22:59,672 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,672 INFO L794 eck$LassoCheckResult]: Stem: 3864#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 3865#L12 main_~i~0 := 0; 3866#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 3869#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 3870#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3874#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3901#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3900#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3899#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3898#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3897#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3896#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3895#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3894#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3893#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3892#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3891#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3890#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 3889#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 3871#L21-2 assume main_~j~0 >= 100; 3868#L25 [2019-12-07 18:22:59,672 INFO L796 eck$LassoCheckResult]: Loop: 3868#L25 assume true; 3868#L25 [2019-12-07 18:22:59,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,672 INFO L82 PathProgramCache]: Analyzing trace with hash -108668362, now seen corresponding path program 14 times [2019-12-07 18:22:59,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213788128] [2019-12-07 18:22:59,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,758 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,758 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213788128] [2019-12-07 18:22:59,758 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2067122795] [2019-12-07 18:22:59,758 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,780 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:22:59,780 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:59,781 INFO L264 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 16 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,782 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,785 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,785 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,785 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2019-12-07 18:22:59,786 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968737916] [2019-12-07 18:22:59,786 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,786 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 31 times [2019-12-07 18:22:59,786 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037525707] [2019-12-07 18:22:59,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,788 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:22:59,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:22:59,789 INFO L87 Difference]: Start difference. First operand 38 states and 57 transitions. cyclomatic complexity: 22 Second operand 17 states. [2019-12-07 18:22:59,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:22:59,808 INFO L93 Difference]: Finished difference Result 40 states and 59 transitions. [2019-12-07 18:22:59,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:22:59,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 59 transitions. [2019-12-07 18:22:59,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 39 states and 58 transitions. [2019-12-07 18:22:59,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:22:59,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:22:59,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 58 transitions. [2019-12-07 18:22:59,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:22:59,809 INFO L688 BuchiCegarLoop]: Abstraction has 39 states and 58 transitions. [2019-12-07 18:22:59,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 58 transitions. [2019-12-07 18:22:59,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2019-12-07 18:22:59,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-12-07 18:22:59,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 58 transitions. [2019-12-07 18:22:59,810 INFO L711 BuchiCegarLoop]: Abstraction has 39 states and 58 transitions. [2019-12-07 18:22:59,810 INFO L591 BuchiCegarLoop]: Abstraction has 39 states and 58 transitions. [2019-12-07 18:22:59,810 INFO L424 BuchiCegarLoop]: ======== Iteration 33============ [2019-12-07 18:22:59,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 58 transitions. [2019-12-07 18:22:59,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:22:59,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:22:59,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:22:59,811 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [16, 1, 1, 1, 1] [2019-12-07 18:22:59,811 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:22:59,811 INFO L794 eck$LassoCheckResult]: Stem: 4019#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 4020#L12 main_~i~0 := 0; 4021#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4027#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4028#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4057#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4055#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4053#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4051#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4049#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4047#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4045#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4043#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4041#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4039#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4037#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4035#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4033#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4031#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 4022#L15-2 assume main_~i~0 >= 100; 4023#L25 [2019-12-07 18:22:59,811 INFO L796 eck$LassoCheckResult]: Loop: 4023#L25 assume true; 4023#L25 [2019-12-07 18:22:59,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,811 INFO L82 PathProgramCache]: Analyzing trace with hash 367296107, now seen corresponding path program 16 times [2019-12-07 18:22:59,811 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,811 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366839750] [2019-12-07 18:22:59,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:22:59,915 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,915 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366839750] [2019-12-07 18:22:59,915 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [917043357] [2019-12-07 18:22:59,915 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:22:59,934 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:22:59,934 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:22:59,935 INFO L264 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 18:22:59,935 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:22:59,938 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:22:59,939 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:22:59,939 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2019-12-07 18:22:59,939 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914219788] [2019-12-07 18:22:59,939 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:22:59,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:22:59,939 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 32 times [2019-12-07 18:22:59,939 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:22:59,939 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424224512] [2019-12-07 18:22:59,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:22:59,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:22:59,940 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:22:59,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:22:59,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:22:59,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:22:59,943 INFO L87 Difference]: Start difference. First operand 39 states and 58 transitions. cyclomatic complexity: 22 Second operand 19 states. [2019-12-07 18:23:00,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:00,019 INFO L93 Difference]: Finished difference Result 214 states and 236 transitions. [2019-12-07 18:23:00,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:23:00,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 214 states and 236 transitions. [2019-12-07 18:23:00,020 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:00,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 214 states to 213 states and 235 transitions. [2019-12-07 18:23:00,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:00,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:00,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 213 states and 235 transitions. [2019-12-07 18:23:00,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:00,022 INFO L688 BuchiCegarLoop]: Abstraction has 213 states and 235 transitions. [2019-12-07 18:23:00,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states and 235 transitions. [2019-12-07 18:23:00,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 40. [2019-12-07 18:23:00,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2019-12-07 18:23:00,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 60 transitions. [2019-12-07 18:23:00,024 INFO L711 BuchiCegarLoop]: Abstraction has 40 states and 60 transitions. [2019-12-07 18:23:00,024 INFO L591 BuchiCegarLoop]: Abstraction has 40 states and 60 transitions. [2019-12-07 18:23:00,024 INFO L424 BuchiCegarLoop]: ======== Iteration 34============ [2019-12-07 18:23:00,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 60 transitions. [2019-12-07 18:23:00,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:00,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:00,025 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [15, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:00,026 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:00,026 INFO L794 eck$LassoCheckResult]: Stem: 4351#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 4352#L12 main_~i~0 := 0; 4353#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 4356#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 4357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4390#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4389#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4388#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4387#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4386#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4385#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4384#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4383#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4382#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4381#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4379#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4378#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4377#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 4358#L21-2 assume main_~j~0 >= 100; 4355#L25 [2019-12-07 18:23:00,026 INFO L796 eck$LassoCheckResult]: Loop: 4355#L25 assume true; 4355#L25 [2019-12-07 18:23:00,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,026 INFO L82 PathProgramCache]: Analyzing trace with hash 926249784, now seen corresponding path program 15 times [2019-12-07 18:23:00,026 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,026 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163382253] [2019-12-07 18:23:00,026 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:00,127 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,127 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163382253] [2019-12-07 18:23:00,128 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1136143911] [2019-12-07 18:23:00,128 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:00,154 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-12-07 18:23:00,154 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:00,154 INFO L264 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 18:23:00,155 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:00,158 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,158 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:00,158 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2019-12-07 18:23:00,158 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223290889] [2019-12-07 18:23:00,158 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:00,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,159 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 33 times [2019-12-07 18:23:00,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578099390] [2019-12-07 18:23:00,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,160 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:00,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:00,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 18:23:00,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:23:00,162 INFO L87 Difference]: Start difference. First operand 40 states and 60 transitions. cyclomatic complexity: 23 Second operand 18 states. [2019-12-07 18:23:00,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:00,186 INFO L93 Difference]: Finished difference Result 42 states and 62 transitions. [2019-12-07 18:23:00,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 18:23:00,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 62 transitions. [2019-12-07 18:23:00,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 41 states and 61 transitions. [2019-12-07 18:23:00,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:00,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:00,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:00,188 INFO L688 BuchiCegarLoop]: Abstraction has 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2019-12-07 18:23:00,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 18:23:00,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L711 BuchiCegarLoop]: Abstraction has 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L591 BuchiCegarLoop]: Abstraction has 41 states and 61 transitions. [2019-12-07 18:23:00,188 INFO L424 BuchiCegarLoop]: ======== Iteration 35============ [2019-12-07 18:23:00,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 61 transitions. [2019-12-07 18:23:00,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:00,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:00,189 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [17, 1, 1, 1, 1] [2019-12-07 18:23:00,189 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:00,189 INFO L794 eck$LassoCheckResult]: Stem: 4514#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 4515#L12 main_~i~0 := 0; 4516#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4522#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4523#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4546#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4544#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4540#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4538#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4530#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4528#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4526#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 4517#L15-2 assume main_~i~0 >= 100; 4518#L25 [2019-12-07 18:23:00,189 INFO L796 eck$LassoCheckResult]: Loop: 4518#L25 assume true; 4518#L25 [2019-12-07 18:23:00,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,189 INFO L82 PathProgramCache]: Analyzing trace with hash -1498720879, now seen corresponding path program 17 times [2019-12-07 18:23:00,189 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457353235] [2019-12-07 18:23:00,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:00,305 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457353235] [2019-12-07 18:23:00,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1324718950] [2019-12-07 18:23:00,305 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:00,327 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2019-12-07 18:23:00,327 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:00,327 INFO L264 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 18:23:00,328 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:00,331 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:00,332 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2019-12-07 18:23:00,332 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945352061] [2019-12-07 18:23:00,332 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:00,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,332 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 34 times [2019-12-07 18:23:00,332 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,332 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222906089] [2019-12-07 18:23:00,332 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,333 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:00,336 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:00,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 18:23:00,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:23:00,336 INFO L87 Difference]: Start difference. First operand 41 states and 61 transitions. cyclomatic complexity: 23 Second operand 20 states. [2019-12-07 18:23:00,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:00,420 INFO L93 Difference]: Finished difference Result 235 states and 258 transitions. [2019-12-07 18:23:00,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:23:00,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235 states and 258 transitions. [2019-12-07 18:23:00,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:00,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235 states to 234 states and 257 transitions. [2019-12-07 18:23:00,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:00,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:00,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234 states and 257 transitions. [2019-12-07 18:23:00,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:00,427 INFO L688 BuchiCegarLoop]: Abstraction has 234 states and 257 transitions. [2019-12-07 18:23:00,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states and 257 transitions. [2019-12-07 18:23:00,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 42. [2019-12-07 18:23:00,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2019-12-07 18:23:00,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 63 transitions. [2019-12-07 18:23:00,429 INFO L711 BuchiCegarLoop]: Abstraction has 42 states and 63 transitions. [2019-12-07 18:23:00,429 INFO L591 BuchiCegarLoop]: Abstraction has 42 states and 63 transitions. [2019-12-07 18:23:00,429 INFO L424 BuchiCegarLoop]: ======== Iteration 36============ [2019-12-07 18:23:00,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 63 transitions. [2019-12-07 18:23:00,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:00,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:00,430 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [16, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:00,430 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:00,430 INFO L794 eck$LassoCheckResult]: Stem: 4873#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 4874#L12 main_~i~0 := 0; 4875#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 4878#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 4879#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4883#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4914#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4913#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4912#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4911#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4910#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4909#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4908#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4907#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4906#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4905#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4904#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4903#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4902#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4901#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 4900#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 4880#L21-2 assume main_~j~0 >= 100; 4877#L25 [2019-12-07 18:23:00,430 INFO L796 eck$LassoCheckResult]: Loop: 4877#L25 assume true; 4877#L25 [2019-12-07 18:23:00,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1351026058, now seen corresponding path program 16 times [2019-12-07 18:23:00,430 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621239588] [2019-12-07 18:23:00,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:00,540 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,540 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621239588] [2019-12-07 18:23:00,540 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1532373036] [2019-12-07 18:23:00,540 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:00,567 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:00,567 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:00,568 INFO L264 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 18:23:00,568 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:00,572 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,572 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:00,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2019-12-07 18:23:00,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206714980] [2019-12-07 18:23:00,572 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:00,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,572 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 35 times [2019-12-07 18:23:00,572 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,572 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363776468] [2019-12-07 18:23:00,572 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,573 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:00,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:00,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 18:23:00,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:23:00,575 INFO L87 Difference]: Start difference. First operand 42 states and 63 transitions. cyclomatic complexity: 24 Second operand 19 states. [2019-12-07 18:23:00,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:00,594 INFO L93 Difference]: Finished difference Result 44 states and 65 transitions. [2019-12-07 18:23:00,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:23:00,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 65 transitions. [2019-12-07 18:23:00,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 43 states and 64 transitions. [2019-12-07 18:23:00,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:00,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:00,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 64 transitions. [2019-12-07 18:23:00,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:00,595 INFO L688 BuchiCegarLoop]: Abstraction has 43 states and 64 transitions. [2019-12-07 18:23:00,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 64 transitions. [2019-12-07 18:23:00,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2019-12-07 18:23:00,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-12-07 18:23:00,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 64 transitions. [2019-12-07 18:23:00,596 INFO L711 BuchiCegarLoop]: Abstraction has 43 states and 64 transitions. [2019-12-07 18:23:00,596 INFO L591 BuchiCegarLoop]: Abstraction has 43 states and 64 transitions. [2019-12-07 18:23:00,596 INFO L424 BuchiCegarLoop]: ======== Iteration 37============ [2019-12-07 18:23:00,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 64 transitions. [2019-12-07 18:23:00,597 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:00,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:00,597 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [18, 1, 1, 1, 1] [2019-12-07 18:23:00,597 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:00,597 INFO L794 eck$LassoCheckResult]: Stem: 5044#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 5045#L12 main_~i~0 := 0; 5046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5053#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5056#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 5047#L15-2 assume main_~i~0 >= 100; 5048#L25 [2019-12-07 18:23:00,597 INFO L796 eck$LassoCheckResult]: Loop: 5048#L25 assume true; 5048#L25 [2019-12-07 18:23:00,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,597 INFO L82 PathProgramCache]: Analyzing trace with hash 784294699, now seen corresponding path program 18 times [2019-12-07 18:23:00,597 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,598 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474320394] [2019-12-07 18:23:00,598 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:00,719 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,720 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474320394] [2019-12-07 18:23:00,720 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1801573474] [2019-12-07 18:23:00,720 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:00,741 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2019-12-07 18:23:00,741 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:00,741 INFO L264 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 18:23:00,742 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:00,746 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,747 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:00,747 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2019-12-07 18:23:00,747 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544262140] [2019-12-07 18:23:00,747 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:00,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,748 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 36 times [2019-12-07 18:23:00,748 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,748 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870510802] [2019-12-07 18:23:00,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,749 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:00,751 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:00,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:23:00,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:23:00,751 INFO L87 Difference]: Start difference. First operand 43 states and 64 transitions. cyclomatic complexity: 24 Second operand 21 states. [2019-12-07 18:23:00,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:00,831 INFO L93 Difference]: Finished difference Result 257 states and 281 transitions. [2019-12-07 18:23:00,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:23:00,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 257 states and 281 transitions. [2019-12-07 18:23:00,832 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:00,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 257 states to 256 states and 280 transitions. [2019-12-07 18:23:00,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:00,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:00,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 280 transitions. [2019-12-07 18:23:00,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:00,833 INFO L688 BuchiCegarLoop]: Abstraction has 256 states and 280 transitions. [2019-12-07 18:23:00,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 280 transitions. [2019-12-07 18:23:00,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 44. [2019-12-07 18:23:00,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2019-12-07 18:23:00,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 66 transitions. [2019-12-07 18:23:00,835 INFO L711 BuchiCegarLoop]: Abstraction has 44 states and 66 transitions. [2019-12-07 18:23:00,835 INFO L591 BuchiCegarLoop]: Abstraction has 44 states and 66 transitions. [2019-12-07 18:23:00,835 INFO L424 BuchiCegarLoop]: ======== Iteration 38============ [2019-12-07 18:23:00,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 66 transitions. [2019-12-07 18:23:00,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:00,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:00,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:00,835 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [17, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:00,835 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:00,836 INFO L794 eck$LassoCheckResult]: Stem: 5431#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 5432#L12 main_~i~0 := 0; 5433#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 5436#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 5437#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5474#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5473#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5472#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5471#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5470#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5469#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5468#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5467#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5466#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5465#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5464#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5463#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5462#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5461#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5460#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 5459#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 5438#L21-2 assume main_~j~0 >= 100; 5435#L25 [2019-12-07 18:23:00,836 INFO L796 eck$LassoCheckResult]: Loop: 5435#L25 assume true; 5435#L25 [2019-12-07 18:23:00,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,836 INFO L82 PathProgramCache]: Analyzing trace with hash 1067866872, now seen corresponding path program 17 times [2019-12-07 18:23:00,836 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,836 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973710232] [2019-12-07 18:23:00,836 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:00,949 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,949 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973710232] [2019-12-07 18:23:00,950 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [116930130] [2019-12-07 18:23:00,950 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:00,975 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2019-12-07 18:23:00,975 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:00,976 INFO L264 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 18:23:00,976 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:00,979 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:00,979 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:00,979 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2019-12-07 18:23:00,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884945588] [2019-12-07 18:23:00,980 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:00,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:00,980 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 37 times [2019-12-07 18:23:00,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:00,980 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504226607] [2019-12-07 18:23:00,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:00,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:00,981 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:00,983 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:00,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 18:23:00,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:23:00,983 INFO L87 Difference]: Start difference. First operand 44 states and 66 transitions. cyclomatic complexity: 25 Second operand 20 states. [2019-12-07 18:23:01,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:01,008 INFO L93 Difference]: Finished difference Result 46 states and 68 transitions. [2019-12-07 18:23:01,009 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 18:23:01,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46 states and 68 transitions. [2019-12-07 18:23:01,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46 states to 45 states and 67 transitions. [2019-12-07 18:23:01,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:01,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:01,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 67 transitions. [2019-12-07 18:23:01,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:01,010 INFO L688 BuchiCegarLoop]: Abstraction has 45 states and 67 transitions. [2019-12-07 18:23:01,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 67 transitions. [2019-12-07 18:23:01,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2019-12-07 18:23:01,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-12-07 18:23:01,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 67 transitions. [2019-12-07 18:23:01,010 INFO L711 BuchiCegarLoop]: Abstraction has 45 states and 67 transitions. [2019-12-07 18:23:01,010 INFO L591 BuchiCegarLoop]: Abstraction has 45 states and 67 transitions. [2019-12-07 18:23:01,011 INFO L424 BuchiCegarLoop]: ======== Iteration 39============ [2019-12-07 18:23:01,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 67 transitions. [2019-12-07 18:23:01,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:01,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:01,011 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [19, 1, 1, 1, 1] [2019-12-07 18:23:01,011 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:01,011 INFO L794 eck$LassoCheckResult]: Stem: 5610#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 5611#L12 main_~i~0 := 0; 5612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5618#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5619#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5654#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5652#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5650#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5648#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5646#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5644#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5642#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5640#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5638#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5636#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5634#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5632#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5630#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5628#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5626#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5624#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5622#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 5613#L15-2 assume main_~i~0 >= 100; 5614#L25 [2019-12-07 18:23:01,011 INFO L796 eck$LassoCheckResult]: Loop: 5614#L25 assume true; 5614#L25 [2019-12-07 18:23:01,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,011 INFO L82 PathProgramCache]: Analyzing trace with hash -1456666415, now seen corresponding path program 19 times [2019-12-07 18:23:01,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,012 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105583469] [2019-12-07 18:23:01,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,146 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,146 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105583469] [2019-12-07 18:23:01,146 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [676768538] [2019-12-07 18:23:01,146 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:01,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,166 INFO L264 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 18:23:01,166 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:01,169 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,170 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:01,170 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2019-12-07 18:23:01,170 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799989445] [2019-12-07 18:23:01,170 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:01,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,170 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 38 times [2019-12-07 18:23:01,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,170 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006321653] [2019-12-07 18:23:01,170 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,171 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:01,173 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:01,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 18:23:01,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:23:01,173 INFO L87 Difference]: Start difference. First operand 45 states and 67 transitions. cyclomatic complexity: 25 Second operand 22 states. [2019-12-07 18:23:01,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:01,251 INFO L93 Difference]: Finished difference Result 280 states and 305 transitions. [2019-12-07 18:23:01,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:23:01,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280 states and 305 transitions. [2019-12-07 18:23:01,252 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:01,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280 states to 279 states and 304 transitions. [2019-12-07 18:23:01,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:01,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:01,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 279 states and 304 transitions. [2019-12-07 18:23:01,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:01,254 INFO L688 BuchiCegarLoop]: Abstraction has 279 states and 304 transitions. [2019-12-07 18:23:01,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states and 304 transitions. [2019-12-07 18:23:01,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 46. [2019-12-07 18:23:01,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2019-12-07 18:23:01,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 69 transitions. [2019-12-07 18:23:01,255 INFO L711 BuchiCegarLoop]: Abstraction has 46 states and 69 transitions. [2019-12-07 18:23:01,255 INFO L591 BuchiCegarLoop]: Abstraction has 46 states and 69 transitions. [2019-12-07 18:23:01,255 INFO L424 BuchiCegarLoop]: ======== Iteration 40============ [2019-12-07 18:23:01,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 69 transitions. [2019-12-07 18:23:01,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:01,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:01,256 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [18, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:01,256 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:01,256 INFO L794 eck$LassoCheckResult]: Stem: 6026#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 6027#L12 main_~i~0 := 0; 6028#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 6031#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 6032#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6036#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6071#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6070#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6069#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6068#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6067#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6066#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6065#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6064#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6063#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6062#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6061#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6060#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6059#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6058#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6057#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6056#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6055#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 6033#L21-2 assume main_~j~0 >= 100; 6030#L25 [2019-12-07 18:23:01,256 INFO L796 eck$LassoCheckResult]: Loop: 6030#L25 assume true; 6030#L25 [2019-12-07 18:23:01,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1255863626, now seen corresponding path program 18 times [2019-12-07 18:23:01,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,256 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928930148] [2019-12-07 18:23:01,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,387 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928930148] [2019-12-07 18:23:01,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [35043015] [2019-12-07 18:23:01,387 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:01,414 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2019-12-07 18:23:01,414 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:01,415 INFO L264 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 20 conjunts are in the unsatisfiable core [2019-12-07 18:23:01,416 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:01,419 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:01,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2019-12-07 18:23:01,419 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338411907] [2019-12-07 18:23:01,420 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:01,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,420 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 39 times [2019-12-07 18:23:01,420 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,420 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224715516] [2019-12-07 18:23:01,420 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,421 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:01,423 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:01,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:23:01,424 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:23:01,424 INFO L87 Difference]: Start difference. First operand 46 states and 69 transitions. cyclomatic complexity: 26 Second operand 21 states. [2019-12-07 18:23:01,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:01,445 INFO L93 Difference]: Finished difference Result 48 states and 71 transitions. [2019-12-07 18:23:01,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 18:23:01,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 71 transitions. [2019-12-07 18:23:01,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 47 states and 70 transitions. [2019-12-07 18:23:01,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:01,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:01,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 70 transitions. [2019-12-07 18:23:01,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:01,447 INFO L688 BuchiCegarLoop]: Abstraction has 47 states and 70 transitions. [2019-12-07 18:23:01,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 70 transitions. [2019-12-07 18:23:01,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2019-12-07 18:23:01,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2019-12-07 18:23:01,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 70 transitions. [2019-12-07 18:23:01,448 INFO L711 BuchiCegarLoop]: Abstraction has 47 states and 70 transitions. [2019-12-07 18:23:01,448 INFO L591 BuchiCegarLoop]: Abstraction has 47 states and 70 transitions. [2019-12-07 18:23:01,448 INFO L424 BuchiCegarLoop]: ======== Iteration 41============ [2019-12-07 18:23:01,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 70 transitions. [2019-12-07 18:23:01,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:01,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:01,449 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [20, 1, 1, 1, 1] [2019-12-07 18:23:01,449 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:01,449 INFO L794 eck$LassoCheckResult]: Stem: 6213#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 6214#L12 main_~i~0 := 0; 6215#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6221#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6222#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6259#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6257#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6255#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6253#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6251#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6249#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6247#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6245#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6243#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6241#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6239#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6237#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6235#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6233#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6231#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6229#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6227#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6225#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 6216#L15-2 assume main_~i~0 >= 100; 6217#L25 [2019-12-07 18:23:01,450 INFO L796 eck$LassoCheckResult]: Loop: 6217#L25 assume true; 6217#L25 [2019-12-07 18:23:01,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,450 INFO L82 PathProgramCache]: Analyzing trace with hash 2087983083, now seen corresponding path program 20 times [2019-12-07 18:23:01,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,450 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147875088] [2019-12-07 18:23:01,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,615 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,615 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147875088] [2019-12-07 18:23:01,615 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [309372504] [2019-12-07 18:23:01,615 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:01,635 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:01,635 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:01,636 INFO L264 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 18:23:01,636 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:01,640 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:01,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2019-12-07 18:23:01,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241128253] [2019-12-07 18:23:01,640 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:01,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,640 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 40 times [2019-12-07 18:23:01,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587275321] [2019-12-07 18:23:01,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,641 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:01,643 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:01,643 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:23:01,643 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:23:01,643 INFO L87 Difference]: Start difference. First operand 47 states and 70 transitions. cyclomatic complexity: 26 Second operand 23 states. [2019-12-07 18:23:01,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:01,722 INFO L93 Difference]: Finished difference Result 304 states and 330 transitions. [2019-12-07 18:23:01,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:23:01,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 330 transitions. [2019-12-07 18:23:01,724 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:01,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 303 states and 329 transitions. [2019-12-07 18:23:01,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:01,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:01,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 329 transitions. [2019-12-07 18:23:01,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:01,725 INFO L688 BuchiCegarLoop]: Abstraction has 303 states and 329 transitions. [2019-12-07 18:23:01,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 329 transitions. [2019-12-07 18:23:01,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 48. [2019-12-07 18:23:01,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2019-12-07 18:23:01,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 72 transitions. [2019-12-07 18:23:01,727 INFO L711 BuchiCegarLoop]: Abstraction has 48 states and 72 transitions. [2019-12-07 18:23:01,727 INFO L591 BuchiCegarLoop]: Abstraction has 48 states and 72 transitions. [2019-12-07 18:23:01,727 INFO L424 BuchiCegarLoop]: ======== Iteration 42============ [2019-12-07 18:23:01,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 72 transitions. [2019-12-07 18:23:01,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:01,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:01,727 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [19, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:01,727 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:01,728 INFO L794 eck$LassoCheckResult]: Stem: 6659#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 6660#L12 main_~i~0 := 0; 6661#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 6664#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 6665#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6669#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6706#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6704#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6703#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6702#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6700#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6699#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6698#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6697#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6696#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6695#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6694#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6693#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6692#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6691#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6690#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 6689#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 6666#L21-2 assume main_~j~0 >= 100; 6663#L25 [2019-12-07 18:23:01,728 INFO L796 eck$LassoCheckResult]: Loop: 6663#L25 assume true; 6663#L25 [2019-12-07 18:23:01,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,728 INFO L82 PathProgramCache]: Analyzing trace with hash -277065032, now seen corresponding path program 19 times [2019-12-07 18:23:01,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798939020] [2019-12-07 18:23:01,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,886 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,886 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798939020] [2019-12-07 18:23:01,886 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1192691830] [2019-12-07 18:23:01,886 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:01,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:01,945 INFO L264 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 18:23:01,945 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:01,949 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:01,949 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:01,949 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2019-12-07 18:23:01,949 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710865169] [2019-12-07 18:23:01,949 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:01,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,950 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 41 times [2019-12-07 18:23:01,950 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,950 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933272043] [2019-12-07 18:23:01,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:01,951 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:01,952 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:01,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 18:23:01,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2019-12-07 18:23:01,953 INFO L87 Difference]: Start difference. First operand 48 states and 72 transitions. cyclomatic complexity: 27 Second operand 22 states. [2019-12-07 18:23:01,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:01,974 INFO L93 Difference]: Finished difference Result 50 states and 74 transitions. [2019-12-07 18:23:01,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-07 18:23:01,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50 states and 74 transitions. [2019-12-07 18:23:01,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50 states to 49 states and 73 transitions. [2019-12-07 18:23:01,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:01,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:01,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 73 transitions. [2019-12-07 18:23:01,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:01,975 INFO L688 BuchiCegarLoop]: Abstraction has 49 states and 73 transitions. [2019-12-07 18:23:01,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 73 transitions. [2019-12-07 18:23:01,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2019-12-07 18:23:01,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2019-12-07 18:23:01,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 73 transitions. [2019-12-07 18:23:01,977 INFO L711 BuchiCegarLoop]: Abstraction has 49 states and 73 transitions. [2019-12-07 18:23:01,977 INFO L591 BuchiCegarLoop]: Abstraction has 49 states and 73 transitions. [2019-12-07 18:23:01,977 INFO L424 BuchiCegarLoop]: ======== Iteration 43============ [2019-12-07 18:23:01,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 73 transitions. [2019-12-07 18:23:01,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:01,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:01,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:01,977 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [21, 1, 1, 1, 1] [2019-12-07 18:23:01,977 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:01,977 INFO L794 eck$LassoCheckResult]: Stem: 6854#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 6855#L12 main_~i~0 := 0; 6856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6863#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6902#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6898#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6896#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6892#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6890#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6888#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6886#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6884#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6880#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6878#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6866#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 6857#L15-2 assume main_~i~0 >= 100; 6858#L25 [2019-12-07 18:23:01,977 INFO L796 eck$LassoCheckResult]: Loop: 6858#L25 assume true; 6858#L25 [2019-12-07 18:23:01,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:01,978 INFO L82 PathProgramCache]: Analyzing trace with hash 302967825, now seen corresponding path program 21 times [2019-12-07 18:23:01,978 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:01,978 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042908052] [2019-12-07 18:23:01,978 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:01,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:02,151 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,152 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042908052] [2019-12-07 18:23:02,152 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1724642060] [2019-12-07 18:23:02,152 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:02,176 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-12-07 18:23:02,176 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:02,177 INFO L264 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 18:23:02,177 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:02,181 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,181 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:02,181 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2019-12-07 18:23:02,181 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969033851] [2019-12-07 18:23:02,182 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:02,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,182 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 42 times [2019-12-07 18:23:02,182 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,182 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131222090] [2019-12-07 18:23:02,182 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,183 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:02,184 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:02,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:23:02,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:23:02,185 INFO L87 Difference]: Start difference. First operand 49 states and 73 transitions. cyclomatic complexity: 27 Second operand 24 states. [2019-12-07 18:23:02,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:02,272 INFO L93 Difference]: Finished difference Result 329 states and 356 transitions. [2019-12-07 18:23:02,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 18:23:02,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 356 transitions. [2019-12-07 18:23:02,274 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:02,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 328 states and 355 transitions. [2019-12-07 18:23:02,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:02,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:02,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328 states and 355 transitions. [2019-12-07 18:23:02,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:02,276 INFO L688 BuchiCegarLoop]: Abstraction has 328 states and 355 transitions. [2019-12-07 18:23:02,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states and 355 transitions. [2019-12-07 18:23:02,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 50. [2019-12-07 18:23:02,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2019-12-07 18:23:02,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 75 transitions. [2019-12-07 18:23:02,277 INFO L711 BuchiCegarLoop]: Abstraction has 50 states and 75 transitions. [2019-12-07 18:23:02,277 INFO L591 BuchiCegarLoop]: Abstraction has 50 states and 75 transitions. [2019-12-07 18:23:02,277 INFO L424 BuchiCegarLoop]: ======== Iteration 44============ [2019-12-07 18:23:02,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 75 transitions. [2019-12-07 18:23:02,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:02,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:02,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:02,278 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [20, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:02,278 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:02,278 INFO L794 eck$LassoCheckResult]: Stem: 7331#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 7332#L12 main_~i~0 := 0; 7333#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 7336#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 7337#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7341#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7379#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7378#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7377#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7376#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7375#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7374#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7373#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7372#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7371#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7369#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7368#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7367#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 7362#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 7338#L21-2 assume main_~j~0 >= 100; 7335#L25 [2019-12-07 18:23:02,278 INFO L796 eck$LassoCheckResult]: Loop: 7335#L25 assume true; 7335#L25 [2019-12-07 18:23:02,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,278 INFO L82 PathProgramCache]: Analyzing trace with hash 920310, now seen corresponding path program 20 times [2019-12-07 18:23:02,278 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,278 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308024381] [2019-12-07 18:23:02,279 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:02,435 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308024381] [2019-12-07 18:23:02,435 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [505317404] [2019-12-07 18:23:02,435 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:02,466 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:02,466 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:02,467 INFO L264 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 18:23:02,467 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:02,472 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,472 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:02,472 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2019-12-07 18:23:02,473 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58168727] [2019-12-07 18:23:02,473 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:02,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,473 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 43 times [2019-12-07 18:23:02,473 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,473 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086598078] [2019-12-07 18:23:02,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,474 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:02,476 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:02,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2019-12-07 18:23:02,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:23:02,476 INFO L87 Difference]: Start difference. First operand 50 states and 75 transitions. cyclomatic complexity: 28 Second operand 23 states. [2019-12-07 18:23:02,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:02,500 INFO L93 Difference]: Finished difference Result 52 states and 77 transitions. [2019-12-07 18:23:02,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:23:02,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 77 transitions. [2019-12-07 18:23:02,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:02,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 51 states and 76 transitions. [2019-12-07 18:23:02,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:02,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:02,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 76 transitions. [2019-12-07 18:23:02,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:02,501 INFO L688 BuchiCegarLoop]: Abstraction has 51 states and 76 transitions. [2019-12-07 18:23:02,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 76 transitions. [2019-12-07 18:23:02,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2019-12-07 18:23:02,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2019-12-07 18:23:02,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 76 transitions. [2019-12-07 18:23:02,502 INFO L711 BuchiCegarLoop]: Abstraction has 51 states and 76 transitions. [2019-12-07 18:23:02,502 INFO L591 BuchiCegarLoop]: Abstraction has 51 states and 76 transitions. [2019-12-07 18:23:02,502 INFO L424 BuchiCegarLoop]: ======== Iteration 45============ [2019-12-07 18:23:02,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 76 transitions. [2019-12-07 18:23:02,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:02,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:02,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:02,503 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1] [2019-12-07 18:23:02,503 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:02,503 INFO L794 eck$LassoCheckResult]: Stem: 7534#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 7535#L12 main_~i~0 := 0; 7536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7543#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7546#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 7537#L15-2 assume main_~i~0 >= 100; 7538#L25 [2019-12-07 18:23:02,503 INFO L796 eck$LassoCheckResult]: Loop: 7538#L25 assume true; 7538#L25 [2019-12-07 18:23:02,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,503 INFO L82 PathProgramCache]: Analyzing trace with hash 802069675, now seen corresponding path program 22 times [2019-12-07 18:23:02,503 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,503 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016309381] [2019-12-07 18:23:02,503 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:02,685 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,685 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016309381] [2019-12-07 18:23:02,686 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1718639379] [2019-12-07 18:23:02,686 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:02,711 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:02,711 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:02,712 INFO L264 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 18:23:02,712 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:02,717 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:02,717 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:02,717 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2019-12-07 18:23:02,717 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [392272741] [2019-12-07 18:23:02,717 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:02,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,718 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 44 times [2019-12-07 18:23:02,718 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,718 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434874095] [2019-12-07 18:23:02,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:02,719 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:02,721 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:02,721 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:23:02,721 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:23:02,721 INFO L87 Difference]: Start difference. First operand 51 states and 76 transitions. cyclomatic complexity: 28 Second operand 25 states. [2019-12-07 18:23:02,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:02,837 INFO L93 Difference]: Finished difference Result 355 states and 383 transitions. [2019-12-07 18:23:02,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:23:02,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355 states and 383 transitions. [2019-12-07 18:23:02,839 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:02,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355 states to 354 states and 382 transitions. [2019-12-07 18:23:02,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:02,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:02,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 382 transitions. [2019-12-07 18:23:02,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:02,841 INFO L688 BuchiCegarLoop]: Abstraction has 354 states and 382 transitions. [2019-12-07 18:23:02,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 382 transitions. [2019-12-07 18:23:02,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 52. [2019-12-07 18:23:02,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2019-12-07 18:23:02,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 78 transitions. [2019-12-07 18:23:02,842 INFO L711 BuchiCegarLoop]: Abstraction has 52 states and 78 transitions. [2019-12-07 18:23:02,842 INFO L591 BuchiCegarLoop]: Abstraction has 52 states and 78 transitions. [2019-12-07 18:23:02,842 INFO L424 BuchiCegarLoop]: ======== Iteration 46============ [2019-12-07 18:23:02,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 78 transitions. [2019-12-07 18:23:02,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:02,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:02,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:02,843 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [21, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:02,843 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:02,843 INFO L794 eck$LassoCheckResult]: Stem: 8043#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 8044#L12 main_~i~0 := 0; 8045#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 8048#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 8049#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8053#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8094#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8093#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8092#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8091#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8090#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8089#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8088#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8087#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8086#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8085#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8084#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8083#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8082#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8081#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8080#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8079#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8078#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8077#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8076#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8075#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 8050#L21-2 assume main_~j~0 >= 100; 8047#L25 [2019-12-07 18:23:02,843 INFO L796 eck$LassoCheckResult]: Loop: 8047#L25 assume true; 8047#L25 [2019-12-07 18:23:02,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:02,844 INFO L82 PathProgramCache]: Analyzing trace with hash 28531320, now seen corresponding path program 21 times [2019-12-07 18:23:02,844 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:02,844 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883453647] [2019-12-07 18:23:02,844 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:02,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:03,009 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,009 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883453647] [2019-12-07 18:23:03,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [446784408] [2019-12-07 18:23:03,010 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:03,041 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-12-07 18:23:03,041 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:03,042 INFO L264 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 18:23:03,042 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:03,046 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:03,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2019-12-07 18:23:03,046 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508790091] [2019-12-07 18:23:03,046 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:03,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,046 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 45 times [2019-12-07 18:23:03,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898421993] [2019-12-07 18:23:03,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,048 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:03,049 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:03,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 18:23:03,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2019-12-07 18:23:03,049 INFO L87 Difference]: Start difference. First operand 52 states and 78 transitions. cyclomatic complexity: 29 Second operand 24 states. [2019-12-07 18:23:03,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:03,078 INFO L93 Difference]: Finished difference Result 54 states and 80 transitions. [2019-12-07 18:23:03,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 18:23:03,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 80 transitions. [2019-12-07 18:23:03,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:03,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 79 transitions. [2019-12-07 18:23:03,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:03,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:03,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 79 transitions. [2019-12-07 18:23:03,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:03,079 INFO L688 BuchiCegarLoop]: Abstraction has 53 states and 79 transitions. [2019-12-07 18:23:03,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 79 transitions. [2019-12-07 18:23:03,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2019-12-07 18:23:03,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2019-12-07 18:23:03,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 79 transitions. [2019-12-07 18:23:03,080 INFO L711 BuchiCegarLoop]: Abstraction has 53 states and 79 transitions. [2019-12-07 18:23:03,080 INFO L591 BuchiCegarLoop]: Abstraction has 53 states and 79 transitions. [2019-12-07 18:23:03,081 INFO L424 BuchiCegarLoop]: ======== Iteration 47============ [2019-12-07 18:23:03,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 79 transitions. [2019-12-07 18:23:03,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:03,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:03,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:03,081 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [23, 1, 1, 1, 1] [2019-12-07 18:23:03,081 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:03,081 INFO L794 eck$LassoCheckResult]: Stem: 8254#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 8255#L12 main_~i~0 := 0; 8256#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8262#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8263#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8306#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8304#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8302#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8300#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8298#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8296#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8294#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8292#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8290#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8288#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8286#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8284#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8282#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8280#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8278#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8276#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8274#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8272#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8270#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8268#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8266#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 8257#L15-2 assume main_~i~0 >= 100; 8258#L25 [2019-12-07 18:23:03,081 INFO L796 eck$LassoCheckResult]: Loop: 8258#L25 assume true; 8258#L25 [2019-12-07 18:23:03,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,082 INFO L82 PathProgramCache]: Analyzing trace with hash -905642159, now seen corresponding path program 23 times [2019-12-07 18:23:03,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,082 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883158491] [2019-12-07 18:23:03,082 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:03,298 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,299 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883158491] [2019-12-07 18:23:03,299 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1710665881] [2019-12-07 18:23:03,299 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:03,330 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2019-12-07 18:23:03,330 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:03,331 INFO L264 TraceCheckSpWp]: Trace formula consists of 99 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 18:23:03,331 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:03,337 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,337 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:03,337 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2019-12-07 18:23:03,337 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128811070] [2019-12-07 18:23:03,338 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:03,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,338 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 46 times [2019-12-07 18:23:03,338 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,338 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369466711] [2019-12-07 18:23:03,338 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,339 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:03,341 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:03,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:23:03,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:23:03,341 INFO L87 Difference]: Start difference. First operand 53 states and 79 transitions. cyclomatic complexity: 29 Second operand 26 states. [2019-12-07 18:23:03,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:03,453 INFO L93 Difference]: Finished difference Result 382 states and 411 transitions. [2019-12-07 18:23:03,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:23:03,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 382 states and 411 transitions. [2019-12-07 18:23:03,455 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:03,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 382 states to 381 states and 410 transitions. [2019-12-07 18:23:03,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:03,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:03,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 381 states and 410 transitions. [2019-12-07 18:23:03,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:03,457 INFO L688 BuchiCegarLoop]: Abstraction has 381 states and 410 transitions. [2019-12-07 18:23:03,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states and 410 transitions. [2019-12-07 18:23:03,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 54. [2019-12-07 18:23:03,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2019-12-07 18:23:03,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 81 transitions. [2019-12-07 18:23:03,459 INFO L711 BuchiCegarLoop]: Abstraction has 54 states and 81 transitions. [2019-12-07 18:23:03,459 INFO L591 BuchiCegarLoop]: Abstraction has 54 states and 81 transitions. [2019-12-07 18:23:03,460 INFO L424 BuchiCegarLoop]: ======== Iteration 48============ [2019-12-07 18:23:03,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 81 transitions. [2019-12-07 18:23:03,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:03,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:03,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:03,460 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:03,460 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:03,461 INFO L794 eck$LassoCheckResult]: Stem: 8796#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 8797#L12 main_~i~0 := 0; 8798#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 8801#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 8802#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8806#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8849#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8848#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8847#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8846#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8845#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8844#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8843#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8842#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8841#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8840#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8839#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8838#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8837#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8836#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8835#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8834#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8833#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8832#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8831#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8830#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 8829#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 8803#L21-2 assume main_~j~0 >= 100; 8800#L25 [2019-12-07 18:23:03,461 INFO L796 eck$LassoCheckResult]: Loop: 8800#L25 assume true; 8800#L25 [2019-12-07 18:23:03,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,461 INFO L82 PathProgramCache]: Analyzing trace with hash 884472630, now seen corresponding path program 22 times [2019-12-07 18:23:03,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603936388] [2019-12-07 18:23:03,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:03,664 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603936388] [2019-12-07 18:23:03,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1867429247] [2019-12-07 18:23:03,664 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:03,694 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:03,694 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:03,695 INFO L264 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 18:23:03,696 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:03,702 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,702 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:03,702 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2019-12-07 18:23:03,702 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331673481] [2019-12-07 18:23:03,702 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:03,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,703 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 47 times [2019-12-07 18:23:03,703 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,703 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105575060] [2019-12-07 18:23:03,703 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,704 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:03,706 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:03,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2019-12-07 18:23:03,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2019-12-07 18:23:03,707 INFO L87 Difference]: Start difference. First operand 54 states and 81 transitions. cyclomatic complexity: 30 Second operand 25 states. [2019-12-07 18:23:03,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:03,734 INFO L93 Difference]: Finished difference Result 56 states and 83 transitions. [2019-12-07 18:23:03,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 18:23:03,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 83 transitions. [2019-12-07 18:23:03,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:03,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 55 states and 82 transitions. [2019-12-07 18:23:03,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:03,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:03,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 82 transitions. [2019-12-07 18:23:03,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:03,736 INFO L688 BuchiCegarLoop]: Abstraction has 55 states and 82 transitions. [2019-12-07 18:23:03,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 82 transitions. [2019-12-07 18:23:03,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2019-12-07 18:23:03,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2019-12-07 18:23:03,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 82 transitions. [2019-12-07 18:23:03,737 INFO L711 BuchiCegarLoop]: Abstraction has 55 states and 82 transitions. [2019-12-07 18:23:03,737 INFO L591 BuchiCegarLoop]: Abstraction has 55 states and 82 transitions. [2019-12-07 18:23:03,737 INFO L424 BuchiCegarLoop]: ======== Iteration 49============ [2019-12-07 18:23:03,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 82 transitions. [2019-12-07 18:23:03,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:03,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:03,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:03,738 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [24, 1, 1, 1, 1] [2019-12-07 18:23:03,738 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:03,738 INFO L794 eck$LassoCheckResult]: Stem: 9015#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 9016#L12 main_~i~0 := 0; 9017#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9023#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9024#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9069#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9067#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9065#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9063#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9061#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9059#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9057#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9055#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9053#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9051#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9049#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9047#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9045#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9043#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9041#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9039#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9037#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9035#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9033#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9031#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9029#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9027#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 9018#L15-2 assume main_~i~0 >= 100; 9019#L25 [2019-12-07 18:23:03,739 INFO L796 eck$LassoCheckResult]: Loop: 9019#L25 assume true; 9019#L25 [2019-12-07 18:23:03,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1989865835, now seen corresponding path program 24 times [2019-12-07 18:23:03,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288588880] [2019-12-07 18:23:03,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:03,956 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288588880] [2019-12-07 18:23:03,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [470172603] [2019-12-07 18:23:03,957 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:03,985 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2019-12-07 18:23:03,985 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:03,986 INFO L264 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 18:23:03,986 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:03,992 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:03,992 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:03,992 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2019-12-07 18:23:03,992 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737080405] [2019-12-07 18:23:03,992 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:03,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:03,992 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 48 times [2019-12-07 18:23:03,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:03,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220268448] [2019-12-07 18:23:03,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:03,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:03,994 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:03,995 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:03,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 18:23:03,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:23:03,996 INFO L87 Difference]: Start difference. First operand 55 states and 82 transitions. cyclomatic complexity: 30 Second operand 27 states. [2019-12-07 18:23:04,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:04,105 INFO L93 Difference]: Finished difference Result 410 states and 440 transitions. [2019-12-07 18:23:04,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:23:04,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 410 states and 440 transitions. [2019-12-07 18:23:04,107 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:04,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 410 states to 409 states and 439 transitions. [2019-12-07 18:23:04,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:04,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:04,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 409 states and 439 transitions. [2019-12-07 18:23:04,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:04,110 INFO L688 BuchiCegarLoop]: Abstraction has 409 states and 439 transitions. [2019-12-07 18:23:04,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 409 states and 439 transitions. [2019-12-07 18:23:04,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 409 to 56. [2019-12-07 18:23:04,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2019-12-07 18:23:04,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 84 transitions. [2019-12-07 18:23:04,112 INFO L711 BuchiCegarLoop]: Abstraction has 56 states and 84 transitions. [2019-12-07 18:23:04,112 INFO L591 BuchiCegarLoop]: Abstraction has 56 states and 84 transitions. [2019-12-07 18:23:04,112 INFO L424 BuchiCegarLoop]: ======== Iteration 50============ [2019-12-07 18:23:04,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 84 transitions. [2019-12-07 18:23:04,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:04,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:04,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:04,113 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [23, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:04,114 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:04,114 INFO L794 eck$LassoCheckResult]: Stem: 9591#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 9592#L12 main_~i~0 := 0; 9593#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 9596#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 9597#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9601#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9646#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9645#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9644#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9643#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9642#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9641#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9640#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9639#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9638#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9637#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9636#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9635#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9634#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9633#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9632#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9631#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9630#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9629#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9628#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9627#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9626#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 9625#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 9598#L21-2 assume main_~j~0 >= 100; 9595#L25 [2019-12-07 18:23:04,114 INFO L796 eck$LassoCheckResult]: Loop: 9595#L25 assume true; 9595#L25 [2019-12-07 18:23:04,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,114 INFO L82 PathProgramCache]: Analyzing trace with hash 1648849464, now seen corresponding path program 23 times [2019-12-07 18:23:04,114 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,115 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248870551] [2019-12-07 18:23:04,115 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:04,309 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,309 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248870551] [2019-12-07 18:23:04,309 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1297393136] [2019-12-07 18:23:04,309 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:04,341 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2019-12-07 18:23:04,341 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:04,342 INFO L264 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 18:23:04,343 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:04,346 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:04,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2019-12-07 18:23:04,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27717417] [2019-12-07 18:23:04,347 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:04,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,347 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 49 times [2019-12-07 18:23:04,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937138745] [2019-12-07 18:23:04,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,348 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:04,349 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:04,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2019-12-07 18:23:04,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:23:04,349 INFO L87 Difference]: Start difference. First operand 56 states and 84 transitions. cyclomatic complexity: 31 Second operand 26 states. [2019-12-07 18:23:04,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:04,369 INFO L93 Difference]: Finished difference Result 58 states and 86 transitions. [2019-12-07 18:23:04,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 18:23:04,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58 states and 86 transitions. [2019-12-07 18:23:04,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:04,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58 states to 57 states and 85 transitions. [2019-12-07 18:23:04,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:04,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:04,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 85 transitions. [2019-12-07 18:23:04,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:04,370 INFO L688 BuchiCegarLoop]: Abstraction has 57 states and 85 transitions. [2019-12-07 18:23:04,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 85 transitions. [2019-12-07 18:23:04,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2019-12-07 18:23:04,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2019-12-07 18:23:04,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 85 transitions. [2019-12-07 18:23:04,371 INFO L711 BuchiCegarLoop]: Abstraction has 57 states and 85 transitions. [2019-12-07 18:23:04,371 INFO L591 BuchiCegarLoop]: Abstraction has 57 states and 85 transitions. [2019-12-07 18:23:04,371 INFO L424 BuchiCegarLoop]: ======== Iteration 51============ [2019-12-07 18:23:04,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 85 transitions. [2019-12-07 18:23:04,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:04,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:04,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:04,372 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [25, 1, 1, 1, 1] [2019-12-07 18:23:04,372 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:04,372 INFO L794 eck$LassoCheckResult]: Stem: 9818#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 9819#L12 main_~i~0 := 0; 9820#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9826#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9827#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9866#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9864#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9860#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9858#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9846#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9844#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9840#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9838#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9834#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9832#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9830#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 9821#L15-2 assume main_~i~0 >= 100; 9822#L25 [2019-12-07 18:23:04,373 INFO L796 eck$LassoCheckResult]: Loop: 9822#L25 assume true; 9822#L25 [2019-12-07 18:23:04,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,373 INFO L82 PathProgramCache]: Analyzing trace with hash 1556300433, now seen corresponding path program 25 times [2019-12-07 18:23:04,373 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,373 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663178200] [2019-12-07 18:23:04,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:04,592 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,593 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663178200] [2019-12-07 18:23:04,593 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1974526167] [2019-12-07 18:23:04,593 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:04,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:04,614 INFO L264 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 18:23:04,615 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:04,620 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,620 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:04,620 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2019-12-07 18:23:04,620 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379835458] [2019-12-07 18:23:04,620 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:04,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,621 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 50 times [2019-12-07 18:23:04,621 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794881207] [2019-12-07 18:23:04,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,622 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:04,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:04,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 18:23:04,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:23:04,629 INFO L87 Difference]: Start difference. First operand 57 states and 85 transitions. cyclomatic complexity: 31 Second operand 28 states. [2019-12-07 18:23:04,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:04,741 INFO L93 Difference]: Finished difference Result 439 states and 470 transitions. [2019-12-07 18:23:04,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:23:04,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 439 states and 470 transitions. [2019-12-07 18:23:04,742 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:04,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 439 states to 438 states and 469 transitions. [2019-12-07 18:23:04,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:04,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:04,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 469 transitions. [2019-12-07 18:23:04,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:04,745 INFO L688 BuchiCegarLoop]: Abstraction has 438 states and 469 transitions. [2019-12-07 18:23:04,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 469 transitions. [2019-12-07 18:23:04,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 58. [2019-12-07 18:23:04,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2019-12-07 18:23:04,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 87 transitions. [2019-12-07 18:23:04,746 INFO L711 BuchiCegarLoop]: Abstraction has 58 states and 87 transitions. [2019-12-07 18:23:04,747 INFO L591 BuchiCegarLoop]: Abstraction has 58 states and 87 transitions. [2019-12-07 18:23:04,747 INFO L424 BuchiCegarLoop]: ======== Iteration 52============ [2019-12-07 18:23:04,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 87 transitions. [2019-12-07 18:23:04,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:04,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:04,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:04,747 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [24, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:04,747 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:04,747 INFO L794 eck$LassoCheckResult]: Stem: 10429#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 10430#L12 main_~i~0 := 0; 10431#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 10434#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 10435#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10439#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10486#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10485#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10484#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10483#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10482#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10481#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10480#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10479#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10478#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10477#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10476#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10475#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10474#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10473#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10472#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10471#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10470#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10469#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10468#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10467#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10466#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10465#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 10464#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 10436#L21-2 assume main_~j~0 >= 100; 10433#L25 [2019-12-07 18:23:04,748 INFO L796 eck$LassoCheckResult]: Loop: 10433#L25 assume true; 10433#L25 [2019-12-07 18:23:04,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,748 INFO L82 PathProgramCache]: Analyzing trace with hash -425272458, now seen corresponding path program 24 times [2019-12-07 18:23:04,748 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,748 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535290519] [2019-12-07 18:23:04,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:04,959 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,959 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535290519] [2019-12-07 18:23:04,959 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1488221541] [2019-12-07 18:23:04,959 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:04,989 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2019-12-07 18:23:04,989 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:04,990 INFO L264 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 18:23:04,990 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:04,994 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:04,994 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:04,994 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2019-12-07 18:23:04,994 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562922134] [2019-12-07 18:23:04,995 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:04,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:04,995 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 51 times [2019-12-07 18:23:04,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:04,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848650096] [2019-12-07 18:23:04,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:04,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:04,996 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:04,997 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:04,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 18:23:04,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2019-12-07 18:23:04,998 INFO L87 Difference]: Start difference. First operand 58 states and 87 transitions. cyclomatic complexity: 32 Second operand 27 states. [2019-12-07 18:23:05,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:05,033 INFO L93 Difference]: Finished difference Result 60 states and 89 transitions. [2019-12-07 18:23:05,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 18:23:05,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 89 transitions. [2019-12-07 18:23:05,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:05,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 59 states and 88 transitions. [2019-12-07 18:23:05,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:05,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:05,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59 states and 88 transitions. [2019-12-07 18:23:05,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:05,034 INFO L688 BuchiCegarLoop]: Abstraction has 59 states and 88 transitions. [2019-12-07 18:23:05,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states and 88 transitions. [2019-12-07 18:23:05,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2019-12-07 18:23:05,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2019-12-07 18:23:05,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 88 transitions. [2019-12-07 18:23:05,035 INFO L711 BuchiCegarLoop]: Abstraction has 59 states and 88 transitions. [2019-12-07 18:23:05,035 INFO L591 BuchiCegarLoop]: Abstraction has 59 states and 88 transitions. [2019-12-07 18:23:05,035 INFO L424 BuchiCegarLoop]: ======== Iteration 53============ [2019-12-07 18:23:05,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 88 transitions. [2019-12-07 18:23:05,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:05,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:05,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:05,035 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [26, 1, 1, 1, 1] [2019-12-07 18:23:05,035 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:05,035 INFO L794 eck$LassoCheckResult]: Stem: 10664#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 10665#L12 main_~i~0 := 0; 10666#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10672#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10673#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10722#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10720#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10718#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10716#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10714#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10712#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10710#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10708#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10706#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10704#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10702#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10700#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10698#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10696#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10694#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10692#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10690#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10688#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10686#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10684#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10682#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10680#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10678#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10676#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 10667#L15-2 assume main_~i~0 >= 100; 10668#L25 [2019-12-07 18:23:05,035 INFO L796 eck$LassoCheckResult]: Loop: 10668#L25 assume true; 10668#L25 [2019-12-07 18:23:05,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,036 INFO L82 PathProgramCache]: Analyzing trace with hash 1000674859, now seen corresponding path program 26 times [2019-12-07 18:23:05,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82122625] [2019-12-07 18:23:05,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:05,266 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82122625] [2019-12-07 18:23:05,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1117330127] [2019-12-07 18:23:05,266 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:05,289 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:05,289 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:05,290 INFO L264 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 28 conjunts are in the unsatisfiable core [2019-12-07 18:23:05,290 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:05,294 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,294 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:05,295 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2019-12-07 18:23:05,295 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [314984841] [2019-12-07 18:23:05,295 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:05,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,295 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 52 times [2019-12-07 18:23:05,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751533250] [2019-12-07 18:23:05,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,296 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:05,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:05,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 18:23:05,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:23:05,298 INFO L87 Difference]: Start difference. First operand 59 states and 88 transitions. cyclomatic complexity: 32 Second operand 29 states. [2019-12-07 18:23:05,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:05,409 INFO L93 Difference]: Finished difference Result 469 states and 501 transitions. [2019-12-07 18:23:05,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 18:23:05,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 469 states and 501 transitions. [2019-12-07 18:23:05,410 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:05,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 469 states to 468 states and 500 transitions. [2019-12-07 18:23:05,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:05,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:05,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 468 states and 500 transitions. [2019-12-07 18:23:05,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:05,412 INFO L688 BuchiCegarLoop]: Abstraction has 468 states and 500 transitions. [2019-12-07 18:23:05,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states and 500 transitions. [2019-12-07 18:23:05,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 60. [2019-12-07 18:23:05,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-12-07 18:23:05,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 90 transitions. [2019-12-07 18:23:05,414 INFO L711 BuchiCegarLoop]: Abstraction has 60 states and 90 transitions. [2019-12-07 18:23:05,414 INFO L591 BuchiCegarLoop]: Abstraction has 60 states and 90 transitions. [2019-12-07 18:23:05,414 INFO L424 BuchiCegarLoop]: ======== Iteration 54============ [2019-12-07 18:23:05,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 90 transitions. [2019-12-07 18:23:05,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:05,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:05,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:05,414 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [25, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:05,414 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:05,414 INFO L794 eck$LassoCheckResult]: Stem: 11311#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 11312#L12 main_~i~0 := 0; 11313#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 11316#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 11317#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11321#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11369#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11368#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11367#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11362#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11360#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11359#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11358#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11356#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11355#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11354#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11353#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11352#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11351#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11350#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11349#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11348#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 11347#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 11318#L21-2 assume main_~j~0 >= 100; 11315#L25 [2019-12-07 18:23:05,414 INFO L796 eck$LassoCheckResult]: Loop: 11315#L25 assume true; 11315#L25 [2019-12-07 18:23:05,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,415 INFO L82 PathProgramCache]: Analyzing trace with hash -298542600, now seen corresponding path program 25 times [2019-12-07 18:23:05,415 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,415 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877103827] [2019-12-07 18:23:05,415 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:05,627 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877103827] [2019-12-07 18:23:05,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [198496192] [2019-12-07 18:23:05,628 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:05,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:05,657 INFO L264 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 18:23:05,657 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:05,661 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,661 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:05,661 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2019-12-07 18:23:05,661 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931710659] [2019-12-07 18:23:05,661 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:05,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,662 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 53 times [2019-12-07 18:23:05,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499895750] [2019-12-07 18:23:05,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,663 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:05,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:05,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 18:23:05,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2019-12-07 18:23:05,665 INFO L87 Difference]: Start difference. First operand 60 states and 90 transitions. cyclomatic complexity: 33 Second operand 28 states. [2019-12-07 18:23:05,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:05,687 INFO L93 Difference]: Finished difference Result 62 states and 92 transitions. [2019-12-07 18:23:05,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-12-07 18:23:05,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 92 transitions. [2019-12-07 18:23:05,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:05,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 61 states and 91 transitions. [2019-12-07 18:23:05,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:05,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:05,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 91 transitions. [2019-12-07 18:23:05,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:05,688 INFO L688 BuchiCegarLoop]: Abstraction has 61 states and 91 transitions. [2019-12-07 18:23:05,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 91 transitions. [2019-12-07 18:23:05,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2019-12-07 18:23:05,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2019-12-07 18:23:05,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 91 transitions. [2019-12-07 18:23:05,689 INFO L711 BuchiCegarLoop]: Abstraction has 61 states and 91 transitions. [2019-12-07 18:23:05,689 INFO L591 BuchiCegarLoop]: Abstraction has 61 states and 91 transitions. [2019-12-07 18:23:05,689 INFO L424 BuchiCegarLoop]: ======== Iteration 55============ [2019-12-07 18:23:05,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 91 transitions. [2019-12-07 18:23:05,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:05,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:05,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:05,689 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [27, 1, 1, 1, 1] [2019-12-07 18:23:05,689 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:05,689 INFO L794 eck$LassoCheckResult]: Stem: 11554#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 11555#L12 main_~i~0 := 0; 11556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11563#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11610#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11608#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11566#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 11557#L15-2 assume main_~i~0 >= 100; 11558#L25 [2019-12-07 18:23:05,689 INFO L796 eck$LassoCheckResult]: Loop: 11558#L25 assume true; 11558#L25 [2019-12-07 18:23:05,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,690 INFO L82 PathProgramCache]: Analyzing trace with hash 956151249, now seen corresponding path program 27 times [2019-12-07 18:23:05,690 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,690 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606442014] [2019-12-07 18:23:05,690 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:05,936 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,937 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606442014] [2019-12-07 18:23:05,937 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [977116334] [2019-12-07 18:23:05,937 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:05,963 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-12-07 18:23:05,963 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:05,964 INFO L264 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 29 conjunts are in the unsatisfiable core [2019-12-07 18:23:05,964 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:05,968 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:05,969 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:05,969 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2019-12-07 18:23:05,969 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035657638] [2019-12-07 18:23:05,969 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:05,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:05,969 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 54 times [2019-12-07 18:23:05,969 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:05,969 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827974029] [2019-12-07 18:23:05,969 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:05,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:05,970 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:05,973 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:05,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 18:23:05,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:23:05,973 INFO L87 Difference]: Start difference. First operand 61 states and 91 transitions. cyclomatic complexity: 33 Second operand 30 states. [2019-12-07 18:23:06,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:06,096 INFO L93 Difference]: Finished difference Result 500 states and 533 transitions. [2019-12-07 18:23:06,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 18:23:06,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 500 states and 533 transitions. [2019-12-07 18:23:06,097 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:06,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 500 states to 499 states and 532 transitions. [2019-12-07 18:23:06,099 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:06,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:06,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 499 states and 532 transitions. [2019-12-07 18:23:06,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:06,100 INFO L688 BuchiCegarLoop]: Abstraction has 499 states and 532 transitions. [2019-12-07 18:23:06,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states and 532 transitions. [2019-12-07 18:23:06,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 62. [2019-12-07 18:23:06,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2019-12-07 18:23:06,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 93 transitions. [2019-12-07 18:23:06,103 INFO L711 BuchiCegarLoop]: Abstraction has 62 states and 93 transitions. [2019-12-07 18:23:06,103 INFO L591 BuchiCegarLoop]: Abstraction has 62 states and 93 transitions. [2019-12-07 18:23:06,103 INFO L424 BuchiCegarLoop]: ======== Iteration 56============ [2019-12-07 18:23:06,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 93 transitions. [2019-12-07 18:23:06,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:06,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:06,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:06,104 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [26, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:06,104 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:06,104 INFO L794 eck$LassoCheckResult]: Stem: 12238#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 12239#L12 main_~i~0 := 0; 12240#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 12243#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 12244#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12248#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12299#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12298#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12297#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12296#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12295#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12294#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12293#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12292#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12291#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12290#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12289#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12288#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12287#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12286#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12285#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12284#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12283#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12282#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12281#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12280#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12279#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12278#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12277#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12276#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 12275#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 12245#L21-2 assume main_~j~0 >= 100; 12242#L25 [2019-12-07 18:23:06,104 INFO L796 eck$LassoCheckResult]: Loop: 12242#L25 assume true; 12242#L25 [2019-12-07 18:23:06,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:06,105 INFO L82 PathProgramCache]: Analyzing trace with hash -664884298, now seen corresponding path program 26 times [2019-12-07 18:23:06,105 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:06,105 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193023848] [2019-12-07 18:23:06,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:06,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:06,354 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:06,354 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193023848] [2019-12-07 18:23:06,354 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1300892122] [2019-12-07 18:23:06,354 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:06,386 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:06,386 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:06,387 INFO L264 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 28 conjunts are in the unsatisfiable core [2019-12-07 18:23:06,387 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:06,391 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:06,391 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:06,391 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2019-12-07 18:23:06,391 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97210887] [2019-12-07 18:23:06,392 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:06,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:06,392 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 55 times [2019-12-07 18:23:06,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:06,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462374775] [2019-12-07 18:23:06,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:06,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:06,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:06,393 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:06,394 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:06,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 18:23:06,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2019-12-07 18:23:06,395 INFO L87 Difference]: Start difference. First operand 62 states and 93 transitions. cyclomatic complexity: 34 Second operand 29 states. [2019-12-07 18:23:06,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:06,426 INFO L93 Difference]: Finished difference Result 64 states and 95 transitions. [2019-12-07 18:23:06,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 18:23:06,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 95 transitions. [2019-12-07 18:23:06,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:06,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 63 states and 94 transitions. [2019-12-07 18:23:06,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:06,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:06,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 94 transitions. [2019-12-07 18:23:06,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:06,427 INFO L688 BuchiCegarLoop]: Abstraction has 63 states and 94 transitions. [2019-12-07 18:23:06,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 94 transitions. [2019-12-07 18:23:06,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2019-12-07 18:23:06,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2019-12-07 18:23:06,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 94 transitions. [2019-12-07 18:23:06,428 INFO L711 BuchiCegarLoop]: Abstraction has 63 states and 94 transitions. [2019-12-07 18:23:06,428 INFO L591 BuchiCegarLoop]: Abstraction has 63 states and 94 transitions. [2019-12-07 18:23:06,428 INFO L424 BuchiCegarLoop]: ======== Iteration 57============ [2019-12-07 18:23:06,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 94 transitions. [2019-12-07 18:23:06,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:06,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:06,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:06,428 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [28, 1, 1, 1, 1] [2019-12-07 18:23:06,428 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:06,428 INFO L794 eck$LassoCheckResult]: Stem: 12489#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 12490#L12 main_~i~0 := 0; 12491#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12497#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12498#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12551#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12549#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12547#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12545#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12543#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12541#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12539#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12537#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12535#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12533#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12531#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12529#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12527#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12525#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12523#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12521#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12519#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12517#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12515#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12513#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12511#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12509#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12507#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12505#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12503#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12501#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 12492#L15-2 assume main_~i~0 >= 100; 12493#L25 [2019-12-07 18:23:06,428 INFO L796 eck$LassoCheckResult]: Loop: 12493#L25 assume true; 12493#L25 [2019-12-07 18:23:06,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:06,429 INFO L82 PathProgramCache]: Analyzing trace with hash -424080661, now seen corresponding path program 28 times [2019-12-07 18:23:06,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:06,429 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345817124] [2019-12-07 18:23:06,429 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:06,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:06,723 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:06,723 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345817124] [2019-12-07 18:23:06,723 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [680435904] [2019-12-07 18:23:06,723 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:06,750 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:06,750 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:06,751 INFO L264 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 18:23:06,751 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:06,755 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:06,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:06,755 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2019-12-07 18:23:06,755 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809176812] [2019-12-07 18:23:06,755 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:06,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:06,756 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 56 times [2019-12-07 18:23:06,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:06,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082852539] [2019-12-07 18:23:06,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:06,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:06,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:06,757 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:06,758 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:06,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 18:23:06,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2019-12-07 18:23:06,759 INFO L87 Difference]: Start difference. First operand 63 states and 94 transitions. cyclomatic complexity: 34 Second operand 31 states. [2019-12-07 18:23:06,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:06,887 INFO L93 Difference]: Finished difference Result 532 states and 566 transitions. [2019-12-07 18:23:06,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:23:06,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 566 transitions. [2019-12-07 18:23:06,888 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:06,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 531 states and 565 transitions. [2019-12-07 18:23:06,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:06,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:06,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 531 states and 565 transitions. [2019-12-07 18:23:06,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:06,891 INFO L688 BuchiCegarLoop]: Abstraction has 531 states and 565 transitions. [2019-12-07 18:23:06,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states and 565 transitions. [2019-12-07 18:23:06,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 64. [2019-12-07 18:23:06,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2019-12-07 18:23:06,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 96 transitions. [2019-12-07 18:23:06,893 INFO L711 BuchiCegarLoop]: Abstraction has 64 states and 96 transitions. [2019-12-07 18:23:06,893 INFO L591 BuchiCegarLoop]: Abstraction has 64 states and 96 transitions. [2019-12-07 18:23:06,893 INFO L424 BuchiCegarLoop]: ======== Iteration 58============ [2019-12-07 18:23:06,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 96 transitions. [2019-12-07 18:23:06,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:06,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:06,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:06,893 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [27, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:06,893 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:06,894 INFO L794 eck$LassoCheckResult]: Stem: 13211#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 13212#L12 main_~i~0 := 0; 13213#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 13216#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 13217#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13221#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13274#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13273#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13272#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13271#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13270#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13269#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13268#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13267#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13266#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13265#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13264#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13263#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13262#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13261#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13260#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13259#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13258#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13257#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13256#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13255#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13254#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13253#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13252#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13251#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13250#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 13249#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 13218#L21-2 assume main_~j~0 >= 100; 13215#L25 [2019-12-07 18:23:06,894 INFO L796 eck$LassoCheckResult]: Loop: 13215#L25 assume true; 13215#L25 [2019-12-07 18:23:06,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:06,894 INFO L82 PathProgramCache]: Analyzing trace with hash 863424952, now seen corresponding path program 27 times [2019-12-07 18:23:06,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:06,894 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682240309] [2019-12-07 18:23:06,894 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:06,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:07,137 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682240309] [2019-12-07 18:23:07,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1987370503] [2019-12-07 18:23:07,137 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:07,169 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-12-07 18:23:07,170 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:07,170 INFO L264 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 29 conjunts are in the unsatisfiable core [2019-12-07 18:23:07,171 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:07,175 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:07,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2019-12-07 18:23:07,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766081520] [2019-12-07 18:23:07,175 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:07,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,176 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 57 times [2019-12-07 18:23:07,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505140746] [2019-12-07 18:23:07,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,177 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:07,178 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:07,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2019-12-07 18:23:07,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2019-12-07 18:23:07,179 INFO L87 Difference]: Start difference. First operand 64 states and 96 transitions. cyclomatic complexity: 35 Second operand 30 states. [2019-12-07 18:23:07,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:07,212 INFO L93 Difference]: Finished difference Result 66 states and 98 transitions. [2019-12-07 18:23:07,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 18:23:07,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 98 transitions. [2019-12-07 18:23:07,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:07,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 65 states and 97 transitions. [2019-12-07 18:23:07,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:07,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:07,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 97 transitions. [2019-12-07 18:23:07,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:07,213 INFO L688 BuchiCegarLoop]: Abstraction has 65 states and 97 transitions. [2019-12-07 18:23:07,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 97 transitions. [2019-12-07 18:23:07,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2019-12-07 18:23:07,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2019-12-07 18:23:07,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 97 transitions. [2019-12-07 18:23:07,214 INFO L711 BuchiCegarLoop]: Abstraction has 65 states and 97 transitions. [2019-12-07 18:23:07,214 INFO L591 BuchiCegarLoop]: Abstraction has 65 states and 97 transitions. [2019-12-07 18:23:07,214 INFO L424 BuchiCegarLoop]: ======== Iteration 59============ [2019-12-07 18:23:07,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 97 transitions. [2019-12-07 18:23:07,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:07,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:07,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:07,214 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [29, 1, 1, 1, 1] [2019-12-07 18:23:07,214 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:07,214 INFO L794 eck$LassoCheckResult]: Stem: 13470#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 13471#L12 main_~i~0 := 0; 13472#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13478#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13479#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13530#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13528#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13526#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13524#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13522#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13520#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13518#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13516#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13514#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13512#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13510#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13508#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13506#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13504#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13502#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13500#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13498#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13496#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13494#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13492#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13490#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13488#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13486#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13484#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13482#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 13473#L15-2 assume main_~i~0 >= 100; 13474#L25 [2019-12-07 18:23:07,214 INFO L796 eck$LassoCheckResult]: Loop: 13474#L25 assume true; 13474#L25 [2019-12-07 18:23:07,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,215 INFO L82 PathProgramCache]: Analyzing trace with hash -261596911, now seen corresponding path program 29 times [2019-12-07 18:23:07,215 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,215 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737038953] [2019-12-07 18:23:07,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:07,484 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,485 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737038953] [2019-12-07 18:23:07,485 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [768308240] [2019-12-07 18:23:07,485 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:07,511 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2019-12-07 18:23:07,511 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:07,512 INFO L264 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 18:23:07,513 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:07,517 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,517 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:07,517 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2019-12-07 18:23:07,517 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2104976013] [2019-12-07 18:23:07,517 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:07,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,518 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 58 times [2019-12-07 18:23:07,518 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,518 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592853448] [2019-12-07 18:23:07,518 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,519 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:07,520 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:07,521 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-12-07 18:23:07,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:23:07,521 INFO L87 Difference]: Start difference. First operand 65 states and 97 transitions. cyclomatic complexity: 35 Second operand 32 states. [2019-12-07 18:23:07,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:07,656 INFO L93 Difference]: Finished difference Result 565 states and 600 transitions. [2019-12-07 18:23:07,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:23:07,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 565 states and 600 transitions. [2019-12-07 18:23:07,657 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:07,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 565 states to 564 states and 599 transitions. [2019-12-07 18:23:07,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:07,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:07,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 564 states and 599 transitions. [2019-12-07 18:23:07,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:07,660 INFO L688 BuchiCegarLoop]: Abstraction has 564 states and 599 transitions. [2019-12-07 18:23:07,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 564 states and 599 transitions. [2019-12-07 18:23:07,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 564 to 66. [2019-12-07 18:23:07,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2019-12-07 18:23:07,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 99 transitions. [2019-12-07 18:23:07,662 INFO L711 BuchiCegarLoop]: Abstraction has 66 states and 99 transitions. [2019-12-07 18:23:07,662 INFO L591 BuchiCegarLoop]: Abstraction has 66 states and 99 transitions. [2019-12-07 18:23:07,662 INFO L424 BuchiCegarLoop]: ======== Iteration 60============ [2019-12-07 18:23:07,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 99 transitions. [2019-12-07 18:23:07,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:07,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:07,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:07,662 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [28, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:07,662 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:07,662 INFO L794 eck$LassoCheckResult]: Stem: 14231#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 14232#L12 main_~i~0 := 0; 14233#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 14236#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 14237#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14241#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14296#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14295#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14294#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14293#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14292#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14291#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14290#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14289#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14288#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14287#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14286#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14285#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14284#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14283#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14282#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14281#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14280#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14279#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14278#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14277#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14276#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14275#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14274#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14273#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14272#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14271#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 14270#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 14238#L21-2 assume main_~j~0 >= 100; 14235#L25 [2019-12-07 18:23:07,662 INFO L796 eck$LassoCheckResult]: Loop: 14235#L25 assume true; 14235#L25 [2019-12-07 18:23:07,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,663 INFO L82 PathProgramCache]: Analyzing trace with hash 996371446, now seen corresponding path program 28 times [2019-12-07 18:23:07,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,663 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952227735] [2019-12-07 18:23:07,663 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:07,921 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,922 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952227735] [2019-12-07 18:23:07,922 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [798724064] [2019-12-07 18:23:07,922 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:07,948 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:07,949 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:07,949 INFO L264 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 18:23:07,950 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:07,954 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:07,954 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:07,954 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2019-12-07 18:23:07,954 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315612392] [2019-12-07 18:23:07,954 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:07,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,954 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 59 times [2019-12-07 18:23:07,955 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,955 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184266218] [2019-12-07 18:23:07,955 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:07,955 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:07,957 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:07,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2019-12-07 18:23:07,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2019-12-07 18:23:07,958 INFO L87 Difference]: Start difference. First operand 66 states and 99 transitions. cyclomatic complexity: 36 Second operand 31 states. [2019-12-07 18:23:07,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:07,992 INFO L93 Difference]: Finished difference Result 68 states and 101 transitions. [2019-12-07 18:23:07,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:23:07,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 101 transitions. [2019-12-07 18:23:07,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:07,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 67 states and 100 transitions. [2019-12-07 18:23:07,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:07,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:07,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 100 transitions. [2019-12-07 18:23:07,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:07,993 INFO L688 BuchiCegarLoop]: Abstraction has 67 states and 100 transitions. [2019-12-07 18:23:07,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 100 transitions. [2019-12-07 18:23:07,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2019-12-07 18:23:07,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2019-12-07 18:23:07,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 100 transitions. [2019-12-07 18:23:07,994 INFO L711 BuchiCegarLoop]: Abstraction has 67 states and 100 transitions. [2019-12-07 18:23:07,994 INFO L591 BuchiCegarLoop]: Abstraction has 67 states and 100 transitions. [2019-12-07 18:23:07,994 INFO L424 BuchiCegarLoop]: ======== Iteration 61============ [2019-12-07 18:23:07,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 100 transitions. [2019-12-07 18:23:07,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:07,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:07,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:07,994 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [30, 1, 1, 1, 1] [2019-12-07 18:23:07,994 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:07,994 INFO L794 eck$LassoCheckResult]: Stem: 14498#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 14499#L12 main_~i~0 := 0; 14500#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14506#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14507#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14546#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14544#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14540#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14538#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14530#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14528#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14526#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14524#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14522#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14520#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14518#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14516#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14514#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14512#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14510#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 14501#L15-2 assume main_~i~0 >= 100; 14502#L25 [2019-12-07 18:23:07,994 INFO L796 eck$LassoCheckResult]: Loop: 14502#L25 assume true; 14502#L25 [2019-12-07 18:23:07,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:07,995 INFO L82 PathProgramCache]: Analyzing trace with hash 480432043, now seen corresponding path program 30 times [2019-12-07 18:23:07,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:07,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455399380] [2019-12-07 18:23:07,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:07,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:08,293 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:08,293 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455399380] [2019-12-07 18:23:08,293 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [337545593] [2019-12-07 18:23:08,293 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:08,322 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2019-12-07 18:23:08,322 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:08,323 INFO L264 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 32 conjunts are in the unsatisfiable core [2019-12-07 18:23:08,323 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:08,327 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:08,327 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:08,328 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2019-12-07 18:23:08,328 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045926780] [2019-12-07 18:23:08,328 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:08,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:08,328 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 60 times [2019-12-07 18:23:08,328 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:08,328 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709952388] [2019-12-07 18:23:08,328 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:08,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:08,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:08,329 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:08,330 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:08,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 18:23:08,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:23:08,331 INFO L87 Difference]: Start difference. First operand 67 states and 100 transitions. cyclomatic complexity: 36 Second operand 33 states. [2019-12-07 18:23:08,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:08,446 INFO L93 Difference]: Finished difference Result 599 states and 635 transitions. [2019-12-07 18:23:08,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:23:08,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 599 states and 635 transitions. [2019-12-07 18:23:08,448 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:08,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 599 states to 598 states and 634 transitions. [2019-12-07 18:23:08,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:08,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:08,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 598 states and 634 transitions. [2019-12-07 18:23:08,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:08,450 INFO L688 BuchiCegarLoop]: Abstraction has 598 states and 634 transitions. [2019-12-07 18:23:08,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states and 634 transitions. [2019-12-07 18:23:08,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 68. [2019-12-07 18:23:08,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2019-12-07 18:23:08,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 102 transitions. [2019-12-07 18:23:08,452 INFO L711 BuchiCegarLoop]: Abstraction has 68 states and 102 transitions. [2019-12-07 18:23:08,452 INFO L591 BuchiCegarLoop]: Abstraction has 68 states and 102 transitions. [2019-12-07 18:23:08,452 INFO L424 BuchiCegarLoop]: ======== Iteration 62============ [2019-12-07 18:23:08,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 102 transitions. [2019-12-07 18:23:08,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:08,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:08,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:08,453 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [29, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:08,453 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:08,453 INFO L794 eck$LassoCheckResult]: Stem: 15299#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 15300#L12 main_~i~0 := 0; 15301#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 15304#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 15305#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15309#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15362#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15360#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15359#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15358#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15356#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15355#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15354#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15353#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15352#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15351#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15350#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15349#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15348#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15347#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15346#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15345#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15344#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15343#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15342#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15341#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15340#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 15339#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 15306#L21-2 assume main_~j~0 >= 100; 15303#L25 [2019-12-07 18:23:08,453 INFO L796 eck$LassoCheckResult]: Loop: 15303#L25 assume true; 15303#L25 [2019-12-07 18:23:08,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:08,453 INFO L82 PathProgramCache]: Analyzing trace with hash 822745464, now seen corresponding path program 29 times [2019-12-07 18:23:08,453 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:08,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024961480] [2019-12-07 18:23:08,453 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:08,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:08,725 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:08,725 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024961480] [2019-12-07 18:23:08,726 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1692676355] [2019-12-07 18:23:08,726 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:08,760 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2019-12-07 18:23:08,760 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:08,761 INFO L264 TraceCheckSpWp]: Trace formula consists of 185 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 18:23:08,762 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:08,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:08,766 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2019-12-07 18:23:08,766 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195944630] [2019-12-07 18:23:08,766 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:08,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:08,766 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 61 times [2019-12-07 18:23:08,766 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:08,766 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744509065] [2019-12-07 18:23:08,766 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:08,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:08,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:08,767 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:08,768 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:08,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-12-07 18:23:08,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:23:08,769 INFO L87 Difference]: Start difference. First operand 68 states and 102 transitions. cyclomatic complexity: 37 Second operand 32 states. [2019-12-07 18:23:08,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:08,805 INFO L93 Difference]: Finished difference Result 70 states and 104 transitions. [2019-12-07 18:23:08,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:23:08,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 104 transitions. [2019-12-07 18:23:08,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:08,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 69 states and 103 transitions. [2019-12-07 18:23:08,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:08,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:08,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 103 transitions. [2019-12-07 18:23:08,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:08,806 INFO L688 BuchiCegarLoop]: Abstraction has 69 states and 103 transitions. [2019-12-07 18:23:08,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 103 transitions. [2019-12-07 18:23:08,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2019-12-07 18:23:08,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2019-12-07 18:23:08,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 103 transitions. [2019-12-07 18:23:08,807 INFO L711 BuchiCegarLoop]: Abstraction has 69 states and 103 transitions. [2019-12-07 18:23:08,807 INFO L591 BuchiCegarLoop]: Abstraction has 69 states and 103 transitions. [2019-12-07 18:23:08,807 INFO L424 BuchiCegarLoop]: ======== Iteration 63============ [2019-12-07 18:23:08,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 103 transitions. [2019-12-07 18:23:08,807 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:08,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:08,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:08,808 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [31, 1, 1, 1, 1] [2019-12-07 18:23:08,808 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:08,808 INFO L794 eck$LassoCheckResult]: Stem: 15574#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 15575#L12 main_~i~0 := 0; 15576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15583#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15642#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15640#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15638#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15636#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15634#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15632#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15630#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15628#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15626#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15624#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15622#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15620#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15618#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15616#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15610#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15608#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15586#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 15577#L15-2 assume main_~i~0 >= 100; 15578#L25 [2019-12-07 18:23:08,808 INFO L796 eck$LassoCheckResult]: Loop: 15578#L25 assume true; 15578#L25 [2019-12-07 18:23:08,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:08,808 INFO L82 PathProgramCache]: Analyzing trace with hash 2008493137, now seen corresponding path program 31 times [2019-12-07 18:23:08,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:08,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112295646] [2019-12-07 18:23:08,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:08,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:09,111 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:09,112 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112295646] [2019-12-07 18:23:09,112 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [726764705] [2019-12-07 18:23:09,112 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:09,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:09,136 INFO L264 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 18:23:09,136 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:09,140 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:09,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:09,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2019-12-07 18:23:09,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832759009] [2019-12-07 18:23:09,141 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:09,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:09,141 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 62 times [2019-12-07 18:23:09,141 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:09,141 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471882816] [2019-12-07 18:23:09,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:09,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:09,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:09,142 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:09,144 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:09,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-12-07 18:23:09,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:23:09,145 INFO L87 Difference]: Start difference. First operand 69 states and 103 transitions. cyclomatic complexity: 37 Second operand 34 states. [2019-12-07 18:23:09,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:09,300 INFO L93 Difference]: Finished difference Result 634 states and 671 transitions. [2019-12-07 18:23:09,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:23:09,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 634 states and 671 transitions. [2019-12-07 18:23:09,302 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:09,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 634 states to 633 states and 670 transitions. [2019-12-07 18:23:09,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:09,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:09,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 670 transitions. [2019-12-07 18:23:09,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:09,305 INFO L688 BuchiCegarLoop]: Abstraction has 633 states and 670 transitions. [2019-12-07 18:23:09,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 670 transitions. [2019-12-07 18:23:09,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 70. [2019-12-07 18:23:09,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2019-12-07 18:23:09,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 105 transitions. [2019-12-07 18:23:09,307 INFO L711 BuchiCegarLoop]: Abstraction has 70 states and 105 transitions. [2019-12-07 18:23:09,307 INFO L591 BuchiCegarLoop]: Abstraction has 70 states and 105 transitions. [2019-12-07 18:23:09,308 INFO L424 BuchiCegarLoop]: ======== Iteration 64============ [2019-12-07 18:23:09,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 105 transitions. [2019-12-07 18:23:09,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:09,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:09,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:09,308 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [30, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:09,309 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:09,309 INFO L794 eck$LassoCheckResult]: Stem: 16416#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 16417#L12 main_~i~0 := 0; 16418#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 16421#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 16422#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16426#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16485#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16484#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16483#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16482#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16481#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16480#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16479#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16478#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16477#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16476#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16475#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16474#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16473#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16472#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16471#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16470#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16469#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16468#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16467#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16466#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16465#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16464#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16463#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16462#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16461#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16460#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16459#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16458#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 16457#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 16423#L21-2 assume main_~j~0 >= 100; 16420#L25 [2019-12-07 18:23:09,309 INFO L796 eck$LassoCheckResult]: Loop: 16420#L25 assume true; 16420#L25 [2019-12-07 18:23:09,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:09,309 INFO L82 PathProgramCache]: Analyzing trace with hash -264692682, now seen corresponding path program 30 times [2019-12-07 18:23:09,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:09,309 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435050979] [2019-12-07 18:23:09,310 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:09,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:09,623 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:09,623 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435050979] [2019-12-07 18:23:09,624 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1006027938] [2019-12-07 18:23:09,624 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:09,658 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2019-12-07 18:23:09,659 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:09,659 INFO L264 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 32 conjunts are in the unsatisfiable core [2019-12-07 18:23:09,660 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:09,664 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:09,664 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:09,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2019-12-07 18:23:09,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164499752] [2019-12-07 18:23:09,665 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:09,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:09,665 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 63 times [2019-12-07 18:23:09,665 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:09,665 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242764264] [2019-12-07 18:23:09,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:09,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:09,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:09,666 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:09,668 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:09,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 18:23:09,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 18:23:09,668 INFO L87 Difference]: Start difference. First operand 70 states and 105 transitions. cyclomatic complexity: 38 Second operand 33 states. [2019-12-07 18:23:09,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:09,691 INFO L93 Difference]: Finished difference Result 72 states and 107 transitions. [2019-12-07 18:23:09,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 18:23:09,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 107 transitions. [2019-12-07 18:23:09,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:09,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 71 states and 106 transitions. [2019-12-07 18:23:09,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:09,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:09,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 106 transitions. [2019-12-07 18:23:09,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:09,692 INFO L688 BuchiCegarLoop]: Abstraction has 71 states and 106 transitions. [2019-12-07 18:23:09,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 106 transitions. [2019-12-07 18:23:09,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2019-12-07 18:23:09,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2019-12-07 18:23:09,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 106 transitions. [2019-12-07 18:23:09,693 INFO L711 BuchiCegarLoop]: Abstraction has 71 states and 106 transitions. [2019-12-07 18:23:09,693 INFO L591 BuchiCegarLoop]: Abstraction has 71 states and 106 transitions. [2019-12-07 18:23:09,693 INFO L424 BuchiCegarLoop]: ======== Iteration 65============ [2019-12-07 18:23:09,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 106 transitions. [2019-12-07 18:23:09,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:09,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:09,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:09,694 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [32, 1, 1, 1, 1] [2019-12-07 18:23:09,694 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:09,694 INFO L794 eck$LassoCheckResult]: Stem: 16699#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 16700#L12 main_~i~0 := 0; 16701#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16707#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16708#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16769#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16767#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16765#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16763#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16761#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16759#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16757#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16755#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16753#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16751#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16749#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16747#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16745#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16743#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16741#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16739#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16737#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16735#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16733#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16731#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16729#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16727#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16725#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16723#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16721#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16719#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16717#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16715#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16713#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16711#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 16702#L15-2 assume main_~i~0 >= 100; 16703#L25 [2019-12-07 18:23:09,694 INFO L796 eck$LassoCheckResult]: Loop: 16703#L25 assume true; 16703#L25 [2019-12-07 18:23:09,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:09,694 INFO L82 PathProgramCache]: Analyzing trace with hash 2133746795, now seen corresponding path program 32 times [2019-12-07 18:23:09,694 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:09,694 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445304367] [2019-12-07 18:23:09,694 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:09,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:10,041 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:10,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445304367] [2019-12-07 18:23:10,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1537102298] [2019-12-07 18:23:10,041 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:10,065 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:10,066 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:10,066 INFO L264 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 34 conjunts are in the unsatisfiable core [2019-12-07 18:23:10,067 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:10,071 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:10,071 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:10,071 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2019-12-07 18:23:10,072 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740034933] [2019-12-07 18:23:10,072 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:10,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:10,072 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 64 times [2019-12-07 18:23:10,072 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:10,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117328871] [2019-12-07 18:23:10,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:10,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:10,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:10,073 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:10,075 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:10,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-12-07 18:23:10,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 18:23:10,075 INFO L87 Difference]: Start difference. First operand 71 states and 106 transitions. cyclomatic complexity: 38 Second operand 35 states. [2019-12-07 18:23:10,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:10,230 INFO L93 Difference]: Finished difference Result 670 states and 708 transitions. [2019-12-07 18:23:10,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 18:23:10,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 670 states and 708 transitions. [2019-12-07 18:23:10,231 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:10,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 670 states to 669 states and 707 transitions. [2019-12-07 18:23:10,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:10,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:10,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 669 states and 707 transitions. [2019-12-07 18:23:10,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:10,234 INFO L688 BuchiCegarLoop]: Abstraction has 669 states and 707 transitions. [2019-12-07 18:23:10,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 669 states and 707 transitions. [2019-12-07 18:23:10,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 669 to 72. [2019-12-07 18:23:10,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2019-12-07 18:23:10,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 108 transitions. [2019-12-07 18:23:10,236 INFO L711 BuchiCegarLoop]: Abstraction has 72 states and 108 transitions. [2019-12-07 18:23:10,236 INFO L591 BuchiCegarLoop]: Abstraction has 72 states and 108 transitions. [2019-12-07 18:23:10,236 INFO L424 BuchiCegarLoop]: ======== Iteration 66============ [2019-12-07 18:23:10,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 108 transitions. [2019-12-07 18:23:10,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:10,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:10,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:10,237 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [31, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:10,237 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:10,237 INFO L794 eck$LassoCheckResult]: Stem: 17583#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 17584#L12 main_~i~0 := 0; 17585#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 17588#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 17589#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17593#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17654#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17653#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17652#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17651#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17650#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17649#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17648#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17647#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17646#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17645#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17644#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17643#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17642#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17641#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17640#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17639#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17638#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17637#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17636#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17635#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17634#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17633#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17632#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17631#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17630#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17629#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17628#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17627#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17626#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 17625#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 17590#L21-2 assume main_~j~0 >= 100; 17587#L25 [2019-12-07 18:23:10,237 INFO L796 eck$LassoCheckResult]: Loop: 17587#L25 assume true; 17587#L25 [2019-12-07 18:23:10,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:10,237 INFO L82 PathProgramCache]: Analyzing trace with hash 384463160, now seen corresponding path program 31 times [2019-12-07 18:23:10,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:10,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683644952] [2019-12-07 18:23:10,237 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:10,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:10,544 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:10,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683644952] [2019-12-07 18:23:10,545 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [846935724] [2019-12-07 18:23:10,545 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:10,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:10,575 INFO L264 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 18:23:10,576 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:10,580 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:10,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:10,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2019-12-07 18:23:10,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4445209] [2019-12-07 18:23:10,581 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:10,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:10,581 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 65 times [2019-12-07 18:23:10,581 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:10,581 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705066865] [2019-12-07 18:23:10,581 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:10,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:10,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:10,582 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:10,583 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:10,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2019-12-07 18:23:10,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 18:23:10,584 INFO L87 Difference]: Start difference. First operand 72 states and 108 transitions. cyclomatic complexity: 39 Second operand 34 states. [2019-12-07 18:23:10,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:10,617 INFO L93 Difference]: Finished difference Result 74 states and 110 transitions. [2019-12-07 18:23:10,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 18:23:10,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74 states and 110 transitions. [2019-12-07 18:23:10,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:10,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74 states to 73 states and 109 transitions. [2019-12-07 18:23:10,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:10,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:10,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 109 transitions. [2019-12-07 18:23:10,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:10,619 INFO L688 BuchiCegarLoop]: Abstraction has 73 states and 109 transitions. [2019-12-07 18:23:10,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 109 transitions. [2019-12-07 18:23:10,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2019-12-07 18:23:10,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2019-12-07 18:23:10,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 109 transitions. [2019-12-07 18:23:10,619 INFO L711 BuchiCegarLoop]: Abstraction has 73 states and 109 transitions. [2019-12-07 18:23:10,619 INFO L591 BuchiCegarLoop]: Abstraction has 73 states and 109 transitions. [2019-12-07 18:23:10,620 INFO L424 BuchiCegarLoop]: ======== Iteration 67============ [2019-12-07 18:23:10,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 109 transitions. [2019-12-07 18:23:10,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:10,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:10,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:10,620 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [33, 1, 1, 1, 1] [2019-12-07 18:23:10,620 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:10,620 INFO L794 eck$LassoCheckResult]: Stem: 17874#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 17875#L12 main_~i~0 := 0; 17876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17883#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17946#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17944#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17940#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17938#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17934#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17932#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17930#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17928#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17926#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17924#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17922#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17920#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17918#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17916#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17914#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17912#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17910#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17908#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17906#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17904#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17902#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17898#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17896#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17892#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17890#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17888#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 17886#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 17877#L15-2 assume main_~i~0 >= 100; 17878#L25 [2019-12-07 18:23:10,620 INFO L796 eck$LassoCheckResult]: Loop: 17878#L25 assume true; 17878#L25 [2019-12-07 18:23:10,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:10,620 INFO L82 PathProgramCache]: Analyzing trace with hash 1721642897, now seen corresponding path program 33 times [2019-12-07 18:23:10,620 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:10,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94418661] [2019-12-07 18:23:10,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:10,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:10,964 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:10,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94418661] [2019-12-07 18:23:10,965 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1040548258] [2019-12-07 18:23:10,965 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:10,994 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-12-07 18:23:10,994 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:10,995 INFO L264 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 18:23:10,996 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:11,000 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:11,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:11,000 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2019-12-07 18:23:11,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900881920] [2019-12-07 18:23:11,000 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:11,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:11,001 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 66 times [2019-12-07 18:23:11,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:11,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585066279] [2019-12-07 18:23:11,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:11,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:11,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:11,002 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:11,003 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:11,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-12-07 18:23:11,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:23:11,004 INFO L87 Difference]: Start difference. First operand 73 states and 109 transitions. cyclomatic complexity: 39 Second operand 36 states. [2019-12-07 18:23:11,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:11,248 INFO L93 Difference]: Finished difference Result 707 states and 746 transitions. [2019-12-07 18:23:11,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:23:11,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 707 states and 746 transitions. [2019-12-07 18:23:11,252 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:11,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 707 states to 706 states and 745 transitions. [2019-12-07 18:23:11,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:11,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:11,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 706 states and 745 transitions. [2019-12-07 18:23:11,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:11,260 INFO L688 BuchiCegarLoop]: Abstraction has 706 states and 745 transitions. [2019-12-07 18:23:11,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states and 745 transitions. [2019-12-07 18:23:11,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 74. [2019-12-07 18:23:11,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2019-12-07 18:23:11,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 111 transitions. [2019-12-07 18:23:11,266 INFO L711 BuchiCegarLoop]: Abstraction has 74 states and 111 transitions. [2019-12-07 18:23:11,266 INFO L591 BuchiCegarLoop]: Abstraction has 74 states and 111 transitions. [2019-12-07 18:23:11,266 INFO L424 BuchiCegarLoop]: ======== Iteration 68============ [2019-12-07 18:23:11,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 111 transitions. [2019-12-07 18:23:11,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:11,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:11,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:11,267 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [32, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:11,268 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:11,268 INFO L794 eck$LassoCheckResult]: Stem: 18801#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 18802#L12 main_~i~0 := 0; 18803#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 18806#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 18807#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18811#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18874#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18873#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18872#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18871#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18870#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18869#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18868#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18867#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18866#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18865#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18864#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18863#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18862#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18861#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18860#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18859#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18858#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18857#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18856#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18855#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18854#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18853#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18852#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18851#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18850#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18849#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18848#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18847#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18846#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18845#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 18844#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 18808#L21-2 assume main_~j~0 >= 100; 18805#L25 [2019-12-07 18:23:11,268 INFO L796 eck$LassoCheckResult]: Loop: 18805#L25 assume true; 18805#L25 [2019-12-07 18:23:11,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:11,269 INFO L82 PathProgramCache]: Analyzing trace with hash -966542218, now seen corresponding path program 32 times [2019-12-07 18:23:11,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:11,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512765670] [2019-12-07 18:23:11,270 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:11,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:11,613 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:11,613 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512765670] [2019-12-07 18:23:11,613 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1943145595] [2019-12-07 18:23:11,613 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:11,643 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:11,643 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:11,644 INFO L264 TraceCheckSpWp]: Trace formula consists of 203 conjuncts, 34 conjunts are in the unsatisfiable core [2019-12-07 18:23:11,644 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:11,648 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:11,649 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:11,649 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2019-12-07 18:23:11,649 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923189446] [2019-12-07 18:23:11,649 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:11,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:11,649 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 67 times [2019-12-07 18:23:11,649 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:11,649 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320481922] [2019-12-07 18:23:11,649 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:11,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:11,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:11,650 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:11,652 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:11,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2019-12-07 18:23:11,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 18:23:11,652 INFO L87 Difference]: Start difference. First operand 74 states and 111 transitions. cyclomatic complexity: 40 Second operand 35 states. [2019-12-07 18:23:11,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:11,691 INFO L93 Difference]: Finished difference Result 76 states and 113 transitions. [2019-12-07 18:23:11,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 18:23:11,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76 states and 113 transitions. [2019-12-07 18:23:11,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:11,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76 states to 75 states and 112 transitions. [2019-12-07 18:23:11,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:11,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:11,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 112 transitions. [2019-12-07 18:23:11,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:11,693 INFO L688 BuchiCegarLoop]: Abstraction has 75 states and 112 transitions. [2019-12-07 18:23:11,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 112 transitions. [2019-12-07 18:23:11,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2019-12-07 18:23:11,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2019-12-07 18:23:11,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 112 transitions. [2019-12-07 18:23:11,694 INFO L711 BuchiCegarLoop]: Abstraction has 75 states and 112 transitions. [2019-12-07 18:23:11,694 INFO L591 BuchiCegarLoop]: Abstraction has 75 states and 112 transitions. [2019-12-07 18:23:11,694 INFO L424 BuchiCegarLoop]: ======== Iteration 69============ [2019-12-07 18:23:11,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 112 transitions. [2019-12-07 18:23:11,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:11,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:11,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:11,694 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [34, 1, 1, 1, 1] [2019-12-07 18:23:11,694 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:11,694 INFO L794 eck$LassoCheckResult]: Stem: 19100#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 19101#L12 main_~i~0 := 0; 19102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19109#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19174#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19172#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19170#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19168#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19166#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19142#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19140#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19136#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19134#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19130#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19128#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19126#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19124#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19122#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19120#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19118#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19116#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 19112#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 19103#L15-2 assume main_~i~0 >= 100; 19104#L25 [2019-12-07 18:23:11,694 INFO L796 eck$LassoCheckResult]: Loop: 19104#L25 assume true; 19104#L25 [2019-12-07 18:23:11,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:11,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1831323947, now seen corresponding path program 34 times [2019-12-07 18:23:11,695 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:11,695 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822778253] [2019-12-07 18:23:11,695 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:11,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:12,059 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:12,059 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822778253] [2019-12-07 18:23:12,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2139134541] [2019-12-07 18:23:12,060 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:12,085 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:12,085 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:12,086 INFO L264 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 36 conjunts are in the unsatisfiable core [2019-12-07 18:23:12,087 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:12,091 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:12,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:12,091 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2019-12-07 18:23:12,092 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785808392] [2019-12-07 18:23:12,092 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:12,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:12,092 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 68 times [2019-12-07 18:23:12,092 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:12,092 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809003433] [2019-12-07 18:23:12,092 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:12,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:12,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:12,093 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:12,095 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:12,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 18:23:12,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:23:12,095 INFO L87 Difference]: Start difference. First operand 75 states and 112 transitions. cyclomatic complexity: 40 Second operand 37 states. [2019-12-07 18:23:12,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:12,249 INFO L93 Difference]: Finished difference Result 745 states and 785 transitions. [2019-12-07 18:23:12,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 18:23:12,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 785 transitions. [2019-12-07 18:23:12,251 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:12,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 744 states and 784 transitions. [2019-12-07 18:23:12,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:12,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:12,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 744 states and 784 transitions. [2019-12-07 18:23:12,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:12,254 INFO L688 BuchiCegarLoop]: Abstraction has 744 states and 784 transitions. [2019-12-07 18:23:12,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 744 states and 784 transitions. [2019-12-07 18:23:12,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 744 to 76. [2019-12-07 18:23:12,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2019-12-07 18:23:12,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 114 transitions. [2019-12-07 18:23:12,256 INFO L711 BuchiCegarLoop]: Abstraction has 76 states and 114 transitions. [2019-12-07 18:23:12,256 INFO L591 BuchiCegarLoop]: Abstraction has 76 states and 114 transitions. [2019-12-07 18:23:12,256 INFO L424 BuchiCegarLoop]: ======== Iteration 70============ [2019-12-07 18:23:12,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 114 transitions. [2019-12-07 18:23:12,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:12,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:12,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:12,257 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [33, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:12,257 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:12,257 INFO L794 eck$LassoCheckResult]: Stem: 20071#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 20072#L12 main_~i~0 := 0; 20073#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 20076#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 20077#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20081#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20139#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20138#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20137#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20136#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20135#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20134#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20133#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20132#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20131#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20130#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20129#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20128#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20127#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20126#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20125#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20124#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20123#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20122#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20121#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20120#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20119#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20118#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20117#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20116#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 20115#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 20078#L21-2 assume main_~j~0 >= 100; 20075#L25 [2019-12-07 18:23:12,257 INFO L796 eck$LassoCheckResult]: Loop: 20075#L25 assume true; 20075#L25 [2019-12-07 18:23:12,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:12,257 INFO L82 PathProgramCache]: Analyzing trace with hash 101964024, now seen corresponding path program 33 times [2019-12-07 18:23:12,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:12,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572861024] [2019-12-07 18:23:12,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:12,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:12,626 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:12,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572861024] [2019-12-07 18:23:12,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1605546353] [2019-12-07 18:23:12,626 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:12,665 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-12-07 18:23:12,665 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:12,666 INFO L264 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 18:23:12,666 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:12,671 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:12,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:12,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2019-12-07 18:23:12,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883387758] [2019-12-07 18:23:12,671 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:12,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:12,671 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 69 times [2019-12-07 18:23:12,671 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:12,672 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053385363] [2019-12-07 18:23:12,672 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:12,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:12,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:12,673 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:12,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:12,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2019-12-07 18:23:12,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:23:12,675 INFO L87 Difference]: Start difference. First operand 76 states and 114 transitions. cyclomatic complexity: 41 Second operand 36 states. [2019-12-07 18:23:12,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:12,707 INFO L93 Difference]: Finished difference Result 78 states and 116 transitions. [2019-12-07 18:23:12,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 18:23:12,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 116 transitions. [2019-12-07 18:23:12,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:12,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 77 states and 115 transitions. [2019-12-07 18:23:12,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:12,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:12,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 115 transitions. [2019-12-07 18:23:12,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:12,708 INFO L688 BuchiCegarLoop]: Abstraction has 77 states and 115 transitions. [2019-12-07 18:23:12,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 115 transitions. [2019-12-07 18:23:12,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2019-12-07 18:23:12,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2019-12-07 18:23:12,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 115 transitions. [2019-12-07 18:23:12,709 INFO L711 BuchiCegarLoop]: Abstraction has 77 states and 115 transitions. [2019-12-07 18:23:12,709 INFO L591 BuchiCegarLoop]: Abstraction has 77 states and 115 transitions. [2019-12-07 18:23:12,709 INFO L424 BuchiCegarLoop]: ======== Iteration 71============ [2019-12-07 18:23:12,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 115 transitions. [2019-12-07 18:23:12,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:12,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:12,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:12,710 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [35, 1, 1, 1, 1] [2019-12-07 18:23:12,710 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:12,710 INFO L794 eck$LassoCheckResult]: Stem: 20378#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 20379#L12 main_~i~0 := 0; 20380#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20386#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20387#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20454#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20452#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20450#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20448#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20446#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20444#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20442#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20440#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20438#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20436#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20434#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20432#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20430#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20428#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20426#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20424#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20422#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20420#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20418#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20416#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20414#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20412#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20410#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20408#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20406#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20404#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20402#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20400#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20398#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20396#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20394#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20392#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 20390#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 20381#L15-2 assume main_~i~0 >= 100; 20382#L25 [2019-12-07 18:23:12,710 INFO L796 eck$LassoCheckResult]: Loop: 20382#L25 assume true; 20382#L25 [2019-12-07 18:23:12,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:12,710 INFO L82 PathProgramCache]: Analyzing trace with hash 936469201, now seen corresponding path program 35 times [2019-12-07 18:23:12,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:12,710 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412468668] [2019-12-07 18:23:12,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:12,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:13,089 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:13,089 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412468668] [2019-12-07 18:23:13,089 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1128400349] [2019-12-07 18:23:13,089 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:13,119 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2019-12-07 18:23:13,119 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:13,120 INFO L264 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 37 conjunts are in the unsatisfiable core [2019-12-07 18:23:13,121 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:13,128 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:13,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:13,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2019-12-07 18:23:13,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705558398] [2019-12-07 18:23:13,129 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:13,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:13,129 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 70 times [2019-12-07 18:23:13,129 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:13,129 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038984270] [2019-12-07 18:23:13,129 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:13,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:13,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:13,130 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:13,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:13,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-12-07 18:23:13,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 18:23:13,132 INFO L87 Difference]: Start difference. First operand 77 states and 115 transitions. cyclomatic complexity: 41 Second operand 38 states. [2019-12-07 18:23:13,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:13,273 INFO L93 Difference]: Finished difference Result 784 states and 825 transitions. [2019-12-07 18:23:13,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:23:13,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 784 states and 825 transitions. [2019-12-07 18:23:13,275 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:13,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 784 states to 783 states and 824 transitions. [2019-12-07 18:23:13,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:13,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:13,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 783 states and 824 transitions. [2019-12-07 18:23:13,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:13,278 INFO L688 BuchiCegarLoop]: Abstraction has 783 states and 824 transitions. [2019-12-07 18:23:13,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 783 states and 824 transitions. [2019-12-07 18:23:13,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 783 to 78. [2019-12-07 18:23:13,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2019-12-07 18:23:13,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 117 transitions. [2019-12-07 18:23:13,280 INFO L711 BuchiCegarLoop]: Abstraction has 78 states and 117 transitions. [2019-12-07 18:23:13,280 INFO L591 BuchiCegarLoop]: Abstraction has 78 states and 117 transitions. [2019-12-07 18:23:13,280 INFO L424 BuchiCegarLoop]: ======== Iteration 72============ [2019-12-07 18:23:13,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 117 transitions. [2019-12-07 18:23:13,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:13,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:13,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:13,281 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [34, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:13,281 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:13,281 INFO L794 eck$LassoCheckResult]: Stem: 21394#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 21395#L12 main_~i~0 := 0; 21396#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 21399#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 21400#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21404#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21471#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21470#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21469#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21468#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21467#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21466#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21465#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21464#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21463#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21462#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21461#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21460#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21459#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21458#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21457#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21456#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21455#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21454#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21453#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21452#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21451#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21450#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21449#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21448#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21447#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21446#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21445#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21444#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21443#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21442#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21440#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 21439#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 21401#L21-2 assume main_~j~0 >= 100; 21398#L25 [2019-12-07 18:23:13,281 INFO L796 eck$LassoCheckResult]: Loop: 21398#L25 assume true; 21398#L25 [2019-12-07 18:23:13,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:13,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1134080842, now seen corresponding path program 34 times [2019-12-07 18:23:13,282 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:13,282 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574991989] [2019-12-07 18:23:13,282 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:13,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:13,642 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:13,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574991989] [2019-12-07 18:23:13,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1046531037] [2019-12-07 18:23:13,642 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:13,674 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:13,674 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:13,675 INFO L264 TraceCheckSpWp]: Trace formula consists of 215 conjuncts, 36 conjunts are in the unsatisfiable core [2019-12-07 18:23:13,675 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:13,680 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:13,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:13,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2019-12-07 18:23:13,680 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499653943] [2019-12-07 18:23:13,680 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:13,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:13,680 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 71 times [2019-12-07 18:23:13,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:13,680 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031172531] [2019-12-07 18:23:13,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:13,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:13,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:13,681 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:13,683 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:13,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 18:23:13,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 18:23:13,683 INFO L87 Difference]: Start difference. First operand 78 states and 117 transitions. cyclomatic complexity: 42 Second operand 37 states. [2019-12-07 18:23:13,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:13,707 INFO L93 Difference]: Finished difference Result 80 states and 119 transitions. [2019-12-07 18:23:13,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 18:23:13,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 119 transitions. [2019-12-07 18:23:13,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:13,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 79 states and 118 transitions. [2019-12-07 18:23:13,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:13,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:13,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 118 transitions. [2019-12-07 18:23:13,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:13,708 INFO L688 BuchiCegarLoop]: Abstraction has 79 states and 118 transitions. [2019-12-07 18:23:13,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 118 transitions. [2019-12-07 18:23:13,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2019-12-07 18:23:13,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2019-12-07 18:23:13,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 118 transitions. [2019-12-07 18:23:13,709 INFO L711 BuchiCegarLoop]: Abstraction has 79 states and 118 transitions. [2019-12-07 18:23:13,709 INFO L591 BuchiCegarLoop]: Abstraction has 79 states and 118 transitions. [2019-12-07 18:23:13,709 INFO L424 BuchiCegarLoop]: ======== Iteration 73============ [2019-12-07 18:23:13,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 118 transitions. [2019-12-07 18:23:13,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:13,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:13,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:13,709 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [36, 1, 1, 1, 1] [2019-12-07 18:23:13,709 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:13,709 INFO L794 eck$LassoCheckResult]: Stem: 21709#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 21710#L12 main_~i~0 := 0; 21711#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21717#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21718#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21787#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21785#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21783#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21781#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21779#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21777#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21775#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21773#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21771#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21769#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21767#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21765#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21763#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21761#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21759#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21757#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21755#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21753#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21751#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21749#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21747#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21745#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21743#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21741#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21739#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21737#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21735#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21733#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21731#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21729#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21727#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21725#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21723#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 21721#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 21712#L15-2 assume main_~i~0 >= 100; 21713#L25 [2019-12-07 18:23:13,709 INFO L796 eck$LassoCheckResult]: Loop: 21713#L25 assume true; 21713#L25 [2019-12-07 18:23:13,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:13,710 INFO L82 PathProgramCache]: Analyzing trace with hash -1034224149, now seen corresponding path program 36 times [2019-12-07 18:23:13,710 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:13,710 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559660479] [2019-12-07 18:23:13,710 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:13,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:14,113 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:14,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1559660479] [2019-12-07 18:23:14,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1675839492] [2019-12-07 18:23:14,113 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:14,144 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2019-12-07 18:23:14,144 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:14,145 INFO L264 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 18:23:14,146 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:14,150 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:14,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:14,150 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2019-12-07 18:23:14,150 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657451893] [2019-12-07 18:23:14,151 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:14,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:14,151 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 72 times [2019-12-07 18:23:14,151 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:14,151 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194939763] [2019-12-07 18:23:14,151 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:14,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:14,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:14,152 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:14,153 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:14,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-12-07 18:23:14,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:23:14,154 INFO L87 Difference]: Start difference. First operand 79 states and 118 transitions. cyclomatic complexity: 42 Second operand 39 states. [2019-12-07 18:23:14,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:14,296 INFO L93 Difference]: Finished difference Result 824 states and 866 transitions. [2019-12-07 18:23:14,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:23:14,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 824 states and 866 transitions. [2019-12-07 18:23:14,298 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:14,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 824 states to 823 states and 865 transitions. [2019-12-07 18:23:14,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:14,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:14,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 823 states and 865 transitions. [2019-12-07 18:23:14,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:14,301 INFO L688 BuchiCegarLoop]: Abstraction has 823 states and 865 transitions. [2019-12-07 18:23:14,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823 states and 865 transitions. [2019-12-07 18:23:14,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823 to 80. [2019-12-07 18:23:14,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2019-12-07 18:23:14,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 120 transitions. [2019-12-07 18:23:14,303 INFO L711 BuchiCegarLoop]: Abstraction has 80 states and 120 transitions. [2019-12-07 18:23:14,303 INFO L591 BuchiCegarLoop]: Abstraction has 80 states and 120 transitions. [2019-12-07 18:23:14,303 INFO L424 BuchiCegarLoop]: ======== Iteration 74============ [2019-12-07 18:23:14,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 120 transitions. [2019-12-07 18:23:14,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:14,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:14,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:14,304 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [35, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:14,304 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:14,304 INFO L794 eck$LassoCheckResult]: Stem: 22771#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 22772#L12 main_~i~0 := 0; 22773#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 22776#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 22777#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22781#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22850#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22849#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22848#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22847#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22846#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22845#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22844#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22843#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22842#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22841#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22840#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22839#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22838#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22837#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22836#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22835#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22834#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22833#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22832#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22831#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22830#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22829#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22828#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22827#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22826#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22825#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22824#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22823#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22822#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22821#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22820#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22819#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22818#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 22817#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 22778#L21-2 assume main_~j~0 >= 100; 22775#L25 [2019-12-07 18:23:14,304 INFO L796 eck$LassoCheckResult]: Loop: 22775#L25 assume true; 22775#L25 [2019-12-07 18:23:14,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:14,304 INFO L82 PathProgramCache]: Analyzing trace with hash -796766024, now seen corresponding path program 35 times [2019-12-07 18:23:14,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:14,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994572536] [2019-12-07 18:23:14,304 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:14,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:14,690 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:14,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994572536] [2019-12-07 18:23:14,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [131372649] [2019-12-07 18:23:14,690 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:14,731 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2019-12-07 18:23:14,731 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:14,732 INFO L264 TraceCheckSpWp]: Trace formula consists of 221 conjuncts, 37 conjunts are in the unsatisfiable core [2019-12-07 18:23:14,732 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:14,737 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:14,737 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:14,737 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2019-12-07 18:23:14,737 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464893364] [2019-12-07 18:23:14,737 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:14,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:14,738 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 73 times [2019-12-07 18:23:14,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:14,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854320733] [2019-12-07 18:23:14,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:14,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:14,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:14,739 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:14,740 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:14,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-12-07 18:23:14,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 18:23:14,741 INFO L87 Difference]: Start difference. First operand 80 states and 120 transitions. cyclomatic complexity: 43 Second operand 38 states. [2019-12-07 18:23:14,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:14,782 INFO L93 Difference]: Finished difference Result 82 states and 122 transitions. [2019-12-07 18:23:14,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 18:23:14,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 122 transitions. [2019-12-07 18:23:14,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:14,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 81 states and 121 transitions. [2019-12-07 18:23:14,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:14,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:14,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 121 transitions. [2019-12-07 18:23:14,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:14,784 INFO L688 BuchiCegarLoop]: Abstraction has 81 states and 121 transitions. [2019-12-07 18:23:14,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 121 transitions. [2019-12-07 18:23:14,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2019-12-07 18:23:14,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2019-12-07 18:23:14,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 121 transitions. [2019-12-07 18:23:14,785 INFO L711 BuchiCegarLoop]: Abstraction has 81 states and 121 transitions. [2019-12-07 18:23:14,785 INFO L591 BuchiCegarLoop]: Abstraction has 81 states and 121 transitions. [2019-12-07 18:23:14,785 INFO L424 BuchiCegarLoop]: ======== Iteration 75============ [2019-12-07 18:23:14,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 121 transitions. [2019-12-07 18:23:14,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:14,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:14,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:14,785 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [37, 1, 1, 1, 1] [2019-12-07 18:23:14,785 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:14,785 INFO L794 eck$LassoCheckResult]: Stem: 23094#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 23095#L12 main_~i~0 := 0; 23096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23103#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23174#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23172#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23170#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23168#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23166#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23142#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23140#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23136#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23134#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23130#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23128#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23126#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23124#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23122#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23120#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23118#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23116#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 23106#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 23097#L15-2 assume main_~i~0 >= 100; 23098#L25 [2019-12-07 18:23:14,785 INFO L796 eck$LassoCheckResult]: Loop: 23098#L25 assume true; 23098#L25 [2019-12-07 18:23:14,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:14,786 INFO L82 PathProgramCache]: Analyzing trace with hash -1996175855, now seen corresponding path program 37 times [2019-12-07 18:23:14,786 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:14,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315461184] [2019-12-07 18:23:14,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:15,207 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:15,207 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315461184] [2019-12-07 18:23:15,207 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1040000400] [2019-12-07 18:23:15,207 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:15,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:15,233 INFO L264 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 39 conjunts are in the unsatisfiable core [2019-12-07 18:23:15,234 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:15,239 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:15,239 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:15,239 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2019-12-07 18:23:15,239 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001863362] [2019-12-07 18:23:15,239 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:15,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:15,239 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 74 times [2019-12-07 18:23:15,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:15,240 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591948642] [2019-12-07 18:23:15,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:15,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:15,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:15,240 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:15,245 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:15,245 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 18:23:15,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 18:23:15,245 INFO L87 Difference]: Start difference. First operand 81 states and 121 transitions. cyclomatic complexity: 43 Second operand 40 states. [2019-12-07 18:23:15,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:15,509 INFO L93 Difference]: Finished difference Result 865 states and 908 transitions. [2019-12-07 18:23:15,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 18:23:15,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 865 states and 908 transitions. [2019-12-07 18:23:15,520 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:15,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 865 states to 864 states and 907 transitions. [2019-12-07 18:23:15,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:15,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:15,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 864 states and 907 transitions. [2019-12-07 18:23:15,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:15,525 INFO L688 BuchiCegarLoop]: Abstraction has 864 states and 907 transitions. [2019-12-07 18:23:15,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states and 907 transitions. [2019-12-07 18:23:15,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 82. [2019-12-07 18:23:15,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2019-12-07 18:23:15,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 123 transitions. [2019-12-07 18:23:15,527 INFO L711 BuchiCegarLoop]: Abstraction has 82 states and 123 transitions. [2019-12-07 18:23:15,527 INFO L591 BuchiCegarLoop]: Abstraction has 82 states and 123 transitions. [2019-12-07 18:23:15,527 INFO L424 BuchiCegarLoop]: ======== Iteration 76============ [2019-12-07 18:23:15,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 123 transitions. [2019-12-07 18:23:15,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:15,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:15,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:15,528 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [36, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:15,528 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:15,528 INFO L794 eck$LassoCheckResult]: Stem: 24203#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 24204#L12 main_~i~0 := 0; 24205#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 24208#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 24209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24213#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24284#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24283#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24282#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24281#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24280#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24279#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24278#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24277#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24276#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24275#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24274#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24273#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24272#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24271#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24270#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24269#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24268#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24267#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24266#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24265#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24264#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24263#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24262#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24261#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24260#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24259#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24258#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24257#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24256#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24255#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24254#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24253#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24252#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24251#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 24250#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 24210#L21-2 assume main_~j~0 >= 100; 24207#L25 [2019-12-07 18:23:15,528 INFO L796 eck$LassoCheckResult]: Loop: 24207#L25 assume true; 24207#L25 [2019-12-07 18:23:15,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:15,528 INFO L82 PathProgramCache]: Analyzing trace with hash 1070058742, now seen corresponding path program 36 times [2019-12-07 18:23:15,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:15,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086334951] [2019-12-07 18:23:15,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:15,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:15,940 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:15,940 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086334951] [2019-12-07 18:23:15,940 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [727099859] [2019-12-07 18:23:15,940 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:15,980 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2019-12-07 18:23:15,980 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:15,981 INFO L264 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 38 conjunts are in the unsatisfiable core [2019-12-07 18:23:15,981 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:15,986 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:15,986 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:15,986 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2019-12-07 18:23:15,986 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797648753] [2019-12-07 18:23:15,987 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:15,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:15,987 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 75 times [2019-12-07 18:23:15,987 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:15,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829165430] [2019-12-07 18:23:15,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:15,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:15,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:15,988 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:15,989 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:15,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-12-07 18:23:15,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 18:23:15,990 INFO L87 Difference]: Start difference. First operand 82 states and 123 transitions. cyclomatic complexity: 44 Second operand 39 states. [2019-12-07 18:23:16,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:16,013 INFO L93 Difference]: Finished difference Result 84 states and 125 transitions. [2019-12-07 18:23:16,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:23:16,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 125 transitions. [2019-12-07 18:23:16,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:16,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 83 states and 124 transitions. [2019-12-07 18:23:16,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:16,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:16,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 124 transitions. [2019-12-07 18:23:16,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:16,015 INFO L688 BuchiCegarLoop]: Abstraction has 83 states and 124 transitions. [2019-12-07 18:23:16,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 124 transitions. [2019-12-07 18:23:16,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2019-12-07 18:23:16,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2019-12-07 18:23:16,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 124 transitions. [2019-12-07 18:23:16,016 INFO L711 BuchiCegarLoop]: Abstraction has 83 states and 124 transitions. [2019-12-07 18:23:16,016 INFO L591 BuchiCegarLoop]: Abstraction has 83 states and 124 transitions. [2019-12-07 18:23:16,016 INFO L424 BuchiCegarLoop]: ======== Iteration 77============ [2019-12-07 18:23:16,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 124 transitions. [2019-12-07 18:23:16,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:16,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:16,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:16,016 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [38, 1, 1, 1, 1] [2019-12-07 18:23:16,016 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:16,016 INFO L794 eck$LassoCheckResult]: Stem: 24534#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 24535#L12 main_~i~0 := 0; 24536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24543#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24616#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24610#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24608#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 24546#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 24537#L15-2 assume main_~i~0 >= 100; 24538#L25 [2019-12-07 18:23:16,016 INFO L796 eck$LassoCheckResult]: Loop: 24538#L25 assume true; 24538#L25 [2019-12-07 18:23:16,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:16,017 INFO L82 PathProgramCache]: Analyzing trace with hash -1751907669, now seen corresponding path program 38 times [2019-12-07 18:23:16,017 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:16,017 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267876577] [2019-12-07 18:23:16,017 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:16,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:16,455 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:16,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267876577] [2019-12-07 18:23:16,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [594776523] [2019-12-07 18:23:16,455 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:16,481 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:16,481 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:16,482 INFO L264 TraceCheckSpWp]: Trace formula consists of 159 conjuncts, 40 conjunts are in the unsatisfiable core [2019-12-07 18:23:16,483 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:16,488 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:16,488 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:16,488 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2019-12-07 18:23:16,488 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083820545] [2019-12-07 18:23:16,488 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:16,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:16,488 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 76 times [2019-12-07 18:23:16,488 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:16,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580245673] [2019-12-07 18:23:16,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:16,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:16,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:16,489 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:16,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:16,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 18:23:16,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 18:23:16,492 INFO L87 Difference]: Start difference. First operand 83 states and 124 transitions. cyclomatic complexity: 44 Second operand 41 states. [2019-12-07 18:23:16,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:16,650 INFO L93 Difference]: Finished difference Result 907 states and 951 transitions. [2019-12-07 18:23:16,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:23:16,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 907 states and 951 transitions. [2019-12-07 18:23:16,652 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:16,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 907 states to 906 states and 950 transitions. [2019-12-07 18:23:16,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:16,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:16,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 906 states and 950 transitions. [2019-12-07 18:23:16,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:16,656 INFO L688 BuchiCegarLoop]: Abstraction has 906 states and 950 transitions. [2019-12-07 18:23:16,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 906 states and 950 transitions. [2019-12-07 18:23:16,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 906 to 84. [2019-12-07 18:23:16,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2019-12-07 18:23:16,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 126 transitions. [2019-12-07 18:23:16,658 INFO L711 BuchiCegarLoop]: Abstraction has 84 states and 126 transitions. [2019-12-07 18:23:16,658 INFO L591 BuchiCegarLoop]: Abstraction has 84 states and 126 transitions. [2019-12-07 18:23:16,658 INFO L424 BuchiCegarLoop]: ======== Iteration 78============ [2019-12-07 18:23:16,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 126 transitions. [2019-12-07 18:23:16,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:16,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:16,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:16,659 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [37, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:16,659 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:16,659 INFO L794 eck$LassoCheckResult]: Stem: 25691#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 25692#L12 main_~i~0 := 0; 25693#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 25696#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 25697#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25774#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25773#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25772#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25771#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25770#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25769#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25768#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25767#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25766#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25765#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25764#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25763#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25762#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25761#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25760#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25759#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25758#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25757#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25756#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25755#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25754#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25753#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25752#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25751#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25750#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25749#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25748#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25747#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25746#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25745#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25744#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25743#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25742#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25741#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25740#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 25739#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 25698#L21-2 assume main_~j~0 >= 100; 25695#L25 [2019-12-07 18:23:16,659 INFO L796 eck$LassoCheckResult]: Loop: 25695#L25 assume true; 25695#L25 [2019-12-07 18:23:16,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:16,659 INFO L82 PathProgramCache]: Analyzing trace with hash -1187915656, now seen corresponding path program 37 times [2019-12-07 18:23:16,659 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:16,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144672467] [2019-12-07 18:23:16,660 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:16,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:17,088 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:17,088 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144672467] [2019-12-07 18:23:17,088 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1367025600] [2019-12-07 18:23:17,088 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:17,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:17,123 INFO L264 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 39 conjunts are in the unsatisfiable core [2019-12-07 18:23:17,124 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:17,131 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:17,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:17,131 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2019-12-07 18:23:17,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330593644] [2019-12-07 18:23:17,131 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:17,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:17,132 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 77 times [2019-12-07 18:23:17,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:17,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087675770] [2019-12-07 18:23:17,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:17,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:17,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:17,133 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:17,134 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:17,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 18:23:17,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 18:23:17,135 INFO L87 Difference]: Start difference. First operand 84 states and 126 transitions. cyclomatic complexity: 45 Second operand 40 states. [2019-12-07 18:23:17,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:17,173 INFO L93 Difference]: Finished difference Result 86 states and 128 transitions. [2019-12-07 18:23:17,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2019-12-07 18:23:17,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 128 transitions. [2019-12-07 18:23:17,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:17,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 85 states and 127 transitions. [2019-12-07 18:23:17,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:17,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:17,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 127 transitions. [2019-12-07 18:23:17,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:17,174 INFO L688 BuchiCegarLoop]: Abstraction has 85 states and 127 transitions. [2019-12-07 18:23:17,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 127 transitions. [2019-12-07 18:23:17,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2019-12-07 18:23:17,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2019-12-07 18:23:17,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 127 transitions. [2019-12-07 18:23:17,175 INFO L711 BuchiCegarLoop]: Abstraction has 85 states and 127 transitions. [2019-12-07 18:23:17,175 INFO L591 BuchiCegarLoop]: Abstraction has 85 states and 127 transitions. [2019-12-07 18:23:17,175 INFO L424 BuchiCegarLoop]: ======== Iteration 79============ [2019-12-07 18:23:17,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 127 transitions. [2019-12-07 18:23:17,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:17,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:17,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:17,176 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [39, 1, 1, 1, 1] [2019-12-07 18:23:17,176 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:17,176 INFO L794 eck$LassoCheckResult]: Stem: 26030#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 26031#L12 main_~i~0 := 0; 26032#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26038#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26039#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26106#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26104#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26100#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26094#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26090#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26088#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26050#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26048#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26044#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 26042#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 26033#L15-2 assume main_~i~0 >= 100; 26034#L25 [2019-12-07 18:23:17,176 INFO L796 eck$LassoCheckResult]: Loop: 26034#L25 assume true; 26034#L25 [2019-12-07 18:23:17,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:17,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1525438801, now seen corresponding path program 39 times [2019-12-07 18:23:17,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:17,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279518534] [2019-12-07 18:23:17,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:17,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:17,636 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:17,636 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279518534] [2019-12-07 18:23:17,636 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2031249968] [2019-12-07 18:23:17,637 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:17,669 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2019-12-07 18:23:17,669 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:17,670 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 41 conjunts are in the unsatisfiable core [2019-12-07 18:23:17,671 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:17,676 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:17,676 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:17,676 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2019-12-07 18:23:17,676 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15451909] [2019-12-07 18:23:17,676 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:17,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:17,676 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 78 times [2019-12-07 18:23:17,676 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:17,676 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234244611] [2019-12-07 18:23:17,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:17,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:17,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:17,677 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:17,679 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:17,679 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2019-12-07 18:23:17,679 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:23:17,680 INFO L87 Difference]: Start difference. First operand 85 states and 127 transitions. cyclomatic complexity: 45 Second operand 42 states. [2019-12-07 18:23:17,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:17,890 INFO L93 Difference]: Finished difference Result 950 states and 995 transitions. [2019-12-07 18:23:17,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:23:17,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 950 states and 995 transitions. [2019-12-07 18:23:17,892 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:17,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 950 states to 949 states and 994 transitions. [2019-12-07 18:23:17,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:17,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:17,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 949 states and 994 transitions. [2019-12-07 18:23:17,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:17,897 INFO L688 BuchiCegarLoop]: Abstraction has 949 states and 994 transitions. [2019-12-07 18:23:17,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 949 states and 994 transitions. [2019-12-07 18:23:17,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 949 to 86. [2019-12-07 18:23:17,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2019-12-07 18:23:17,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 129 transitions. [2019-12-07 18:23:17,900 INFO L711 BuchiCegarLoop]: Abstraction has 86 states and 129 transitions. [2019-12-07 18:23:17,900 INFO L591 BuchiCegarLoop]: Abstraction has 86 states and 129 transitions. [2019-12-07 18:23:17,901 INFO L424 BuchiCegarLoop]: ======== Iteration 80============ [2019-12-07 18:23:17,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 129 transitions. [2019-12-07 18:23:17,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:17,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:17,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:17,901 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [38, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:17,901 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:17,901 INFO L794 eck$LassoCheckResult]: Stem: 27236#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 27237#L12 main_~i~0 := 0; 27238#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 27241#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 27242#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27246#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27321#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27320#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27319#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27318#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27317#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27316#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27315#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27314#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27313#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27312#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27311#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27310#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27309#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27308#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27307#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27306#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27305#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27304#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27303#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27302#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27301#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27300#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27299#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27298#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27297#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27296#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27295#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27294#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27293#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27292#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27291#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27290#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27289#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27288#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27287#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27286#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 27285#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 27243#L21-2 assume main_~j~0 >= 100; 27240#L25 [2019-12-07 18:23:17,902 INFO L796 eck$LassoCheckResult]: Loop: 27240#L25 assume true; 27240#L25 [2019-12-07 18:23:17,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:17,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1829322038, now seen corresponding path program 38 times [2019-12-07 18:23:17,902 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:17,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794830440] [2019-12-07 18:23:17,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:17,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:18,348 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:18,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794830440] [2019-12-07 18:23:18,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1530779820] [2019-12-07 18:23:18,348 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:18,381 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:23:18,381 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:18,383 INFO L264 TraceCheckSpWp]: Trace formula consists of 239 conjuncts, 40 conjunts are in the unsatisfiable core [2019-12-07 18:23:18,383 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:18,388 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:18,388 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:18,388 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2019-12-07 18:23:18,388 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925736667] [2019-12-07 18:23:18,389 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:18,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:18,389 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 79 times [2019-12-07 18:23:18,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:18,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786046736] [2019-12-07 18:23:18,389 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:18,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:18,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:18,390 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:18,391 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:18,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2019-12-07 18:23:18,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 18:23:18,392 INFO L87 Difference]: Start difference. First operand 86 states and 129 transitions. cyclomatic complexity: 46 Second operand 41 states. [2019-12-07 18:23:18,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:18,439 INFO L93 Difference]: Finished difference Result 88 states and 131 transitions. [2019-12-07 18:23:18,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:23:18,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 131 transitions. [2019-12-07 18:23:18,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:18,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 87 states and 130 transitions. [2019-12-07 18:23:18,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:18,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:18,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 130 transitions. [2019-12-07 18:23:18,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:18,441 INFO L688 BuchiCegarLoop]: Abstraction has 87 states and 130 transitions. [2019-12-07 18:23:18,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 130 transitions. [2019-12-07 18:23:18,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2019-12-07 18:23:18,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2019-12-07 18:23:18,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 130 transitions. [2019-12-07 18:23:18,442 INFO L711 BuchiCegarLoop]: Abstraction has 87 states and 130 transitions. [2019-12-07 18:23:18,442 INFO L591 BuchiCegarLoop]: Abstraction has 87 states and 130 transitions. [2019-12-07 18:23:18,442 INFO L424 BuchiCegarLoop]: ======== Iteration 81============ [2019-12-07 18:23:18,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 130 transitions. [2019-12-07 18:23:18,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:18,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:18,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:18,442 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [40, 1, 1, 1, 1] [2019-12-07 18:23:18,442 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:18,443 INFO L794 eck$LassoCheckResult]: Stem: 27583#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 27584#L12 main_~i~0 := 0; 27585#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27591#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27669#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27667#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27665#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27663#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27661#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27659#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27657#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27655#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27653#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27651#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27649#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27647#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27645#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27643#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27641#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27639#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27637#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27635#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27633#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27631#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27629#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27627#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27625#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27623#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27621#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27619#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27617#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27615#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27613#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27611#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27609#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27607#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27605#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27603#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27601#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27599#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27597#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 27595#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 27586#L15-2 assume main_~i~0 >= 100; 27587#L25 [2019-12-07 18:23:18,443 INFO L796 eck$LassoCheckResult]: Loop: 27587#L25 assume true; 27587#L25 [2019-12-07 18:23:18,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:18,443 INFO L82 PathProgramCache]: Analyzing trace with hash 43964267, now seen corresponding path program 40 times [2019-12-07 18:23:18,443 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:18,443 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843429028] [2019-12-07 18:23:18,443 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:18,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:18,935 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:18,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843429028] [2019-12-07 18:23:18,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [72895043] [2019-12-07 18:23:18,936 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:18,962 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:23:18,963 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:18,963 INFO L264 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 42 conjunts are in the unsatisfiable core [2019-12-07 18:23:18,964 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:18,969 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:18,969 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:18,969 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2019-12-07 18:23:18,969 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465884469] [2019-12-07 18:23:18,969 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:18,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:18,970 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 80 times [2019-12-07 18:23:18,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:18,970 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404529530] [2019-12-07 18:23:18,970 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:18,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:18,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:18,971 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:18,972 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:18,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2019-12-07 18:23:18,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:23:18,973 INFO L87 Difference]: Start difference. First operand 87 states and 130 transitions. cyclomatic complexity: 46 Second operand 43 states. [2019-12-07 18:23:19,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:19,187 INFO L93 Difference]: Finished difference Result 994 states and 1040 transitions. [2019-12-07 18:23:19,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2019-12-07 18:23:19,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 994 states and 1040 transitions. [2019-12-07 18:23:19,192 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:19,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 994 states to 993 states and 1039 transitions. [2019-12-07 18:23:19,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:19,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:19,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1039 transitions. [2019-12-07 18:23:19,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:19,201 INFO L688 BuchiCegarLoop]: Abstraction has 993 states and 1039 transitions. [2019-12-07 18:23:19,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1039 transitions. [2019-12-07 18:23:19,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 88. [2019-12-07 18:23:19,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2019-12-07 18:23:19,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 132 transitions. [2019-12-07 18:23:19,208 INFO L711 BuchiCegarLoop]: Abstraction has 88 states and 132 transitions. [2019-12-07 18:23:19,208 INFO L591 BuchiCegarLoop]: Abstraction has 88 states and 132 transitions. [2019-12-07 18:23:19,208 INFO L424 BuchiCegarLoop]: ======== Iteration 82============ [2019-12-07 18:23:19,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 132 transitions. [2019-12-07 18:23:19,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:19,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:19,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:19,209 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [39, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:19,209 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:19,210 INFO L794 eck$LassoCheckResult]: Stem: 28839#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 28840#L12 main_~i~0 := 0; 28841#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 28844#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 28845#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28849#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28926#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28925#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28924#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28923#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28922#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28921#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28920#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28919#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28918#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28917#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28916#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28915#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28914#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28913#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28912#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28911#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28910#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28909#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28908#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28907#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28906#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28905#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28904#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28903#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28902#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28901#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28900#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28899#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28898#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28897#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28896#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28895#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28894#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28893#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28892#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28891#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28890#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 28889#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 28846#L21-2 assume main_~j~0 >= 100; 28843#L25 [2019-12-07 18:23:19,210 INFO L796 eck$LassoCheckResult]: Loop: 28843#L25 assume true; 28843#L25 [2019-12-07 18:23:19,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:19,210 INFO L82 PathProgramCache]: Analyzing trace with hash 874410040, now seen corresponding path program 39 times [2019-12-07 18:23:19,211 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:19,211 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882119822] [2019-12-07 18:23:19,211 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:19,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:19,688 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:19,688 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882119822] [2019-12-07 18:23:19,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1670776634] [2019-12-07 18:23:19,689 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:19,731 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2019-12-07 18:23:19,731 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:19,732 INFO L264 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 41 conjunts are in the unsatisfiable core [2019-12-07 18:23:19,733 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:19,738 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:19,738 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:19,738 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2019-12-07 18:23:19,738 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269367044] [2019-12-07 18:23:19,738 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:19,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:19,739 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 81 times [2019-12-07 18:23:19,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:19,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280666533] [2019-12-07 18:23:19,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:19,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:19,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:19,740 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:19,741 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:19,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2019-12-07 18:23:19,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:23:19,742 INFO L87 Difference]: Start difference. First operand 88 states and 132 transitions. cyclomatic complexity: 47 Second operand 42 states. [2019-12-07 18:23:19,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:19,790 INFO L93 Difference]: Finished difference Result 90 states and 134 transitions. [2019-12-07 18:23:19,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 18:23:19,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 134 transitions. [2019-12-07 18:23:19,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:19,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 89 states and 133 transitions. [2019-12-07 18:23:19,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:23:19,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:23:19,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 133 transitions. [2019-12-07 18:23:19,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:19,791 INFO L688 BuchiCegarLoop]: Abstraction has 89 states and 133 transitions. [2019-12-07 18:23:19,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 133 transitions. [2019-12-07 18:23:19,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2019-12-07 18:23:19,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2019-12-07 18:23:19,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 133 transitions. [2019-12-07 18:23:19,793 INFO L711 BuchiCegarLoop]: Abstraction has 89 states and 133 transitions. [2019-12-07 18:23:19,793 INFO L591 BuchiCegarLoop]: Abstraction has 89 states and 133 transitions. [2019-12-07 18:23:19,793 INFO L424 BuchiCegarLoop]: ======== Iteration 83============ [2019-12-07 18:23:19,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 133 transitions. [2019-12-07 18:23:19,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:19,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:19,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:19,794 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [41, 1, 1, 1, 1] [2019-12-07 18:23:19,794 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:19,794 INFO L794 eck$LassoCheckResult]: Stem: 29194#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 29195#L12 main_~i~0 := 0; 29196#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29202#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29203#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29282#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29280#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29278#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29276#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29274#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29272#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29270#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29268#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29266#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29264#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29262#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29260#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29258#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29256#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29254#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29252#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29250#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29248#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29246#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29244#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29242#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29240#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29238#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29236#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29234#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29232#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29230#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29228#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29226#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29224#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29222#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29220#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29218#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29216#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29214#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29212#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29210#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29208#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 29206#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 29197#L15-2 assume main_~i~0 >= 100; 29198#L25 [2019-12-07 18:23:19,794 INFO L796 eck$LassoCheckResult]: Loop: 29198#L25 assume true; 29198#L25 [2019-12-07 18:23:19,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:19,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1362893969, now seen corresponding path program 41 times [2019-12-07 18:23:19,795 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:19,795 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023654952] [2019-12-07 18:23:19,795 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:19,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:23:20,305 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:20,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023654952] [2019-12-07 18:23:20,305 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [824918195] [2019-12-07 18:23:20,305 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:23:20,339 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2019-12-07 18:23:20,339 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:23:20,340 INFO L264 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 43 conjunts are in the unsatisfiable core [2019-12-07 18:23:20,340 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:23:20,351 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:23:20,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:23:20,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2019-12-07 18:23:20,352 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302335685] [2019-12-07 18:23:20,352 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:23:20,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:23:20,352 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 82 times [2019-12-07 18:23:20,353 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:23:20,353 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759930067] [2019-12-07 18:23:20,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:23:20,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:20,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:23:20,354 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:23:20,356 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:23:20,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2019-12-07 18:23:20,357 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 18:23:20,357 INFO L87 Difference]: Start difference. First operand 89 states and 133 transitions. cyclomatic complexity: 47 Second operand 44 states. [2019-12-07 18:23:20,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:23:20,527 INFO L93 Difference]: Finished difference Result 1039 states and 1086 transitions. [2019-12-07 18:23:20,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2019-12-07 18:23:20,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1039 states and 1086 transitions. [2019-12-07 18:23:20,529 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:23:20,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1039 states to 1038 states and 1085 transitions. [2019-12-07 18:23:20,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:23:20,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:23:20,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1038 states and 1085 transitions. [2019-12-07 18:23:20,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:23:20,533 INFO L688 BuchiCegarLoop]: Abstraction has 1038 states and 1085 transitions. [2019-12-07 18:23:20,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1038 states and 1085 transitions. [2019-12-07 18:23:20,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1038 to 90. [2019-12-07 18:23:20,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2019-12-07 18:23:20,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 135 transitions. [2019-12-07 18:23:20,536 INFO L711 BuchiCegarLoop]: Abstraction has 90 states and 135 transitions. [2019-12-07 18:23:20,536 INFO L591 BuchiCegarLoop]: Abstraction has 90 states and 135 transitions. [2019-12-07 18:23:20,536 INFO L424 BuchiCegarLoop]: ======== Iteration 84============ [2019-12-07 18:23:20,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 135 transitions. [2019-12-07 18:23:20,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:23:20,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:23:20,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:23:20,536 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [40, 1, 1, 1, 1, 1, 1] [2019-12-07 18:23:20,536 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:23:20,536 INFO L794 eck$LassoCheckResult]: Stem: 30501#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 30502#L12 main_~i~0 := 0; 30503#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 30506#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 30507#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30511#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30590#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30589#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30588#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30587#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30586#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30585#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30584#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30583#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30582#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30581#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30580#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30579#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30578#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30577#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30576#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30575#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30574#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30573#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30572#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30571#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30570#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30569#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30568#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30567#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30566#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30565#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30564#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30563#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30562#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30561#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30560#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30559#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30558#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30557#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30556#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30555#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30554#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30553#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 30552#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 30508#L21-2 assume main_~j~0 >= 100; 30505#L25 WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [2019-12-07 18:25:22,542 INFO L796 eck$LassoCheckResult]: Loop: 156845#L25 assume true; 156845#L25 [2019-12-07 18:25:22,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:22,542 INFO L82 PathProgramCache]: Analyzing trace with hash 277611126, now seen corresponding path program 80 times [2019-12-07 18:25:22,542 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:22,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517439103] [2019-12-07 18:25:22,543 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:22,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:24,356 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:24,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517439103] [2019-12-07 18:25:24,356 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1747263161] [2019-12-07 18:25:24,356 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 166 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 166 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:24,410 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:25:24,410 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:24,412 INFO L264 TraceCheckSpWp]: Trace formula consists of 491 conjuncts, 82 conjunts are in the unsatisfiable core [2019-12-07 18:25:24,412 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:24,423 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:24,423 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:24,423 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [82, 82] total 82 [2019-12-07 18:25:24,423 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893864079] [2019-12-07 18:25:24,423 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:24,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:24,423 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 163 times [2019-12-07 18:25:24,423 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:24,423 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813297310] [2019-12-07 18:25:24,423 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:24,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:24,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:24,424 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:24,426 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:24,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2019-12-07 18:25:24,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3403, Invalid=3403, Unknown=0, NotChecked=0, Total=6806 [2019-12-07 18:25:24,427 INFO L87 Difference]: Start difference. First operand 170 states and 255 transitions. cyclomatic complexity: 88 Second operand 83 states. [2019-12-07 18:25:24,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:24,489 INFO L93 Difference]: Finished difference Result 172 states and 257 transitions. [2019-12-07 18:25:24,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2019-12-07 18:25:24,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 172 states and 257 transitions. [2019-12-07 18:25:24,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:24,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 172 states to 171 states and 256 transitions. [2019-12-07 18:25:24,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:24,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:24,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 256 transitions. [2019-12-07 18:25:24,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:24,491 INFO L688 BuchiCegarLoop]: Abstraction has 171 states and 256 transitions. [2019-12-07 18:25:24,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 256 transitions. [2019-12-07 18:25:24,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2019-12-07 18:25:24,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2019-12-07 18:25:24,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 256 transitions. [2019-12-07 18:25:24,491 INFO L711 BuchiCegarLoop]: Abstraction has 171 states and 256 transitions. [2019-12-07 18:25:24,491 INFO L591 BuchiCegarLoop]: Abstraction has 171 states and 256 transitions. [2019-12-07 18:25:24,491 INFO L424 BuchiCegarLoop]: ======== Iteration 165============ [2019-12-07 18:25:24,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 256 transitions. [2019-12-07 18:25:24,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:24,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:24,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:24,492 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [82, 1, 1, 1, 1] [2019-12-07 18:25:24,492 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:24,492 INFO L794 eck$LassoCheckResult]: Stem: 157524#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 157525#L12 main_~i~0 := 0; 157526#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157533#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157694#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157692#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157690#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157688#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157686#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157684#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157682#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157680#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157678#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157676#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157674#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157672#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157670#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157668#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157666#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157664#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157662#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157660#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157658#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157656#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157654#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157652#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157650#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157648#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157646#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157644#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157642#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157640#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157638#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157636#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157634#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157632#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157630#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157628#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157626#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157624#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157622#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157620#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157618#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157616#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157610#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157608#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157546#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157544#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157540#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157538#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 157536#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 157527#L15-2 assume main_~i~0 >= 100; 157528#L25 [2019-12-07 18:25:24,492 INFO L796 eck$LassoCheckResult]: Loop: 157528#L25 assume true; 157528#L25 [2019-12-07 18:25:24,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:24,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1088881877, now seen corresponding path program 82 times [2019-12-07 18:25:24,492 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:24,492 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247772601] [2019-12-07 18:25:24,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:24,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:26,413 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:26,413 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247772601] [2019-12-07 18:25:26,414 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2004722513] [2019-12-07 18:25:26,414 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 167 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 167 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:26,455 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:25:26,455 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:26,457 INFO L264 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 84 conjunts are in the unsatisfiable core [2019-12-07 18:25:26,457 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:26,468 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:26,468 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:26,468 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [84, 84] total 84 [2019-12-07 18:25:26,468 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856235813] [2019-12-07 18:25:26,468 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:26,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:26,469 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 164 times [2019-12-07 18:25:26,469 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:26,469 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653189656] [2019-12-07 18:25:26,469 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:26,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:26,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:26,470 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:26,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:26,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2019-12-07 18:25:26,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3570, Invalid=3570, Unknown=0, NotChecked=0, Total=7140 [2019-12-07 18:25:26,472 INFO L87 Difference]: Start difference. First operand 171 states and 256 transitions. cyclomatic complexity: 88 Second operand 85 states. [2019-12-07 18:25:27,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:27,407 INFO L93 Difference]: Finished difference Result 3745 states and 3833 transitions. [2019-12-07 18:25:27,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2019-12-07 18:25:27,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3745 states and 3833 transitions. [2019-12-07 18:25:27,413 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:27,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3745 states to 3744 states and 3832 transitions. [2019-12-07 18:25:27,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:27,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:27,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3744 states and 3832 transitions. [2019-12-07 18:25:27,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:27,417 INFO L688 BuchiCegarLoop]: Abstraction has 3744 states and 3832 transitions. [2019-12-07 18:25:27,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3744 states and 3832 transitions. [2019-12-07 18:25:27,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3744 to 172. [2019-12-07 18:25:27,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2019-12-07 18:25:27,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 258 transitions. [2019-12-07 18:25:27,421 INFO L711 BuchiCegarLoop]: Abstraction has 172 states and 258 transitions. [2019-12-07 18:25:27,421 INFO L591 BuchiCegarLoop]: Abstraction has 172 states and 258 transitions. [2019-12-07 18:25:27,421 INFO L424 BuchiCegarLoop]: ======== Iteration 166============ [2019-12-07 18:25:27,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 258 transitions. [2019-12-07 18:25:27,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:27,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:27,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:27,421 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [81, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:27,421 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:27,422 INFO L794 eck$LassoCheckResult]: Stem: 161783#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 161784#L12 main_~i~0 := 0; 161785#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 161788#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 161789#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161793#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161954#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161953#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161952#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161951#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161950#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161949#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161948#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161947#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161946#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161945#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161944#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161943#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161942#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161941#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161940#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161939#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161938#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161937#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161936#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161935#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161934#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161933#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161932#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161931#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161930#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161929#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161928#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161927#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161926#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161925#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161924#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161923#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161922#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161921#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161920#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161919#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161918#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161917#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161916#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161915#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161914#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161913#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161912#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161911#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161910#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161909#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161908#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161907#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161906#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161905#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161904#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161903#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161902#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161901#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161900#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161899#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161898#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161897#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161896#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161895#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161894#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161893#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161892#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161891#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161890#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161889#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161888#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161887#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161886#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161885#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161884#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161883#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161882#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161881#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161880#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161879#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161878#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161877#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161876#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 161875#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 161790#L21-2 assume main_~j~0 >= 100; 161787#L25 [2019-12-07 18:25:27,422 INFO L796 eck$LassoCheckResult]: Loop: 161787#L25 assume true; 161787#L25 [2019-12-07 18:25:27,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:27,422 INFO L82 PathProgramCache]: Analyzing trace with hash 16012024, now seen corresponding path program 81 times [2019-12-07 18:25:27,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:27,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407326690] [2019-12-07 18:25:27,422 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:27,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:29,275 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:29,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407326690] [2019-12-07 18:25:29,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [531904987] [2019-12-07 18:25:29,276 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 168 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 168 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:29,365 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2019-12-07 18:25:29,365 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:29,367 INFO L264 TraceCheckSpWp]: Trace formula consists of 497 conjuncts, 83 conjunts are in the unsatisfiable core [2019-12-07 18:25:29,368 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:29,378 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:29,378 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:29,379 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [83, 83] total 83 [2019-12-07 18:25:29,379 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103230566] [2019-12-07 18:25:29,379 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:29,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:29,379 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 165 times [2019-12-07 18:25:29,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:29,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155349863] [2019-12-07 18:25:29,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:29,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:29,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:29,380 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:29,381 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:29,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2019-12-07 18:25:29,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2019-12-07 18:25:29,382 INFO L87 Difference]: Start difference. First operand 172 states and 258 transitions. cyclomatic complexity: 89 Second operand 84 states. [2019-12-07 18:25:29,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:29,481 INFO L93 Difference]: Finished difference Result 174 states and 260 transitions. [2019-12-07 18:25:29,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2019-12-07 18:25:29,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 260 transitions. [2019-12-07 18:25:29,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:29,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 173 states and 259 transitions. [2019-12-07 18:25:29,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:29,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:29,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173 states and 259 transitions. [2019-12-07 18:25:29,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:29,482 INFO L688 BuchiCegarLoop]: Abstraction has 173 states and 259 transitions. [2019-12-07 18:25:29,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states and 259 transitions. [2019-12-07 18:25:29,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2019-12-07 18:25:29,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2019-12-07 18:25:29,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 259 transitions. [2019-12-07 18:25:29,483 INFO L711 BuchiCegarLoop]: Abstraction has 173 states and 259 transitions. [2019-12-07 18:25:29,483 INFO L591 BuchiCegarLoop]: Abstraction has 173 states and 259 transitions. [2019-12-07 18:25:29,483 INFO L424 BuchiCegarLoop]: ======== Iteration 167============ [2019-12-07 18:25:29,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173 states and 259 transitions. [2019-12-07 18:25:29,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:29,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:29,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:29,484 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [83, 1, 1, 1, 1] [2019-12-07 18:25:29,484 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:29,484 INFO L794 eck$LassoCheckResult]: Stem: 162474#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 162475#L12 main_~i~0 := 0; 162476#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162482#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162483#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162646#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162644#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162642#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162640#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162638#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162636#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162634#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162632#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162630#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162628#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162626#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162624#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162622#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162620#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162618#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162616#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162614#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162612#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162610#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162608#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162546#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162544#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162540#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162538#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162530#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162528#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162526#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162524#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162522#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162520#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162518#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162516#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162514#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162512#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162510#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162508#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162506#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162504#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162502#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162500#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162498#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162496#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162494#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162492#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162490#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162488#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 162486#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 162477#L15-2 assume main_~i~0 >= 100; 162478#L25 [2019-12-07 18:25:29,484 INFO L796 eck$LassoCheckResult]: Loop: 162478#L25 assume true; 162478#L25 [2019-12-07 18:25:29,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:29,484 INFO L82 PathProgramCache]: Analyzing trace with hash 604401873, now seen corresponding path program 83 times [2019-12-07 18:25:29,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:29,485 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642999983] [2019-12-07 18:25:29,485 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:29,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:31,416 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:31,417 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642999983] [2019-12-07 18:25:31,417 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [606172766] [2019-12-07 18:25:31,417 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 169 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 169 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:31,482 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 43 check-sat command(s) [2019-12-07 18:25:31,482 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:31,484 INFO L264 TraceCheckSpWp]: Trace formula consists of 339 conjuncts, 85 conjunts are in the unsatisfiable core [2019-12-07 18:25:31,484 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:31,495 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:31,495 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:31,495 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [85, 85] total 85 [2019-12-07 18:25:31,495 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204492476] [2019-12-07 18:25:31,496 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:31,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:31,496 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 166 times [2019-12-07 18:25:31,496 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:31,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098330283] [2019-12-07 18:25:31,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:31,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:31,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:31,496 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:31,498 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:31,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2019-12-07 18:25:31,498 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2019-12-07 18:25:31,498 INFO L87 Difference]: Start difference. First operand 173 states and 259 transitions. cyclomatic complexity: 89 Second operand 86 states. [2019-12-07 18:25:32,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:32,539 INFO L93 Difference]: Finished difference Result 3832 states and 3921 transitions. [2019-12-07 18:25:32,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 18:25:32,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3832 states and 3921 transitions. [2019-12-07 18:25:32,546 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:32,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3832 states to 3831 states and 3920 transitions. [2019-12-07 18:25:32,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:32,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:32,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3831 states and 3920 transitions. [2019-12-07 18:25:32,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:32,550 INFO L688 BuchiCegarLoop]: Abstraction has 3831 states and 3920 transitions. [2019-12-07 18:25:32,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3831 states and 3920 transitions. [2019-12-07 18:25:32,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3831 to 174. [2019-12-07 18:25:32,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2019-12-07 18:25:32,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 261 transitions. [2019-12-07 18:25:32,555 INFO L711 BuchiCegarLoop]: Abstraction has 174 states and 261 transitions. [2019-12-07 18:25:32,555 INFO L591 BuchiCegarLoop]: Abstraction has 174 states and 261 transitions. [2019-12-07 18:25:32,555 INFO L424 BuchiCegarLoop]: ======== Iteration 168============ [2019-12-07 18:25:32,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 174 states and 261 transitions. [2019-12-07 18:25:32,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:32,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:32,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:32,556 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [82, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:32,556 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:32,556 INFO L794 eck$LassoCheckResult]: Stem: 166826#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 166827#L12 main_~i~0 := 0; 166828#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 166831#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 166832#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166836#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166999#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166998#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166997#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166996#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166995#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166994#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166993#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166992#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166991#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166990#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166989#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166988#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166987#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166986#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166985#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166984#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166983#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166982#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166981#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166980#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166979#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166978#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166977#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166976#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166975#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166974#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166973#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166972#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166971#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166970#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166969#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166968#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166967#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166966#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166965#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166964#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166963#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166962#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166961#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166960#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166959#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166958#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166957#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166956#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166955#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166954#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166953#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166952#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166951#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166950#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166949#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166948#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166947#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166946#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166945#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166944#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166943#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166942#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166941#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166940#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166939#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166938#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166937#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166936#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166935#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166934#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166933#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166932#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166931#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166930#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166929#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166928#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166927#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166926#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166925#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166924#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166923#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166922#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166921#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166920#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 166919#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 166833#L21-2 assume main_~j~0 >= 100; 166830#L25 [2019-12-07 18:25:32,556 INFO L796 eck$LassoCheckResult]: Loop: 166830#L25 assume true; 166830#L25 [2019-12-07 18:25:32,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:32,556 INFO L82 PathProgramCache]: Analyzing trace with hash 496374454, now seen corresponding path program 82 times [2019-12-07 18:25:32,556 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:32,556 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745522521] [2019-12-07 18:25:32,556 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:32,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:34,453 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:34,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745522521] [2019-12-07 18:25:34,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1967459053] [2019-12-07 18:25:34,454 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 170 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 170 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:34,511 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:25:34,512 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:34,513 INFO L264 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 84 conjunts are in the unsatisfiable core [2019-12-07 18:25:34,514 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:34,525 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:34,525 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:34,525 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [84, 84] total 84 [2019-12-07 18:25:34,525 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005949745] [2019-12-07 18:25:34,525 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:34,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:34,525 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 167 times [2019-12-07 18:25:34,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:34,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039086011] [2019-12-07 18:25:34,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:34,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:34,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:34,526 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:34,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:34,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2019-12-07 18:25:34,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3570, Invalid=3570, Unknown=0, NotChecked=0, Total=7140 [2019-12-07 18:25:34,528 INFO L87 Difference]: Start difference. First operand 174 states and 261 transitions. cyclomatic complexity: 90 Second operand 85 states. [2019-12-07 18:25:34,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:34,599 INFO L93 Difference]: Finished difference Result 176 states and 263 transitions. [2019-12-07 18:25:34,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2019-12-07 18:25:34,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 263 transitions. [2019-12-07 18:25:34,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:34,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 175 states and 262 transitions. [2019-12-07 18:25:34,600 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:34,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:34,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175 states and 262 transitions. [2019-12-07 18:25:34,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:34,600 INFO L688 BuchiCegarLoop]: Abstraction has 175 states and 262 transitions. [2019-12-07 18:25:34,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states and 262 transitions. [2019-12-07 18:25:34,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2019-12-07 18:25:34,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2019-12-07 18:25:34,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 262 transitions. [2019-12-07 18:25:34,601 INFO L711 BuchiCegarLoop]: Abstraction has 175 states and 262 transitions. [2019-12-07 18:25:34,601 INFO L591 BuchiCegarLoop]: Abstraction has 175 states and 262 transitions. [2019-12-07 18:25:34,601 INFO L424 BuchiCegarLoop]: ======== Iteration 169============ [2019-12-07 18:25:34,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 175 states and 262 transitions. [2019-12-07 18:25:34,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:34,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:34,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:34,601 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [84, 1, 1, 1, 1] [2019-12-07 18:25:34,601 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:34,601 INFO L794 eck$LassoCheckResult]: Stem: 167525#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 167526#L12 main_~i~0 := 0; 167527#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167533#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167699#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167697#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167695#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167693#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167691#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167689#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167687#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167685#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167683#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167681#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167679#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167677#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167675#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167673#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167671#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167669#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167667#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167665#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167663#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167661#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167659#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167657#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167655#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167653#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167651#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167649#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167647#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167645#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167643#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167641#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167639#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167637#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167635#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167633#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167631#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167629#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167627#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167625#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167623#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167621#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167619#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167617#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167615#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167613#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167611#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167609#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167607#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167605#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167603#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167601#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167599#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167597#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167595#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167593#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167591#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167589#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167587#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167585#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167583#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167581#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167579#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167577#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167575#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167573#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167571#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167569#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167567#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167565#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167563#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167561#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167559#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167557#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167555#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167553#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167551#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167549#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167547#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167545#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167543#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167541#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167539#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 167537#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 167528#L15-2 assume main_~i~0 >= 100; 167529#L25 [2019-12-07 18:25:34,601 INFO L796 eck$LassoCheckResult]: Loop: 167529#L25 assume true; 167529#L25 [2019-12-07 18:25:34,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:34,602 INFO L82 PathProgramCache]: Analyzing trace with hash 1556590571, now seen corresponding path program 84 times [2019-12-07 18:25:34,602 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:34,602 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237420915] [2019-12-07 18:25:34,602 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:34,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:36,629 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:36,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237420915] [2019-12-07 18:25:36,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [783076519] [2019-12-07 18:25:36,629 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 171 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 171 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:36,693 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2019-12-07 18:25:36,693 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:36,695 INFO L264 TraceCheckSpWp]: Trace formula consists of 343 conjuncts, 86 conjunts are in the unsatisfiable core [2019-12-07 18:25:36,695 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:36,706 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:36,706 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:36,706 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [86, 86] total 86 [2019-12-07 18:25:36,706 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429013966] [2019-12-07 18:25:36,707 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:36,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:36,707 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 168 times [2019-12-07 18:25:36,707 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:36,707 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879594097] [2019-12-07 18:25:36,707 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:36,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:36,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:36,707 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:36,709 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:36,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2019-12-07 18:25:36,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3741, Invalid=3741, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 18:25:36,709 INFO L87 Difference]: Start difference. First operand 175 states and 262 transitions. cyclomatic complexity: 90 Second operand 87 states. [2019-12-07 18:25:37,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:37,724 INFO L93 Difference]: Finished difference Result 3920 states and 4010 transitions. [2019-12-07 18:25:37,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2019-12-07 18:25:37,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3920 states and 4010 transitions. [2019-12-07 18:25:37,730 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:37,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3920 states to 3919 states and 4009 transitions. [2019-12-07 18:25:37,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:37,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:37,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3919 states and 4009 transitions. [2019-12-07 18:25:37,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:37,735 INFO L688 BuchiCegarLoop]: Abstraction has 3919 states and 4009 transitions. [2019-12-07 18:25:37,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3919 states and 4009 transitions. [2019-12-07 18:25:37,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3919 to 176. [2019-12-07 18:25:37,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2019-12-07 18:25:37,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 264 transitions. [2019-12-07 18:25:37,739 INFO L711 BuchiCegarLoop]: Abstraction has 176 states and 264 transitions. [2019-12-07 18:25:37,739 INFO L591 BuchiCegarLoop]: Abstraction has 176 states and 264 transitions. [2019-12-07 18:25:37,739 INFO L424 BuchiCegarLoop]: ======== Iteration 170============ [2019-12-07 18:25:37,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 264 transitions. [2019-12-07 18:25:37,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:37,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:37,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:37,740 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [83, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:37,740 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:37,740 INFO L794 eck$LassoCheckResult]: Stem: 171971#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 171972#L12 main_~i~0 := 0; 171973#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 171976#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 171977#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 171981#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172139#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172138#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172137#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172136#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172135#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172134#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172133#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172132#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172131#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172130#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172129#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172128#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172127#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172126#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172125#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172124#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172123#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172122#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172121#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172120#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172119#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172118#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172117#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172116#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172115#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172114#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172113#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172112#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172111#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172110#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172109#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172108#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172107#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172106#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172105#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172104#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172103#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172102#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172101#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172100#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172099#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172098#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172097#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172096#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172095#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172094#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172093#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172092#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172091#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172090#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172089#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172088#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172087#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172086#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172085#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172084#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172083#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172082#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172081#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172080#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172079#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172078#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172077#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172076#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172075#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172074#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172073#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172072#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172071#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172070#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172069#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172068#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172067#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172066#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 172065#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 171978#L21-2 assume main_~j~0 >= 100; 171975#L25 [2019-12-07 18:25:37,740 INFO L796 eck$LassoCheckResult]: Loop: 171975#L25 assume true; 171975#L25 [2019-12-07 18:25:37,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:37,740 INFO L82 PathProgramCache]: Analyzing trace with hash -1792259400, now seen corresponding path program 83 times [2019-12-07 18:25:37,740 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:37,741 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430747058] [2019-12-07 18:25:37,741 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:37,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:39,686 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:39,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430747058] [2019-12-07 18:25:39,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [486763410] [2019-12-07 18:25:39,687 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 172 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 172 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:39,780 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 43 check-sat command(s) [2019-12-07 18:25:39,780 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:39,783 INFO L264 TraceCheckSpWp]: Trace formula consists of 509 conjuncts, 85 conjunts are in the unsatisfiable core [2019-12-07 18:25:39,783 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:39,794 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:39,794 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:39,795 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [85, 85] total 85 [2019-12-07 18:25:39,795 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989163852] [2019-12-07 18:25:39,795 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:39,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:39,795 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 169 times [2019-12-07 18:25:39,795 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:39,795 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670075786] [2019-12-07 18:25:39,795 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:39,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:39,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:39,796 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:39,798 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:39,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2019-12-07 18:25:39,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2019-12-07 18:25:39,798 INFO L87 Difference]: Start difference. First operand 176 states and 264 transitions. cyclomatic complexity: 91 Second operand 86 states. [2019-12-07 18:25:39,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:39,897 INFO L93 Difference]: Finished difference Result 178 states and 266 transitions. [2019-12-07 18:25:39,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 18:25:39,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 266 transitions. [2019-12-07 18:25:39,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:39,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 177 states and 265 transitions. [2019-12-07 18:25:39,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:39,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:39,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177 states and 265 transitions. [2019-12-07 18:25:39,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:39,898 INFO L688 BuchiCegarLoop]: Abstraction has 177 states and 265 transitions. [2019-12-07 18:25:39,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states and 265 transitions. [2019-12-07 18:25:39,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2019-12-07 18:25:39,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2019-12-07 18:25:39,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 265 transitions. [2019-12-07 18:25:39,899 INFO L711 BuchiCegarLoop]: Abstraction has 177 states and 265 transitions. [2019-12-07 18:25:39,899 INFO L591 BuchiCegarLoop]: Abstraction has 177 states and 265 transitions. [2019-12-07 18:25:39,899 INFO L424 BuchiCegarLoop]: ======== Iteration 171============ [2019-12-07 18:25:39,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 265 transitions. [2019-12-07 18:25:39,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:39,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:39,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:39,899 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [85, 1, 1, 1, 1] [2019-12-07 18:25:39,900 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:39,900 INFO L794 eck$LassoCheckResult]: Stem: 172678#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 172679#L12 main_~i~0 := 0; 172680#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172686#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172687#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172846#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172844#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172840#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172838#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172834#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172832#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172830#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172828#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172826#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172824#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172822#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172820#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172818#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172816#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172814#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172812#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172810#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172808#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172806#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172804#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172802#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172800#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172798#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172796#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172794#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172792#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172790#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172788#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172786#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172784#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172782#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172780#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172778#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172776#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172774#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172772#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172770#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172768#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172766#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172764#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172762#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172760#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172758#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172756#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172754#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172752#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172750#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172748#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172746#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172744#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172742#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172740#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172738#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172736#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172734#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172732#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172730#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172728#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172726#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172724#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172722#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172720#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172718#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172716#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172714#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172712#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172710#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172708#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172706#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172704#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172702#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172700#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172698#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172696#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172694#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172692#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 172690#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 172681#L15-2 assume main_~i~0 >= 100; 172682#L25 [2019-12-07 18:25:39,900 INFO L796 eck$LassoCheckResult]: Loop: 172682#L25 assume true; 172682#L25 [2019-12-07 18:25:39,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:39,900 INFO L82 PathProgramCache]: Analyzing trace with hash 1009669137, now seen corresponding path program 85 times [2019-12-07 18:25:39,900 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:39,900 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037777804] [2019-12-07 18:25:39,900 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:39,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:41,930 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:41,930 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037777804] [2019-12-07 18:25:41,930 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [930107999] [2019-12-07 18:25:41,930 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 173 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 173 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:41,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:41,972 INFO L264 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 87 conjunts are in the unsatisfiable core [2019-12-07 18:25:41,973 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:41,984 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:41,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:41,985 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [87, 87] total 87 [2019-12-07 18:25:41,985 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500161634] [2019-12-07 18:25:41,985 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:41,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:41,985 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 170 times [2019-12-07 18:25:41,985 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:41,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141551606] [2019-12-07 18:25:41,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:41,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:41,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:41,986 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:41,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:41,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2019-12-07 18:25:41,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2019-12-07 18:25:41,988 INFO L87 Difference]: Start difference. First operand 177 states and 265 transitions. cyclomatic complexity: 91 Second operand 88 states. [2019-12-07 18:25:43,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:43,064 INFO L93 Difference]: Finished difference Result 4009 states and 4100 transitions. [2019-12-07 18:25:43,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-12-07 18:25:43,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4009 states and 4100 transitions. [2019-12-07 18:25:43,077 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:43,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4009 states to 4008 states and 4099 transitions. [2019-12-07 18:25:43,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:43,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:43,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4008 states and 4099 transitions. [2019-12-07 18:25:43,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:43,085 INFO L688 BuchiCegarLoop]: Abstraction has 4008 states and 4099 transitions. [2019-12-07 18:25:43,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4008 states and 4099 transitions. [2019-12-07 18:25:43,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4008 to 178. [2019-12-07 18:25:43,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2019-12-07 18:25:43,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 267 transitions. [2019-12-07 18:25:43,091 INFO L711 BuchiCegarLoop]: Abstraction has 178 states and 267 transitions. [2019-12-07 18:25:43,091 INFO L591 BuchiCegarLoop]: Abstraction has 178 states and 267 transitions. [2019-12-07 18:25:43,091 INFO L424 BuchiCegarLoop]: ======== Iteration 172============ [2019-12-07 18:25:43,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 267 transitions. [2019-12-07 18:25:43,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:43,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:43,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:43,092 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [84, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:43,092 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:43,092 INFO L794 eck$LassoCheckResult]: Stem: 177219#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 177220#L12 main_~i~0 := 0; 177221#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 177224#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 177225#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177229#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177396#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177395#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177394#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177393#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177392#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177391#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177390#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177389#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177388#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177387#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177386#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177385#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177384#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177383#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177382#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177381#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177379#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177378#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177377#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177376#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177375#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177374#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177373#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177372#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177371#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177369#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177368#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177367#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177362#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177360#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177359#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177358#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177356#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177355#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177354#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177353#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177352#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177351#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177350#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177349#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177348#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177347#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177346#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177345#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177344#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177343#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177342#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177341#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177340#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177339#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177338#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177337#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177336#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177335#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177334#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177333#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177332#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177331#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177330#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177329#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177328#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177327#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177326#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177325#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177324#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177323#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177322#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177321#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177320#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177319#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177318#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177317#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177316#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177315#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 177314#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 177226#L21-2 assume main_~j~0 >= 100; 177223#L25 [2019-12-07 18:25:43,092 INFO L796 eck$LassoCheckResult]: Loop: 177223#L25 assume true; 177223#L25 [2019-12-07 18:25:43,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:43,093 INFO L82 PathProgramCache]: Analyzing trace with hash 274535158, now seen corresponding path program 84 times [2019-12-07 18:25:43,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:43,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839184555] [2019-12-07 18:25:43,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:43,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:45,090 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:45,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839184555] [2019-12-07 18:25:45,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [720620144] [2019-12-07 18:25:45,091 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 174 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 174 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:45,183 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2019-12-07 18:25:45,183 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:45,185 INFO L264 TraceCheckSpWp]: Trace formula consists of 515 conjuncts, 86 conjunts are in the unsatisfiable core [2019-12-07 18:25:45,186 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:45,197 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:45,197 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:45,197 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [86, 86] total 86 [2019-12-07 18:25:45,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464957914] [2019-12-07 18:25:45,198 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:45,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:45,198 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 171 times [2019-12-07 18:25:45,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:45,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367256917] [2019-12-07 18:25:45,198 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:45,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:45,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:45,199 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:45,200 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:45,200 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2019-12-07 18:25:45,201 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3741, Invalid=3741, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 18:25:45,201 INFO L87 Difference]: Start difference. First operand 178 states and 267 transitions. cyclomatic complexity: 92 Second operand 87 states. [2019-12-07 18:25:45,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:45,306 INFO L93 Difference]: Finished difference Result 180 states and 269 transitions. [2019-12-07 18:25:45,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2019-12-07 18:25:45,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 269 transitions. [2019-12-07 18:25:45,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:45,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 179 states and 268 transitions. [2019-12-07 18:25:45,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:45,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:45,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 268 transitions. [2019-12-07 18:25:45,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:45,307 INFO L688 BuchiCegarLoop]: Abstraction has 179 states and 268 transitions. [2019-12-07 18:25:45,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 268 transitions. [2019-12-07 18:25:45,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2019-12-07 18:25:45,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2019-12-07 18:25:45,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 268 transitions. [2019-12-07 18:25:45,308 INFO L711 BuchiCegarLoop]: Abstraction has 179 states and 268 transitions. [2019-12-07 18:25:45,308 INFO L591 BuchiCegarLoop]: Abstraction has 179 states and 268 transitions. [2019-12-07 18:25:45,308 INFO L424 BuchiCegarLoop]: ======== Iteration 173============ [2019-12-07 18:25:45,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 268 transitions. [2019-12-07 18:25:45,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:45,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:45,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:45,309 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [86, 1, 1, 1, 1] [2019-12-07 18:25:45,309 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:45,309 INFO L794 eck$LassoCheckResult]: Stem: 177934#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 177935#L12 main_~i~0 := 0; 177936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177943#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178106#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178104#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178100#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178094#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178090#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178088#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178050#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178048#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178044#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178042#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178040#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178038#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178036#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178034#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178032#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178030#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178028#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178026#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178024#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178022#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178020#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178018#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178016#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178014#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178012#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178010#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178008#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178006#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178004#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178002#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 178000#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177998#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177996#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177994#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177992#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177990#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177988#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177986#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177984#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177980#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177978#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177974#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177972#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177970#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177968#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177966#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177964#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177962#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177960#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177958#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177956#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177954#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177952#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177950#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177948#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 177946#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 177937#L15-2 assume main_~i~0 >= 100; 177938#L25 [2019-12-07 18:25:45,309 INFO L796 eck$LassoCheckResult]: Loop: 177938#L25 assume true; 177938#L25 [2019-12-07 18:25:45,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:45,309 INFO L82 PathProgramCache]: Analyzing trace with hash 1234973867, now seen corresponding path program 86 times [2019-12-07 18:25:45,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:45,309 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663179774] [2019-12-07 18:25:45,309 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:45,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:47,411 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:47,411 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663179774] [2019-12-07 18:25:47,411 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [938441479] [2019-12-07 18:25:47,411 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 175 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 175 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:47,451 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:25:47,452 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:47,453 INFO L264 TraceCheckSpWp]: Trace formula consists of 351 conjuncts, 88 conjunts are in the unsatisfiable core [2019-12-07 18:25:47,454 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:47,465 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:47,465 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:47,465 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [88, 88] total 88 [2019-12-07 18:25:47,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983847477] [2019-12-07 18:25:47,466 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:47,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:47,466 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 172 times [2019-12-07 18:25:47,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:47,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851586793] [2019-12-07 18:25:47,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:47,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:47,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:47,467 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:47,468 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:47,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2019-12-07 18:25:47,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3916, Invalid=3916, Unknown=0, NotChecked=0, Total=7832 [2019-12-07 18:25:47,469 INFO L87 Difference]: Start difference. First operand 179 states and 268 transitions. cyclomatic complexity: 92 Second operand 89 states. [2019-12-07 18:25:48,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:48,721 INFO L93 Difference]: Finished difference Result 4099 states and 4191 transitions. [2019-12-07 18:25:48,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2019-12-07 18:25:48,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4099 states and 4191 transitions. [2019-12-07 18:25:48,728 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:48,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4099 states to 4098 states and 4190 transitions. [2019-12-07 18:25:48,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:48,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:48,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4098 states and 4190 transitions. [2019-12-07 18:25:48,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:48,733 INFO L688 BuchiCegarLoop]: Abstraction has 4098 states and 4190 transitions. [2019-12-07 18:25:48,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4098 states and 4190 transitions. [2019-12-07 18:25:48,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4098 to 180. [2019-12-07 18:25:48,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2019-12-07 18:25:48,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 270 transitions. [2019-12-07 18:25:48,738 INFO L711 BuchiCegarLoop]: Abstraction has 180 states and 270 transitions. [2019-12-07 18:25:48,738 INFO L591 BuchiCegarLoop]: Abstraction has 180 states and 270 transitions. [2019-12-07 18:25:48,738 INFO L424 BuchiCegarLoop]: ======== Iteration 174============ [2019-12-07 18:25:48,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 270 transitions. [2019-12-07 18:25:48,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:48,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:48,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:48,738 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [85, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:48,738 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:48,739 INFO L794 eck$LassoCheckResult]: Stem: 182571#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 182572#L12 main_~i~0 := 0; 182573#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 182576#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 182577#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182581#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182750#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182749#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182748#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182747#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182746#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182745#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182744#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182743#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182742#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182741#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182740#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182739#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182738#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182737#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182736#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182735#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182734#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182733#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182732#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182731#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182730#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182729#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182728#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182727#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182726#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182725#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182724#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182723#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182722#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182721#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182720#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182719#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182718#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182717#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182716#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182715#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182714#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182713#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182712#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182711#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182710#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182709#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182708#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182707#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182706#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182704#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182703#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182702#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182700#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182699#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182698#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182697#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182696#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182695#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182694#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182693#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182692#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182691#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182690#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182689#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182688#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182687#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182686#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182685#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182684#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182683#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182682#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182681#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182680#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182679#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182678#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182677#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182676#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182675#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182674#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182673#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182672#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182671#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182670#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182669#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182668#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 182667#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 182578#L21-2 assume main_~j~0 >= 100; 182575#L25 [2019-12-07 18:25:48,739 INFO L796 eck$LassoCheckResult]: Loop: 182575#L25 assume true; 182575#L25 [2019-12-07 18:25:48,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:48,739 INFO L82 PathProgramCache]: Analyzing trace with hash -79342984, now seen corresponding path program 85 times [2019-12-07 18:25:48,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:48,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907149294] [2019-12-07 18:25:48,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:48,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:50,780 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:50,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907149294] [2019-12-07 18:25:50,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [249523994] [2019-12-07 18:25:50,780 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 176 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 176 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:50,837 INFO L264 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 87 conjunts are in the unsatisfiable core [2019-12-07 18:25:50,838 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:50,849 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:50,849 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:50,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [87, 87] total 87 [2019-12-07 18:25:50,850 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853472631] [2019-12-07 18:25:50,850 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:50,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:50,850 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 173 times [2019-12-07 18:25:50,850 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:50,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639107534] [2019-12-07 18:25:50,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:50,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:50,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:50,851 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:50,852 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:50,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2019-12-07 18:25:50,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2019-12-07 18:25:50,853 INFO L87 Difference]: Start difference. First operand 180 states and 270 transitions. cyclomatic complexity: 93 Second operand 88 states. [2019-12-07 18:25:50,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:50,933 INFO L93 Difference]: Finished difference Result 182 states and 272 transitions. [2019-12-07 18:25:50,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-12-07 18:25:50,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182 states and 272 transitions. [2019-12-07 18:25:50,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:50,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182 states to 181 states and 271 transitions. [2019-12-07 18:25:50,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:50,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:50,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:50,935 INFO L688 BuchiCegarLoop]: Abstraction has 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 181. [2019-12-07 18:25:50,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 181 states. [2019-12-07 18:25:50,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L711 BuchiCegarLoop]: Abstraction has 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L591 BuchiCegarLoop]: Abstraction has 181 states and 271 transitions. [2019-12-07 18:25:50,935 INFO L424 BuchiCegarLoop]: ======== Iteration 175============ [2019-12-07 18:25:50,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181 states and 271 transitions. [2019-12-07 18:25:50,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:50,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:50,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:50,936 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [87, 1, 1, 1, 1] [2019-12-07 18:25:50,936 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:50,936 INFO L794 eck$LassoCheckResult]: Stem: 183294#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 183295#L12 main_~i~0 := 0; 183296#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183302#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183303#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183474#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183472#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183470#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183468#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183466#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183464#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183462#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183460#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183458#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183456#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183454#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183452#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183450#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183448#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183446#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183444#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183442#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183440#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183438#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183436#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183434#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183432#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183430#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183428#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183426#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183424#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183422#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183420#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183418#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183416#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183414#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183412#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183410#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183408#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183406#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183404#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183402#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183400#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183398#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183396#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183394#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183392#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183390#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183388#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183386#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183384#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183382#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183380#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183378#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183376#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183374#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183372#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183370#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183368#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183366#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183364#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183362#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183360#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183358#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183356#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183354#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183352#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183350#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183348#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183346#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183344#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183342#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183340#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183338#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183336#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183334#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183332#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183330#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183328#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183326#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183324#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183322#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183320#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183318#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183316#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183314#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183312#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183310#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183308#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 183306#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 183297#L15-2 assume main_~i~0 >= 100; 183298#L25 [2019-12-07 18:25:50,936 INFO L796 eck$LassoCheckResult]: Loop: 183298#L25 assume true; 183298#L25 [2019-12-07 18:25:50,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:50,936 INFO L82 PathProgramCache]: Analyzing trace with hash -370514095, now seen corresponding path program 87 times [2019-12-07 18:25:50,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:50,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979608214] [2019-12-07 18:25:50,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:50,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:53,055 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:53,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979608214] [2019-12-07 18:25:53,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1376604304] [2019-12-07 18:25:53,055 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 177 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 177 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:53,127 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 45 check-sat command(s) [2019-12-07 18:25:53,127 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:53,129 INFO L264 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 89 conjunts are in the unsatisfiable core [2019-12-07 18:25:53,129 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:53,141 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:53,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:53,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [89, 89] total 89 [2019-12-07 18:25:53,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980943733] [2019-12-07 18:25:53,141 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:53,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:53,141 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 174 times [2019-12-07 18:25:53,142 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:53,142 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637926090] [2019-12-07 18:25:53,142 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:53,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:53,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:53,142 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:53,143 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:53,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2019-12-07 18:25:53,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2019-12-07 18:25:53,144 INFO L87 Difference]: Start difference. First operand 181 states and 271 transitions. cyclomatic complexity: 93 Second operand 90 states. [2019-12-07 18:25:54,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:54,082 INFO L93 Difference]: Finished difference Result 4190 states and 4283 transitions. [2019-12-07 18:25:54,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2019-12-07 18:25:54,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4190 states and 4283 transitions. [2019-12-07 18:25:54,088 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:54,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4190 states to 4189 states and 4282 transitions. [2019-12-07 18:25:54,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:54,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:54,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4189 states and 4282 transitions. [2019-12-07 18:25:54,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:54,093 INFO L688 BuchiCegarLoop]: Abstraction has 4189 states and 4282 transitions. [2019-12-07 18:25:54,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4189 states and 4282 transitions. [2019-12-07 18:25:54,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4189 to 182. [2019-12-07 18:25:54,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2019-12-07 18:25:54,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 273 transitions. [2019-12-07 18:25:54,097 INFO L711 BuchiCegarLoop]: Abstraction has 182 states and 273 transitions. [2019-12-07 18:25:54,097 INFO L591 BuchiCegarLoop]: Abstraction has 182 states and 273 transitions. [2019-12-07 18:25:54,098 INFO L424 BuchiCegarLoop]: ======== Iteration 176============ [2019-12-07 18:25:54,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 273 transitions. [2019-12-07 18:25:54,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:54,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:54,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:54,098 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [86, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:54,098 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:54,098 INFO L794 eck$LassoCheckResult]: Stem: 188028#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 188029#L12 main_~i~0 := 0; 188030#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 188033#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 188034#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188038#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188208#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188207#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188206#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188205#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188204#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188203#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188202#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188201#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188200#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188199#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188198#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188197#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188196#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188195#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188194#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188193#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188192#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188191#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188190#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188189#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188188#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188187#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188186#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188185#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188184#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188183#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188182#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188181#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188180#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188179#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188178#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188177#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188176#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188175#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188174#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188173#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188172#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188171#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188170#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188169#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188168#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188167#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188166#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188165#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188164#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188163#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188162#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188161#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188160#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188159#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188158#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188157#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188156#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188155#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188154#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188153#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188152#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188151#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188150#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188149#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188148#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188147#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188139#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188138#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188137#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188136#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188135#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188134#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188133#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188132#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188131#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188130#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188129#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188128#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188127#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188126#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 188125#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 188035#L21-2 assume main_~j~0 >= 100; 188032#L25 [2019-12-07 18:25:54,098 INFO L796 eck$LassoCheckResult]: Loop: 188032#L25 assume true; 188032#L25 [2019-12-07 18:25:54,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:54,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1835336502, now seen corresponding path program 86 times [2019-12-07 18:25:54,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:54,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456344962] [2019-12-07 18:25:54,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:54,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:56,248 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:56,248 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456344962] [2019-12-07 18:25:56,248 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1309543588] [2019-12-07 18:25:56,248 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 178 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 178 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:56,305 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:25:56,305 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:56,307 INFO L264 TraceCheckSpWp]: Trace formula consists of 527 conjuncts, 88 conjunts are in the unsatisfiable core [2019-12-07 18:25:56,307 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:56,319 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:56,319 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:56,319 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [88, 88] total 88 [2019-12-07 18:25:56,319 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264086187] [2019-12-07 18:25:56,319 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:56,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:56,319 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 175 times [2019-12-07 18:25:56,320 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:56,320 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086685877] [2019-12-07 18:25:56,320 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:56,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:56,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:56,320 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:56,321 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:56,322 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2019-12-07 18:25:56,322 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3916, Invalid=3916, Unknown=0, NotChecked=0, Total=7832 [2019-12-07 18:25:56,322 INFO L87 Difference]: Start difference. First operand 182 states and 273 transitions. cyclomatic complexity: 94 Second operand 89 states. [2019-12-07 18:25:56,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:56,396 INFO L93 Difference]: Finished difference Result 184 states and 275 transitions. [2019-12-07 18:25:56,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2019-12-07 18:25:56,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 275 transitions. [2019-12-07 18:25:56,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:56,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 183 states and 274 transitions. [2019-12-07 18:25:56,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:25:56,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:25:56,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:56,398 INFO L688 BuchiCegarLoop]: Abstraction has 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2019-12-07 18:25:56,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2019-12-07 18:25:56,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L711 BuchiCegarLoop]: Abstraction has 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L591 BuchiCegarLoop]: Abstraction has 183 states and 274 transitions. [2019-12-07 18:25:56,398 INFO L424 BuchiCegarLoop]: ======== Iteration 177============ [2019-12-07 18:25:56,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 183 states and 274 transitions. [2019-12-07 18:25:56,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:56,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:56,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:56,399 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [88, 1, 1, 1, 1] [2019-12-07 18:25:56,399 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:56,399 INFO L794 eck$LassoCheckResult]: Stem: 188759#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 188760#L12 main_~i~0 := 0; 188761#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188767#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188768#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188941#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188939#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188937#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188935#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188933#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188931#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188929#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188927#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188925#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188923#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188921#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188919#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188917#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188915#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188913#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188911#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188909#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188907#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188905#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188903#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188901#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188899#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188897#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188895#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188893#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188891#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188889#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188887#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188885#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188883#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188881#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188879#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188877#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188875#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188873#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188871#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188869#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188867#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188865#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188863#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188861#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188859#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188857#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188855#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188853#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188851#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188849#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188847#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188845#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188843#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188841#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188839#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188837#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188835#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188833#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188831#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188829#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188827#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188825#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188823#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188821#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188819#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188817#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188815#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188813#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188811#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188809#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188807#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188805#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188803#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188801#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188799#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188797#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188795#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188793#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188791#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188789#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188787#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188785#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188783#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188781#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188779#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188777#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188775#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188773#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 188771#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 188762#L15-2 assume main_~i~0 >= 100; 188763#L25 [2019-12-07 18:25:56,399 INFO L796 eck$LassoCheckResult]: Loop: 188763#L25 assume true; 188763#L25 [2019-12-07 18:25:56,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:56,399 INFO L82 PathProgramCache]: Analyzing trace with hash 1398966635, now seen corresponding path program 88 times [2019-12-07 18:25:56,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:56,400 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832501407] [2019-12-07 18:25:56,400 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:56,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:25:58,563 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:58,563 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832501407] [2019-12-07 18:25:58,564 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [513850209] [2019-12-07 18:25:58,564 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 179 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 179 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:25:58,605 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:25:58,605 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:25:58,607 INFO L264 TraceCheckSpWp]: Trace formula consists of 359 conjuncts, 90 conjunts are in the unsatisfiable core [2019-12-07 18:25:58,608 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:25:58,620 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:25:58,620 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:25:58,620 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [90, 90] total 90 [2019-12-07 18:25:58,620 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713408058] [2019-12-07 18:25:58,620 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:25:58,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:58,620 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 176 times [2019-12-07 18:25:58,620 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:58,620 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463117128] [2019-12-07 18:25:58,620 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:25:58,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:58,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:25:58,621 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:25:58,623 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:25:58,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-12-07 18:25:58,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4095, Invalid=4095, Unknown=0, NotChecked=0, Total=8190 [2019-12-07 18:25:58,623 INFO L87 Difference]: Start difference. First operand 183 states and 274 transitions. cyclomatic complexity: 94 Second operand 91 states. [2019-12-07 18:25:59,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:25:59,958 INFO L93 Difference]: Finished difference Result 4282 states and 4376 transitions. [2019-12-07 18:25:59,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2019-12-07 18:25:59,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4282 states and 4376 transitions. [2019-12-07 18:25:59,972 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:25:59,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4282 states to 4281 states and 4375 transitions. [2019-12-07 18:25:59,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:25:59,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:25:59,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4281 states and 4375 transitions. [2019-12-07 18:25:59,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:25:59,978 INFO L688 BuchiCegarLoop]: Abstraction has 4281 states and 4375 transitions. [2019-12-07 18:25:59,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4281 states and 4375 transitions. [2019-12-07 18:25:59,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4281 to 184. [2019-12-07 18:25:59,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2019-12-07 18:25:59,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 276 transitions. [2019-12-07 18:25:59,982 INFO L711 BuchiCegarLoop]: Abstraction has 184 states and 276 transitions. [2019-12-07 18:25:59,982 INFO L591 BuchiCegarLoop]: Abstraction has 184 states and 276 transitions. [2019-12-07 18:25:59,982 INFO L424 BuchiCegarLoop]: ======== Iteration 178============ [2019-12-07 18:25:59,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184 states and 276 transitions. [2019-12-07 18:25:59,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:25:59,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:25:59,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:25:59,983 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [87, 1, 1, 1, 1, 1, 1] [2019-12-07 18:25:59,983 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:25:59,983 INFO L794 eck$LassoCheckResult]: Stem: 193591#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 193592#L12 main_~i~0 := 0; 193593#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 193596#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 193597#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193601#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193774#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193773#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193772#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193771#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193770#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193769#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193768#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193767#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193766#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193765#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193764#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193763#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193762#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193761#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193760#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193759#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193758#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193757#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193756#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193755#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193754#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193753#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193752#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193751#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193750#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193749#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193748#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193747#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193746#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193745#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193744#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193743#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193742#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193741#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193740#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193739#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193738#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193737#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193736#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193735#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193734#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193733#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193732#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193731#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193730#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193729#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193728#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193727#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193726#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193725#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193724#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193723#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193722#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193721#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193720#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193719#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193718#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193717#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193716#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193715#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193714#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193713#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193712#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193711#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193710#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193709#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193708#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193707#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193706#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193704#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193703#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193702#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193700#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193699#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193698#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193697#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193696#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193695#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193694#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193693#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193692#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193691#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193690#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 193689#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 193598#L21-2 assume main_~j~0 >= 100; 193595#L25 [2019-12-07 18:25:59,983 INFO L796 eck$LassoCheckResult]: Loop: 193595#L25 assume true; 193595#L25 [2019-12-07 18:25:59,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:25:59,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1060858424, now seen corresponding path program 87 times [2019-12-07 18:25:59,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:25:59,984 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934468884] [2019-12-07 18:25:59,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:00,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:02,122 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:02,122 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934468884] [2019-12-07 18:26:02,122 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [412117835] [2019-12-07 18:26:02,122 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 180 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 180 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:02,223 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 45 check-sat command(s) [2019-12-07 18:26:02,223 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:02,225 INFO L264 TraceCheckSpWp]: Trace formula consists of 533 conjuncts, 89 conjunts are in the unsatisfiable core [2019-12-07 18:26:02,226 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:02,237 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:02,238 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:02,238 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [89, 89] total 89 [2019-12-07 18:26:02,238 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764149554] [2019-12-07 18:26:02,238 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:02,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:02,238 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 177 times [2019-12-07 18:26:02,238 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:02,238 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577054948] [2019-12-07 18:26:02,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:02,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:02,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:02,239 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:02,240 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:02,241 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2019-12-07 18:26:02,241 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2019-12-07 18:26:02,241 INFO L87 Difference]: Start difference. First operand 184 states and 276 transitions. cyclomatic complexity: 95 Second operand 90 states. [2019-12-07 18:26:02,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:02,374 INFO L93 Difference]: Finished difference Result 186 states and 278 transitions. [2019-12-07 18:26:02,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2019-12-07 18:26:02,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 278 transitions. [2019-12-07 18:26:02,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:02,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 185 states and 277 transitions. [2019-12-07 18:26:02,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:02,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:02,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 185 states and 277 transitions. [2019-12-07 18:26:02,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:02,376 INFO L688 BuchiCegarLoop]: Abstraction has 185 states and 277 transitions. [2019-12-07 18:26:02,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states and 277 transitions. [2019-12-07 18:26:02,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 185. [2019-12-07 18:26:02,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2019-12-07 18:26:02,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 277 transitions. [2019-12-07 18:26:02,377 INFO L711 BuchiCegarLoop]: Abstraction has 185 states and 277 transitions. [2019-12-07 18:26:02,377 INFO L591 BuchiCegarLoop]: Abstraction has 185 states and 277 transitions. [2019-12-07 18:26:02,377 INFO L424 BuchiCegarLoop]: ======== Iteration 179============ [2019-12-07 18:26:02,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 277 transitions. [2019-12-07 18:26:02,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:02,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:02,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:02,378 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [89, 1, 1, 1, 1] [2019-12-07 18:26:02,379 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:02,379 INFO L794 eck$LassoCheckResult]: Stem: 194330#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 194331#L12 main_~i~0 := 0; 194332#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194338#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194339#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194514#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194512#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194510#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194508#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194506#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194504#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194502#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194500#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194498#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194496#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194494#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194492#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194490#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194488#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194486#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194484#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194482#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194480#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194478#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194476#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194474#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194472#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194470#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194468#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194466#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194464#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194462#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194460#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194458#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194456#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194454#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194452#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194450#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194448#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194446#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194444#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194442#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194440#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194438#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194436#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194434#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194432#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194430#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194428#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194426#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194424#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194422#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194420#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194418#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194416#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194414#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194412#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194410#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194408#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194406#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194404#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194402#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194400#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194398#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194396#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194394#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194392#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194390#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194388#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194386#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194384#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194382#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194380#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194378#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194376#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194374#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194372#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194370#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194368#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194366#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194364#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194362#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194360#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194358#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194356#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194354#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194352#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194350#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194348#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194346#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194344#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 194342#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 194333#L15-2 assume main_~i~0 >= 100; 194334#L25 [2019-12-07 18:26:02,379 INFO L796 eck$LassoCheckResult]: Loop: 194334#L25 assume true; 194334#L25 [2019-12-07 18:26:02,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:02,379 INFO L82 PathProgramCache]: Analyzing trace with hash 418294417, now seen corresponding path program 89 times [2019-12-07 18:26:02,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:02,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539177332] [2019-12-07 18:26:02,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:02,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:04,599 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:04,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539177332] [2019-12-07 18:26:04,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1085811450] [2019-12-07 18:26:04,599 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 181 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 181 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:04,669 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 46 check-sat command(s) [2019-12-07 18:26:04,669 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:04,671 INFO L264 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 91 conjunts are in the unsatisfiable core [2019-12-07 18:26:04,672 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:04,684 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:04,684 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:04,684 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [91, 91] total 91 [2019-12-07 18:26:04,684 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471887421] [2019-12-07 18:26:04,684 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:04,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:04,684 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 178 times [2019-12-07 18:26:04,684 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:04,684 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963826865] [2019-12-07 18:26:04,684 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:04,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:04,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:04,685 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:04,688 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:04,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2019-12-07 18:26:04,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2019-12-07 18:26:04,689 INFO L87 Difference]: Start difference. First operand 185 states and 277 transitions. cyclomatic complexity: 95 Second operand 92 states. [2019-12-07 18:26:06,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:06,079 INFO L93 Difference]: Finished difference Result 4375 states and 4470 transitions. [2019-12-07 18:26:06,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-12-07 18:26:06,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4375 states and 4470 transitions. [2019-12-07 18:26:06,086 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:06,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4375 states to 4374 states and 4469 transitions. [2019-12-07 18:26:06,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:06,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:06,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4374 states and 4469 transitions. [2019-12-07 18:26:06,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:06,090 INFO L688 BuchiCegarLoop]: Abstraction has 4374 states and 4469 transitions. [2019-12-07 18:26:06,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4374 states and 4469 transitions. [2019-12-07 18:26:06,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4374 to 186. [2019-12-07 18:26:06,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2019-12-07 18:26:06,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 279 transitions. [2019-12-07 18:26:06,095 INFO L711 BuchiCegarLoop]: Abstraction has 186 states and 279 transitions. [2019-12-07 18:26:06,095 INFO L591 BuchiCegarLoop]: Abstraction has 186 states and 279 transitions. [2019-12-07 18:26:06,095 INFO L424 BuchiCegarLoop]: ======== Iteration 180============ [2019-12-07 18:26:06,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 279 transitions. [2019-12-07 18:26:06,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:06,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:06,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:06,096 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [88, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:06,096 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:06,096 INFO L794 eck$LassoCheckResult]: Stem: 199261#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 199262#L12 main_~i~0 := 0; 199263#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 199266#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 199267#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199271#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199446#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199445#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199444#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199443#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199442#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199440#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199439#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199438#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199437#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199436#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199435#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199434#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199433#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199432#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199431#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199430#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199429#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199428#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199427#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199426#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199425#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199424#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199423#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199422#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199421#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199420#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199419#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199418#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199417#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199416#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199415#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199414#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199413#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199412#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199411#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199410#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199409#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199408#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199407#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199406#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199405#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199404#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199403#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199402#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199401#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199400#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199399#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199398#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199397#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199396#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199395#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199394#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199393#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199392#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199391#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199390#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199389#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199388#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199387#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199386#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199385#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199384#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199383#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199382#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199381#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199379#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199378#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199377#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199376#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199375#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199374#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199373#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199372#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199371#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199369#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199368#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199367#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199362#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 199360#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 199268#L21-2 assume main_~j~0 >= 100; 199265#L25 [2019-12-07 18:26:06,096 INFO L796 eck$LassoCheckResult]: Loop: 199265#L25 assume true; 199265#L25 [2019-12-07 18:26:06,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:06,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1473125514, now seen corresponding path program 88 times [2019-12-07 18:26:06,096 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:06,096 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476837076] [2019-12-07 18:26:06,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:06,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:08,282 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:08,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476837076] [2019-12-07 18:26:08,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [798126108] [2019-12-07 18:26:08,283 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 182 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 182 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:08,342 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:26:08,342 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:08,344 INFO L264 TraceCheckSpWp]: Trace formula consists of 539 conjuncts, 90 conjunts are in the unsatisfiable core [2019-12-07 18:26:08,345 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:08,357 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:08,357 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:08,357 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [90, 90] total 90 [2019-12-07 18:26:08,357 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278094983] [2019-12-07 18:26:08,357 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:08,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:08,357 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 179 times [2019-12-07 18:26:08,357 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:08,358 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919681837] [2019-12-07 18:26:08,358 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:08,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:08,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:08,358 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:08,360 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:08,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-12-07 18:26:08,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4095, Invalid=4095, Unknown=0, NotChecked=0, Total=8190 [2019-12-07 18:26:08,360 INFO L87 Difference]: Start difference. First operand 186 states and 279 transitions. cyclomatic complexity: 96 Second operand 91 states. [2019-12-07 18:26:08,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:08,463 INFO L93 Difference]: Finished difference Result 188 states and 281 transitions. [2019-12-07 18:26:08,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2019-12-07 18:26:08,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 188 states and 281 transitions. [2019-12-07 18:26:08,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:08,464 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 188 states to 187 states and 280 transitions. [2019-12-07 18:26:08,464 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:08,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:08,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 187 states and 280 transitions. [2019-12-07 18:26:08,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:08,464 INFO L688 BuchiCegarLoop]: Abstraction has 187 states and 280 transitions. [2019-12-07 18:26:08,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states and 280 transitions. [2019-12-07 18:26:08,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2019-12-07 18:26:08,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2019-12-07 18:26:08,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 280 transitions. [2019-12-07 18:26:08,465 INFO L711 BuchiCegarLoop]: Abstraction has 187 states and 280 transitions. [2019-12-07 18:26:08,465 INFO L591 BuchiCegarLoop]: Abstraction has 187 states and 280 transitions. [2019-12-07 18:26:08,465 INFO L424 BuchiCegarLoop]: ======== Iteration 181============ [2019-12-07 18:26:08,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 187 states and 280 transitions. [2019-12-07 18:26:08,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:08,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:08,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:08,465 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [90, 1, 1, 1, 1] [2019-12-07 18:26:08,465 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:08,466 INFO L794 eck$LassoCheckResult]: Stem: 200008#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 200009#L12 main_~i~0 := 0; 200010#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200016#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200017#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200194#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200192#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200190#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200188#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200186#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200184#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200182#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200180#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200178#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200176#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200174#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200172#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200170#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200168#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200166#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200142#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200140#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200136#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200134#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200130#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200128#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200126#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200124#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200122#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200120#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200118#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200116#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200106#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200104#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200100#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200094#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200090#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200088#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200050#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200048#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200044#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200042#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200040#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200038#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200036#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200034#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200032#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200030#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200028#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200026#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200024#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200022#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 200020#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 200011#L15-2 assume main_~i~0 >= 100; 200012#L25 [2019-12-07 18:26:08,466 INFO L796 eck$LassoCheckResult]: Loop: 200012#L25 assume true; 200012#L25 [2019-12-07 18:26:08,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:08,466 INFO L82 PathProgramCache]: Analyzing trace with hash 82226731, now seen corresponding path program 90 times [2019-12-07 18:26:08,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:08,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006480165] [2019-12-07 18:26:08,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:08,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:10,735 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:10,735 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006480165] [2019-12-07 18:26:10,736 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [83458454] [2019-12-07 18:26:10,736 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 183 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 183 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:10,805 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 46 check-sat command(s) [2019-12-07 18:26:10,805 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:10,807 INFO L264 TraceCheckSpWp]: Trace formula consists of 367 conjuncts, 92 conjunts are in the unsatisfiable core [2019-12-07 18:26:10,808 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:10,820 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:10,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:10,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [92, 92] total 92 [2019-12-07 18:26:10,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202470188] [2019-12-07 18:26:10,820 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:10,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:10,820 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 180 times [2019-12-07 18:26:10,820 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:10,821 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215116881] [2019-12-07 18:26:10,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:10,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:10,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:10,821 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:10,823 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:10,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2019-12-07 18:26:10,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4278, Invalid=4278, Unknown=0, NotChecked=0, Total=8556 [2019-12-07 18:26:10,823 INFO L87 Difference]: Start difference. First operand 187 states and 280 transitions. cyclomatic complexity: 96 Second operand 93 states. [2019-12-07 18:26:12,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:12,036 INFO L93 Difference]: Finished difference Result 4469 states and 4565 transitions. [2019-12-07 18:26:12,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2019-12-07 18:26:12,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4469 states and 4565 transitions. [2019-12-07 18:26:12,042 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:12,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4469 states to 4468 states and 4564 transitions. [2019-12-07 18:26:12,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:12,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:12,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4468 states and 4564 transitions. [2019-12-07 18:26:12,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:12,046 INFO L688 BuchiCegarLoop]: Abstraction has 4468 states and 4564 transitions. [2019-12-07 18:26:12,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4468 states and 4564 transitions. [2019-12-07 18:26:12,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4468 to 188. [2019-12-07 18:26:12,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2019-12-07 18:26:12,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 282 transitions. [2019-12-07 18:26:12,051 INFO L711 BuchiCegarLoop]: Abstraction has 188 states and 282 transitions. [2019-12-07 18:26:12,051 INFO L591 BuchiCegarLoop]: Abstraction has 188 states and 282 transitions. [2019-12-07 18:26:12,051 INFO L424 BuchiCegarLoop]: ======== Iteration 182============ [2019-12-07 18:26:12,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 282 transitions. [2019-12-07 18:26:12,051 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:12,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:12,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:12,052 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [89, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:12,052 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:12,052 INFO L794 eck$LassoCheckResult]: Stem: 205039#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 205040#L12 main_~i~0 := 0; 205041#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 205044#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 205045#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205049#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205226#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205225#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205224#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205223#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205222#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205221#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205220#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205219#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205218#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205217#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205216#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205215#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205214#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205213#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205212#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205211#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205210#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205208#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205207#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205206#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205205#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205204#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205203#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205202#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205201#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205200#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205199#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205198#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205197#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205196#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205195#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205194#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205193#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205192#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205191#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205190#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205189#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205188#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205187#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205186#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205185#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205184#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205183#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205182#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205181#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205180#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205179#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205178#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205177#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205176#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205175#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205174#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205173#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205172#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205171#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205170#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205169#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205168#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205167#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205166#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205165#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205164#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205163#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205162#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205161#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205160#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205159#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205158#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205157#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205156#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205155#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205154#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205153#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205152#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205151#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205150#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205149#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205148#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205147#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 205139#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 205046#L21-2 assume main_~j~0 >= 100; 205043#L25 [2019-12-07 18:26:12,052 INFO L796 eck$LassoCheckResult]: Loop: 205043#L25 assume true; 205043#L25 [2019-12-07 18:26:12,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:12,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1577751032, now seen corresponding path program 89 times [2019-12-07 18:26:12,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:12,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49604312] [2019-12-07 18:26:12,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:12,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:14,290 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:14,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49604312] [2019-12-07 18:26:14,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1455921641] [2019-12-07 18:26:14,290 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 184 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 184 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:14,389 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 46 check-sat command(s) [2019-12-07 18:26:14,390 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:14,392 INFO L264 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 91 conjunts are in the unsatisfiable core [2019-12-07 18:26:14,393 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:14,405 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:14,405 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:14,405 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [91, 91] total 91 [2019-12-07 18:26:14,405 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676275776] [2019-12-07 18:26:14,405 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:14,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:14,405 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 181 times [2019-12-07 18:26:14,405 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:14,405 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659639298] [2019-12-07 18:26:14,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:14,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:14,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:14,406 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:14,408 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:14,408 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2019-12-07 18:26:14,408 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2019-12-07 18:26:14,408 INFO L87 Difference]: Start difference. First operand 188 states and 282 transitions. cyclomatic complexity: 97 Second operand 92 states. [2019-12-07 18:26:14,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:14,489 INFO L93 Difference]: Finished difference Result 190 states and 284 transitions. [2019-12-07 18:26:14,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-12-07 18:26:14,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190 states and 284 transitions. [2019-12-07 18:26:14,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:14,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190 states to 189 states and 283 transitions. [2019-12-07 18:26:14,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:14,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:14,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 189 states and 283 transitions. [2019-12-07 18:26:14,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:14,490 INFO L688 BuchiCegarLoop]: Abstraction has 189 states and 283 transitions. [2019-12-07 18:26:14,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states and 283 transitions. [2019-12-07 18:26:14,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2019-12-07 18:26:14,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2019-12-07 18:26:14,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 283 transitions. [2019-12-07 18:26:14,491 INFO L711 BuchiCegarLoop]: Abstraction has 189 states and 283 transitions. [2019-12-07 18:26:14,491 INFO L591 BuchiCegarLoop]: Abstraction has 189 states and 283 transitions. [2019-12-07 18:26:14,491 INFO L424 BuchiCegarLoop]: ======== Iteration 183============ [2019-12-07 18:26:14,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 189 states and 283 transitions. [2019-12-07 18:26:14,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:14,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:14,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:14,492 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [91, 1, 1, 1, 1] [2019-12-07 18:26:14,492 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:14,492 INFO L794 eck$LassoCheckResult]: Stem: 205794#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 205795#L12 main_~i~0 := 0; 205796#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205802#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205803#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205980#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205978#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205974#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205972#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205970#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205968#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205966#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205964#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205962#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205960#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205958#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205956#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205954#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205952#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205950#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205948#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205946#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205944#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205940#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205938#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205934#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205932#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205930#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205928#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205926#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205924#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205922#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205920#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205918#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205916#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205914#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205912#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205910#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205908#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205906#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205904#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205902#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205898#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205896#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205892#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205890#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205888#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205886#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205884#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205880#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205878#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205866#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205864#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205860#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205858#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205846#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205844#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205840#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205838#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205834#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205832#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205830#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205828#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205826#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205824#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205822#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205820#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205818#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205816#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205814#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205812#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205810#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205808#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 205806#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 205797#L15-2 assume main_~i~0 >= 100; 205798#L25 [2019-12-07 18:26:14,492 INFO L796 eck$LassoCheckResult]: Loop: 205798#L25 assume true; 205798#L25 [2019-12-07 18:26:14,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:14,492 INFO L82 PathProgramCache]: Analyzing trace with hash -1745936943, now seen corresponding path program 91 times [2019-12-07 18:26:14,492 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:14,492 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366365831] [2019-12-07 18:26:14,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:14,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:16,827 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:16,827 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366365831] [2019-12-07 18:26:16,827 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [727435333] [2019-12-07 18:26:16,827 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 185 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 185 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:16,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:16,877 INFO L264 TraceCheckSpWp]: Trace formula consists of 371 conjuncts, 93 conjunts are in the unsatisfiable core [2019-12-07 18:26:16,878 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:16,899 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:16,900 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:16,900 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [93, 93] total 93 [2019-12-07 18:26:16,900 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566174728] [2019-12-07 18:26:16,900 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:16,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:16,900 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 182 times [2019-12-07 18:26:16,900 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:16,900 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732943946] [2019-12-07 18:26:16,900 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:16,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:16,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:16,901 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:16,903 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:16,903 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-12-07 18:26:16,903 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2019-12-07 18:26:16,903 INFO L87 Difference]: Start difference. First operand 189 states and 283 transitions. cyclomatic complexity: 97 Second operand 94 states. [2019-12-07 18:26:18,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:18,188 INFO L93 Difference]: Finished difference Result 4564 states and 4661 transitions. [2019-12-07 18:26:18,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2019-12-07 18:26:18,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4564 states and 4661 transitions. [2019-12-07 18:26:18,195 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:18,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4564 states to 4563 states and 4660 transitions. [2019-12-07 18:26:18,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:18,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:18,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4563 states and 4660 transitions. [2019-12-07 18:26:18,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:18,200 INFO L688 BuchiCegarLoop]: Abstraction has 4563 states and 4660 transitions. [2019-12-07 18:26:18,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4563 states and 4660 transitions. [2019-12-07 18:26:18,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4563 to 190. [2019-12-07 18:26:18,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2019-12-07 18:26:18,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 285 transitions. [2019-12-07 18:26:18,205 INFO L711 BuchiCegarLoop]: Abstraction has 190 states and 285 transitions. [2019-12-07 18:26:18,205 INFO L591 BuchiCegarLoop]: Abstraction has 190 states and 285 transitions. [2019-12-07 18:26:18,205 INFO L424 BuchiCegarLoop]: ======== Iteration 184============ [2019-12-07 18:26:18,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 285 transitions. [2019-12-07 18:26:18,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:18,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:18,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:18,206 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [90, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:18,206 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:18,206 INFO L794 eck$LassoCheckResult]: Stem: 210926#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 210927#L12 main_~i~0 := 0; 210928#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 210931#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 210932#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 210936#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211115#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211114#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211113#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211112#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211111#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211110#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211109#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211108#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211107#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211106#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211105#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211104#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211103#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211102#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211101#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211100#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211099#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211098#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211097#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211096#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211095#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211094#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211093#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211092#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211091#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211090#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211089#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211088#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211087#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211086#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211085#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211084#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211083#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211082#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211081#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211080#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211079#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211078#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211077#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211076#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211075#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211074#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211073#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211072#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211071#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211070#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211069#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211068#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211067#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211066#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211065#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211064#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211063#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211062#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211061#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211060#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211059#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211058#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211057#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211056#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211055#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211054#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211053#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211052#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211051#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211050#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211049#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211048#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211047#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211046#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211045#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211044#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211043#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211042#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211041#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211040#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211039#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211038#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211037#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211036#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211035#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211034#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211033#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211032#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211031#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211030#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211029#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211028#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 211027#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 210933#L21-2 assume main_~j~0 >= 100; 210930#L25 [2019-12-07 18:26:18,206 INFO L796 eck$LassoCheckResult]: Loop: 210930#L25 assume true; 210930#L25 [2019-12-07 18:26:18,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:18,206 INFO L82 PathProgramCache]: Analyzing trace with hash 1665643446, now seen corresponding path program 90 times [2019-12-07 18:26:18,206 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:18,207 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679963994] [2019-12-07 18:26:18,207 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:18,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,475 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,475 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679963994] [2019-12-07 18:26:20,475 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1878997624] [2019-12-07 18:26:20,475 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 186 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 186 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:20,578 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 46 check-sat command(s) [2019-12-07 18:26:20,578 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:20,580 INFO L264 TraceCheckSpWp]: Trace formula consists of 551 conjuncts, 92 conjunts are in the unsatisfiable core [2019-12-07 18:26:20,581 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:20,593 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,593 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:20,594 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [92, 92] total 92 [2019-12-07 18:26:20,594 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187150348] [2019-12-07 18:26:20,594 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,594 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 183 times [2019-12-07 18:26:20,594 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,594 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526374771] [2019-12-07 18:26:20,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:20,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:20,595 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:20,600 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2019-12-07 18:26:20,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4278, Invalid=4278, Unknown=0, NotChecked=0, Total=8556 [2019-12-07 18:26:20,601 INFO L87 Difference]: Start difference. First operand 190 states and 285 transitions. cyclomatic complexity: 98 Second operand 93 states. [2019-12-07 18:26:20,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,700 INFO L93 Difference]: Finished difference Result 192 states and 287 transitions. [2019-12-07 18:26:20,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2019-12-07 18:26:20,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192 states and 287 transitions. [2019-12-07 18:26:20,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:20,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192 states to 191 states and 286 transitions. [2019-12-07 18:26:20,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:20,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:20,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191 states and 286 transitions. [2019-12-07 18:26:20,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:20,703 INFO L688 BuchiCegarLoop]: Abstraction has 191 states and 286 transitions. [2019-12-07 18:26:20,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states and 286 transitions. [2019-12-07 18:26:20,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 191. [2019-12-07 18:26:20,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2019-12-07 18:26:20,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 286 transitions. [2019-12-07 18:26:20,705 INFO L711 BuchiCegarLoop]: Abstraction has 191 states and 286 transitions. [2019-12-07 18:26:20,705 INFO L591 BuchiCegarLoop]: Abstraction has 191 states and 286 transitions. [2019-12-07 18:26:20,706 INFO L424 BuchiCegarLoop]: ======== Iteration 185============ [2019-12-07 18:26:20,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 286 transitions. [2019-12-07 18:26:20,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:20,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,707 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [92, 1, 1, 1, 1] [2019-12-07 18:26:20,707 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:20,707 INFO L794 eck$LassoCheckResult]: Stem: 211689#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 211690#L12 main_~i~0 := 0; 211691#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211697#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211698#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211879#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211877#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211875#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211873#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211871#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211869#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211867#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211865#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211863#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211861#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211859#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211857#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211855#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211853#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211851#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211849#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211847#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211845#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211843#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211841#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211839#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211837#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211835#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211833#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211831#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211829#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211827#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211825#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211823#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211821#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211819#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211817#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211815#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211813#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211811#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211809#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211807#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211805#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211803#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211801#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211799#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211797#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211795#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211793#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211791#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211789#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211787#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211785#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211783#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211781#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211779#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211777#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211775#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211773#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211771#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211769#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211767#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211765#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211763#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211761#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211759#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211757#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211755#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211753#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211751#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211749#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211747#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211745#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211743#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211741#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211739#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211737#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211735#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211733#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211731#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211729#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211727#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211725#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211723#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211721#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211719#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211717#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211715#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211713#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211711#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211709#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211707#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211705#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211703#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 211701#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 211692#L15-2 assume main_~i~0 >= 100; 211693#L25 [2019-12-07 18:26:20,708 INFO L796 eck$LassoCheckResult]: Loop: 211693#L25 assume true; 211693#L25 [2019-12-07 18:26:20,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,708 INFO L82 PathProgramCache]: Analyzing trace with hash 1710531307, now seen corresponding path program 92 times [2019-12-07 18:26:20,708 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,708 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987150557] [2019-12-07 18:26:20,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:23,081 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:23,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987150557] [2019-12-07 18:26:23,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1031716666] [2019-12-07 18:26:23,081 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 187 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 187 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:23,125 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:26:23,125 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:23,127 INFO L264 TraceCheckSpWp]: Trace formula consists of 375 conjuncts, 94 conjunts are in the unsatisfiable core [2019-12-07 18:26:23,127 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:23,140 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:23,140 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:23,140 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [94, 94] total 94 [2019-12-07 18:26:23,140 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [394068253] [2019-12-07 18:26:23,140 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:23,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,140 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 184 times [2019-12-07 18:26:23,141 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,141 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334632101] [2019-12-07 18:26:23,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,141 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,143 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:23,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2019-12-07 18:26:23,143 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4465, Invalid=4465, Unknown=0, NotChecked=0, Total=8930 [2019-12-07 18:26:23,143 INFO L87 Difference]: Start difference. First operand 191 states and 286 transitions. cyclomatic complexity: 98 Second operand 95 states. [2019-12-07 18:26:25,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:25,330 INFO L93 Difference]: Finished difference Result 4660 states and 4758 transitions. [2019-12-07 18:26:25,331 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-12-07 18:26:25,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4660 states and 4758 transitions. [2019-12-07 18:26:25,341 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:25,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4660 states to 4659 states and 4757 transitions. [2019-12-07 18:26:25,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:25,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:25,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4659 states and 4757 transitions. [2019-12-07 18:26:25,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:25,348 INFO L688 BuchiCegarLoop]: Abstraction has 4659 states and 4757 transitions. [2019-12-07 18:26:25,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4659 states and 4757 transitions. [2019-12-07 18:26:25,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4659 to 192. [2019-12-07 18:26:25,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2019-12-07 18:26:25,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 288 transitions. [2019-12-07 18:26:25,355 INFO L711 BuchiCegarLoop]: Abstraction has 192 states and 288 transitions. [2019-12-07 18:26:25,355 INFO L591 BuchiCegarLoop]: Abstraction has 192 states and 288 transitions. [2019-12-07 18:26:25,355 INFO L424 BuchiCegarLoop]: ======== Iteration 186============ [2019-12-07 18:26:25,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 288 transitions. [2019-12-07 18:26:25,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:25,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:25,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:25,356 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [91, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:25,356 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:25,356 INFO L794 eck$LassoCheckResult]: Stem: 216923#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 216924#L12 main_~i~0 := 0; 216925#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 216928#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 216929#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 216933#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217114#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217113#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217112#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217111#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217110#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217109#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217108#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217107#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217106#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217105#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217104#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217103#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217102#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217101#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217100#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217099#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217098#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217097#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217096#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217095#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217094#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217093#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217092#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217091#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217090#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217089#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217088#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217087#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217086#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217085#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217084#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217083#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217082#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217081#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217080#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217079#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217078#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217077#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217076#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217075#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217074#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217073#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217072#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217071#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217070#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217069#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217068#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217067#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217066#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217065#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217064#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217063#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217062#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217061#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217060#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217059#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217058#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217057#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217056#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217055#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217054#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217053#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217052#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217051#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217050#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217049#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217048#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217047#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217046#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217045#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217044#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217043#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217042#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217041#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217040#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217039#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217038#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217037#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217036#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217035#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217034#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217033#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217032#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217031#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217030#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217029#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217028#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217027#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217026#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 217025#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 216930#L21-2 assume main_~j~0 >= 100; 216927#L25 [2019-12-07 18:26:25,356 INFO L796 eck$LassoCheckResult]: Loop: 216927#L25 assume true; 216927#L25 [2019-12-07 18:26:25,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:25,356 INFO L82 PathProgramCache]: Analyzing trace with hash 95340984, now seen corresponding path program 91 times [2019-12-07 18:26:25,356 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:25,356 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397063161] [2019-12-07 18:26:25,356 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:25,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:27,698 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:27,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397063161] [2019-12-07 18:26:27,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [219520652] [2019-12-07 18:26:27,698 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 188 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 188 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:27,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:27,763 INFO L264 TraceCheckSpWp]: Trace formula consists of 557 conjuncts, 93 conjunts are in the unsatisfiable core [2019-12-07 18:26:27,764 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:27,776 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:27,776 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:27,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [93, 93] total 93 [2019-12-07 18:26:27,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419348289] [2019-12-07 18:26:27,777 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:27,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:27,777 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 185 times [2019-12-07 18:26:27,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:27,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682465799] [2019-12-07 18:26:27,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:27,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:27,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:27,778 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:27,780 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:27,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-12-07 18:26:27,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2019-12-07 18:26:27,781 INFO L87 Difference]: Start difference. First operand 192 states and 288 transitions. cyclomatic complexity: 99 Second operand 94 states. [2019-12-07 18:26:27,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:27,899 INFO L93 Difference]: Finished difference Result 194 states and 290 transitions. [2019-12-07 18:26:27,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2019-12-07 18:26:27,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 290 transitions. [2019-12-07 18:26:27,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:27,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 193 states and 289 transitions. [2019-12-07 18:26:27,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:27,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:27,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 289 transitions. [2019-12-07 18:26:27,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:27,900 INFO L688 BuchiCegarLoop]: Abstraction has 193 states and 289 transitions. [2019-12-07 18:26:27,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 289 transitions. [2019-12-07 18:26:27,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. [2019-12-07 18:26:27,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. [2019-12-07 18:26:27,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 289 transitions. [2019-12-07 18:26:27,901 INFO L711 BuchiCegarLoop]: Abstraction has 193 states and 289 transitions. [2019-12-07 18:26:27,901 INFO L591 BuchiCegarLoop]: Abstraction has 193 states and 289 transitions. [2019-12-07 18:26:27,901 INFO L424 BuchiCegarLoop]: ======== Iteration 187============ [2019-12-07 18:26:27,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 289 transitions. [2019-12-07 18:26:27,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:27,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:27,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:27,902 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [93, 1, 1, 1, 1] [2019-12-07 18:26:27,902 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:27,902 INFO L794 eck$LassoCheckResult]: Stem: 217694#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 217695#L12 main_~i~0 := 0; 217696#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217702#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217703#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217886#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217884#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217880#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217878#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217866#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217864#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217860#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217858#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217846#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217844#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217840#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217838#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217834#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217832#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217830#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217828#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217826#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217824#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217822#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217820#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217818#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217816#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217814#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217812#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217810#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217808#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217806#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217804#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217802#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217800#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217798#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217796#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217794#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217792#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217790#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217788#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217786#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217784#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217782#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217780#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217778#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217776#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217774#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217772#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217770#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217768#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217766#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217764#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217762#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217760#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217758#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217756#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217754#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217752#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217750#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217748#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217746#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217744#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217742#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217740#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217738#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217736#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217734#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217732#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217730#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217728#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217726#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217724#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217722#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217720#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217718#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217716#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217714#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217712#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217710#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217708#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 217706#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 217697#L15-2 assume main_~i~0 >= 100; 217698#L25 [2019-12-07 18:26:27,902 INFO L796 eck$LassoCheckResult]: Loop: 217698#L25 assume true; 217698#L25 [2019-12-07 18:26:27,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:27,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1486864657, now seen corresponding path program 93 times [2019-12-07 18:26:27,902 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:27,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704475078] [2019-12-07 18:26:27,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:27,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:30,303 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:30,303 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1704475078] [2019-12-07 18:26:30,303 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [403751965] [2019-12-07 18:26:30,304 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 189 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 189 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:30,380 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2019-12-07 18:26:30,380 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:30,382 INFO L264 TraceCheckSpWp]: Trace formula consists of 379 conjuncts, 95 conjunts are in the unsatisfiable core [2019-12-07 18:26:30,382 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:30,395 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:30,395 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:30,395 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [95, 95] total 95 [2019-12-07 18:26:30,395 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127406179] [2019-12-07 18:26:30,396 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:30,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:30,396 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 186 times [2019-12-07 18:26:30,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:30,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866414599] [2019-12-07 18:26:30,396 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:30,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:30,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:30,396 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:30,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:30,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2019-12-07 18:26:30,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2019-12-07 18:26:30,398 INFO L87 Difference]: Start difference. First operand 193 states and 289 transitions. cyclomatic complexity: 99 Second operand 96 states. [2019-12-07 18:26:31,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:31,669 INFO L93 Difference]: Finished difference Result 4757 states and 4856 transitions. [2019-12-07 18:26:31,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2019-12-07 18:26:31,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4757 states and 4856 transitions. [2019-12-07 18:26:31,676 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:31,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4757 states to 4756 states and 4855 transitions. [2019-12-07 18:26:31,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:31,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:31,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4756 states and 4855 transitions. [2019-12-07 18:26:31,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:31,681 INFO L688 BuchiCegarLoop]: Abstraction has 4756 states and 4855 transitions. [2019-12-07 18:26:31,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4756 states and 4855 transitions. [2019-12-07 18:26:31,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4756 to 194. [2019-12-07 18:26:31,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2019-12-07 18:26:31,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 291 transitions. [2019-12-07 18:26:31,686 INFO L711 BuchiCegarLoop]: Abstraction has 194 states and 291 transitions. [2019-12-07 18:26:31,686 INFO L591 BuchiCegarLoop]: Abstraction has 194 states and 291 transitions. [2019-12-07 18:26:31,686 INFO L424 BuchiCegarLoop]: ======== Iteration 188============ [2019-12-07 18:26:31,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 291 transitions. [2019-12-07 18:26:31,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:31,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:31,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:31,686 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [92, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:31,686 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:31,686 INFO L794 eck$LassoCheckResult]: Stem: 223031#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 223032#L12 main_~i~0 := 0; 223033#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 223036#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 223037#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223041#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223224#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223223#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223222#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223221#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223220#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223219#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223218#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223217#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223216#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223215#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223214#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223213#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223212#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223211#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223210#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223208#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223207#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223206#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223205#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223204#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223203#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223202#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223201#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223200#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223199#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223198#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223197#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223196#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223195#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223194#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223193#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223192#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223191#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223190#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223189#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223188#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223187#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223186#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223185#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223184#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223183#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223182#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223181#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223180#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223179#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223178#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223177#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223176#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223175#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223174#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223173#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223172#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223171#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223170#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223169#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223168#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223167#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223166#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223165#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223164#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223163#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223162#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223161#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223160#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223159#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223158#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223157#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223156#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223155#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223154#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223153#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223152#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223151#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223150#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223149#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223148#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223147#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223139#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223138#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223137#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223136#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223135#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 223134#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 223038#L21-2 assume main_~j~0 >= 100; 223035#L25 [2019-12-07 18:26:31,687 INFO L796 eck$LassoCheckResult]: Loop: 223035#L25 assume true; 223035#L25 [2019-12-07 18:26:31,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:31,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1339395082, now seen corresponding path program 92 times [2019-12-07 18:26:31,687 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:31,687 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681572000] [2019-12-07 18:26:31,687 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:31,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:34,057 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:34,057 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681572000] [2019-12-07 18:26:34,057 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [559182361] [2019-12-07 18:26:34,057 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 190 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 190 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:34,118 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:26:34,118 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:34,120 INFO L264 TraceCheckSpWp]: Trace formula consists of 563 conjuncts, 94 conjunts are in the unsatisfiable core [2019-12-07 18:26:34,121 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:34,134 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:34,134 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:34,134 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [94, 94] total 94 [2019-12-07 18:26:34,134 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462514122] [2019-12-07 18:26:34,134 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:34,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:34,134 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 187 times [2019-12-07 18:26:34,135 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:34,135 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613433034] [2019-12-07 18:26:34,135 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:34,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:34,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:34,135 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:34,137 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:34,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2019-12-07 18:26:34,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4465, Invalid=4465, Unknown=0, NotChecked=0, Total=8930 [2019-12-07 18:26:34,138 INFO L87 Difference]: Start difference. First operand 194 states and 291 transitions. cyclomatic complexity: 100 Second operand 95 states. [2019-12-07 18:26:34,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:34,291 INFO L93 Difference]: Finished difference Result 196 states and 293 transitions. [2019-12-07 18:26:34,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-12-07 18:26:34,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196 states and 293 transitions. [2019-12-07 18:26:34,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:34,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196 states to 195 states and 292 transitions. [2019-12-07 18:26:34,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:34,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:34,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 292 transitions. [2019-12-07 18:26:34,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:34,293 INFO L688 BuchiCegarLoop]: Abstraction has 195 states and 292 transitions. [2019-12-07 18:26:34,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 292 transitions. [2019-12-07 18:26:34,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2019-12-07 18:26:34,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2019-12-07 18:26:34,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 292 transitions. [2019-12-07 18:26:34,294 INFO L711 BuchiCegarLoop]: Abstraction has 195 states and 292 transitions. [2019-12-07 18:26:34,294 INFO L591 BuchiCegarLoop]: Abstraction has 195 states and 292 transitions. [2019-12-07 18:26:34,294 INFO L424 BuchiCegarLoop]: ======== Iteration 189============ [2019-12-07 18:26:34,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 292 transitions. [2019-12-07 18:26:34,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:34,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:34,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:34,295 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1] [2019-12-07 18:26:34,295 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:34,296 INFO L794 eck$LassoCheckResult]: Stem: 223810#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 223811#L12 main_~i~0 := 0; 223812#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223818#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223819#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 224004#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 224002#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 224000#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223998#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223996#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223994#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223992#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223990#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223988#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223986#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223984#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223980#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223978#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223974#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223972#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223970#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223968#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223966#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223964#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223962#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223960#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223958#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223956#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223954#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223952#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223950#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223948#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223946#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223944#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223940#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223938#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223934#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223932#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223930#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223928#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223926#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223924#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223922#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223920#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223918#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223916#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223914#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223912#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223910#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223908#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223906#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223904#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223902#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223898#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223896#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223892#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223890#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223888#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223886#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223884#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223880#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223878#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223866#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223864#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223860#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223858#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223846#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223844#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223840#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223838#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223834#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223832#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223830#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223828#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223826#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223824#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 223822#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 223813#L15-2 assume main_~i~0 >= 100; 223814#L25 [2019-12-07 18:26:34,296 INFO L796 eck$LassoCheckResult]: Loop: 223814#L25 assume true; 223814#L25 [2019-12-07 18:26:34,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:34,296 INFO L82 PathProgramCache]: Analyzing trace with hash -1151834197, now seen corresponding path program 94 times [2019-12-07 18:26:34,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:34,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573249156] [2019-12-07 18:26:34,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:34,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:36,798 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:36,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573249156] [2019-12-07 18:26:36,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1294012191] [2019-12-07 18:26:36,799 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 191 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 191 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:36,842 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:26:36,842 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:36,844 INFO L264 TraceCheckSpWp]: Trace formula consists of 383 conjuncts, 96 conjunts are in the unsatisfiable core [2019-12-07 18:26:36,845 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:36,858 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:36,858 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:36,858 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96] total 96 [2019-12-07 18:26:36,858 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179467597] [2019-12-07 18:26:36,858 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:36,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:36,858 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 188 times [2019-12-07 18:26:36,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:36,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814706796] [2019-12-07 18:26:36,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:36,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:36,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:36,859 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:36,860 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:36,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2019-12-07 18:26:36,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2019-12-07 18:26:36,861 INFO L87 Difference]: Start difference. First operand 195 states and 292 transitions. cyclomatic complexity: 100 Second operand 97 states. [2019-12-07 18:26:38,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:38,361 INFO L93 Difference]: Finished difference Result 4855 states and 4955 transitions. [2019-12-07 18:26:38,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2019-12-07 18:26:38,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4855 states and 4955 transitions. [2019-12-07 18:26:38,368 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:38,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4855 states to 4854 states and 4954 transitions. [2019-12-07 18:26:38,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:38,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:38,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4854 states and 4954 transitions. [2019-12-07 18:26:38,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:38,373 INFO L688 BuchiCegarLoop]: Abstraction has 4854 states and 4954 transitions. [2019-12-07 18:26:38,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4854 states and 4954 transitions. [2019-12-07 18:26:38,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4854 to 196. [2019-12-07 18:26:38,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2019-12-07 18:26:38,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 294 transitions. [2019-12-07 18:26:38,378 INFO L711 BuchiCegarLoop]: Abstraction has 196 states and 294 transitions. [2019-12-07 18:26:38,378 INFO L591 BuchiCegarLoop]: Abstraction has 196 states and 294 transitions. [2019-12-07 18:26:38,378 INFO L424 BuchiCegarLoop]: ======== Iteration 190============ [2019-12-07 18:26:38,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 294 transitions. [2019-12-07 18:26:38,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:38,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:38,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:38,379 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [93, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:38,379 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:38,379 INFO L794 eck$LassoCheckResult]: Stem: 229251#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 229252#L12 main_~i~0 := 0; 229253#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 229256#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 229257#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229261#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229446#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229445#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229444#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229443#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229442#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229440#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229439#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229438#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229437#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229436#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229435#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229434#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229433#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229432#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229431#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229430#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229429#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229428#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229427#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229426#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229425#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229424#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229423#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229422#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229421#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229420#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229419#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229418#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229417#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229416#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229415#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229414#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229413#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229412#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229411#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229410#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229409#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229408#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229407#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229406#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229405#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229404#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229403#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229402#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229401#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229400#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229399#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229398#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229397#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229396#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229395#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229394#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229393#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229392#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229391#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229390#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229389#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229388#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229387#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229386#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229385#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229384#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229383#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229382#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229381#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229379#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229378#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229377#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229376#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229375#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229374#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229373#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229372#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229371#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229370#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229369#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229368#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229367#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229366#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229365#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229364#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229363#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229362#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229361#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229360#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229359#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229358#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229357#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229356#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 229355#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 229258#L21-2 assume main_~j~0 >= 100; 229255#L25 [2019-12-07 18:26:38,379 INFO L796 eck$LassoCheckResult]: Loop: 229255#L25 assume true; 229255#L25 [2019-12-07 18:26:38,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:38,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1428427128, now seen corresponding path program 93 times [2019-12-07 18:26:38,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:38,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162671227] [2019-12-07 18:26:38,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:38,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:40,804 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:40,804 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162671227] [2019-12-07 18:26:40,804 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1088814638] [2019-12-07 18:26:40,804 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 192 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 192 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:40,917 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2019-12-07 18:26:40,917 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:40,919 INFO L264 TraceCheckSpWp]: Trace formula consists of 569 conjuncts, 95 conjunts are in the unsatisfiable core [2019-12-07 18:26:40,920 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:40,933 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:40,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:40,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [95, 95] total 95 [2019-12-07 18:26:40,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191074400] [2019-12-07 18:26:40,933 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:40,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:40,934 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 189 times [2019-12-07 18:26:40,934 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:40,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421334860] [2019-12-07 18:26:40,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:40,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:40,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:40,934 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:40,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:40,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2019-12-07 18:26:40,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2019-12-07 18:26:40,937 INFO L87 Difference]: Start difference. First operand 196 states and 294 transitions. cyclomatic complexity: 101 Second operand 96 states. [2019-12-07 18:26:41,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:41,009 INFO L93 Difference]: Finished difference Result 198 states and 296 transitions. [2019-12-07 18:26:41,009 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2019-12-07 18:26:41,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 296 transitions. [2019-12-07 18:26:41,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:41,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 197 states and 295 transitions. [2019-12-07 18:26:41,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:41,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:41,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 295 transitions. [2019-12-07 18:26:41,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:41,010 INFO L688 BuchiCegarLoop]: Abstraction has 197 states and 295 transitions. [2019-12-07 18:26:41,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 295 transitions. [2019-12-07 18:26:41,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2019-12-07 18:26:41,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2019-12-07 18:26:41,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 295 transitions. [2019-12-07 18:26:41,011 INFO L711 BuchiCegarLoop]: Abstraction has 197 states and 295 transitions. [2019-12-07 18:26:41,011 INFO L591 BuchiCegarLoop]: Abstraction has 197 states and 295 transitions. [2019-12-07 18:26:41,011 INFO L424 BuchiCegarLoop]: ======== Iteration 191============ [2019-12-07 18:26:41,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197 states and 295 transitions. [2019-12-07 18:26:41,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:41,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:41,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:41,011 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [95, 1, 1, 1, 1] [2019-12-07 18:26:41,011 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:41,012 INFO L794 eck$LassoCheckResult]: Stem: 230038#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 230039#L12 main_~i~0 := 0; 230040#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230047#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230234#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230232#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230230#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230228#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230226#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230224#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230222#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230220#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230218#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230216#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230214#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230212#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230210#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230208#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230206#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230204#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230202#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230200#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230198#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230196#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230194#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230192#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230190#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230188#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230186#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230184#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230182#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230180#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230178#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230176#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230174#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230172#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230170#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230168#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230166#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230142#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230140#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230136#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230134#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230130#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230128#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230126#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230124#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230122#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230120#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230118#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230116#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230106#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230104#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230102#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230100#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230094#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230090#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230088#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 230050#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 230041#L15-2 assume main_~i~0 >= 100; 230042#L25 [2019-12-07 18:26:41,012 INFO L796 eck$LassoCheckResult]: Loop: 230042#L25 assume true; 230042#L25 [2019-12-07 18:26:41,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:41,012 INFO L82 PathProgramCache]: Analyzing trace with hash -1347120047, now seen corresponding path program 95 times [2019-12-07 18:26:41,012 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:41,012 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697724600] [2019-12-07 18:26:41,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:41,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:43,521 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:43,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697724600] [2019-12-07 18:26:43,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1476050416] [2019-12-07 18:26:43,522 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 193 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 193 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:43,598 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2019-12-07 18:26:43,598 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:43,600 INFO L264 TraceCheckSpWp]: Trace formula consists of 387 conjuncts, 97 conjunts are in the unsatisfiable core [2019-12-07 18:26:43,601 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:43,614 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:43,614 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:43,614 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 97] total 97 [2019-12-07 18:26:43,614 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152551778] [2019-12-07 18:26:43,614 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:43,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:43,615 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 190 times [2019-12-07 18:26:43,615 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:43,615 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975790776] [2019-12-07 18:26:43,615 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:43,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:43,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:43,615 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:43,617 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:43,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2019-12-07 18:26:43,618 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2019-12-07 18:26:43,618 INFO L87 Difference]: Start difference. First operand 197 states and 295 transitions. cyclomatic complexity: 101 Second operand 98 states. [2019-12-07 18:26:44,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:44,867 INFO L93 Difference]: Finished difference Result 4954 states and 5055 transitions. [2019-12-07 18:26:44,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2019-12-07 18:26:44,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4954 states and 5055 transitions. [2019-12-07 18:26:44,875 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:44,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4954 states to 4953 states and 5054 transitions. [2019-12-07 18:26:44,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:44,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:44,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4953 states and 5054 transitions. [2019-12-07 18:26:44,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:44,880 INFO L688 BuchiCegarLoop]: Abstraction has 4953 states and 5054 transitions. [2019-12-07 18:26:44,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4953 states and 5054 transitions. [2019-12-07 18:26:44,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4953 to 198. [2019-12-07 18:26:44,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2019-12-07 18:26:44,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 297 transitions. [2019-12-07 18:26:44,885 INFO L711 BuchiCegarLoop]: Abstraction has 198 states and 297 transitions. [2019-12-07 18:26:44,885 INFO L591 BuchiCegarLoop]: Abstraction has 198 states and 297 transitions. [2019-12-07 18:26:44,885 INFO L424 BuchiCegarLoop]: ======== Iteration 192============ [2019-12-07 18:26:44,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 297 transitions. [2019-12-07 18:26:44,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:44,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:44,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:44,886 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:44,886 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:44,886 INFO L794 eck$LassoCheckResult]: Stem: 235584#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 235585#L12 main_~i~0 := 0; 235586#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 235589#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 235590#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235594#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235781#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235780#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235779#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235778#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235777#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235776#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235775#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235774#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235773#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235772#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235771#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235770#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235769#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235768#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235767#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235766#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235765#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235764#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235763#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235762#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235761#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235760#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235759#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235758#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235757#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235756#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235755#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235754#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235753#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235752#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235751#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235750#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235749#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235748#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235747#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235746#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235745#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235744#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235743#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235742#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235741#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235740#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235739#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235738#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235737#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235736#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235735#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235734#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235733#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235732#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235731#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235730#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235729#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235728#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235727#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235726#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235725#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235724#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235723#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235722#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235721#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235720#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235719#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235718#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235717#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235716#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235715#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235714#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235713#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235712#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235711#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235710#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235709#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235708#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235707#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235706#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235704#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235703#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235702#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235700#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235699#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235698#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235697#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235696#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235695#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235694#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235693#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235692#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235691#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235690#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 235689#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 235591#L21-2 assume main_~j~0 >= 100; 235588#L25 [2019-12-07 18:26:44,886 INFO L796 eck$LassoCheckResult]: Loop: 235588#L25 assume true; 235588#L25 [2019-12-07 18:26:44,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:44,886 INFO L82 PathProgramCache]: Analyzing trace with hash 1331569718, now seen corresponding path program 94 times [2019-12-07 18:26:44,886 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:44,886 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452694508] [2019-12-07 18:26:44,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:44,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:47,383 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:47,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452694508] [2019-12-07 18:26:47,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [845303058] [2019-12-07 18:26:47,383 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 194 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 194 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:47,448 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 18:26:47,448 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:47,450 INFO L264 TraceCheckSpWp]: Trace formula consists of 575 conjuncts, 96 conjunts are in the unsatisfiable core [2019-12-07 18:26:47,451 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:47,464 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:47,464 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:47,464 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96] total 96 [2019-12-07 18:26:47,464 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856743342] [2019-12-07 18:26:47,464 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:47,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:47,464 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 191 times [2019-12-07 18:26:47,464 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:47,465 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425194094] [2019-12-07 18:26:47,465 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:47,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:47,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:47,465 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:47,467 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:47,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2019-12-07 18:26:47,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2019-12-07 18:26:47,467 INFO L87 Difference]: Start difference. First operand 198 states and 297 transitions. cyclomatic complexity: 102 Second operand 97 states. [2019-12-07 18:26:47,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:47,624 INFO L93 Difference]: Finished difference Result 200 states and 299 transitions. [2019-12-07 18:26:47,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2019-12-07 18:26:47,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 200 states and 299 transitions. [2019-12-07 18:26:47,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:47,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 200 states to 199 states and 298 transitions. [2019-12-07 18:26:47,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:47,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:47,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199 states and 298 transitions. [2019-12-07 18:26:47,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:47,628 INFO L688 BuchiCegarLoop]: Abstraction has 199 states and 298 transitions. [2019-12-07 18:26:47,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states and 298 transitions. [2019-12-07 18:26:47,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 199. [2019-12-07 18:26:47,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2019-12-07 18:26:47,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 298 transitions. [2019-12-07 18:26:47,630 INFO L711 BuchiCegarLoop]: Abstraction has 199 states and 298 transitions. [2019-12-07 18:26:47,630 INFO L591 BuchiCegarLoop]: Abstraction has 199 states and 298 transitions. [2019-12-07 18:26:47,630 INFO L424 BuchiCegarLoop]: ======== Iteration 193============ [2019-12-07 18:26:47,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199 states and 298 transitions. [2019-12-07 18:26:47,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:47,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:47,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:47,632 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [96, 1, 1, 1, 1] [2019-12-07 18:26:47,632 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:47,632 INFO L794 eck$LassoCheckResult]: Stem: 236379#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 236380#L12 main_~i~0 := 0; 236381#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236387#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236388#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236577#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236575#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236573#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236571#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236569#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236567#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236565#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236563#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236561#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236559#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236557#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236555#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236553#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236551#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236549#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236547#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236545#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236543#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236541#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236539#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236537#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236535#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236533#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236531#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236529#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236527#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236525#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236523#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236521#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236519#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236517#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236515#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236513#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236511#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236509#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236507#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236505#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236503#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236501#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236499#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236497#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236495#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236493#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236491#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236489#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236487#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236485#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236483#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236481#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236479#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236477#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236475#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236473#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236471#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236469#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236467#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236465#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236463#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236461#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236459#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236457#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236455#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236453#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236451#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236449#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236447#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236445#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236443#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236441#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236439#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236437#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236435#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236433#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236431#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236429#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236427#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236425#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236423#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236421#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236419#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236417#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236415#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236413#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236411#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236409#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236407#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236405#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236403#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236401#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236399#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236397#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236395#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236393#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 236391#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 236382#L15-2 assume main_~i~0 >= 100; 236383#L25 [2019-12-07 18:26:47,633 INFO L796 eck$LassoCheckResult]: Loop: 236383#L25 assume true; 236383#L25 [2019-12-07 18:26:47,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:47,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1188953195, now seen corresponding path program 96 times [2019-12-07 18:26:47,633 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:47,633 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807256530] [2019-12-07 18:26:47,633 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:47,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:50,210 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:50,210 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807256530] [2019-12-07 18:26:50,210 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2045823234] [2019-12-07 18:26:50,210 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 195 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 195 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:50,287 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-12-07 18:26:50,287 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:50,289 INFO L264 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 98 conjunts are in the unsatisfiable core [2019-12-07 18:26:50,290 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:50,303 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:50,303 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:50,303 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [98, 98] total 98 [2019-12-07 18:26:50,303 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172342623] [2019-12-07 18:26:50,303 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:50,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:50,304 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 192 times [2019-12-07 18:26:50,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:50,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408701899] [2019-12-07 18:26:50,304 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:50,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:50,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:50,304 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:50,306 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:50,307 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2019-12-07 18:26:50,307 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4851, Invalid=4851, Unknown=0, NotChecked=0, Total=9702 [2019-12-07 18:26:50,307 INFO L87 Difference]: Start difference. First operand 199 states and 298 transitions. cyclomatic complexity: 102 Second operand 99 states. [2019-12-07 18:26:51,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:51,583 INFO L93 Difference]: Finished difference Result 5054 states and 5156 transitions. [2019-12-07 18:26:51,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2019-12-07 18:26:51,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5054 states and 5156 transitions. [2019-12-07 18:26:51,591 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:51,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5054 states to 5053 states and 5155 transitions. [2019-12-07 18:26:51,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:51,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:51,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5053 states and 5155 transitions. [2019-12-07 18:26:51,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:51,597 INFO L688 BuchiCegarLoop]: Abstraction has 5053 states and 5155 transitions. [2019-12-07 18:26:51,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5053 states and 5155 transitions. [2019-12-07 18:26:51,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5053 to 200. [2019-12-07 18:26:51,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2019-12-07 18:26:51,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 300 transitions. [2019-12-07 18:26:51,603 INFO L711 BuchiCegarLoop]: Abstraction has 200 states and 300 transitions. [2019-12-07 18:26:51,603 INFO L591 BuchiCegarLoop]: Abstraction has 200 states and 300 transitions. [2019-12-07 18:26:51,603 INFO L424 BuchiCegarLoop]: ======== Iteration 194============ [2019-12-07 18:26:51,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 200 states and 300 transitions. [2019-12-07 18:26:51,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:51,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:51,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:51,603 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [95, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:51,604 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:51,604 INFO L794 eck$LassoCheckResult]: Stem: 242031#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 242032#L12 main_~i~0 := 0; 242033#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 242036#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 242037#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242041#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242230#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242229#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242228#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242227#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242226#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242225#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242224#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242223#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242222#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242221#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242220#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242219#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242218#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242217#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242216#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242215#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242214#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242213#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242212#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242211#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242210#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242208#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242207#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242206#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242205#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242204#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242203#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242202#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242201#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242200#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242199#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242198#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242197#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242196#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242195#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242194#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242193#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242192#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242191#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242190#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242189#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242188#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242187#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242186#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242185#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242184#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242183#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242182#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242181#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242180#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242179#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242178#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242177#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242176#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242175#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242174#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242173#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242172#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242171#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242170#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242169#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242168#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242167#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242166#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242165#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242164#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242163#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242162#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242161#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242160#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242159#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242158#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242157#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242156#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242155#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242154#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242153#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242152#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242151#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242150#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242149#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242148#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242147#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242146#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242145#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242144#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242143#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242142#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242141#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242140#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242139#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242138#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 242137#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 242038#L21-2 assume main_~j~0 >= 100; 242035#L25 [2019-12-07 18:26:51,604 INFO L796 eck$LassoCheckResult]: Loop: 242035#L25 assume true; 242035#L25 [2019-12-07 18:26:51,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:51,604 INFO L82 PathProgramCache]: Analyzing trace with hash -1671009992, now seen corresponding path program 95 times [2019-12-07 18:26:51,604 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:51,604 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520504431] [2019-12-07 18:26:51,604 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:51,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:54,126 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:54,126 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520504431] [2019-12-07 18:26:54,126 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1325154000] [2019-12-07 18:26:54,126 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 196 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 196 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:54,238 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2019-12-07 18:26:54,238 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:26:54,241 INFO L264 TraceCheckSpWp]: Trace formula consists of 581 conjuncts, 97 conjunts are in the unsatisfiable core [2019-12-07 18:26:54,242 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:54,255 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:54,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:54,256 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 97] total 97 [2019-12-07 18:26:54,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498821088] [2019-12-07 18:26:54,256 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:54,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:54,256 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 193 times [2019-12-07 18:26:54,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:54,256 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268961474] [2019-12-07 18:26:54,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:54,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:54,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:54,257 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:54,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:54,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2019-12-07 18:26:54,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2019-12-07 18:26:54,259 INFO L87 Difference]: Start difference. First operand 200 states and 300 transitions. cyclomatic complexity: 103 Second operand 98 states. [2019-12-07 18:26:54,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:54,337 INFO L93 Difference]: Finished difference Result 202 states and 302 transitions. [2019-12-07 18:26:54,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2019-12-07 18:26:54,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202 states and 302 transitions. [2019-12-07 18:26:54,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:54,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202 states to 201 states and 301 transitions. [2019-12-07 18:26:54,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:26:54,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:26:54,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 301 transitions. [2019-12-07 18:26:54,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:54,338 INFO L688 BuchiCegarLoop]: Abstraction has 201 states and 301 transitions. [2019-12-07 18:26:54,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 301 transitions. [2019-12-07 18:26:54,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2019-12-07 18:26:54,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2019-12-07 18:26:54,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 301 transitions. [2019-12-07 18:26:54,339 INFO L711 BuchiCegarLoop]: Abstraction has 201 states and 301 transitions. [2019-12-07 18:26:54,339 INFO L591 BuchiCegarLoop]: Abstraction has 201 states and 301 transitions. [2019-12-07 18:26:54,339 INFO L424 BuchiCegarLoop]: ======== Iteration 195============ [2019-12-07 18:26:54,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 301 transitions. [2019-12-07 18:26:54,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:54,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:54,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:54,339 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [97, 1, 1, 1, 1] [2019-12-07 18:26:54,339 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:54,339 INFO L794 eck$LassoCheckResult]: Stem: 242834#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 242835#L12 main_~i~0 := 0; 242836#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242842#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242843#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243034#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243032#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243030#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243028#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243026#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243024#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243022#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243020#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243018#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243016#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243014#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243012#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243010#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243008#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243006#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243004#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243002#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 243000#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242998#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242996#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242994#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242992#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242990#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242988#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242986#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242984#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242980#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242978#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242974#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242972#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242970#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242968#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242966#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242964#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242962#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242960#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242958#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242956#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242954#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242952#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242950#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242948#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242946#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242944#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242940#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242938#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242934#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242932#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242930#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242928#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242926#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242924#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242922#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242920#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242918#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242916#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242914#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242912#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242910#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242908#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242906#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242904#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242902#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242898#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242896#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242892#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242890#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242888#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242886#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242884#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242882#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242880#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242878#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242876#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242874#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242872#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242870#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242868#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242866#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242864#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242862#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242860#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242858#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242856#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242854#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242852#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242850#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242848#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 242846#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 242837#L15-2 assume main_~i~0 >= 100; 242838#L25 [2019-12-07 18:26:54,340 INFO L796 eck$LassoCheckResult]: Loop: 242838#L25 assume true; 242838#L25 [2019-12-07 18:26:54,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:54,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1797154927, now seen corresponding path program 97 times [2019-12-07 18:26:54,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:54,340 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388043136] [2019-12-07 18:26:54,340 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:54,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:57,101 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:57,101 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388043136] [2019-12-07 18:26:57,101 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [21312108] [2019-12-07 18:26:57,101 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 197 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 197 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:26:57,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:57,148 INFO L264 TraceCheckSpWp]: Trace formula consists of 395 conjuncts, 99 conjunts are in the unsatisfiable core [2019-12-07 18:26:57,149 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:26:57,162 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:57,162 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:26:57,162 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [99, 99] total 99 [2019-12-07 18:26:57,163 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300777392] [2019-12-07 18:26:57,163 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:57,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:57,163 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 194 times [2019-12-07 18:26:57,163 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:57,163 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669059080] [2019-12-07 18:26:57,163 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:57,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:57,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:57,164 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:57,165 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:57,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-12-07 18:26:57,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2019-12-07 18:26:57,166 INFO L87 Difference]: Start difference. First operand 201 states and 301 transitions. cyclomatic complexity: 103 Second operand 100 states. [2019-12-07 18:26:58,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:58,226 INFO L93 Difference]: Finished difference Result 5155 states and 5258 transitions. [2019-12-07 18:26:58,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2019-12-07 18:26:58,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5155 states and 5258 transitions. [2019-12-07 18:26:58,234 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:26:58,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5155 states to 5154 states and 5257 transitions. [2019-12-07 18:26:58,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:26:58,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:26:58,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5154 states and 5257 transitions. [2019-12-07 18:26:58,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:26:58,239 INFO L688 BuchiCegarLoop]: Abstraction has 5154 states and 5257 transitions. [2019-12-07 18:26:58,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5154 states and 5257 transitions. [2019-12-07 18:26:58,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5154 to 202. [2019-12-07 18:26:58,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2019-12-07 18:26:58,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 303 transitions. [2019-12-07 18:26:58,245 INFO L711 BuchiCegarLoop]: Abstraction has 202 states and 303 transitions. [2019-12-07 18:26:58,245 INFO L591 BuchiCegarLoop]: Abstraction has 202 states and 303 transitions. [2019-12-07 18:26:58,245 INFO L424 BuchiCegarLoop]: ======== Iteration 196============ [2019-12-07 18:26:58,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202 states and 303 transitions. [2019-12-07 18:26:58,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:26:58,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:58,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:58,245 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [96, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:58,245 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:26:58,246 INFO L794 eck$LassoCheckResult]: Stem: 248593#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 248594#L12 main_~i~0 := 0; 248595#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 248598#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 248599#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248603#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248794#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248793#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248792#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248791#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248790#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248789#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248788#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248787#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248786#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248785#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248784#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248783#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248782#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248781#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248780#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248779#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248778#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248777#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248776#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248775#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248774#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248773#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248772#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248771#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248770#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248769#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248768#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248767#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248766#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248765#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248764#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248763#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248762#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248761#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248760#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248759#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248758#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248757#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248756#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248755#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248754#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248753#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248752#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248751#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248750#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248749#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248748#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248747#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248746#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248745#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248744#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248743#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248742#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248741#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248740#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248739#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248738#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248737#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248736#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248735#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248734#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248733#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248732#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248731#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248730#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248729#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248728#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248727#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248726#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248725#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248724#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248723#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248722#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248721#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248720#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248719#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248718#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248717#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248716#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248715#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248714#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248713#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248712#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248711#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248710#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248709#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248708#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248707#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248706#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248705#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248704#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248703#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248702#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248701#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 248700#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 248600#L21-2 assume main_~j~0 >= 100; 248597#L25 [2019-12-07 18:26:58,246 INFO L796 eck$LassoCheckResult]: Loop: 248597#L25 assume true; 248597#L25 [2019-12-07 18:26:58,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:58,246 INFO L82 PathProgramCache]: Analyzing trace with hash -261700490, now seen corresponding path program 96 times [2019-12-07 18:26:58,246 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:58,246 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056024057] [2019-12-07 18:26:58,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:58,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:00,818 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:00,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056024057] [2019-12-07 18:27:00,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1377116212] [2019-12-07 18:27:00,818 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 198 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 198 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:27:00,927 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-12-07 18:27:00,927 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:27:00,929 INFO L264 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 98 conjunts are in the unsatisfiable core [2019-12-07 18:27:00,930 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:27:00,944 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:00,944 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:27:00,944 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [98, 98] total 98 [2019-12-07 18:27:00,944 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026103569] [2019-12-07 18:27:00,944 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:27:00,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:00,944 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 195 times [2019-12-07 18:27:00,944 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:00,944 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942750885] [2019-12-07 18:27:00,944 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:00,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:00,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:00,945 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:00,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:27:00,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2019-12-07 18:27:00,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4851, Invalid=4851, Unknown=0, NotChecked=0, Total=9702 [2019-12-07 18:27:00,947 INFO L87 Difference]: Start difference. First operand 202 states and 303 transitions. cyclomatic complexity: 104 Second operand 99 states. [2019-12-07 18:27:01,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:27:01,042 INFO L93 Difference]: Finished difference Result 204 states and 305 transitions. [2019-12-07 18:27:01,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2019-12-07 18:27:01,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 305 transitions. [2019-12-07 18:27:01,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:01,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 203 states and 304 transitions. [2019-12-07 18:27:01,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:27:01,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:27:01,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 304 transitions. [2019-12-07 18:27:01,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:27:01,043 INFO L688 BuchiCegarLoop]: Abstraction has 203 states and 304 transitions. [2019-12-07 18:27:01,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 304 transitions. [2019-12-07 18:27:01,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 203. [2019-12-07 18:27:01,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2019-12-07 18:27:01,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 304 transitions. [2019-12-07 18:27:01,045 INFO L711 BuchiCegarLoop]: Abstraction has 203 states and 304 transitions. [2019-12-07 18:27:01,045 INFO L591 BuchiCegarLoop]: Abstraction has 203 states and 304 transitions. [2019-12-07 18:27:01,045 INFO L424 BuchiCegarLoop]: ======== Iteration 197============ [2019-12-07 18:27:01,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 304 transitions. [2019-12-07 18:27:01,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:01,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:27:01,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:27:01,045 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [98, 1, 1, 1, 1] [2019-12-07 18:27:01,045 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:27:01,046 INFO L794 eck$LassoCheckResult]: Stem: 249404#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 249405#L12 main_~i~0 := 0; 249406#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249412#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249413#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249606#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249604#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249602#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249600#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249598#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249596#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249594#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249592#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249590#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249588#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249586#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249584#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249582#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249580#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249578#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249576#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249574#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249572#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249570#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249568#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249566#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249564#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249562#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249560#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249558#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249556#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249554#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249552#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249550#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249548#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249546#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249544#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249542#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249540#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249538#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249536#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249534#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249532#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249530#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249528#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249526#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249524#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249522#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249520#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249518#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249516#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249514#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249512#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249510#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249508#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249506#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249504#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249502#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249500#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249498#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249496#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249494#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249492#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249490#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249488#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249486#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249484#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249482#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249480#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249478#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249476#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249474#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249472#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249470#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249468#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249466#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249464#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249462#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249460#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249458#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249456#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249454#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249452#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249450#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249448#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249446#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249444#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249442#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249440#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249438#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249436#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249434#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249432#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249430#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249428#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249426#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249424#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249422#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249420#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249418#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 249416#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 249407#L15-2 assume main_~i~0 >= 100; 249408#L25 [2019-12-07 18:27:01,046 INFO L796 eck$LassoCheckResult]: Loop: 249408#L25 assume true; 249408#L25 [2019-12-07 18:27:01,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:01,046 INFO L82 PathProgramCache]: Analyzing trace with hash 122773803, now seen corresponding path program 98 times [2019-12-07 18:27:01,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:01,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119389779] [2019-12-07 18:27:01,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:01,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:03,714 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:03,714 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119389779] [2019-12-07 18:27:03,715 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1533072747] [2019-12-07 18:27:03,715 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 199 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 199 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:27:03,760 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:27:03,760 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:27:03,762 INFO L264 TraceCheckSpWp]: Trace formula consists of 399 conjuncts, 100 conjunts are in the unsatisfiable core [2019-12-07 18:27:03,763 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:27:03,777 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:03,777 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:27:03,777 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [100, 100] total 100 [2019-12-07 18:27:03,777 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995905776] [2019-12-07 18:27:03,777 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:27:03,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:03,777 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 196 times [2019-12-07 18:27:03,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:03,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972778790] [2019-12-07 18:27:03,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:03,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:03,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:03,778 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:03,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:27:03,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2019-12-07 18:27:03,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5050, Invalid=5050, Unknown=0, NotChecked=0, Total=10100 [2019-12-07 18:27:03,780 INFO L87 Difference]: Start difference. First operand 203 states and 304 transitions. cyclomatic complexity: 104 Second operand 101 states. [2019-12-07 18:27:05,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:27:05,525 INFO L93 Difference]: Finished difference Result 5257 states and 5361 transitions. [2019-12-07 18:27:05,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2019-12-07 18:27:05,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5257 states and 5361 transitions. [2019-12-07 18:27:05,533 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:27:05,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5257 states to 5256 states and 5360 transitions. [2019-12-07 18:27:05,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:27:05,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:27:05,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5256 states and 5360 transitions. [2019-12-07 18:27:05,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:27:05,538 INFO L688 BuchiCegarLoop]: Abstraction has 5256 states and 5360 transitions. [2019-12-07 18:27:05,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5256 states and 5360 transitions. [2019-12-07 18:27:05,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5256 to 204. [2019-12-07 18:27:05,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2019-12-07 18:27:05,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 306 transitions. [2019-12-07 18:27:05,543 INFO L711 BuchiCegarLoop]: Abstraction has 204 states and 306 transitions. [2019-12-07 18:27:05,543 INFO L591 BuchiCegarLoop]: Abstraction has 204 states and 306 transitions. [2019-12-07 18:27:05,543 INFO L424 BuchiCegarLoop]: ======== Iteration 198============ [2019-12-07 18:27:05,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 306 transitions. [2019-12-07 18:27:05,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:05,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:27:05,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:27:05,544 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [97, 1, 1, 1, 1, 1, 1] [2019-12-07 18:27:05,544 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:27:05,544 INFO L794 eck$LassoCheckResult]: Stem: 255271#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 255272#L12 main_~i~0 := 0; 255273#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 255276#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 255277#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255281#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255474#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255473#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255472#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255471#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255470#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255469#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255468#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255467#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255466#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255465#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255464#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255463#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255462#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255461#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255460#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255459#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255458#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255457#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255456#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255455#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255454#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255453#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255452#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255451#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255450#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255449#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255448#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255447#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255446#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255445#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255444#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255443#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255442#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255441#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255440#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255439#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255438#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255437#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255436#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255435#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255434#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255433#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255432#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255431#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255430#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255429#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255428#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255427#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255426#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255425#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255424#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255423#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255422#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255421#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255420#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255419#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255418#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255417#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255416#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255415#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255414#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255413#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255412#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255411#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255410#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255409#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255408#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255407#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255406#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255405#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255404#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255403#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255402#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255401#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255400#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255399#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255398#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255397#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255396#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255395#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255394#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255393#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255392#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255391#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255390#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255389#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255388#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255387#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255386#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255385#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255384#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255383#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255382#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255381#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255380#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 255379#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 255278#L21-2 assume main_~j~0 >= 100; 255275#L25 [2019-12-07 18:27:05,544 INFO L796 eck$LassoCheckResult]: Loop: 255275#L25 assume true; 255275#L25 [2019-12-07 18:27:05,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:05,544 INFO L82 PathProgramCache]: Analyzing trace with hash 477221112, now seen corresponding path program 97 times [2019-12-07 18:27:05,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:05,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629563862] [2019-12-07 18:27:05,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:05,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:08,195 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:08,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629563862] [2019-12-07 18:27:08,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1084131706] [2019-12-07 18:27:08,195 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 200 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 200 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:27:08,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:08,260 INFO L264 TraceCheckSpWp]: Trace formula consists of 593 conjuncts, 99 conjunts are in the unsatisfiable core [2019-12-07 18:27:08,261 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:27:08,275 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:08,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:27:08,275 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [99, 99] total 99 [2019-12-07 18:27:08,275 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769643667] [2019-12-07 18:27:08,275 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:27:08,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:08,275 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 197 times [2019-12-07 18:27:08,275 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:08,275 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581890442] [2019-12-07 18:27:08,276 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:08,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:08,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:08,276 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:08,277 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:27:08,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-12-07 18:27:08,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2019-12-07 18:27:08,278 INFO L87 Difference]: Start difference. First operand 204 states and 306 transitions. cyclomatic complexity: 105 Second operand 100 states. [2019-12-07 18:27:08,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:27:08,419 INFO L93 Difference]: Finished difference Result 206 states and 308 transitions. [2019-12-07 18:27:08,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2019-12-07 18:27:08,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 206 states and 308 transitions. [2019-12-07 18:27:08,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:08,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 206 states to 205 states and 307 transitions. [2019-12-07 18:27:08,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:27:08,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:27:08,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205 states and 307 transitions. [2019-12-07 18:27:08,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:27:08,421 INFO L688 BuchiCegarLoop]: Abstraction has 205 states and 307 transitions. [2019-12-07 18:27:08,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states and 307 transitions. [2019-12-07 18:27:08,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 205. [2019-12-07 18:27:08,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2019-12-07 18:27:08,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 307 transitions. [2019-12-07 18:27:08,423 INFO L711 BuchiCegarLoop]: Abstraction has 205 states and 307 transitions. [2019-12-07 18:27:08,423 INFO L591 BuchiCegarLoop]: Abstraction has 205 states and 307 transitions. [2019-12-07 18:27:08,423 INFO L424 BuchiCegarLoop]: ======== Iteration 199============ [2019-12-07 18:27:08,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 205 states and 307 transitions. [2019-12-07 18:27:08,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:08,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:27:08,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:27:08,424 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [99, 1, 1, 1, 1] [2019-12-07 18:27:08,424 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:27:08,424 INFO L794 eck$LassoCheckResult]: Stem: 256090#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 256091#L12 main_~i~0 := 0; 256092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256099#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256294#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256292#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256290#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256288#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256286#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256284#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256282#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256280#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256278#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256276#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256274#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256272#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256270#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256268#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256266#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256264#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256262#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256260#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256258#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256256#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256254#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256252#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256250#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256248#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256246#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256244#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256242#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256240#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256238#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256236#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256234#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256232#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256230#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256228#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256226#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256224#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256222#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256220#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256218#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256216#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256214#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256212#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256210#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256208#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256206#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256204#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256202#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256200#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256198#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256196#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256194#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256192#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256190#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256188#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256186#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256184#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256182#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256180#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256178#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256176#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256174#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256172#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256170#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256168#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256166#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256164#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256162#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256160#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256158#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256156#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256154#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256152#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256150#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256148#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256146#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256144#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256142#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256140#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256138#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256136#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256134#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256132#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256130#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256128#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256126#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256124#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256122#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256120#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256118#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256116#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256114#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256112#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256110#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256108#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256106#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256104#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 256102#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 256093#L15-2 assume main_~i~0 >= 100; 256094#L25 [2019-12-07 18:27:08,424 INFO L796 eck$LassoCheckResult]: Loop: 256094#L25 assume true; 256094#L25 [2019-12-07 18:27:08,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:08,424 INFO L82 PathProgramCache]: Analyzing trace with hash -488977711, now seen corresponding path program 99 times [2019-12-07 18:27:08,424 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:08,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676289211] [2019-12-07 18:27:08,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:08,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:11,155 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:11,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1676289211] [2019-12-07 18:27:11,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [174658569] [2019-12-07 18:27:11,156 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 201 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 201 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:27:11,243 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 51 check-sat command(s) [2019-12-07 18:27:11,244 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:27:11,246 INFO L264 TraceCheckSpWp]: Trace formula consists of 403 conjuncts, 101 conjunts are in the unsatisfiable core [2019-12-07 18:27:11,246 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:27:11,260 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:11,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:27:11,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [101, 101] total 101 [2019-12-07 18:27:11,261 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112981322] [2019-12-07 18:27:11,261 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:27:11,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:11,261 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 198 times [2019-12-07 18:27:11,261 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:11,261 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767625067] [2019-12-07 18:27:11,261 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:11,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:11,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:11,262 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:11,264 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:27:11,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2019-12-07 18:27:11,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2019-12-07 18:27:11,265 INFO L87 Difference]: Start difference. First operand 205 states and 307 transitions. cyclomatic complexity: 105 Second operand 102 states. [2019-12-07 18:27:12,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:27:12,636 INFO L93 Difference]: Finished difference Result 5359 states and 5464 transitions. [2019-12-07 18:27:12,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2019-12-07 18:27:12,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5359 states and 5464 transitions. [2019-12-07 18:27:12,644 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2019-12-07 18:27:12,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5359 states to 5358 states and 5463 transitions. [2019-12-07 18:27:12,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2019-12-07 18:27:12,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2019-12-07 18:27:12,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5358 states and 5463 transitions. [2019-12-07 18:27:12,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:27:12,650 INFO L688 BuchiCegarLoop]: Abstraction has 5358 states and 5463 transitions. [2019-12-07 18:27:12,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5358 states and 5463 transitions. [2019-12-07 18:27:12,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5358 to 206. [2019-12-07 18:27:12,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2019-12-07 18:27:12,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 309 transitions. [2019-12-07 18:27:12,656 INFO L711 BuchiCegarLoop]: Abstraction has 206 states and 309 transitions. [2019-12-07 18:27:12,656 INFO L591 BuchiCegarLoop]: Abstraction has 206 states and 309 transitions. [2019-12-07 18:27:12,656 INFO L424 BuchiCegarLoop]: ======== Iteration 200============ [2019-12-07 18:27:12,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 309 transitions. [2019-12-07 18:27:12,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:12,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:27:12,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:27:12,656 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [98, 1, 1, 1, 1, 1, 1] [2019-12-07 18:27:12,656 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:27:12,657 INFO L794 eck$LassoCheckResult]: Stem: 262065#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 262066#L12 main_~i~0 := 0; 262067#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 262070#L15-2 assume !(main_~i~0 >= 100);main_~j~0 := 0; 262071#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262075#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262270#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262269#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262268#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262267#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262266#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262265#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262264#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262263#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262262#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262261#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262260#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262259#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262258#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262257#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262256#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262255#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262254#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262253#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262252#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262251#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262250#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262249#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262248#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262247#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262246#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262245#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262244#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262243#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262242#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262241#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262240#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262239#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262238#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262237#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262236#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262235#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262234#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262233#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262232#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262231#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262230#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262229#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262228#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262227#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262226#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262225#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262224#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262223#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262222#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262221#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262220#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262219#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262218#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262217#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262216#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262215#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262214#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262213#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262212#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262211#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262210#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262209#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262208#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262207#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262206#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262205#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262204#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262203#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262202#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262201#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262200#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262199#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262198#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262197#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262196#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262195#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262194#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262193#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262192#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262191#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262190#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262189#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262188#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262187#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262186#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262185#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262184#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262183#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262182#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262181#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262180#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262179#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262178#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262177#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262176#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262175#L21-1 assume !!(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3;main_#t~post4 := main_~i~0;main_~i~0 := 1 + main_#t~post4;havoc main_#t~post4;main_#t~post5 := main_~j~0;main_~j~0 := 1 + main_#t~post5;havoc main_#t~post5; 262174#L21-1 assume !(0 != main_#t~nondet3 && main_~i~0 < 1000000);havoc main_#t~nondet3; 262072#L21-2 assume main_~j~0 >= 100; 262069#L25 [2019-12-07 18:27:12,657 INFO L796 eck$LassoCheckResult]: Loop: 262069#L25 assume true; 262069#L25 [2019-12-07 18:27:12,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:12,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1908954294, now seen corresponding path program 98 times [2019-12-07 18:27:12,657 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:12,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352369511] [2019-12-07 18:27:12,657 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:12,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:27:15,344 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:15,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352369511] [2019-12-07 18:27:15,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [820005386] [2019-12-07 18:27:15,344 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/z3 Starting monitored process 202 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 202 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 18:27:15,407 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 18:27:15,408 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 18:27:15,410 INFO L264 TraceCheckSpWp]: Trace formula consists of 599 conjuncts, 100 conjunts are in the unsatisfiable core [2019-12-07 18:27:15,411 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 18:27:15,425 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:27:15,425 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 18:27:15,425 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [100, 100] total 100 [2019-12-07 18:27:15,425 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591828377] [2019-12-07 18:27:15,425 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:27:15,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:15,425 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 199 times [2019-12-07 18:27:15,425 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:15,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712094194] [2019-12-07 18:27:15,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:15,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,426 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:15,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:27:15,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2019-12-07 18:27:15,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5050, Invalid=5050, Unknown=0, NotChecked=0, Total=10100 [2019-12-07 18:27:15,428 INFO L87 Difference]: Start difference. First operand 206 states and 309 transitions. cyclomatic complexity: 106 Second operand 101 states. [2019-12-07 18:27:15,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:27:15,581 INFO L93 Difference]: Finished difference Result 208 states and 311 transitions. [2019-12-07 18:27:15,581 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2019-12-07 18:27:15,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 311 transitions. [2019-12-07 18:27:15,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:15,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 207 states and 310 transitions. [2019-12-07 18:27:15,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2019-12-07 18:27:15,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2019-12-07 18:27:15,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 207 states and 310 transitions. [2019-12-07 18:27:15,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 18:27:15,582 INFO L688 BuchiCegarLoop]: Abstraction has 207 states and 310 transitions. [2019-12-07 18:27:15,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states and 310 transitions. [2019-12-07 18:27:15,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2019-12-07 18:27:15,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-12-07 18:27:15,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 310 transitions. [2019-12-07 18:27:15,584 INFO L711 BuchiCegarLoop]: Abstraction has 207 states and 310 transitions. [2019-12-07 18:27:15,584 INFO L591 BuchiCegarLoop]: Abstraction has 207 states and 310 transitions. [2019-12-07 18:27:15,584 INFO L424 BuchiCegarLoop]: ======== Iteration 201============ [2019-12-07 18:27:15,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207 states and 310 transitions. [2019-12-07 18:27:15,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2019-12-07 18:27:15,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:27:15,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:27:15,585 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [100, 1, 1, 1, 1] [2019-12-07 18:27:15,585 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1] [2019-12-07 18:27:15,585 INFO L794 eck$LassoCheckResult]: Stem: 262892#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~post2, main_#t~nondet1, main_#t~post4, main_#t~post5, main_#t~nondet3, main_~i~0, main_~j~0;havoc main_~i~0;havoc main_~j~0; 262893#L12 main_~i~0 := 0; 262894#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262900#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262901#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263098#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263096#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263094#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263092#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263090#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263088#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263086#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263084#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263082#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263080#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263078#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263076#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263074#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263072#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263070#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263068#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263066#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263064#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263062#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263060#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263058#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263056#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263054#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263052#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263050#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263048#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263046#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263044#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263042#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263040#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263038#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263036#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263034#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263032#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263030#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263028#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263026#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263024#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263022#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263020#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263018#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263016#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263014#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263012#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263010#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263008#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263006#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263004#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263002#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 263000#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262998#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262996#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262994#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262992#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262990#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262988#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262986#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262984#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262982#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262980#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262978#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262976#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262974#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262972#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262970#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262968#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262966#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262964#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262962#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262960#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262958#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262956#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262954#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262952#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262950#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262948#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262946#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262944#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262942#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262940#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262938#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262936#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262934#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262932#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262930#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262928#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262926#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262924#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262922#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262920#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262918#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262916#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262914#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262912#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262910#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262908#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262906#L15-1 assume !!(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1;main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 262904#L15-1 assume !(0 != main_#t~nondet1 && main_~i~0 < 1000000);havoc main_#t~nondet1; 262895#L15-2 assume main_~i~0 >= 100; 262896#L25 [2019-12-07 18:27:15,585 INFO L796 eck$LassoCheckResult]: Loop: 262896#L25 assume true; 262896#L25 [2019-12-07 18:27:15,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:15,585 INFO L82 PathProgramCache]: Analyzing trace with hash 2021561835, now seen corresponding path program 100 times [2019-12-07 18:27:15,585 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:15,585 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704847166] [2019-12-07 18:27:15,585 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:15,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,648 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:15,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:15,648 INFO L82 PathProgramCache]: Analyzing trace with hash 83, now seen corresponding path program 200 times [2019-12-07 18:27:15,648 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:15,648 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094882889] [2019-12-07 18:27:15,648 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:15,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,649 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:15,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:27:15,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1756092503, now seen corresponding path program 1 times [2019-12-07 18:27:15,649 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:27:15,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523513651] [2019-12-07 18:27:15,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:27:15,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:27:15,694 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:27:20,057 WARN L192 SmtUtils]: Spent 4.35 s on a formula simplification. DAG size of input: 713 DAG size of output: 607 [2019-12-07 18:27:20,134 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:27:20 BoogieIcfgContainer [2019-12-07 18:27:20,135 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:27:20,135 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:27:20,135 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:27:20,135 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:27:20,135 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:22:55" (3/4) ... [2019-12-07 18:27:20,137 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:27:20,194 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_b0d93738-31d1-4753-9106-a2a8c2edf704/bin/uautomizer/witness.graphml [2019-12-07 18:27:20,195 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:27:20,196 INFO L168 Benchmark]: Toolchain (without parser) took 264658.25 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 133.2 MB). Free memory was 938.7 MB in the beginning and 1.0 GB in the end (delta: -80.0 MB). Peak memory consumption was 53.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:27:20,196 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:27:20,196 INFO L168 Benchmark]: CACSL2BoogieTranslator took 170.72 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 938.7 MB in the beginning and 1.1 GB in the end (delta: -155.8 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. [2019-12-07 18:27:20,196 INFO L168 Benchmark]: Boogie Procedure Inliner took 22.30 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:27:20,197 INFO L168 Benchmark]: Boogie Preprocessor took 12.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:27:20,197 INFO L168 Benchmark]: RCFGBuilder took 169.25 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.2 MB). Peak memory consumption was 19.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:27:20,197 INFO L168 Benchmark]: BuchiAutomizer took 264221.04 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 35.1 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.7 MB). Peak memory consumption was 371.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:27:20,197 INFO L168 Benchmark]: Witness Printer took 59.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:27:20,199 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 170.72 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 938.7 MB in the beginning and 1.1 GB in the end (delta: -155.8 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 22.30 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 12.31 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 169.25 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.2 MB). Peak memory consumption was 19.2 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 264221.04 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 35.1 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 47.7 MB). Peak memory consumption was 371.0 MB. Max. memory is 11.5 GB. * Witness Printer took 59.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 8.9 MB). Peak memory consumption was 8.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 200 terminating modules (199 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -2 * i + 1999999 and consists of 4 locations. 199 modules have a trivial ranking function, the largest among these consists of 102 locations. The remainder module has 207 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 264.1s and 201 iterations. TraceHistogramMax:100. Analysis of lassos took 203.7s. Construction of modules took 26.1s. Büchi inclusion checks took 32.6s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 200. Automata minimization 0.4s AutomataMinimizationTime, 200 MinimizatonAttempts, 177054 StatesRemovedByMinimization, 101 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had 207 states and ocurred in iteration 200. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 1401 SDtfs, 19918 SDslu, 18376 SDs, 0 SdLazy, 37559 SolverSat, 9893 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 26.1s Time LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN199 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital14 mio100 ax100 hnf100 lsp71 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: sat Degree: 0 Time: 19ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 10]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34d731ac=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30a8d41=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@4033c839=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@3e8b6eb4=0, i=100, j=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@32a9b0ce=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 10]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L11] int i, j; [L13] i = 0 [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L16] i++ [L15] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L18] COND TRUE i >= 100 Loop: [L18] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...