./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e3d58fadf54daed6107b58402b79d250d23d0301 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:50:22,358 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:50:22,360 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:50:22,368 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:50:22,369 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:50:22,370 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:50:22,371 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:50:22,372 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:50:22,374 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:50:22,375 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:50:22,376 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:50:22,377 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:50:22,377 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:50:22,378 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:50:22,379 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:50:22,380 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:50:22,380 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:50:22,381 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:50:22,383 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:50:22,384 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:50:22,386 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:50:22,386 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:50:22,387 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:50:22,387 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:50:22,389 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:50:22,389 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:50:22,389 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:50:22,390 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:50:22,390 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:50:22,391 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:50:22,391 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:50:22,391 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:50:22,392 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:50:22,392 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:50:22,393 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:50:22,393 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:50:22,393 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:50:22,393 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:50:22,394 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:50:22,394 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:50:22,394 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:50:22,395 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 18:50:22,405 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:50:22,406 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:50:22,406 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:50:22,407 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:50:22,407 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:50:22,407 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:50:22,408 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:50:22,409 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:50:22,409 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:50:22,409 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:50:22,410 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:50:22,410 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:50:22,410 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:50:22,410 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e3d58fadf54daed6107b58402b79d250d23d0301 [2019-12-07 18:50:22,511 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:50:22,521 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:50:22,524 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:50:22,525 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:50:22,525 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:50:22,526 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2019-12-07 18:50:22,568 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/data/6970907b7/6ac1e2a50d06459da2cce0f0b39cfe8b/FLAG8b7903504 [2019-12-07 18:50:23,014 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:50:23,014 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2019-12-07 18:50:23,020 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/data/6970907b7/6ac1e2a50d06459da2cce0f0b39cfe8b/FLAG8b7903504 [2019-12-07 18:50:23,029 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/data/6970907b7/6ac1e2a50d06459da2cce0f0b39cfe8b [2019-12-07 18:50:23,031 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:50:23,032 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:50:23,032 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:50:23,032 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:50:23,035 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:50:23,035 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,037 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@8a8f29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23, skipping insertion in model container [2019-12-07 18:50:23,037 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,042 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:50:23,062 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:50:23,219 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:50:23,224 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:50:23,249 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:50:23,262 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:50:23,262 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23 WrapperNode [2019-12-07 18:50:23,262 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:50:23,263 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:50:23,263 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:50:23,263 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:50:23,268 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,273 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,296 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:50:23,297 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:50:23,297 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:50:23,297 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:50:23,303 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,303 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,305 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,305 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,312 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,321 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,323 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... [2019-12-07 18:50:23,326 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:50:23,326 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:50:23,326 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:50:23,326 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:50:23,327 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:50:23,366 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:50:23,366 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:50:23,752 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:50:23,752 INFO L287 CfgBuilder]: Removed 103 assume(true) statements. [2019-12-07 18:50:23,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:50:23 BoogieIcfgContainer [2019-12-07 18:50:23,753 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:50:23,754 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:50:23,754 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:50:23,756 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:50:23,756 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:50:23,756 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:50:23" (1/3) ... [2019-12-07 18:50:23,757 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c2bf0e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:50:23, skipping insertion in model container [2019-12-07 18:50:23,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:50:23,757 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:50:23" (2/3) ... [2019-12-07 18:50:23,758 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c2bf0e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:50:23, skipping insertion in model container [2019-12-07 18:50:23,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:50:23,758 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:50:23" (3/3) ... [2019-12-07 18:50:23,759 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2019-12-07 18:50:23,786 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:50:23,787 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:50:23,787 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:50:23,787 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:50:23,787 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:50:23,787 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:50:23,787 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:50:23,787 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:50:23,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states. [2019-12-07 18:50:23,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2019-12-07 18:50:23,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:23,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:23,831 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:23,831 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:23,831 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:50:23,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states. [2019-12-07 18:50:23,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2019-12-07 18:50:23,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:23,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:23,839 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:23,840 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:23,845 INFO L794 eck$LassoCheckResult]: Stem: 50#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 9#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 71#L506true havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82#L214true assume !(1 == ~m_i~0);~m_st~0 := 2; 121#L221-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 41#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 49#L231-1true assume !(0 == ~M_E~0); 25#L334-1true assume !(0 == ~T1_E~0); 34#L339-1true assume !(0 == ~T2_E~0); 149#L344-1true assume !(0 == ~E_M~0); 180#L349-1true assume !(0 == ~E_1~0); 93#L354-1true assume !(0 == ~E_2~0); 118#L359-1true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 201#L156true assume 1 == ~m_pc~0; 138#L157true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 202#L167true is_master_triggered_#res := is_master_triggered_~__retres1~0; 139#L168true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 208#L415true assume !(0 != activate_threads_~tmp~1); 176#L415-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3#L175true assume 1 == ~t1_pc~0; 47#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4#L186true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48#L187true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 84#L423true assume !(0 != activate_threads_~tmp___0~0); 86#L423-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117#L194true assume !(1 == ~t2_pc~0); 113#L194-2true is_transmit2_triggered_~__retres1~2 := 0; 119#L205true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 188#L206true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 107#L431true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 89#L431-2true assume !(1 == ~M_E~0); 33#L372-1true assume !(1 == ~T1_E~0); 148#L377-1true assume !(1 == ~T2_E~0); 177#L382-1true assume !(1 == ~E_M~0); 90#L387-1true assume 1 == ~E_1~0;~E_1~0 := 2; 115#L392-1true assume !(1 == ~E_2~0); 28#L543-1true [2019-12-07 18:50:23,846 INFO L796 eck$LassoCheckResult]: Loop: 28#L543-1true assume !false; 8#L544true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 126#L309true assume false; 72#L324true start_simulation_~kernel_st~0 := 2; 80#L214-1true start_simulation_~kernel_st~0 := 3; 26#L334-2true assume 0 == ~M_E~0;~M_E~0 := 1; 27#L334-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 36#L339-3true assume !(0 == ~T2_E~0); 151#L344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 190#L349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 101#L354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 109#L359-3true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 162#L156-12true assume 1 == ~m_pc~0; 145#L157-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 217#L167-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L168-4true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 156#L415-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 157#L415-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 85#L175-12true assume !(1 == ~t1_pc~0); 83#L175-14true is_transmit1_triggered_~__retres1~1 := 0; 14#L186-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55#L187-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 69#L423-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62#L423-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104#L194-12true assume !(1 == ~t2_pc~0); 210#L194-14true is_transmit2_triggered_~__retres1~2 := 0; 99#L205-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170#L206-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 196#L431-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 203#L431-14true assume !(1 == ~M_E~0); 35#L372-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 150#L377-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 185#L382-3true assume 1 == ~E_M~0;~E_M~0 := 2; 97#L387-3true assume 1 == ~E_1~0;~E_1~0 := 2; 120#L392-3true assume 1 == ~E_2~0;~E_2~0 := 2; 127#L397-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 205#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 192#L261-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 29#L262-1true start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 129#L562true assume !(0 == start_simulation_~tmp~3); 130#L562-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 204#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 187#L261-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 37#L262-2true stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 70#L517true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 122#L524true stop_simulation_#res := stop_simulation_~__retres2~0; 199#L525true start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 168#L575true assume !(0 != start_simulation_~tmp___0~1); 28#L543-1true [2019-12-07 18:50:23,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:23,850 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2019-12-07 18:50:23,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:23,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074417331] [2019-12-07 18:50:23,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:23,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:23,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:23,952 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074417331] [2019-12-07 18:50:23,952 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:23,953 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:23,954 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571304783] [2019-12-07 18:50:23,957 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:23,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:23,958 INFO L82 PathProgramCache]: Analyzing trace with hash -1944420535, now seen corresponding path program 1 times [2019-12-07 18:50:23,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:23,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112457463] [2019-12-07 18:50:23,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:23,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:23,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:23,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112457463] [2019-12-07 18:50:23,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:23,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:23,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840306189] [2019-12-07 18:50:23,976 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:23,976 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:23,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:23,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:23,987 INFO L87 Difference]: Start difference. First operand 217 states. Second operand 3 states. [2019-12-07 18:50:24,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,010 INFO L93 Difference]: Finished difference Result 217 states and 327 transitions. [2019-12-07 18:50:24,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 327 transitions. [2019-12-07 18:50:24,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2019-12-07 18:50:24,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 212 states and 322 transitions. [2019-12-07 18:50:24,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2019-12-07 18:50:24,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2019-12-07 18:50:24,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 322 transitions. [2019-12-07 18:50:24,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,023 INFO L688 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2019-12-07 18:50:24,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 322 transitions. [2019-12-07 18:50:24,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2019-12-07 18:50:24,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2019-12-07 18:50:24,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 322 transitions. [2019-12-07 18:50:24,050 INFO L711 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2019-12-07 18:50:24,050 INFO L591 BuchiCegarLoop]: Abstraction has 212 states and 322 transitions. [2019-12-07 18:50:24,050 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:50:24,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 322 transitions. [2019-12-07 18:50:24,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2019-12-07 18:50:24,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,053 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,053 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,054 INFO L794 eck$LassoCheckResult]: Stem: 517#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 456#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 457#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 539#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 549#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 511#L231-1 assume !(0 == ~M_E~0); 483#L334-1 assume !(0 == ~T1_E~0); 484#L339-1 assume !(0 == ~T2_E~0); 499#L344-1 assume !(0 == ~E_M~0); 634#L349-1 assume !(0 == ~E_1~0); 561#L354-1 assume !(0 == ~E_2~0); 562#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 592#L156 assume 1 == ~m_pc~0; 617#L157 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 618#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 620#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 621#L415 assume !(0 != activate_threads_~tmp~1); 649#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 443#L175 assume 1 == ~t1_pc~0; 444#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 446#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 447#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 516#L423 assume !(0 != activate_threads_~tmp___0~0); 550#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 552#L194 assume !(1 == ~t2_pc~0); 587#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 588#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 593#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 580#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 555#L431-2 assume !(1 == ~M_E~0); 497#L372-1 assume !(1 == ~T1_E~0); 498#L377-1 assume !(1 == ~T2_E~0); 633#L382-1 assume !(1 == ~E_M~0); 556#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 557#L392-1 assume !(1 == ~E_2~0); 488#L543-1 [2019-12-07 18:50:24,054 INFO L796 eck$LassoCheckResult]: Loop: 488#L543-1 assume !false; 454#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 455#L309 assume !false; 597#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 644#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 453#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 491#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 492#L276 assume !(0 != eval_~tmp~0); 540#L324 start_simulation_~kernel_st~0 := 2; 541#L214-1 start_simulation_~kernel_st~0 := 3; 485#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 486#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 487#L339-3 assume !(0 == ~T2_E~0); 502#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 636#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 573#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 574#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 583#L156-12 assume 1 == ~m_pc~0; 627#L157-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 628#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 630#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 631#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 642#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 551#L175-12 assume 1 == ~t1_pc~0; 521#L176-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 465#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 466#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 523#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 531#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 532#L194-12 assume !(1 == ~t2_pc~0); 576#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 570#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 571#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 646#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 653#L431-14 assume !(1 == ~M_E~0); 500#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 501#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 635#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 567#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 568#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 594#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 598#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 451#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 489#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 490#L562 assume !(0 == start_simulation_~tmp~3); 533#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 599#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 449#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 503#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 504#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 538#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 595#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 645#L575 assume !(0 != start_simulation_~tmp___0~1); 488#L543-1 [2019-12-07 18:50:24,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,054 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2019-12-07 18:50:24,054 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,054 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676713365] [2019-12-07 18:50:24,055 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,074 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1676713365] [2019-12-07 18:50:24,074 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,074 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,074 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490916458] [2019-12-07 18:50:24,075 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,075 INFO L82 PathProgramCache]: Analyzing trace with hash -837799223, now seen corresponding path program 1 times [2019-12-07 18:50:24,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136785768] [2019-12-07 18:50:24,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136785768] [2019-12-07 18:50:24,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,113 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,113 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890114238] [2019-12-07 18:50:24,113 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,114 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,114 INFO L87 Difference]: Start difference. First operand 212 states and 322 transitions. cyclomatic complexity: 111 Second operand 3 states. [2019-12-07 18:50:24,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,126 INFO L93 Difference]: Finished difference Result 212 states and 321 transitions. [2019-12-07 18:50:24,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 321 transitions. [2019-12-07 18:50:24,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2019-12-07 18:50:24,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 321 transitions. [2019-12-07 18:50:24,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2019-12-07 18:50:24,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2019-12-07 18:50:24,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 321 transitions. [2019-12-07 18:50:24,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,134 INFO L688 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2019-12-07 18:50:24,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 321 transitions. [2019-12-07 18:50:24,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 212. [2019-12-07 18:50:24,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2019-12-07 18:50:24,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 321 transitions. [2019-12-07 18:50:24,143 INFO L711 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2019-12-07 18:50:24,143 INFO L591 BuchiCegarLoop]: Abstraction has 212 states and 321 transitions. [2019-12-07 18:50:24,143 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:50:24,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 321 transitions. [2019-12-07 18:50:24,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 173 [2019-12-07 18:50:24,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,147 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,147 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,147 INFO L794 eck$LassoCheckResult]: Stem: 948#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 887#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 888#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 970#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 980#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 941#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 942#L231-1 assume !(0 == ~M_E~0); 914#L334-1 assume !(0 == ~T1_E~0); 915#L339-1 assume !(0 == ~T2_E~0); 930#L344-1 assume !(0 == ~E_M~0); 1065#L349-1 assume !(0 == ~E_1~0); 992#L354-1 assume !(0 == ~E_2~0); 993#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1023#L156 assume 1 == ~m_pc~0; 1048#L157 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1049#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1051#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1052#L415 assume !(0 != activate_threads_~tmp~1); 1080#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 874#L175 assume 1 == ~t1_pc~0; 875#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 877#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 878#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 947#L423 assume !(0 != activate_threads_~tmp___0~0); 981#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 983#L194 assume !(1 == ~t2_pc~0); 1018#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 1019#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1024#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1011#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 986#L431-2 assume !(1 == ~M_E~0); 928#L372-1 assume !(1 == ~T1_E~0); 929#L377-1 assume !(1 == ~T2_E~0); 1064#L382-1 assume !(1 == ~E_M~0); 987#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 988#L392-1 assume !(1 == ~E_2~0); 919#L543-1 [2019-12-07 18:50:24,148 INFO L796 eck$LassoCheckResult]: Loop: 919#L543-1 assume !false; 885#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 886#L309 assume !false; 1028#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1075#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 884#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 922#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 923#L276 assume !(0 != eval_~tmp~0); 971#L324 start_simulation_~kernel_st~0 := 2; 972#L214-1 start_simulation_~kernel_st~0 := 3; 916#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 917#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 918#L339-3 assume !(0 == ~T2_E~0); 933#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1067#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1004#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1005#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1014#L156-12 assume 1 == ~m_pc~0; 1058#L157-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1059#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1061#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1062#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1073#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 982#L175-12 assume 1 == ~t1_pc~0; 952#L176-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 896#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 897#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 954#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 962#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 963#L194-12 assume 1 == ~t2_pc~0; 1006#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1001#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1002#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1077#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1084#L431-14 assume !(1 == ~M_E~0); 931#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 932#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1066#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 998#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 999#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1025#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1029#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 882#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 920#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 921#L562 assume !(0 == start_simulation_~tmp~3); 964#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1030#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 880#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 934#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 935#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 969#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 1026#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1076#L575 assume !(0 != start_simulation_~tmp___0~1); 919#L543-1 [2019-12-07 18:50:24,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,148 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2019-12-07 18:50:24,148 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,148 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721167242] [2019-12-07 18:50:24,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,171 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721167242] [2019-12-07 18:50:24,171 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,171 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:24,171 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173577060] [2019-12-07 18:50:24,172 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,172 INFO L82 PathProgramCache]: Analyzing trace with hash 752595754, now seen corresponding path program 1 times [2019-12-07 18:50:24,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19019281] [2019-12-07 18:50:24,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19019281] [2019-12-07 18:50:24,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,200 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385990199] [2019-12-07 18:50:24,201 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,202 INFO L87 Difference]: Start difference. First operand 212 states and 321 transitions. cyclomatic complexity: 110 Second operand 3 states. [2019-12-07 18:50:24,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,238 INFO L93 Difference]: Finished difference Result 378 states and 561 transitions. [2019-12-07 18:50:24,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 378 states and 561 transitions. [2019-12-07 18:50:24,241 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 338 [2019-12-07 18:50:24,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 378 states to 378 states and 561 transitions. [2019-12-07 18:50:24,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 378 [2019-12-07 18:50:24,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 378 [2019-12-07 18:50:24,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 378 states and 561 transitions. [2019-12-07 18:50:24,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,245 INFO L688 BuchiCegarLoop]: Abstraction has 378 states and 561 transitions. [2019-12-07 18:50:24,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states and 561 transitions. [2019-12-07 18:50:24,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 359. [2019-12-07 18:50:24,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2019-12-07 18:50:24,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 535 transitions. [2019-12-07 18:50:24,254 INFO L711 BuchiCegarLoop]: Abstraction has 359 states and 535 transitions. [2019-12-07 18:50:24,254 INFO L591 BuchiCegarLoop]: Abstraction has 359 states and 535 transitions. [2019-12-07 18:50:24,254 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:50:24,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 359 states and 535 transitions. [2019-12-07 18:50:24,256 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2019-12-07 18:50:24,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,257 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,257 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,257 INFO L794 eck$LassoCheckResult]: Stem: 1545#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1484#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1485#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1570#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 1581#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1538#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1539#L231-1 assume !(0 == ~M_E~0); 1510#L334-1 assume !(0 == ~T1_E~0); 1511#L339-1 assume !(0 == ~T2_E~0); 1527#L344-1 assume !(0 == ~E_M~0); 1667#L349-1 assume !(0 == ~E_1~0); 1594#L354-1 assume !(0 == ~E_2~0); 1595#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1627#L156 assume !(1 == ~m_pc~0); 1689#L156-2 is_master_triggered_~__retres1~0 := 0; 1690#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1653#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1654#L415 assume !(0 != activate_threads_~tmp~1); 1685#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1471#L175 assume 1 == ~t1_pc~0; 1472#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1474#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1475#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1544#L423 assume !(0 != activate_threads_~tmp___0~0); 1582#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1584#L194 assume !(1 == ~t2_pc~0); 1621#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 1622#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1628#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1614#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1587#L431-2 assume !(1 == ~M_E~0); 1525#L372-1 assume !(1 == ~T1_E~0); 1526#L377-1 assume !(1 == ~T2_E~0); 1666#L382-1 assume !(1 == ~E_M~0); 1588#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1589#L392-1 assume !(1 == ~E_2~0); 1624#L543-1 [2019-12-07 18:50:24,257 INFO L796 eck$LassoCheckResult]: Loop: 1624#L543-1 assume !false; 1733#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1730#L309 assume !false; 1728#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1723#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1722#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1721#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1720#L276 assume !(0 != eval_~tmp~0); 1571#L324 start_simulation_~kernel_st~0 := 2; 1572#L214-1 start_simulation_~kernel_st~0 := 3; 1579#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1514#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1515#L339-3 assume !(0 == ~T2_E~0); 1530#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1669#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1607#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1608#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1617#L156-12 assume !(1 == ~m_pc~0); 1678#L156-14 is_master_triggered_~__retres1~0 := 0; 1829#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1828#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1827#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1826#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1825#L175-12 assume !(1 == ~t1_pc~0); 1824#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 1822#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1821#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1820#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1561#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1562#L194-12 assume 1 == ~t2_pc~0; 1609#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1604#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1605#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1680#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1691#L431-14 assume !(1 == ~M_E~0); 1528#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1529#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1668#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1601#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1602#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1629#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1634#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1479#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1517#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1518#L562 assume !(0 == start_simulation_~tmp~3); 1563#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1635#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1755#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1751#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 1748#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1745#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 1743#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1739#L575 assume !(0 != start_simulation_~tmp___0~1); 1624#L543-1 [2019-12-07 18:50:24,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,257 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2019-12-07 18:50:24,258 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046000243] [2019-12-07 18:50:24,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046000243] [2019-12-07 18:50:24,276 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,276 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:24,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388155733] [2019-12-07 18:50:24,276 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,277 INFO L82 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 1 times [2019-12-07 18:50:24,277 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,277 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243391491] [2019-12-07 18:50:24,277 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243391491] [2019-12-07 18:50:24,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,298 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,298 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481861276] [2019-12-07 18:50:24,298 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,299 INFO L87 Difference]: Start difference. First operand 359 states and 535 transitions. cyclomatic complexity: 178 Second operand 3 states. [2019-12-07 18:50:24,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,328 INFO L93 Difference]: Finished difference Result 629 states and 927 transitions. [2019-12-07 18:50:24,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 629 states and 927 transitions. [2019-12-07 18:50:24,332 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2019-12-07 18:50:24,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 629 states to 629 states and 927 transitions. [2019-12-07 18:50:24,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 629 [2019-12-07 18:50:24,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 629 [2019-12-07 18:50:24,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 629 states and 927 transitions. [2019-12-07 18:50:24,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,338 INFO L688 BuchiCegarLoop]: Abstraction has 629 states and 927 transitions. [2019-12-07 18:50:24,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states and 927 transitions. [2019-12-07 18:50:24,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 625. [2019-12-07 18:50:24,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2019-12-07 18:50:24,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 923 transitions. [2019-12-07 18:50:24,348 INFO L711 BuchiCegarLoop]: Abstraction has 625 states and 923 transitions. [2019-12-07 18:50:24,348 INFO L591 BuchiCegarLoop]: Abstraction has 625 states and 923 transitions. [2019-12-07 18:50:24,349 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:50:24,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 625 states and 923 transitions. [2019-12-07 18:50:24,351 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2019-12-07 18:50:24,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,353 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,353 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,353 INFO L794 eck$LassoCheckResult]: Stem: 2539#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2478#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2479#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2570#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 2583#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2529#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2530#L231-1 assume !(0 == ~M_E~0); 2502#L334-1 assume !(0 == ~T1_E~0); 2503#L339-1 assume !(0 == ~T2_E~0); 2518#L344-1 assume !(0 == ~E_M~0); 2673#L349-1 assume !(0 == ~E_1~0); 2597#L354-1 assume !(0 == ~E_2~0); 2598#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2632#L156 assume !(1 == ~m_pc~0); 2706#L156-2 is_master_triggered_~__retres1~0 := 0; 2707#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2659#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2660#L415 assume !(0 != activate_threads_~tmp~1); 2697#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2466#L175 assume !(1 == ~t1_pc~0); 2467#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 2470#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2471#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2538#L423 assume !(0 != activate_threads_~tmp___0~0); 2585#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2587#L194 assume !(1 == ~t2_pc~0); 2627#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 2628#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2633#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2622#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2590#L431-2 assume !(1 == ~M_E~0); 2516#L372-1 assume !(1 == ~T1_E~0); 2517#L377-1 assume !(1 == ~T2_E~0); 2672#L382-1 assume !(1 == ~E_M~0); 2591#L387-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2592#L392-1 assume !(1 == ~E_2~0); 2507#L543-1 [2019-12-07 18:50:24,353 INFO L796 eck$LassoCheckResult]: Loop: 2507#L543-1 assume !false; 2476#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2477#L309 assume !false; 2638#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2684#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2475#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2510#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2511#L276 assume !(0 != eval_~tmp~0); 2573#L324 start_simulation_~kernel_st~0 := 2; 2574#L214-1 start_simulation_~kernel_st~0 := 3; 2504#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2505#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2506#L339-3 assume !(0 == ~T2_E~0); 2521#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2703#L349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2612#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2613#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2623#L156-12 assume !(1 == ~m_pc~0); 2685#L156-14 is_master_triggered_~__retres1~0 := 0; 2702#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2669#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2670#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2682#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2586#L175-12 assume !(1 == ~t1_pc~0); 2584#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 2486#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2487#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2549#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2559#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2560#L194-12 assume 1 == ~t2_pc~0; 2614#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2609#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2610#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2689#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2708#L431-14 assume !(1 == ~M_E~0); 2519#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2520#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2674#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2605#L387-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2606#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2634#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2639#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2473#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2508#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2509#L562 assume !(0 == start_simulation_~tmp~3); 2561#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2641#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2469#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2522#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 2523#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2569#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 2635#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2688#L575 assume !(0 != start_simulation_~tmp___0~1); 2507#L543-1 [2019-12-07 18:50:24,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,354 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2019-12-07 18:50:24,354 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,354 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069921781] [2019-12-07 18:50:24,354 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069921781] [2019-12-07 18:50:24,376 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,376 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:24,376 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883730575] [2019-12-07 18:50:24,376 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1069365080, now seen corresponding path program 2 times [2019-12-07 18:50:24,377 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,377 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508254019] [2019-12-07 18:50:24,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,397 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508254019] [2019-12-07 18:50:24,398 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,398 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,398 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083498156] [2019-12-07 18:50:24,398 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,399 INFO L87 Difference]: Start difference. First operand 625 states and 923 transitions. cyclomatic complexity: 302 Second operand 3 states. [2019-12-07 18:50:24,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,424 INFO L93 Difference]: Finished difference Result 625 states and 901 transitions. [2019-12-07 18:50:24,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 625 states and 901 transitions. [2019-12-07 18:50:24,430 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2019-12-07 18:50:24,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 625 states to 625 states and 901 transitions. [2019-12-07 18:50:24,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 625 [2019-12-07 18:50:24,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 625 [2019-12-07 18:50:24,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 625 states and 901 transitions. [2019-12-07 18:50:24,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,437 INFO L688 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2019-12-07 18:50:24,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 625 states and 901 transitions. [2019-12-07 18:50:24,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 625 to 625. [2019-12-07 18:50:24,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2019-12-07 18:50:24,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 901 transitions. [2019-12-07 18:50:24,450 INFO L711 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2019-12-07 18:50:24,451 INFO L591 BuchiCegarLoop]: Abstraction has 625 states and 901 transitions. [2019-12-07 18:50:24,451 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:50:24,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 625 states and 901 transitions. [2019-12-07 18:50:24,454 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2019-12-07 18:50:24,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,456 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,456 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,456 INFO L794 eck$LassoCheckResult]: Stem: 3795#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 3735#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3736#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3822#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 3832#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3787#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3788#L231-1 assume !(0 == ~M_E~0); 3760#L334-1 assume !(0 == ~T1_E~0); 3761#L339-1 assume !(0 == ~T2_E~0); 3776#L344-1 assume !(0 == ~E_M~0); 3918#L349-1 assume !(0 == ~E_1~0); 3844#L354-1 assume !(0 == ~E_2~0); 3845#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3877#L156 assume !(1 == ~m_pc~0); 3951#L156-2 is_master_triggered_~__retres1~0 := 0; 3952#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3904#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3905#L415 assume !(0 != activate_threads_~tmp~1); 3944#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3723#L175 assume !(1 == ~t1_pc~0); 3724#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 3725#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3726#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3794#L423 assume !(0 != activate_threads_~tmp___0~0); 3833#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3835#L194 assume !(1 == ~t2_pc~0); 3871#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 3872#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3878#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3864#L431 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3838#L431-2 assume !(1 == ~M_E~0); 3774#L372-1 assume !(1 == ~T1_E~0); 3775#L377-1 assume !(1 == ~T2_E~0); 3917#L382-1 assume !(1 == ~E_M~0); 3839#L387-1 assume !(1 == ~E_1~0); 3840#L392-1 assume !(1 == ~E_2~0); 3874#L543-1 [2019-12-07 18:50:24,456 INFO L796 eck$LassoCheckResult]: Loop: 3874#L543-1 assume !false; 4166#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4163#L309 assume !false; 4160#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3955#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3732#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4150#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4145#L276 assume !(0 != eval_~tmp~0); 3823#L324 start_simulation_~kernel_st~0 := 2; 3824#L214-1 start_simulation_~kernel_st~0 := 3; 3762#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3763#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3764#L339-3 assume !(0 == ~T2_E~0); 3779#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3920#L349-3 assume !(0 == ~E_1~0); 3857#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3858#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3867#L156-12 assume !(1 == ~m_pc~0); 3932#L156-14 is_master_triggered_~__retres1~0 := 0; 3948#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3914#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3915#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3926#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4281#L175-12 assume !(1 == ~t1_pc~0); 4280#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 4278#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4277#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4276#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4275#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4274#L194-12 assume 1 == ~t2_pc~0; 4272#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4269#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4268#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4265#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4264#L431-14 assume !(1 == ~M_E~0); 4252#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4249#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4247#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4242#L387-3 assume !(1 == ~E_1~0); 4236#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4231#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4225#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4219#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4214#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4207#L562 assume !(0 == start_simulation_~tmp~3); 4202#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4195#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4190#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4186#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 4182#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4181#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 4180#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4177#L575 assume !(0 != start_simulation_~tmp___0~1); 3874#L543-1 [2019-12-07 18:50:24,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,457 INFO L82 PathProgramCache]: Analyzing trace with hash 545629602, now seen corresponding path program 1 times [2019-12-07 18:50:24,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106446835] [2019-12-07 18:50:24,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106446835] [2019-12-07 18:50:24,503 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,503 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:50:24,503 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587397468] [2019-12-07 18:50:24,503 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,503 INFO L82 PathProgramCache]: Analyzing trace with hash 100371372, now seen corresponding path program 1 times [2019-12-07 18:50:24,504 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,504 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862890146] [2019-12-07 18:50:24,504 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,524 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862890146] [2019-12-07 18:50:24,524 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,525 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,525 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977481747] [2019-12-07 18:50:24,525 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,525 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:50:24,526 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:50:24,526 INFO L87 Difference]: Start difference. First operand 625 states and 901 transitions. cyclomatic complexity: 280 Second operand 5 states. [2019-12-07 18:50:24,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,651 INFO L93 Difference]: Finished difference Result 1460 states and 2110 transitions. [2019-12-07 18:50:24,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:50:24,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1460 states and 2110 transitions. [2019-12-07 18:50:24,659 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1384 [2019-12-07 18:50:24,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1460 states to 1460 states and 2110 transitions. [2019-12-07 18:50:24,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1460 [2019-12-07 18:50:24,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1460 [2019-12-07 18:50:24,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1460 states and 2110 transitions. [2019-12-07 18:50:24,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,671 INFO L688 BuchiCegarLoop]: Abstraction has 1460 states and 2110 transitions. [2019-12-07 18:50:24,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1460 states and 2110 transitions. [2019-12-07 18:50:24,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1460 to 676. [2019-12-07 18:50:24,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 676 states. [2019-12-07 18:50:24,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 952 transitions. [2019-12-07 18:50:24,686 INFO L711 BuchiCegarLoop]: Abstraction has 676 states and 952 transitions. [2019-12-07 18:50:24,686 INFO L591 BuchiCegarLoop]: Abstraction has 676 states and 952 transitions. [2019-12-07 18:50:24,686 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:50:24,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 676 states and 952 transitions. [2019-12-07 18:50:24,689 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 628 [2019-12-07 18:50:24,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,690 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,690 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,690 INFO L794 eck$LassoCheckResult]: Stem: 5896#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5833#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5834#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5922#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 5939#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5887#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5888#L231-1 assume !(0 == ~M_E~0); 5860#L334-1 assume !(0 == ~T1_E~0); 5861#L339-1 assume !(0 == ~T2_E~0); 5876#L344-1 assume !(0 == ~E_M~0); 6038#L349-1 assume !(0 == ~E_1~0); 5954#L354-1 assume !(0 == ~E_2~0); 5955#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5994#L156 assume !(1 == ~m_pc~0); 6087#L156-2 is_master_triggered_~__retres1~0 := 0; 6088#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6024#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6025#L415 assume !(0 != activate_threads_~tmp~1); 6070#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5821#L175 assume !(1 == ~t1_pc~0); 5822#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 5823#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5824#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5895#L423 assume !(0 != activate_threads_~tmp___0~0); 5941#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5943#L194 assume !(1 == ~t2_pc~0); 5988#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 5989#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5995#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5978#L431 assume !(0 != activate_threads_~tmp___1~0); 5946#L431-2 assume !(1 == ~M_E~0); 5874#L372-1 assume !(1 == ~T1_E~0); 5875#L377-1 assume !(1 == ~T2_E~0); 6037#L382-1 assume !(1 == ~E_M~0); 5947#L387-1 assume !(1 == ~E_1~0); 5948#L392-1 assume !(1 == ~E_2~0); 5991#L543-1 [2019-12-07 18:50:24,690 INFO L796 eck$LassoCheckResult]: Loop: 5991#L543-1 assume !false; 6443#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6227#L309 assume !false; 6436#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6432#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6402#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6276#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6272#L276 assume !(0 != eval_~tmp~0); 5923#L324 start_simulation_~kernel_st~0 := 2; 5924#L214-1 start_simulation_~kernel_st~0 := 3; 5862#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5863#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5864#L339-3 assume !(0 == ~T2_E~0); 5879#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6040#L349-3 assume !(0 == ~E_1~0); 5968#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5969#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5981#L156-12 assume !(1 == ~m_pc~0); 6053#L156-14 is_master_triggered_~__retres1~0 := 0; 6085#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6431#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6430#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6429#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6428#L175-12 assume !(1 == ~t1_pc~0); 6427#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 6426#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6425#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6424#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6423#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5970#L194-12 assume 1 == ~t2_pc~0; 5971#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6421#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6419#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6417#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6415#L431-14 assume !(1 == ~M_E~0); 6413#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6411#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6409#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6407#L387-3 assume !(1 == ~E_1~0); 6405#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6403#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6397#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6383#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6357#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6004#L562 assume !(0 == start_simulation_~tmp~3); 6005#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6464#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6462#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6461#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 6460#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6459#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 6458#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6446#L575 assume !(0 != start_simulation_~tmp___0~1); 5991#L543-1 [2019-12-07 18:50:24,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2019-12-07 18:50:24,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117985939] [2019-12-07 18:50:24,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,720 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:24,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,721 INFO L82 PathProgramCache]: Analyzing trace with hash 100371372, now seen corresponding path program 2 times [2019-12-07 18:50:24,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,721 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302497446] [2019-12-07 18:50:24,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302497446] [2019-12-07 18:50:24,750 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:24,751 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921295499] [2019-12-07 18:50:24,751 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,751 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,751 INFO L87 Difference]: Start difference. First operand 676 states and 952 transitions. cyclomatic complexity: 280 Second operand 3 states. [2019-12-07 18:50:24,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,769 INFO L93 Difference]: Finished difference Result 820 states and 1143 transitions. [2019-12-07 18:50:24,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 820 states and 1143 transitions. [2019-12-07 18:50:24,774 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 744 [2019-12-07 18:50:24,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 820 states to 820 states and 1143 transitions. [2019-12-07 18:50:24,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 820 [2019-12-07 18:50:24,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 820 [2019-12-07 18:50:24,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 820 states and 1143 transitions. [2019-12-07 18:50:24,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,780 INFO L688 BuchiCegarLoop]: Abstraction has 820 states and 1143 transitions. [2019-12-07 18:50:24,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 820 states and 1143 transitions. [2019-12-07 18:50:24,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 820 to 820. [2019-12-07 18:50:24,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 820 states. [2019-12-07 18:50:24,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 820 states to 820 states and 1143 transitions. [2019-12-07 18:50:24,789 INFO L711 BuchiCegarLoop]: Abstraction has 820 states and 1143 transitions. [2019-12-07 18:50:24,789 INFO L591 BuchiCegarLoop]: Abstraction has 820 states and 1143 transitions. [2019-12-07 18:50:24,790 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:50:24,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 820 states and 1143 transitions. [2019-12-07 18:50:24,792 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 744 [2019-12-07 18:50:24,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,793 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,793 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,793 INFO L794 eck$LassoCheckResult]: Stem: 7399#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7335#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7336#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7426#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 7440#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7390#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7391#L231-1 assume 0 == ~M_E~0;~M_E~0 := 1; 7362#L334-1 assume !(0 == ~T1_E~0); 7363#L339-1 assume !(0 == ~T2_E~0); 7379#L344-1 assume !(0 == ~E_M~0); 7607#L349-1 assume !(0 == ~E_1~0); 7455#L354-1 assume !(0 == ~E_2~0); 7456#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7493#L156 assume !(1 == ~m_pc~0); 7577#L156-2 is_master_triggered_~__retres1~0 := 0; 7578#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7584#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7602#L415 assume !(0 != activate_threads_~tmp~1); 7562#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7323#L175 assume !(1 == ~t1_pc~0); 7324#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 7325#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7326#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7397#L423 assume !(0 != activate_threads_~tmp___0~0); 7445#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7446#L194 assume !(1 == ~t2_pc~0); 7491#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 7599#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7597#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7593#L431 assume !(0 != activate_threads_~tmp___1~0); 7449#L431-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7377#L372-1 assume !(1 == ~T1_E~0); 7378#L377-1 assume !(1 == ~T2_E~0); 7534#L382-1 assume !(1 == ~E_M~0); 7450#L387-1 assume !(1 == ~E_1~0); 7451#L392-1 assume !(1 == ~E_2~0); 7489#L543-1 [2019-12-07 18:50:24,793 INFO L796 eck$LassoCheckResult]: Loop: 7489#L543-1 assume !false; 7984#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7981#L309 assume !false; 7979#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7862#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7859#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7856#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7851#L276 assume !(0 != eval_~tmp~0); 7427#L324 start_simulation_~kernel_st~0 := 2; 7428#L214-1 start_simulation_~kernel_st~0 := 3; 7364#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7365#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8138#L339-3 assume !(0 == ~T2_E~0); 8137#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8135#L349-3 assume !(0 == ~E_1~0); 8134#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8112#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8111#L156-12 assume !(1 == ~m_pc~0); 8110#L156-14 is_master_triggered_~__retres1~0 := 0; 8109#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8108#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 8107#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8106#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8105#L175-12 assume !(1 == ~t1_pc~0); 8104#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 8103#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7407#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7408#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7417#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7418#L194-12 assume !(1 == ~t2_pc~0); 7472#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 7466#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7467#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7556#L431-12 assume !(0 != activate_threads_~tmp___1~0); 7579#L431-14 assume 1 == ~M_E~0;~M_E~0 := 2; 7380#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7381#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7537#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7570#L387-3 assume !(1 == ~E_1~0); 7861#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7858#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7854#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7850#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7848#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 7845#L562 assume !(0 == start_simulation_~tmp~3); 7419#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7503#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7328#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7383#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 7384#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7425#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 7496#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 7583#L575 assume !(0 != start_simulation_~tmp___0~1); 7489#L543-1 [2019-12-07 18:50:24,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,793 INFO L82 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2019-12-07 18:50:24,794 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,794 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260841963] [2019-12-07 18:50:24,794 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,805 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260841963] [2019-12-07 18:50:24,805 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,805 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:24,805 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722459473] [2019-12-07 18:50:24,805 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:24,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,805 INFO L82 PathProgramCache]: Analyzing trace with hash -618728313, now seen corresponding path program 1 times [2019-12-07 18:50:24,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,806 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382966353] [2019-12-07 18:50:24,806 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,827 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382966353] [2019-12-07 18:50:24,828 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,828 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:50:24,828 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519543302] [2019-12-07 18:50:24,828 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,828 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:24,828 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:24,828 INFO L87 Difference]: Start difference. First operand 820 states and 1143 transitions. cyclomatic complexity: 327 Second operand 3 states. [2019-12-07 18:50:24,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,838 INFO L93 Difference]: Finished difference Result 676 states and 938 transitions. [2019-12-07 18:50:24,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:24,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 676 states and 938 transitions. [2019-12-07 18:50:24,841 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 628 [2019-12-07 18:50:24,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 676 states to 676 states and 938 transitions. [2019-12-07 18:50:24,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 676 [2019-12-07 18:50:24,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 676 [2019-12-07 18:50:24,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 676 states and 938 transitions. [2019-12-07 18:50:24,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,845 INFO L688 BuchiCegarLoop]: Abstraction has 676 states and 938 transitions. [2019-12-07 18:50:24,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states and 938 transitions. [2019-12-07 18:50:24,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 676. [2019-12-07 18:50:24,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 676 states. [2019-12-07 18:50:24,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 938 transitions. [2019-12-07 18:50:24,853 INFO L711 BuchiCegarLoop]: Abstraction has 676 states and 938 transitions. [2019-12-07 18:50:24,853 INFO L591 BuchiCegarLoop]: Abstraction has 676 states and 938 transitions. [2019-12-07 18:50:24,853 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:50:24,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 676 states and 938 transitions. [2019-12-07 18:50:24,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 628 [2019-12-07 18:50:24,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,855 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,855 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,855 INFO L794 eck$LassoCheckResult]: Stem: 8905#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8840#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8841#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8931#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 8942#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8893#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8894#L231-1 assume !(0 == ~M_E~0); 8866#L334-1 assume !(0 == ~T1_E~0); 8867#L339-1 assume !(0 == ~T2_E~0); 8882#L344-1 assume !(0 == ~E_M~0); 9029#L349-1 assume !(0 == ~E_1~0); 8955#L354-1 assume !(0 == ~E_2~0); 8956#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8989#L156 assume !(1 == ~m_pc~0); 9065#L156-2 is_master_triggered_~__retres1~0 := 0; 9066#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9015#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9016#L415 assume !(0 != activate_threads_~tmp~1); 9055#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8828#L175 assume !(1 == ~t1_pc~0); 8829#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 8832#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8833#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8904#L423 assume !(0 != activate_threads_~tmp___0~0); 8943#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8945#L194 assume !(1 == ~t2_pc~0); 8982#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 8983#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8990#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8977#L431 assume !(0 != activate_threads_~tmp___1~0); 8948#L431-2 assume !(1 == ~M_E~0); 8880#L372-1 assume !(1 == ~T1_E~0); 8881#L377-1 assume !(1 == ~T2_E~0); 9028#L382-1 assume !(1 == ~E_M~0); 8949#L387-1 assume !(1 == ~E_1~0); 8950#L392-1 assume !(1 == ~E_2~0); 8987#L543-1 [2019-12-07 18:50:24,856 INFO L796 eck$LassoCheckResult]: Loop: 8987#L543-1 assume !false; 9145#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9140#L309 assume !false; 9138#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9134#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9133#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9132#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9129#L276 assume !(0 != eval_~tmp~0); 9130#L324 start_simulation_~kernel_st~0 := 2; 9257#L214-1 start_simulation_~kernel_st~0 := 3; 9255#L334-2 assume !(0 == ~M_E~0); 9254#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9253#L339-3 assume !(0 == ~T2_E~0); 9252#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9251#L349-3 assume !(0 == ~E_1~0); 9249#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9248#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9247#L156-12 assume !(1 == ~m_pc~0); 9245#L156-14 is_master_triggered_~__retres1~0 := 0; 9244#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9243#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9242#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9240#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9238#L175-12 assume !(1 == ~t1_pc~0); 9236#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 9234#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9232#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9230#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9228#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9226#L194-12 assume !(1 == ~t2_pc~0); 9222#L194-14 is_transmit2_triggered_~__retres1~2 := 0; 9220#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9218#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9216#L431-12 assume !(0 != activate_threads_~tmp___1~0); 9214#L431-14 assume !(1 == ~M_E~0); 9210#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9208#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9206#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9204#L387-3 assume !(1 == ~E_1~0); 9201#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9199#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9195#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9192#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9190#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 9188#L562 assume !(0 == start_simulation_~tmp~3); 9186#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9182#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9179#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9177#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 9175#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9173#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 9171#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 9169#L575 assume !(0 != start_simulation_~tmp___0~1); 8987#L543-1 [2019-12-07 18:50:24,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,856 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2019-12-07 18:50:24,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770223352] [2019-12-07 18:50:24,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,866 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:24,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1089901963, now seen corresponding path program 1 times [2019-12-07 18:50:24,866 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,866 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814668322] [2019-12-07 18:50:24,866 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:24,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:24,885 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814668322] [2019-12-07 18:50:24,885 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:24,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:50:24,886 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445220887] [2019-12-07 18:50:24,886 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:24,886 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:24,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:50:24,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:50:24,886 INFO L87 Difference]: Start difference. First operand 676 states and 938 transitions. cyclomatic complexity: 266 Second operand 5 states. [2019-12-07 18:50:24,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:24,949 INFO L93 Difference]: Finished difference Result 1160 states and 1584 transitions. [2019-12-07 18:50:24,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:50:24,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1160 states and 1584 transitions. [2019-12-07 18:50:24,956 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1104 [2019-12-07 18:50:24,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1160 states to 1160 states and 1584 transitions. [2019-12-07 18:50:24,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1160 [2019-12-07 18:50:24,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1160 [2019-12-07 18:50:24,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1160 states and 1584 transitions. [2019-12-07 18:50:24,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:24,966 INFO L688 BuchiCegarLoop]: Abstraction has 1160 states and 1584 transitions. [2019-12-07 18:50:24,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1160 states and 1584 transitions. [2019-12-07 18:50:24,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1160 to 688. [2019-12-07 18:50:24,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 688 states. [2019-12-07 18:50:24,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 950 transitions. [2019-12-07 18:50:24,976 INFO L711 BuchiCegarLoop]: Abstraction has 688 states and 950 transitions. [2019-12-07 18:50:24,976 INFO L591 BuchiCegarLoop]: Abstraction has 688 states and 950 transitions. [2019-12-07 18:50:24,976 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:50:24,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 950 transitions. [2019-12-07 18:50:24,978 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 640 [2019-12-07 18:50:24,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:24,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:24,979 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,979 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:24,979 INFO L794 eck$LassoCheckResult]: Stem: 10754#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10693#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10694#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10783#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 10794#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10745#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10746#L231-1 assume !(0 == ~M_E~0); 10718#L334-1 assume !(0 == ~T1_E~0); 10719#L339-1 assume !(0 == ~T2_E~0); 10734#L344-1 assume !(0 == ~E_M~0); 10889#L349-1 assume !(0 == ~E_1~0); 10810#L354-1 assume !(0 == ~E_2~0); 10811#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10847#L156 assume !(1 == ~m_pc~0); 10930#L156-2 is_master_triggered_~__retres1~0 := 0; 10931#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10875#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10876#L415 assume !(0 != activate_threads_~tmp~1); 10918#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10680#L175 assume !(1 == ~t1_pc~0); 10681#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 10684#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10685#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10753#L423 assume !(0 != activate_threads_~tmp___0~0); 10796#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10799#L194 assume !(1 == ~t2_pc~0); 10841#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 10842#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10848#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10835#L431 assume !(0 != activate_threads_~tmp___1~0); 10803#L431-2 assume !(1 == ~M_E~0); 10732#L372-1 assume !(1 == ~T1_E~0); 10733#L377-1 assume !(1 == ~T2_E~0); 10888#L382-1 assume !(1 == ~E_M~0); 10804#L387-1 assume !(1 == ~E_1~0); 10805#L392-1 assume !(1 == ~E_2~0); 10844#L543-1 [2019-12-07 18:50:24,979 INFO L796 eck$LassoCheckResult]: Loop: 10844#L543-1 assume !false; 11161#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11160#L309 assume !false; 10904#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10905#L244 assume !(0 == ~m_st~0); 10748#L248 assume !(0 == ~t1_st~0); 10688#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 10690#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11158#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11157#L276 assume !(0 != eval_~tmp~0); 10784#L324 start_simulation_~kernel_st~0 := 2; 10785#L214-1 start_simulation_~kernel_st~0 := 3; 10720#L334-2 assume !(0 == ~M_E~0); 10721#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10722#L339-3 assume !(0 == ~T2_E~0); 10737#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10895#L349-3 assume !(0 == ~E_1~0); 10825#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10826#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10836#L156-12 assume !(1 == ~m_pc~0); 10906#L156-14 is_master_triggered_~__retres1~0 := 0; 11232#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10885#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10886#L415-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10901#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10902#L175-12 assume !(1 == ~t1_pc~0); 11231#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 11230#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11229#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 11228#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11227#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11226#L194-12 assume 1 == ~t2_pc~0; 11224#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11222#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11220#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11218#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11217#L431-14 assume !(1 == ~M_E~0); 11216#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11215#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11214#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11213#L387-3 assume !(1 == ~E_1~0); 11212#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11211#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11209#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11205#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11202#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 11198#L562 assume !(0 == start_simulation_~tmp~3); 11194#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11192#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 11187#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11183#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 11179#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11175#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 11172#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 11168#L575 assume !(0 != start_simulation_~tmp___0~1); 10844#L543-1 [2019-12-07 18:50:24,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,979 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2019-12-07 18:50:24,979 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,980 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768037788] [2019-12-07 18:50:24,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:24,989 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:24,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:24,989 INFO L82 PathProgramCache]: Analyzing trace with hash -640188235, now seen corresponding path program 1 times [2019-12-07 18:50:24,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:24,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330022875] [2019-12-07 18:50:24,990 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:24,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,024 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330022875] [2019-12-07 18:50:25,024 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,024 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:50:25,024 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865252342] [2019-12-07 18:50:25,024 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:25,025 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:50:25,025 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:50:25,025 INFO L87 Difference]: Start difference. First operand 688 states and 950 transitions. cyclomatic complexity: 266 Second operand 5 states. [2019-12-07 18:50:25,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,120 INFO L93 Difference]: Finished difference Result 1317 states and 1797 transitions. [2019-12-07 18:50:25,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:50:25,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1317 states and 1797 transitions. [2019-12-07 18:50:25,125 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1265 [2019-12-07 18:50:25,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1317 states to 1317 states and 1797 transitions. [2019-12-07 18:50:25,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1317 [2019-12-07 18:50:25,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1317 [2019-12-07 18:50:25,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1317 states and 1797 transitions. [2019-12-07 18:50:25,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:25,134 INFO L688 BuchiCegarLoop]: Abstraction has 1317 states and 1797 transitions. [2019-12-07 18:50:25,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1317 states and 1797 transitions. [2019-12-07 18:50:25,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1317 to 715. [2019-12-07 18:50:25,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 715 states. [2019-12-07 18:50:25,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 715 states to 715 states and 969 transitions. [2019-12-07 18:50:25,143 INFO L711 BuchiCegarLoop]: Abstraction has 715 states and 969 transitions. [2019-12-07 18:50:25,143 INFO L591 BuchiCegarLoop]: Abstraction has 715 states and 969 transitions. [2019-12-07 18:50:25,143 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:50:25,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 715 states and 969 transitions. [2019-12-07 18:50:25,145 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 667 [2019-12-07 18:50:25,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:25,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:25,146 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,146 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,146 INFO L794 eck$LassoCheckResult]: Stem: 12773#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12711#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12712#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12798#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 12809#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12763#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12764#L231-1 assume !(0 == ~M_E~0); 12736#L334-1 assume !(0 == ~T1_E~0); 12737#L339-1 assume !(0 == ~T2_E~0); 12752#L344-1 assume !(0 == ~E_M~0); 12900#L349-1 assume !(0 == ~E_1~0); 12822#L354-1 assume !(0 == ~E_2~0); 12823#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12857#L156 assume !(1 == ~m_pc~0); 12946#L156-2 is_master_triggered_~__retres1~0 := 0; 12947#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12886#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12887#L415 assume !(0 != activate_threads_~tmp~1); 12933#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12698#L175 assume !(1 == ~t1_pc~0); 12699#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 12702#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12703#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12772#L423 assume !(0 != activate_threads_~tmp___0~0); 12811#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12813#L194 assume !(1 == ~t2_pc~0); 12851#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 12852#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12942#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12846#L431 assume !(0 != activate_threads_~tmp___1~0); 12816#L431-2 assume !(1 == ~M_E~0); 12750#L372-1 assume !(1 == ~T1_E~0); 12751#L377-1 assume !(1 == ~T2_E~0); 12899#L382-1 assume !(1 == ~E_M~0); 12817#L387-1 assume !(1 == ~E_1~0); 12818#L392-1 assume !(1 == ~E_2~0); 12854#L543-1 [2019-12-07 18:50:25,146 INFO L796 eck$LassoCheckResult]: Loop: 12854#L543-1 assume !false; 13172#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13170#L309 assume !false; 13168#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13165#L244 assume !(0 == ~m_st~0); 13166#L248 assume !(0 == ~t1_st~0); 13164#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 13161#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13121#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13122#L276 assume !(0 != eval_~tmp~0); 13154#L324 start_simulation_~kernel_st~0 := 2; 13151#L214-1 start_simulation_~kernel_st~0 := 3; 13148#L334-2 assume !(0 == ~M_E~0); 13146#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13144#L339-3 assume !(0 == ~T2_E~0); 13142#L344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13140#L349-3 assume !(0 == ~E_1~0); 13138#L354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13136#L359-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12917#L156-12 assume !(1 == ~m_pc~0); 12918#L156-14 is_master_triggered_~__retres1~0 := 0; 13195#L167-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13191#L168-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 13187#L415-12 assume !(0 != activate_threads_~tmp~1); 13183#L415-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13178#L175-12 assume !(1 == ~t1_pc~0); 13176#L175-14 is_transmit1_triggered_~__retres1~1 := 0; 13171#L186-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13169#L187-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13167#L423-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13163#L423-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13160#L194-12 assume 1 == ~t2_pc~0; 13157#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13155#L205-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13152#L206-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13149#L431-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13147#L431-14 assume !(1 == ~M_E~0); 13145#L372-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13143#L377-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13141#L382-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13139#L387-3 assume !(1 == ~E_1~0); 13137#L392-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13135#L397-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13133#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13130#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13128#L262-1 start_simulation_#t~ret9 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 13125#L562 assume !(0 == start_simulation_~tmp~3); 13126#L562-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret8, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13202#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13199#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13196#L262-2 stop_simulation_#t~ret8 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret8;havoc stop_simulation_#t~ret8; 13192#L517 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13188#L524 stop_simulation_#res := stop_simulation_~__retres2~0; 13184#L525 start_simulation_#t~ret10 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 13179#L575 assume !(0 != start_simulation_~tmp___0~1); 12854#L543-1 [2019-12-07 18:50:25,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2019-12-07 18:50:25,147 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,147 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766687961] [2019-12-07 18:50:25,147 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,158 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,158 INFO L82 PathProgramCache]: Analyzing trace with hash -365428621, now seen corresponding path program 1 times [2019-12-07 18:50:25,158 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619615374] [2019-12-07 18:50:25,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619615374] [2019-12-07 18:50:25,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,179 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:25,179 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713790591] [2019-12-07 18:50:25,179 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:50:25,179 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:25,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:25,179 INFO L87 Difference]: Start difference. First operand 715 states and 969 transitions. cyclomatic complexity: 258 Second operand 3 states. [2019-12-07 18:50:25,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,206 INFO L93 Difference]: Finished difference Result 1118 states and 1489 transitions. [2019-12-07 18:50:25,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:25,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1118 states and 1489 transitions. [2019-12-07 18:50:25,212 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1064 [2019-12-07 18:50:25,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1118 states to 1118 states and 1489 transitions. [2019-12-07 18:50:25,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1118 [2019-12-07 18:50:25,220 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1118 [2019-12-07 18:50:25,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1118 states and 1489 transitions. [2019-12-07 18:50:25,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:25,222 INFO L688 BuchiCegarLoop]: Abstraction has 1118 states and 1489 transitions. [2019-12-07 18:50:25,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1118 states and 1489 transitions. [2019-12-07 18:50:25,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1118 to 1083. [2019-12-07 18:50:25,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1083 states. [2019-12-07 18:50:25,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1083 states to 1083 states and 1444 transitions. [2019-12-07 18:50:25,238 INFO L711 BuchiCegarLoop]: Abstraction has 1083 states and 1444 transitions. [2019-12-07 18:50:25,238 INFO L591 BuchiCegarLoop]: Abstraction has 1083 states and 1444 transitions. [2019-12-07 18:50:25,238 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:50:25,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1083 states and 1444 transitions. [2019-12-07 18:50:25,241 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1029 [2019-12-07 18:50:25,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:25,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:25,241 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,242 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,242 INFO L794 eck$LassoCheckResult]: Stem: 14612#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 14550#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14551#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14641#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 14652#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14603#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14604#L231-1 assume !(0 == ~M_E~0); 14575#L334-1 assume !(0 == ~T1_E~0); 14576#L339-1 assume !(0 == ~T2_E~0); 14591#L344-1 assume !(0 == ~E_M~0); 14745#L349-1 assume !(0 == ~E_1~0); 14666#L354-1 assume !(0 == ~E_2~0); 14667#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14701#L156 assume !(1 == ~m_pc~0); 14785#L156-2 is_master_triggered_~__retres1~0 := 0; 14786#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14731#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 14732#L415 assume !(0 != activate_threads_~tmp~1); 14772#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14537#L175 assume !(1 == ~t1_pc~0); 14538#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 14541#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14542#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14611#L423 assume !(0 != activate_threads_~tmp___0~0); 14655#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14657#L194 assume !(1 == ~t2_pc~0); 14695#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 14696#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14702#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14690#L431 assume !(0 != activate_threads_~tmp___1~0); 14660#L431-2 assume !(1 == ~M_E~0); 14589#L372-1 assume !(1 == ~T1_E~0); 14590#L377-1 assume !(1 == ~T2_E~0); 14744#L382-1 assume !(1 == ~E_M~0); 14661#L387-1 assume !(1 == ~E_1~0); 14662#L392-1 assume !(1 == ~E_2~0); 14699#L543-1 assume !false; 15353#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15349#L309 [2019-12-07 18:50:25,242 INFO L796 eck$LassoCheckResult]: Loop: 15349#L309 assume !false; 15345#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15341#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15338#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15336#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15331#L276 assume 0 != eval_~tmp~0; 15330#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 14585#L284 assume !(0 != eval_~tmp_ndt_1~0); 14586#L281 assume !(0 == ~t1_st~0); 15307#L295 assume !(0 == ~t2_st~0); 15349#L309 [2019-12-07 18:50:25,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,242 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2019-12-07 18:50:25,242 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,242 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946623160] [2019-12-07 18:50:25,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,252 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,252 INFO L82 PathProgramCache]: Analyzing trace with hash -1924965839, now seen corresponding path program 1 times [2019-12-07 18:50:25,252 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,252 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78886501] [2019-12-07 18:50:25,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,257 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,257 INFO L82 PathProgramCache]: Analyzing trace with hash -460324554, now seen corresponding path program 1 times [2019-12-07 18:50:25,258 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288434332] [2019-12-07 18:50:25,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,273 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288434332] [2019-12-07 18:50:25,273 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,273 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:25,273 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660837883] [2019-12-07 18:50:25,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:25,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:25,314 INFO L87 Difference]: Start difference. First operand 1083 states and 1444 transitions. cyclomatic complexity: 367 Second operand 3 states. [2019-12-07 18:50:25,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,354 INFO L93 Difference]: Finished difference Result 1950 states and 2570 transitions. [2019-12-07 18:50:25,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:25,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1950 states and 2570 transitions. [2019-12-07 18:50:25,365 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1666 [2019-12-07 18:50:25,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1950 states to 1950 states and 2570 transitions. [2019-12-07 18:50:25,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1950 [2019-12-07 18:50:25,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1950 [2019-12-07 18:50:25,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1950 states and 2570 transitions. [2019-12-07 18:50:25,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:25,382 INFO L688 BuchiCegarLoop]: Abstraction has 1950 states and 2570 transitions. [2019-12-07 18:50:25,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1950 states and 2570 transitions. [2019-12-07 18:50:25,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1950 to 1898. [2019-12-07 18:50:25,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1898 states. [2019-12-07 18:50:25,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1898 states to 1898 states and 2506 transitions. [2019-12-07 18:50:25,409 INFO L711 BuchiCegarLoop]: Abstraction has 1898 states and 2506 transitions. [2019-12-07 18:50:25,409 INFO L591 BuchiCegarLoop]: Abstraction has 1898 states and 2506 transitions. [2019-12-07 18:50:25,409 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:50:25,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1898 states and 2506 transitions. [2019-12-07 18:50:25,414 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1614 [2019-12-07 18:50:25,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:25,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:25,415 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,415 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,415 INFO L794 eck$LassoCheckResult]: Stem: 17656#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17591#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17592#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17682#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 17695#L221-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 17645#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17646#L231-1 assume !(0 == ~M_E~0); 17616#L334-1 assume !(0 == ~T1_E~0); 17617#L339-1 assume !(0 == ~T2_E~0); 17632#L344-1 assume !(0 == ~E_M~0); 17792#L349-1 assume !(0 == ~E_1~0); 17711#L354-1 assume !(0 == ~E_2~0); 17712#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17747#L156 assume !(1 == ~m_pc~0); 17834#L156-2 is_master_triggered_~__retres1~0 := 0; 17835#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17778#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 17779#L415 assume !(0 != activate_threads_~tmp~1); 17823#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17578#L175 assume !(1 == ~t1_pc~0); 17579#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 17582#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17583#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 17655#L423 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17697#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18527#L194 assume !(1 == ~t2_pc~0); 18525#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 17748#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17749#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17735#L431 assume !(0 != activate_threads_~tmp___1~0); 17705#L431-2 assume !(1 == ~M_E~0); 17630#L372-1 assume !(1 == ~T1_E~0); 17631#L377-1 assume !(1 == ~T2_E~0); 17791#L382-1 assume !(1 == ~E_M~0); 17706#L387-1 assume !(1 == ~E_1~0); 17707#L392-1 assume !(1 == ~E_2~0); 17744#L543-1 assume !false; 18450#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 18446#L309 [2019-12-07 18:50:25,415 INFO L796 eck$LassoCheckResult]: Loop: 18446#L309 assume !false; 18444#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 18441#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 18439#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 18431#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 18426#L276 assume 0 != eval_~tmp~0; 18420#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 18414#L284 assume !(0 != eval_~tmp_ndt_1~0); 18415#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 18430#L298 assume !(0 != eval_~tmp_ndt_2~0); 18454#L295 assume !(0 == ~t2_st~0); 18446#L309 [2019-12-07 18:50:25,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,416 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2019-12-07 18:50:25,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791027355] [2019-12-07 18:50:25,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,424 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791027355] [2019-12-07 18:50:25,424 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,424 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:50:25,425 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607651986] [2019-12-07 18:50:25,425 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:50:25,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,425 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 1 times [2019-12-07 18:50:25,425 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,425 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531625002] [2019-12-07 18:50:25,425 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,430 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:25,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:25,472 INFO L87 Difference]: Start difference. First operand 1898 states and 2506 transitions. cyclomatic complexity: 617 Second operand 3 states. [2019-12-07 18:50:25,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,478 INFO L93 Difference]: Finished difference Result 1225 states and 1616 transitions. [2019-12-07 18:50:25,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:25,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1225 states and 1616 transitions. [2019-12-07 18:50:25,483 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1169 [2019-12-07 18:50:25,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1225 states to 1225 states and 1616 transitions. [2019-12-07 18:50:25,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1225 [2019-12-07 18:50:25,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1225 [2019-12-07 18:50:25,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1225 states and 1616 transitions. [2019-12-07 18:50:25,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:25,494 INFO L688 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2019-12-07 18:50:25,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1225 states and 1616 transitions. [2019-12-07 18:50:25,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1225 to 1225. [2019-12-07 18:50:25,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1225 states. [2019-12-07 18:50:25,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 1225 states and 1616 transitions. [2019-12-07 18:50:25,511 INFO L711 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2019-12-07 18:50:25,511 INFO L591 BuchiCegarLoop]: Abstraction has 1225 states and 1616 transitions. [2019-12-07 18:50:25,512 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:50:25,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1225 states and 1616 transitions. [2019-12-07 18:50:25,514 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1169 [2019-12-07 18:50:25,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:25,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:25,514 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,514 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,514 INFO L794 eck$LassoCheckResult]: Stem: 20786#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 20720#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 20721#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20814#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 20825#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20776#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20777#L231-1 assume !(0 == ~M_E~0); 20747#L334-1 assume !(0 == ~T1_E~0); 20748#L339-1 assume !(0 == ~T2_E~0); 20763#L344-1 assume !(0 == ~E_M~0); 20920#L349-1 assume !(0 == ~E_1~0); 20838#L354-1 assume !(0 == ~E_2~0); 20839#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20872#L156 assume !(1 == ~m_pc~0); 20968#L156-2 is_master_triggered_~__retres1~0 := 0; 20969#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20906#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 20907#L415 assume !(0 != activate_threads_~tmp~1); 20956#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20707#L175 assume !(1 == ~t1_pc~0); 20708#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 20711#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20712#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20785#L423 assume !(0 != activate_threads_~tmp___0~0); 20826#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20828#L194 assume !(1 == ~t2_pc~0); 20866#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 20867#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20964#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20860#L431 assume !(0 != activate_threads_~tmp___1~0); 20832#L431-2 assume !(1 == ~M_E~0); 20761#L372-1 assume !(1 == ~T1_E~0); 20762#L377-1 assume !(1 == ~T2_E~0); 20919#L382-1 assume !(1 == ~E_M~0); 20833#L387-1 assume !(1 == ~E_1~0); 20834#L392-1 assume !(1 == ~E_2~0); 20869#L543-1 assume !false; 21051#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 21049#L309 [2019-12-07 18:50:25,515 INFO L796 eck$LassoCheckResult]: Loop: 21049#L309 assume !false; 21047#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 21043#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 21041#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 21039#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 21037#L276 assume 0 != eval_~tmp~0; 21033#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 21029#L284 assume !(0 != eval_~tmp_ndt_1~0); 21030#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 21061#L298 assume !(0 != eval_~tmp_ndt_2~0); 21055#L295 assume !(0 == ~t2_st~0); 21049#L309 [2019-12-07 18:50:25,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,515 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2019-12-07 18:50:25,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082265745] [2019-12-07 18:50:25,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,523 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,523 INFO L82 PathProgramCache]: Analyzing trace with hash 455496318, now seen corresponding path program 2 times [2019-12-07 18:50:25,523 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,524 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956926925] [2019-12-07 18:50:25,524 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,528 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,528 INFO L82 PathProgramCache]: Analyzing trace with hash -1385264103, now seen corresponding path program 1 times [2019-12-07 18:50:25,528 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,528 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542975999] [2019-12-07 18:50:25,528 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:50:25,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:50:25,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542975999] [2019-12-07 18:50:25,542 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:50:25,542 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:50:25,542 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830399805] [2019-12-07 18:50:25,587 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:50:25,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:50:25,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:50:25,588 INFO L87 Difference]: Start difference. First operand 1225 states and 1616 transitions. cyclomatic complexity: 397 Second operand 3 states. [2019-12-07 18:50:25,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:50:25,615 INFO L93 Difference]: Finished difference Result 1951 states and 2556 transitions. [2019-12-07 18:50:25,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:50:25,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1951 states and 2556 transitions. [2019-12-07 18:50:25,620 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1881 [2019-12-07 18:50:25,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1951 states to 1951 states and 2556 transitions. [2019-12-07 18:50:25,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1951 [2019-12-07 18:50:25,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1951 [2019-12-07 18:50:25,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1951 states and 2556 transitions. [2019-12-07 18:50:25,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:50:25,632 INFO L688 BuchiCegarLoop]: Abstraction has 1951 states and 2556 transitions. [2019-12-07 18:50:25,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1951 states and 2556 transitions. [2019-12-07 18:50:25,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1951 to 1915. [2019-12-07 18:50:25,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1915 states. [2019-12-07 18:50:25,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1915 states to 1915 states and 2520 transitions. [2019-12-07 18:50:25,663 INFO L711 BuchiCegarLoop]: Abstraction has 1915 states and 2520 transitions. [2019-12-07 18:50:25,663 INFO L591 BuchiCegarLoop]: Abstraction has 1915 states and 2520 transitions. [2019-12-07 18:50:25,663 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:50:25,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1915 states and 2520 transitions. [2019-12-07 18:50:25,668 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1845 [2019-12-07 18:50:25,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:50:25,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:50:25,669 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,669 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:50:25,669 INFO L794 eck$LassoCheckResult]: Stem: 23973#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 23903#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 23904#L506 havoc start_simulation_#t~ret9, start_simulation_#t~ret10, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24007#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 24020#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23960#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23961#L231-1 assume !(0 == ~M_E~0); 23930#L334-1 assume !(0 == ~T1_E~0); 23931#L339-1 assume !(0 == ~T2_E~0); 23947#L344-1 assume !(0 == ~E_M~0); 24111#L349-1 assume !(0 == ~E_1~0); 24032#L354-1 assume !(0 == ~E_2~0); 24033#L359-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24066#L156 assume !(1 == ~m_pc~0); 24158#L156-2 is_master_triggered_~__retres1~0 := 0; 24159#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24097#L168 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 24098#L415 assume !(0 != activate_threads_~tmp~1); 24144#L415-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23891#L175 assume !(1 == ~t1_pc~0); 23892#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 23893#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23894#L187 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23972#L423 assume !(0 != activate_threads_~tmp___0~0); 24021#L423-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24023#L194 assume !(1 == ~t2_pc~0); 24060#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 24061#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24151#L206 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 24053#L431 assume !(0 != activate_threads_~tmp___1~0); 24026#L431-2 assume !(1 == ~M_E~0); 23945#L372-1 assume !(1 == ~T1_E~0); 23946#L377-1 assume !(1 == ~T2_E~0); 24110#L382-1 assume !(1 == ~E_M~0); 24027#L387-1 assume !(1 == ~E_1~0); 24028#L392-1 assume !(1 == ~E_2~0); 24063#L543-1 assume !false; 25486#L544 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 25485#L309 [2019-12-07 18:50:25,670 INFO L796 eck$LassoCheckResult]: Loop: 25485#L309 assume !false; 25484#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25481#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25480#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25479#L262 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 25478#L276 assume 0 != eval_~tmp~0; 25476#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 23940#L284 assume !(0 != eval_~tmp_ndt_1~0); 23941#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 25491#L298 assume !(0 != eval_~tmp_ndt_2~0); 25489#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 25011#L312 assume !(0 != eval_~tmp_ndt_3~0); 25485#L309 [2019-12-07 18:50:25,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,670 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2019-12-07 18:50:25,670 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,670 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232906239] [2019-12-07 18:50:25,671 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,682 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,683 INFO L82 PathProgramCache]: Analyzing trace with hash 1235481233, now seen corresponding path program 1 times [2019-12-07 18:50:25,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344022091] [2019-12-07 18:50:25,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,689 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:50:25,689 INFO L82 PathProgramCache]: Analyzing trace with hash 6483030, now seen corresponding path program 1 times [2019-12-07 18:50:25,689 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:50:25,689 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684366560] [2019-12-07 18:50:25,690 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:50:25,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:50:25,703 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:50:25,979 WARN L192 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2019-12-07 18:50:26,051 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:50:26 BoogieIcfgContainer [2019-12-07 18:50:26,051 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:50:26,051 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:50:26,051 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:50:26,051 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:50:26,052 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:50:23" (3/4) ... [2019-12-07 18:50:26,054 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:50:26,093 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_1cef51f7-d463-42a8-b4a8-14a909190e66/bin/uautomizer/witness.graphml [2019-12-07 18:50:26,093 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:50:26,094 INFO L168 Benchmark]: Toolchain (without parser) took 3062.70 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 165.7 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -114.6 MB). Peak memory consumption was 51.1 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,094 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:50:26,095 INFO L168 Benchmark]: CACSL2BoogieTranslator took 230.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -157.2 MB). Peak memory consumption was 24.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,095 INFO L168 Benchmark]: Boogie Procedure Inliner took 33.63 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:50:26,095 INFO L168 Benchmark]: Boogie Preprocessor took 29.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,095 INFO L168 Benchmark]: RCFGBuilder took 427.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 60.8 MB). Peak memory consumption was 60.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,095 INFO L168 Benchmark]: BuchiAutomizer took 2297.24 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 64.0 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -31.1 MB). Peak memory consumption was 32.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,096 INFO L168 Benchmark]: Witness Printer took 41.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:50:26,097 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 230.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -157.2 MB). Peak memory consumption was 24.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 33.63 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 29.31 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 427.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 60.8 MB). Peak memory consumption was 60.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 2297.24 ms. Allocated memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: 64.0 MB). Free memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: -31.1 MB). Peak memory consumption was 32.9 MB. Max. memory is 11.5 GB. * Witness Printer took 41.98 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.2 MB). Peak memory consumption was 2.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1915 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.2s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 1.1s. Construction of modules took 0.2s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 14 MinimizatonAttempts, 2004 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1915 states and ocurred in iteration 14. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 4414 SDtfs, 4669 SDslu, 4566 SDs, 0 SdLazy, 316 SolverSat, 133 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.2s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65990d97=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@434137e8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@226d265d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45414937=0, T2_E=2, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f1aed03=0, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40038a15=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a6e5b31=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@46c1d3fe=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@192c42cd=0, t1_st=0, \result=0, t2_pc=0, local=0, m_st=0, tmp___1=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int t2_st ; [L20] int m_i ; [L21] int t1_i ; [L22] int t2_i ; [L23] int M_E = 2; [L24] int T1_E = 2; [L25] int T2_E = 2; [L26] int E_M = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L33] int token ; [L35] int local ; [L588] int __retres1 ; [L502] m_i = 1 [L503] t1_i = 1 [L504] t2_i = 1 [L529] int kernel_st ; [L530] int tmp ; [L531] int tmp___0 ; [L535] kernel_st = 0 [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_M == 0) [L354] COND FALSE !(E_1 == 0) [L359] COND FALSE !(E_2 == 0) [L407] int tmp ; [L408] int tmp___0 ; [L409] int tmp___1 ; [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L413] tmp = is_master_triggered() [L415] COND FALSE !(\read(tmp)) [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L421] tmp___0 = is_transmit1_triggered() [L423] COND FALSE !(\read(tmp___0)) [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L429] tmp___1 = is_transmit2_triggered() [L431] COND FALSE !(\read(tmp___1)) [L372] COND FALSE !(M_E == 1) [L377] COND FALSE !(T1_E == 1) [L382] COND FALSE !(T2_E == 1) [L387] COND FALSE !(E_M == 1) [L392] COND FALSE !(E_1 == 1) [L397] COND FALSE !(E_2 == 1) [L543] COND TRUE 1 [L546] kernel_st = 1 [L267] int tmp ; Loop: [L271] COND TRUE 1 [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...