./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 69fb30bd96659b6c61b59030d7ea8c3053fedc35 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:24:01,187 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:24:01,188 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:24:01,196 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:24:01,196 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:24:01,197 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:24:01,198 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:24:01,200 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:24:01,201 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:24:01,202 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:24:01,203 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:24:01,204 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:24:01,204 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:24:01,205 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:24:01,205 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:24:01,206 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:24:01,207 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:24:01,208 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:24:01,209 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:24:01,211 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:24:01,212 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:24:01,212 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:24:01,213 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:24:01,213 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:24:01,215 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:24:01,215 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:24:01,215 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:24:01,216 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:24:01,216 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:24:01,217 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:24:01,217 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:24:01,218 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:24:01,218 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:24:01,219 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:24:01,220 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:24:01,220 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:24:01,220 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:24:01,220 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:24:01,221 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:24:01,221 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:24:01,222 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:24:01,222 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 18:24:01,236 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:24:01,236 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:24:01,237 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:24:01,237 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:24:01,237 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:24:01,238 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:24:01,238 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:24:01,238 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:24:01,238 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:24:01,238 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:24:01,238 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:24:01,239 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:24:01,239 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:24:01,240 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:24:01,241 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:24:01,241 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:24:01,241 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:24:01,241 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:24:01,241 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:24:01,242 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:24:01,242 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:24:01,242 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:24:01,243 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:24:01,243 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 69fb30bd96659b6c61b59030d7ea8c3053fedc35 [2019-12-07 18:24:01,340 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:24:01,350 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:24:01,354 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:24:01,355 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:24:01,355 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:24:01,356 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2019-12-07 18:24:01,401 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/data/b2c16d267/b4e99e101acf411bbce70ed368009f6e/FLAGc8ae1717f [2019-12-07 18:24:01,732 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:24:01,733 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2019-12-07 18:24:01,741 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/data/b2c16d267/b4e99e101acf411bbce70ed368009f6e/FLAGc8ae1717f [2019-12-07 18:24:01,751 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/data/b2c16d267/b4e99e101acf411bbce70ed368009f6e [2019-12-07 18:24:01,753 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:24:01,754 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:24:01,754 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:24:01,755 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:24:01,757 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:24:01,757 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:24:01" (1/1) ... [2019-12-07 18:24:01,759 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38a937d5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:01, skipping insertion in model container [2019-12-07 18:24:01,759 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:24:01" (1/1) ... [2019-12-07 18:24:01,764 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:24:01,789 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:24:01,955 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:24:01,958 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:24:01,986 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:24:01,999 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:24:02,000 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02 WrapperNode [2019-12-07 18:24:02,000 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:24:02,000 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:24:02,000 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:24:02,000 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:24:02,006 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,011 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,037 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:24:02,038 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:24:02,038 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:24:02,038 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:24:02,044 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,044 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,047 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,047 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,055 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,064 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,066 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... [2019-12-07 18:24:02,071 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:24:02,071 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:24:02,071 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:24:02,071 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:24:02,072 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:24:02,119 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:24:02,120 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:24:02,623 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:24:02,623 INFO L287 CfgBuilder]: Removed 132 assume(true) statements. [2019-12-07 18:24:02,624 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:24:02 BoogieIcfgContainer [2019-12-07 18:24:02,624 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:24:02,624 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:24:02,625 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:24:02,627 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:24:02,627 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:24:02,627 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:24:01" (1/3) ... [2019-12-07 18:24:02,628 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e05105b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:24:02, skipping insertion in model container [2019-12-07 18:24:02,628 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:24:02,628 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:24:02" (2/3) ... [2019-12-07 18:24:02,628 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e05105b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:24:02, skipping insertion in model container [2019-12-07 18:24:02,628 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:24:02,629 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:24:02" (3/3) ... [2019-12-07 18:24:02,630 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2019-12-07 18:24:02,658 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:24:02,658 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:24:02,658 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:24:02,658 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:24:02,658 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:24:02,658 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:24:02,658 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:24:02,658 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:24:02,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states. [2019-12-07 18:24:02,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 259 [2019-12-07 18:24:02,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:02,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:02,708 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,708 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,708 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:24:02,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states. [2019-12-07 18:24:02,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 259 [2019-12-07 18:24:02,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:02,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:02,719 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,719 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,725 INFO L794 eck$LassoCheckResult]: Stem: 119#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8#L643true havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 250#L287true assume !(1 == ~m_i~0);~m_st~0 := 2; 289#L294-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 167#L299-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 209#L304-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 228#L309-1true assume !(0 == ~M_E~0); 156#L431-1true assume !(0 == ~T1_E~0); 186#L436-1true assume !(0 == ~T2_E~0); 239#L441-1true assume !(0 == ~T3_E~0); 109#L446-1true assume !(0 == ~E_M~0); 127#L451-1true assume 0 == ~E_1~0;~E_1~0 := 1; 148#L456-1true assume !(0 == ~E_2~0); 39#L461-1true assume !(0 == ~E_3~0); 76#L466-1true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 222#L210true assume 1 == ~m_pc~0; 304#L211true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 223#L221true is_master_triggered_#res := is_master_triggered_~__retres1~0; 305#L222true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15#L533true assume !(0 != activate_threads_~tmp~1); 144#L533-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84#L229true assume !(1 == ~t1_pc~0); 99#L229-2true is_transmit1_triggered_~__retres1~1 := 0; 85#L240true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11#L241true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 169#L541true assume !(0 != activate_threads_~tmp___0~0); 171#L541-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114#L248true assume 1 == ~t2_pc~0; 208#L249true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 116#L259true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 210#L260true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 57#L549true assume !(0 != activate_threads_~tmp___1~0); 33#L549-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 284#L267true assume 1 == ~t3_pc~0; 73#L268true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 285#L278true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 74#L279true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 216#L557true assume !(0 != activate_threads_~tmp___2~0); 224#L557-2true assume 1 == ~M_E~0;~M_E~0 := 2; 106#L479-1true assume !(1 == ~T1_E~0); 125#L484-1true assume !(1 == ~T2_E~0); 146#L489-1true assume !(1 == ~T3_E~0); 34#L494-1true assume !(1 == ~E_M~0); 72#L499-1true assume !(1 == ~E_1~0); 262#L504-1true assume !(1 == ~E_2~0); 286#L509-1true assume !(1 == ~E_3~0); 271#L680-1true [2019-12-07 18:24:02,725 INFO L796 eck$LassoCheckResult]: Loop: 271#L680-1true assume !false; 55#L681true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 43#L406true assume !true; 287#L421true start_simulation_~kernel_st~0 := 2; 225#L287-1true start_simulation_~kernel_st~0 := 3; 158#L431-2true assume 0 == ~M_E~0;~M_E~0 := 1; 160#L431-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 199#L436-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 243#L441-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 115#L446-3true assume !(0 == ~E_M~0); 132#L451-3true assume 0 == ~E_1~0;~E_1~0 := 1; 152#L456-3true assume 0 == ~E_2~0;~E_2~0 := 1; 50#L461-3true assume 0 == ~E_3~0;~E_3~0 := 1; 81#L466-3true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 204#L210-15true assume !(1 == ~m_pc~0); 194#L210-17true is_master_triggered_~__retres1~0 := 0; 234#L221-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 315#L222-5true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 138#L533-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 124#L533-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70#L229-15true assume !(1 == ~t1_pc~0); 52#L229-17true is_transmit1_triggered_~__retres1~1 := 0; 92#L240-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24#L241-5true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 294#L541-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 299#L541-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 226#L248-15true assume 1 == ~t2_pc~0; 166#L249-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 247#L259-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 183#L260-5true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14#L549-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 143#L549-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86#L267-15true assume !(1 == ~t3_pc~0); 83#L267-17true is_transmit3_triggered_~__retres1~3 := 0; 261#L278-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42#L279-5true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 168#L557-15true assume !(0 != activate_threads_~tmp___2~0); 170#L557-17true assume 1 == ~M_E~0;~M_E~0 := 2; 112#L479-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 130#L484-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 150#L489-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 46#L494-3true assume 1 == ~E_M~0;~E_M~0 := 2; 77#L499-3true assume 1 == ~E_1~0;~E_1~0 := 2; 266#L504-3true assume 1 == ~E_2~0;~E_2~0 := 2; 288#L509-3true assume !(1 == ~E_3~0); 306#L514-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 280#L322-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 279#L344-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 61#L345-1true start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 122#L699true assume !(0 == start_simulation_~tmp~3); 123#L699-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 282#L322-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 281#L344-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 64#L345-2true stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7#L654true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 103#L661true stop_simulation_#res := stop_simulation_~__retres2~0; 180#L662true start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 308#L712true assume !(0 != start_simulation_~tmp___0~1); 271#L680-1true [2019-12-07 18:24:02,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:02,730 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2019-12-07 18:24:02,736 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:02,736 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643691657] [2019-12-07 18:24:02,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:02,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:02,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:02,837 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643691657] [2019-12-07 18:24:02,838 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:02,838 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:02,839 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471286910] [2019-12-07 18:24:02,842 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:02,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:02,842 INFO L82 PathProgramCache]: Analyzing trace with hash 1954748526, now seen corresponding path program 1 times [2019-12-07 18:24:02,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:02,843 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913389557] [2019-12-07 18:24:02,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:02,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:02,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:02,856 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913389557] [2019-12-07 18:24:02,857 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:02,857 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:02,857 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023954886] [2019-12-07 18:24:02,858 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:02,859 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:02,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:02,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:02,870 INFO L87 Difference]: Start difference. First operand 314 states. Second operand 3 states. [2019-12-07 18:24:02,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:02,901 INFO L93 Difference]: Finished difference Result 314 states and 476 transitions. [2019-12-07 18:24:02,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:02,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 476 transitions. [2019-12-07 18:24:02,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:02,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 308 states and 470 transitions. [2019-12-07 18:24:02,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2019-12-07 18:24:02,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2019-12-07 18:24:02,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 470 transitions. [2019-12-07 18:24:02,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:02,921 INFO L688 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2019-12-07 18:24:02,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 470 transitions. [2019-12-07 18:24:02,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2019-12-07 18:24:02,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2019-12-07 18:24:02,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 470 transitions. [2019-12-07 18:24:02,955 INFO L711 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2019-12-07 18:24:02,955 INFO L591 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2019-12-07 18:24:02,955 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:24:02,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 470 transitions. [2019-12-07 18:24:02,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:02,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:02,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:02,959 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,959 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:02,960 INFO L794 eck$LassoCheckResult]: Stem: 819#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 664#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 648#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 649#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 933#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 867#L299-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 868#L304-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 906#L309-1 assume !(0 == ~M_E~0); 849#L431-1 assume !(0 == ~T1_E~0); 850#L436-1 assume !(0 == ~T2_E~0); 887#L441-1 assume !(0 == ~T3_E~0); 801#L446-1 assume !(0 == ~E_M~0); 802#L451-1 assume 0 == ~E_1~0;~E_1~0 := 1; 827#L456-1 assume !(0 == ~E_2~0); 714#L461-1 assume !(0 == ~E_3~0); 715#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 773#L210 assume 1 == ~m_pc~0; 922#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 913#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 923#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 662#L533 assume !(0 != activate_threads_~tmp~1); 663#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 780#L229 assume !(1 == ~t1_pc~0); 654#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 653#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 655#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 656#L541 assume !(0 != activate_threads_~tmp___0~0); 870#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 811#L248 assume 1 == ~t2_pc~0; 812#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 804#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 815#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 743#L549 assume !(0 != activate_threads_~tmp___1~0); 700#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 701#L267 assume 1 == ~t3_pc~0; 768#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 769#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 771#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 772#L557 assume !(0 != activate_threads_~tmp___2~0); 918#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 794#L479-1 assume !(1 == ~T1_E~0); 795#L484-1 assume !(1 == ~T2_E~0); 826#L489-1 assume !(1 == ~T3_E~0); 705#L494-1 assume !(1 == ~E_M~0); 706#L499-1 assume !(1 == ~E_1~0); 767#L504-1 assume !(1 == ~E_2~0); 935#L509-1 assume !(1 == ~E_3~0); 937#L680-1 [2019-12-07 18:24:02,960 INFO L796 eck$LassoCheckResult]: Loop: 937#L680-1 assume !false; 741#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 642#L406 assume !false; 720#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 938#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 747#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 744#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 745#L359 assume !(0 != eval_~tmp~0); 897#L421 start_simulation_~kernel_st~0 := 2; 924#L287-1 start_simulation_~kernel_st~0 := 3; 852#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 853#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 855#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 901#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 813#L446-3 assume !(0 == ~E_M~0); 814#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 832#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 736#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 737#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 779#L210-15 assume 1 == ~m_pc~0; 903#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 895#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 929#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 837#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 823#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 766#L229-15 assume 1 == ~t1_pc~0; 675#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 676#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 680#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 681#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 942#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 925#L248-15 assume !(1 == ~t2_pc~0); 865#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 864#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 881#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 660#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 661#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 781#L267-15 assume 1 == ~t3_pc~0; 711#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 712#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 716#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 717#L557-15 assume !(0 != activate_threads_~tmp___2~0); 869#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 807#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 808#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 830#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 724#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 725#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 774#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 936#L509-3 assume !(1 == ~E_3~0); 940#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 939#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 751#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 748#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 749#L699 assume !(0 == start_simulation_~tmp~3); 782#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 822#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 755#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 752#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 643#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 644#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 791#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 879#L712 assume !(0 != start_simulation_~tmp___0~1); 937#L680-1 [2019-12-07 18:24:02,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:02,961 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2019-12-07 18:24:02,961 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:02,961 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491880468] [2019-12-07 18:24:02,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:02,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:02,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:02,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491880468] [2019-12-07 18:24:02,992 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:02,992 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:02,993 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915606499] [2019-12-07 18:24:02,993 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:02,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:02,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1189287647, now seen corresponding path program 1 times [2019-12-07 18:24:02,994 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:02,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569271854] [2019-12-07 18:24:02,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,051 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569271854] [2019-12-07 18:24:03,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804497864] [2019-12-07 18:24:03,052 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,053 INFO L87 Difference]: Start difference. First operand 308 states and 470 transitions. cyclomatic complexity: 163 Second operand 3 states. [2019-12-07 18:24:03,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,065 INFO L93 Difference]: Finished difference Result 308 states and 469 transitions. [2019-12-07 18:24:03,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 469 transitions. [2019-12-07 18:24:03,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 469 transitions. [2019-12-07 18:24:03,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2019-12-07 18:24:03,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2019-12-07 18:24:03,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 469 transitions. [2019-12-07 18:24:03,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,072 INFO L688 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2019-12-07 18:24:03,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 469 transitions. [2019-12-07 18:24:03,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2019-12-07 18:24:03,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2019-12-07 18:24:03,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 469 transitions. [2019-12-07 18:24:03,081 INFO L711 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2019-12-07 18:24:03,081 INFO L591 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2019-12-07 18:24:03,081 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:24:03,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 469 transitions. [2019-12-07 18:24:03,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,084 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,084 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,085 INFO L794 eck$LassoCheckResult]: Stem: 1442#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1287#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1273#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1274#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 1556#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1490#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1491#L304-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1530#L309-1 assume !(0 == ~M_E~0); 1472#L431-1 assume !(0 == ~T1_E~0); 1473#L436-1 assume !(0 == ~T2_E~0); 1510#L441-1 assume !(0 == ~T3_E~0); 1424#L446-1 assume !(0 == ~E_M~0); 1425#L451-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1452#L456-1 assume !(0 == ~E_2~0); 1337#L461-1 assume !(0 == ~E_3~0); 1338#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1396#L210 assume 1 == ~m_pc~0; 1545#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1536#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1546#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1285#L533 assume !(0 != activate_threads_~tmp~1); 1286#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1403#L229 assume !(1 == ~t1_pc~0); 1277#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 1276#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1278#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1279#L541 assume !(0 != activate_threads_~tmp___0~0); 1493#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1436#L248 assume 1 == ~t2_pc~0; 1437#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1427#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1438#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1366#L549 assume !(0 != activate_threads_~tmp___1~0); 1323#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1324#L267 assume 1 == ~t3_pc~0; 1391#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1392#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1394#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1395#L557 assume !(0 != activate_threads_~tmp___2~0); 1541#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1420#L479-1 assume !(1 == ~T1_E~0); 1421#L484-1 assume !(1 == ~T2_E~0); 1449#L489-1 assume !(1 == ~T3_E~0); 1328#L494-1 assume !(1 == ~E_M~0); 1329#L499-1 assume !(1 == ~E_1~0); 1390#L504-1 assume !(1 == ~E_2~0); 1558#L509-1 assume !(1 == ~E_3~0); 1560#L680-1 [2019-12-07 18:24:03,085 INFO L796 eck$LassoCheckResult]: Loop: 1560#L680-1 assume !false; 1364#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1263#L406 assume !false; 1343#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1561#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1370#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1367#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1368#L359 assume !(0 != eval_~tmp~0); 1520#L421 start_simulation_~kernel_st~0 := 2; 1547#L287-1 start_simulation_~kernel_st~0 := 3; 1475#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1476#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1478#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1524#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1434#L446-3 assume !(0 == ~E_M~0); 1435#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1455#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1356#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1357#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1399#L210-15 assume 1 == ~m_pc~0; 1526#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1518#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1552#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1460#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1446#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1387#L229-15 assume 1 == ~t1_pc~0; 1298#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1299#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1303#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1304#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1565#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1548#L248-15 assume !(1 == ~t2_pc~0); 1489#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 1488#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1504#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1283#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1284#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1404#L267-15 assume 1 == ~t3_pc~0; 1334#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1335#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1341#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1342#L557-15 assume !(0 != activate_threads_~tmp___2~0); 1492#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1430#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1431#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1454#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1350#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1351#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1397#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1559#L509-3 assume !(1 == ~E_3~0); 1563#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1562#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1374#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1371#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1372#L699 assume !(0 == start_simulation_~tmp~3); 1405#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1445#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1378#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1376#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1269#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1270#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 1414#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1502#L712 assume !(0 != start_simulation_~tmp___0~1); 1560#L680-1 [2019-12-07 18:24:03,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,085 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2019-12-07 18:24:03,085 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,085 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595971796] [2019-12-07 18:24:03,085 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595971796] [2019-12-07 18:24:03,103 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,103 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,104 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735383350] [2019-12-07 18:24:03,104 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,104 INFO L82 PathProgramCache]: Analyzing trace with hash 1189287647, now seen corresponding path program 2 times [2019-12-07 18:24:03,104 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,104 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668653036] [2019-12-07 18:24:03,105 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668653036] [2019-12-07 18:24:03,134 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,134 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,134 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074491217] [2019-12-07 18:24:03,135 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,135 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,135 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,135 INFO L87 Difference]: Start difference. First operand 308 states and 469 transitions. cyclomatic complexity: 162 Second operand 3 states. [2019-12-07 18:24:03,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,145 INFO L93 Difference]: Finished difference Result 308 states and 468 transitions. [2019-12-07 18:24:03,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 468 transitions. [2019-12-07 18:24:03,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,151 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 468 transitions. [2019-12-07 18:24:03,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2019-12-07 18:24:03,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2019-12-07 18:24:03,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 468 transitions. [2019-12-07 18:24:03,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,154 INFO L688 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2019-12-07 18:24:03,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 468 transitions. [2019-12-07 18:24:03,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2019-12-07 18:24:03,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2019-12-07 18:24:03,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 468 transitions. [2019-12-07 18:24:03,161 INFO L711 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2019-12-07 18:24:03,162 INFO L591 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2019-12-07 18:24:03,162 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:24:03,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 468 transitions. [2019-12-07 18:24:03,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,164 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,164 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,165 INFO L794 eck$LassoCheckResult]: Stem: 2065#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1910#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1894#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1895#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 2179#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2113#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2114#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2152#L309-1 assume !(0 == ~M_E~0); 2095#L431-1 assume !(0 == ~T1_E~0); 2096#L436-1 assume !(0 == ~T2_E~0); 2132#L441-1 assume !(0 == ~T3_E~0); 2047#L446-1 assume !(0 == ~E_M~0); 2048#L451-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2073#L456-1 assume !(0 == ~E_2~0); 1957#L461-1 assume !(0 == ~E_3~0); 1958#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2019#L210 assume 1 == ~m_pc~0; 2168#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2159#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2169#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1908#L533 assume !(0 != activate_threads_~tmp~1); 1909#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2026#L229 assume !(1 == ~t1_pc~0); 1900#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 1899#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1901#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1902#L541 assume !(0 != activate_threads_~tmp___0~0); 2116#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2057#L248 assume 1 == ~t2_pc~0; 2058#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2050#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2061#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1989#L549 assume !(0 != activate_threads_~tmp___1~0); 1946#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1947#L267 assume 1 == ~t3_pc~0; 2014#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2015#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2017#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2018#L557 assume !(0 != activate_threads_~tmp___2~0); 2162#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2040#L479-1 assume !(1 == ~T1_E~0); 2041#L484-1 assume !(1 == ~T2_E~0); 2070#L489-1 assume !(1 == ~T3_E~0); 1948#L494-1 assume !(1 == ~E_M~0); 1949#L499-1 assume !(1 == ~E_1~0); 2013#L504-1 assume !(1 == ~E_2~0); 2181#L509-1 assume !(1 == ~E_3~0); 2183#L680-1 [2019-12-07 18:24:03,165 INFO L796 eck$LassoCheckResult]: Loop: 2183#L680-1 assume !false; 1987#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1886#L406 assume !false; 1966#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2184#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1993#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1990#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1991#L359 assume !(0 != eval_~tmp~0); 2142#L421 start_simulation_~kernel_st~0 := 2; 2170#L287-1 start_simulation_~kernel_st~0 := 3; 2098#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2099#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2101#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2147#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2059#L446-3 assume !(0 == ~E_M~0); 2060#L451-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2078#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1979#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1980#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2025#L210-15 assume 1 == ~m_pc~0; 2149#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2141#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2175#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2083#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2069#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2010#L229-15 assume 1 == ~t1_pc~0; 1921#L230-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1922#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1926#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1927#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2188#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2171#L248-15 assume !(1 == ~t2_pc~0); 2112#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 2111#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2127#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1906#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1907#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2027#L267-15 assume 1 == ~t3_pc~0; 1959#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1960#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1964#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1965#L557-15 assume !(0 != activate_threads_~tmp___2~0); 2115#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2053#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2054#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2077#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1973#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1974#L499-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2020#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2182#L509-3 assume !(1 == ~E_3~0); 2186#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2185#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1997#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1994#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1995#L699 assume !(0 == start_simulation_~tmp~3); 2028#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2068#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2001#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1999#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1892#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1893#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 2037#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2125#L712 assume !(0 != start_simulation_~tmp___0~1); 2183#L680-1 [2019-12-07 18:24:03,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,165 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2019-12-07 18:24:03,165 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,165 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667820420] [2019-12-07 18:24:03,165 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667820420] [2019-12-07 18:24:03,189 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,189 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:03,189 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087908242] [2019-12-07 18:24:03,190 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,190 INFO L82 PathProgramCache]: Analyzing trace with hash 1189287647, now seen corresponding path program 3 times [2019-12-07 18:24:03,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803559273] [2019-12-07 18:24:03,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803559273] [2019-12-07 18:24:03,224 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,224 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,224 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838583547] [2019-12-07 18:24:03,224 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,225 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,225 INFO L87 Difference]: Start difference. First operand 308 states and 468 transitions. cyclomatic complexity: 161 Second operand 3 states. [2019-12-07 18:24:03,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,253 INFO L93 Difference]: Finished difference Result 308 states and 457 transitions. [2019-12-07 18:24:03,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 457 transitions. [2019-12-07 18:24:03,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 457 transitions. [2019-12-07 18:24:03,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2019-12-07 18:24:03,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2019-12-07 18:24:03,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 457 transitions. [2019-12-07 18:24:03,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,258 INFO L688 BuchiCegarLoop]: Abstraction has 308 states and 457 transitions. [2019-12-07 18:24:03,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 457 transitions. [2019-12-07 18:24:03,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2019-12-07 18:24:03,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2019-12-07 18:24:03,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 457 transitions. [2019-12-07 18:24:03,264 INFO L711 BuchiCegarLoop]: Abstraction has 308 states and 457 transitions. [2019-12-07 18:24:03,264 INFO L591 BuchiCegarLoop]: Abstraction has 308 states and 457 transitions. [2019-12-07 18:24:03,264 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:24:03,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 457 transitions. [2019-12-07 18:24:03,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2019-12-07 18:24:03,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,266 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,267 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,267 INFO L794 eck$LassoCheckResult]: Stem: 2688#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2532#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2517#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2518#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 2802#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2736#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2737#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2775#L309-1 assume !(0 == ~M_E~0); 2718#L431-1 assume !(0 == ~T1_E~0); 2719#L436-1 assume !(0 == ~T2_E~0); 2755#L441-1 assume !(0 == ~T3_E~0); 2670#L446-1 assume !(0 == ~E_M~0); 2671#L451-1 assume !(0 == ~E_1~0); 2696#L456-1 assume !(0 == ~E_2~0); 2575#L461-1 assume !(0 == ~E_3~0); 2576#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2641#L210 assume 1 == ~m_pc~0; 2791#L211 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2782#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2792#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2530#L533 assume !(0 != activate_threads_~tmp~1); 2531#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2648#L229 assume !(1 == ~t1_pc~0); 2522#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 2649#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2523#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2524#L541 assume !(0 != activate_threads_~tmp___0~0); 2739#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2680#L248 assume 1 == ~t2_pc~0; 2681#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2673#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2684#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2608#L549 assume !(0 != activate_threads_~tmp___1~0); 2563#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2564#L267 assume 1 == ~t3_pc~0; 2635#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2636#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2638#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2639#L557 assume !(0 != activate_threads_~tmp___2~0); 2785#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2663#L479-1 assume !(1 == ~T1_E~0); 2664#L484-1 assume !(1 == ~T2_E~0); 2693#L489-1 assume !(1 == ~T3_E~0); 2565#L494-1 assume !(1 == ~E_M~0); 2566#L499-1 assume !(1 == ~E_1~0); 2634#L504-1 assume !(1 == ~E_2~0); 2804#L509-1 assume !(1 == ~E_3~0); 2806#L680-1 [2019-12-07 18:24:03,267 INFO L796 eck$LassoCheckResult]: Loop: 2806#L680-1 assume !false; 2606#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2509#L406 assume !false; 2584#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2807#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2613#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2609#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2610#L359 assume !(0 != eval_~tmp~0); 2765#L421 start_simulation_~kernel_st~0 := 2; 2793#L287-1 start_simulation_~kernel_st~0 := 3; 2721#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2722#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2724#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2770#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2682#L446-3 assume !(0 == ~E_M~0); 2683#L451-3 assume !(0 == ~E_1~0); 2701#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2597#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2598#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2647#L210-15 assume 1 == ~m_pc~0; 2772#L211-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2764#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2798#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2706#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2692#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2631#L229-15 assume !(1 == ~t1_pc~0); 2543#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 2602#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2546#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2547#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2811#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2794#L248-15 assume 1 == ~t2_pc~0; 2733#L249-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2734#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2750#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2528#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2529#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2650#L267-15 assume 1 == ~t3_pc~0; 2577#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2578#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2582#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2583#L557-15 assume !(0 != activate_threads_~tmp___2~0); 2738#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2676#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2677#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2700#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2591#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2592#L499-3 assume !(1 == ~E_1~0); 2642#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2805#L509-3 assume !(1 == ~E_3~0); 2809#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2808#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2617#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2614#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2615#L699 assume !(0 == start_simulation_~tmp~3); 2651#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2691#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2621#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2619#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2515#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2516#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 2660#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2748#L712 assume !(0 != start_simulation_~tmp___0~1); 2806#L680-1 [2019-12-07 18:24:03,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,267 INFO L82 PathProgramCache]: Analyzing trace with hash 989493984, now seen corresponding path program 1 times [2019-12-07 18:24:03,268 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,268 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541290005] [2019-12-07 18:24:03,268 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,285 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541290005] [2019-12-07 18:24:03,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,285 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:03,285 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244150826] [2019-12-07 18:24:03,285 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,286 INFO L82 PathProgramCache]: Analyzing trace with hash 1711727387, now seen corresponding path program 1 times [2019-12-07 18:24:03,286 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,286 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756316782] [2019-12-07 18:24:03,286 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756316782] [2019-12-07 18:24:03,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,310 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142078890] [2019-12-07 18:24:03,310 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,311 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,311 INFO L87 Difference]: Start difference. First operand 308 states and 457 transitions. cyclomatic complexity: 150 Second operand 3 states. [2019-12-07 18:24:03,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,347 INFO L93 Difference]: Finished difference Result 552 states and 805 transitions. [2019-12-07 18:24:03,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 805 transitions. [2019-12-07 18:24:03,351 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 500 [2019-12-07 18:24:03,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 805 transitions. [2019-12-07 18:24:03,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2019-12-07 18:24:03,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2019-12-07 18:24:03,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 805 transitions. [2019-12-07 18:24:03,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,355 INFO L688 BuchiCegarLoop]: Abstraction has 552 states and 805 transitions. [2019-12-07 18:24:03,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 805 transitions. [2019-12-07 18:24:03,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 526. [2019-12-07 18:24:03,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 526 states. [2019-12-07 18:24:03,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 769 transitions. [2019-12-07 18:24:03,364 INFO L711 BuchiCegarLoop]: Abstraction has 526 states and 769 transitions. [2019-12-07 18:24:03,364 INFO L591 BuchiCegarLoop]: Abstraction has 526 states and 769 transitions. [2019-12-07 18:24:03,364 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:24:03,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 526 states and 769 transitions. [2019-12-07 18:24:03,366 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 474 [2019-12-07 18:24:03,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,368 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,368 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,368 INFO L794 eck$LassoCheckResult]: Stem: 3559#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3399#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3386#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3387#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 3679#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3610#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3611#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3651#L309-1 assume !(0 == ~M_E~0); 3592#L431-1 assume !(0 == ~T1_E~0); 3593#L436-1 assume !(0 == ~T2_E~0); 3630#L441-1 assume !(0 == ~T3_E~0); 3541#L446-1 assume !(0 == ~E_M~0); 3542#L451-1 assume !(0 == ~E_1~0); 3569#L456-1 assume !(0 == ~E_2~0); 3445#L461-1 assume !(0 == ~E_3~0); 3446#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3509#L210 assume !(1 == ~m_pc~0); 3655#L210-2 is_master_triggered_~__retres1~0 := 0; 3656#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3666#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3397#L533 assume !(0 != activate_threads_~tmp~1); 3398#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3517#L229 assume !(1 == ~t1_pc~0); 3389#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 3518#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3390#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3391#L541 assume !(0 != activate_threads_~tmp___0~0); 3613#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3553#L248 assume 1 == ~t2_pc~0; 3554#L249 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3544#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3555#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3476#L549 assume !(0 != activate_threads_~tmp___1~0); 3430#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3431#L267 assume 1 == ~t3_pc~0; 3503#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3504#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3507#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3508#L557 assume !(0 != activate_threads_~tmp___2~0); 3662#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 3537#L479-1 assume !(1 == ~T1_E~0); 3538#L484-1 assume !(1 == ~T2_E~0); 3566#L489-1 assume !(1 == ~T3_E~0); 3435#L494-1 assume !(1 == ~E_M~0); 3436#L499-1 assume !(1 == ~E_1~0); 3502#L504-1 assume !(1 == ~E_2~0); 3681#L509-1 assume !(1 == ~E_3~0); 3683#L680-1 [2019-12-07 18:24:03,368 INFO L796 eck$LassoCheckResult]: Loop: 3683#L680-1 assume !false; 3474#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3376#L406 assume !false; 3451#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3684#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3481#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3477#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3478#L359 assume !(0 != eval_~tmp~0); 3640#L421 start_simulation_~kernel_st~0 := 2; 3667#L287-1 start_simulation_~kernel_st~0 := 3; 3595#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3596#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3598#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3646#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3551#L446-3 assume !(0 == ~E_M~0); 3552#L451-3 assume !(0 == ~E_1~0); 3573#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3464#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3465#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3516#L210-15 assume !(1 == ~m_pc~0); 3638#L210-17 is_master_triggered_~__retres1~0 := 0; 3639#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3671#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3578#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3563#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3499#L229-15 assume !(1 == ~t1_pc~0); 3410#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 3836#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3835#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3834#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3833#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3832#L248-15 assume !(1 == ~t2_pc~0); 3830#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 3677#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3624#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3395#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3396#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3827#L267-15 assume 1 == ~t3_pc~0; 3825#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3824#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3823#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3821#L557-15 assume !(0 != activate_threads_~tmp___2~0); 3819#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3817#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3815#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3814#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3811#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3810#L499-3 assume !(1 == ~E_1~0); 3809#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3686#L509-3 assume !(1 == ~E_3~0); 3687#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3685#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3485#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3482#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3483#L699 assume !(0 == start_simulation_~tmp~3); 3520#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3562#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3489#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3487#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 3379#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3380#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 3530#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3622#L712 assume !(0 != start_simulation_~tmp___0~1); 3683#L680-1 [2019-12-07 18:24:03,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,369 INFO L82 PathProgramCache]: Analyzing trace with hash -781976991, now seen corresponding path program 1 times [2019-12-07 18:24:03,369 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,369 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670235989] [2019-12-07 18:24:03,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,386 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670235989] [2019-12-07 18:24:03,386 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,386 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:03,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858316839] [2019-12-07 18:24:03,387 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1355599321, now seen corresponding path program 1 times [2019-12-07 18:24:03,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018768197] [2019-12-07 18:24:03,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,409 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018768197] [2019-12-07 18:24:03,409 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,409 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,409 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652933950] [2019-12-07 18:24:03,410 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,410 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,410 INFO L87 Difference]: Start difference. First operand 526 states and 769 transitions. cyclomatic complexity: 245 Second operand 3 states. [2019-12-07 18:24:03,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,457 INFO L93 Difference]: Finished difference Result 935 states and 1355 transitions. [2019-12-07 18:24:03,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 935 states and 1355 transitions. [2019-12-07 18:24:03,463 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 878 [2019-12-07 18:24:03,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 935 states to 935 states and 1355 transitions. [2019-12-07 18:24:03,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 935 [2019-12-07 18:24:03,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 935 [2019-12-07 18:24:03,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 935 states and 1355 transitions. [2019-12-07 18:24:03,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,473 INFO L688 BuchiCegarLoop]: Abstraction has 935 states and 1355 transitions. [2019-12-07 18:24:03,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 935 states and 1355 transitions. [2019-12-07 18:24:03,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 935 to 931. [2019-12-07 18:24:03,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 931 states. [2019-12-07 18:24:03,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 931 states to 931 states and 1351 transitions. [2019-12-07 18:24:03,491 INFO L711 BuchiCegarLoop]: Abstraction has 931 states and 1351 transitions. [2019-12-07 18:24:03,492 INFO L591 BuchiCegarLoop]: Abstraction has 931 states and 1351 transitions. [2019-12-07 18:24:03,492 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:24:03,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 931 states and 1351 transitions. [2019-12-07 18:24:03,496 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 874 [2019-12-07 18:24:03,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,498 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,498 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,498 INFO L794 eck$LassoCheckResult]: Stem: 5029#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4867#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4854#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4855#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 5163#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5083#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5084#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5131#L309-1 assume !(0 == ~M_E~0); 5064#L431-1 assume !(0 == ~T1_E~0); 5065#L436-1 assume !(0 == ~T2_E~0); 5105#L441-1 assume !(0 == ~T3_E~0); 5012#L446-1 assume !(0 == ~E_M~0); 5013#L451-1 assume !(0 == ~E_1~0); 5039#L456-1 assume !(0 == ~E_2~0); 4913#L461-1 assume !(0 == ~E_3~0); 4914#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4976#L210 assume !(1 == ~m_pc~0); 5135#L210-2 is_master_triggered_~__retres1~0 := 0; 5136#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5145#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4865#L533 assume !(0 != activate_threads_~tmp~1); 4866#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4983#L229 assume !(1 == ~t1_pc~0); 4857#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 4984#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4858#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4859#L541 assume !(0 != activate_threads_~tmp___0~0); 5087#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5024#L248 assume !(1 == ~t2_pc~0); 5014#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 5015#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5025#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4943#L549 assume !(0 != activate_threads_~tmp___1~0); 4898#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4899#L267 assume 1 == ~t3_pc~0; 4970#L268 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4971#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4974#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4975#L557 assume !(0 != activate_threads_~tmp___2~0); 5141#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 5008#L479-1 assume !(1 == ~T1_E~0); 5009#L484-1 assume !(1 == ~T2_E~0); 5036#L489-1 assume !(1 == ~T3_E~0); 4903#L494-1 assume !(1 == ~E_M~0); 4904#L499-1 assume !(1 == ~E_1~0); 4969#L504-1 assume !(1 == ~E_2~0); 5167#L509-1 assume !(1 == ~E_3~0); 5178#L680-1 [2019-12-07 18:24:03,498 INFO L796 eck$LassoCheckResult]: Loop: 5178#L680-1 assume !false; 5590#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5061#L406 assume !false; 5175#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5176#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4948#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4945#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4946#L359 assume !(0 != eval_~tmp~0); 5118#L421 start_simulation_~kernel_st~0 := 2; 5146#L287-1 start_simulation_~kernel_st~0 := 3; 5147#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5753#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5123#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5124#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5022#L446-3 assume !(0 == ~E_M~0); 5023#L451-3 assume !(0 == ~E_1~0); 5043#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4932#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4933#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4979#L210-15 assume !(1 == ~m_pc~0); 5739#L210-17 is_master_triggered_~__retres1~0 := 0; 5732#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5731#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5730#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5729#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5728#L229-15 assume !(1 == ~t1_pc~0); 5726#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 5725#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5724#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5723#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5722#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5692#L248-15 assume !(1 == ~t2_pc~0); 5691#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 5690#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5677#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5676#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5674#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5672#L267-15 assume 1 == ~t3_pc~0; 5669#L268-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5667#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5665#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5663#L557-15 assume !(0 != activate_threads_~tmp___2~0); 5661#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5659#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5657#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5654#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5652#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5650#L499-3 assume !(1 == ~E_1~0); 5648#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5646#L509-3 assume !(1 == ~E_3~0); 5644#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5639#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5635#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5633#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5630#L699 assume !(0 == start_simulation_~tmp~3); 5628#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5621#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5618#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5616#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 5596#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5595#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 5594#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5593#L712 assume !(0 != start_simulation_~tmp___0~1); 5178#L680-1 [2019-12-07 18:24:03,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,498 INFO L82 PathProgramCache]: Analyzing trace with hash 209187682, now seen corresponding path program 1 times [2019-12-07 18:24:03,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,499 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982404808] [2019-12-07 18:24:03,499 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,514 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982404808] [2019-12-07 18:24:03,514 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,514 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:03,514 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079345005] [2019-12-07 18:24:03,515 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,515 INFO L82 PathProgramCache]: Analyzing trace with hash 1355599321, now seen corresponding path program 2 times [2019-12-07 18:24:03,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581649828] [2019-12-07 18:24:03,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,531 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581649828] [2019-12-07 18:24:03,532 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,532 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,532 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203840496] [2019-12-07 18:24:03,532 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,532 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,532 INFO L87 Difference]: Start difference. First operand 931 states and 1351 transitions. cyclomatic complexity: 424 Second operand 3 states. [2019-12-07 18:24:03,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,568 INFO L93 Difference]: Finished difference Result 1684 states and 2428 transitions. [2019-12-07 18:24:03,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1684 states and 2428 transitions. [2019-12-07 18:24:03,577 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1612 [2019-12-07 18:24:03,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1684 states to 1684 states and 2428 transitions. [2019-12-07 18:24:03,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1684 [2019-12-07 18:24:03,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1684 [2019-12-07 18:24:03,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1684 states and 2428 transitions. [2019-12-07 18:24:03,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,590 INFO L688 BuchiCegarLoop]: Abstraction has 1684 states and 2428 transitions. [2019-12-07 18:24:03,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1684 states and 2428 transitions. [2019-12-07 18:24:03,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1684 to 1676. [2019-12-07 18:24:03,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1676 states. [2019-12-07 18:24:03,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1676 states to 1676 states and 2420 transitions. [2019-12-07 18:24:03,611 INFO L711 BuchiCegarLoop]: Abstraction has 1676 states and 2420 transitions. [2019-12-07 18:24:03,612 INFO L591 BuchiCegarLoop]: Abstraction has 1676 states and 2420 transitions. [2019-12-07 18:24:03,612 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:24:03,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1676 states and 2420 transitions. [2019-12-07 18:24:03,617 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1604 [2019-12-07 18:24:03,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,618 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,618 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,618 INFO L794 eck$LassoCheckResult]: Stem: 7650#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7489#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7474#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7475#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 7779#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7700#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7701#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7747#L309-1 assume !(0 == ~M_E~0); 7682#L431-1 assume !(0 == ~T1_E~0); 7683#L436-1 assume !(0 == ~T2_E~0); 7721#L441-1 assume !(0 == ~T3_E~0); 7633#L446-1 assume !(0 == ~E_M~0); 7634#L451-1 assume !(0 == ~E_1~0); 7658#L456-1 assume !(0 == ~E_2~0); 7533#L461-1 assume !(0 == ~E_3~0); 7534#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7598#L210 assume !(1 == ~m_pc~0); 7753#L210-2 is_master_triggered_~__retres1~0 := 0; 7754#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7764#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7487#L533 assume !(0 != activate_threads_~tmp~1); 7488#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7608#L229 assume !(1 == ~t1_pc~0); 7479#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 7609#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7480#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7481#L541 assume !(0 != activate_threads_~tmp___0~0); 7703#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7643#L248 assume !(1 == ~t2_pc~0); 7635#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 7636#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7646#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7567#L549 assume !(0 != activate_threads_~tmp___1~0); 7521#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7522#L267 assume !(1 == ~t3_pc~0); 7791#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 7792#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7594#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7595#L557 assume !(0 != activate_threads_~tmp___2~0); 7757#L557-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7627#L479-1 assume !(1 == ~T1_E~0); 7628#L484-1 assume !(1 == ~T2_E~0); 7655#L489-1 assume !(1 == ~T3_E~0); 7523#L494-1 assume !(1 == ~E_M~0); 7524#L499-1 assume !(1 == ~E_1~0); 7593#L504-1 assume !(1 == ~E_2~0); 7786#L509-1 assume !(1 == ~E_3~0); 7795#L680-1 [2019-12-07 18:24:03,619 INFO L796 eck$LassoCheckResult]: Loop: 7795#L680-1 assume !false; 7565#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 7542#L406 assume !false; 7543#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7797#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7572#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7568#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7569#L359 assume !(0 != eval_~tmp~0); 7732#L421 start_simulation_~kernel_st~0 := 2; 7765#L287-1 start_simulation_~kernel_st~0 := 3; 7685#L431-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7686#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7688#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7738#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7644#L446-3 assume !(0 == ~E_M~0); 7645#L451-3 assume !(0 == ~E_1~0); 7663#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7556#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7557#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7604#L210-15 assume !(1 == ~m_pc~0); 7730#L210-17 is_master_triggered_~__retres1~0 := 0; 7731#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7771#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7669#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7654#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7590#L229-15 assume !(1 == ~t1_pc~0); 7500#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 7561#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7501#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7502#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7803#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7766#L248-15 assume !(1 == ~t2_pc~0); 7762#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 7763#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7715#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7485#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7486#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7610#L267-15 assume !(1 == ~t3_pc~0); 7606#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 7607#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7540#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7541#L557-15 assume !(0 != activate_threads_~tmp___2~0); 7702#L557-17 assume 1 == ~M_E~0;~M_E~0 := 2; 7639#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7640#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7662#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7547#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7548#L499-3 assume !(1 == ~E_1~0); 7599#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7799#L509-3 assume !(1 == ~E_3~0); 7800#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7798#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7576#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7573#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 7574#L699 assume !(0 == start_simulation_~tmp~3); 7611#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7653#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7580#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7578#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7472#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7473#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 7624#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 7713#L712 assume !(0 != start_simulation_~tmp___0~1); 7795#L680-1 [2019-12-07 18:24:03,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1070137053, now seen corresponding path program 1 times [2019-12-07 18:24:03,619 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,619 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92230365] [2019-12-07 18:24:03,619 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,634 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92230365] [2019-12-07 18:24:03,634 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,635 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:03,635 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048351433] [2019-12-07 18:24:03,635 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:03,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,635 INFO L82 PathProgramCache]: Analyzing trace with hash 1994383800, now seen corresponding path program 1 times [2019-12-07 18:24:03,635 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223550798] [2019-12-07 18:24:03,636 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,651 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223550798] [2019-12-07 18:24:03,651 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,651 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,651 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777091538] [2019-12-07 18:24:03,651 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,652 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,652 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,652 INFO L87 Difference]: Start difference. First operand 1676 states and 2420 transitions. cyclomatic complexity: 752 Second operand 3 states. [2019-12-07 18:24:03,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,679 INFO L93 Difference]: Finished difference Result 3084 states and 4462 transitions. [2019-12-07 18:24:03,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3084 states and 4462 transitions. [2019-12-07 18:24:03,698 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2988 [2019-12-07 18:24:03,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3084 states to 3084 states and 4462 transitions. [2019-12-07 18:24:03,720 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3084 [2019-12-07 18:24:03,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3084 [2019-12-07 18:24:03,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3084 states and 4462 transitions. [2019-12-07 18:24:03,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,726 INFO L688 BuchiCegarLoop]: Abstraction has 3084 states and 4462 transitions. [2019-12-07 18:24:03,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states and 4462 transitions. [2019-12-07 18:24:03,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 3084. [2019-12-07 18:24:03,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3084 states. [2019-12-07 18:24:03,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3084 states to 3084 states and 4462 transitions. [2019-12-07 18:24:03,770 INFO L711 BuchiCegarLoop]: Abstraction has 3084 states and 4462 transitions. [2019-12-07 18:24:03,770 INFO L591 BuchiCegarLoop]: Abstraction has 3084 states and 4462 transitions. [2019-12-07 18:24:03,770 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:24:03,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3084 states and 4462 transitions. [2019-12-07 18:24:03,779 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2988 [2019-12-07 18:24:03,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:03,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:03,780 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,780 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:03,780 INFO L794 eck$LassoCheckResult]: Stem: 12417#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12256#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12241#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12242#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 12561#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12475#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12476#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12524#L309-1 assume !(0 == ~M_E~0); 12457#L431-1 assume !(0 == ~T1_E~0); 12458#L436-1 assume !(0 == ~T2_E~0); 12495#L441-1 assume !(0 == ~T3_E~0); 12400#L446-1 assume !(0 == ~E_M~0); 12401#L451-1 assume !(0 == ~E_1~0); 12428#L456-1 assume !(0 == ~E_2~0); 12300#L461-1 assume !(0 == ~E_3~0); 12301#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12365#L210 assume !(1 == ~m_pc~0); 12529#L210-2 is_master_triggered_~__retres1~0 := 0; 12530#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12543#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12254#L533 assume !(0 != activate_threads_~tmp~1); 12255#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12374#L229 assume !(1 == ~t1_pc~0); 12246#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 12375#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12247#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12248#L541 assume !(0 != activate_threads_~tmp___0~0); 12478#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12410#L248 assume !(1 == ~t2_pc~0); 12402#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 12403#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12413#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12334#L549 assume !(0 != activate_threads_~tmp___1~0); 12288#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12289#L267 assume !(1 == ~t3_pc~0); 12576#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 12577#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12362#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12363#L557 assume !(0 != activate_threads_~tmp___2~0); 12533#L557-2 assume !(1 == ~M_E~0); 12394#L479-1 assume !(1 == ~T1_E~0); 12395#L484-1 assume !(1 == ~T2_E~0); 12425#L489-1 assume !(1 == ~T3_E~0); 12290#L494-1 assume !(1 == ~E_M~0); 12291#L499-1 assume !(1 == ~E_1~0); 12361#L504-1 assume !(1 == ~E_2~0); 12571#L509-1 assume !(1 == ~E_3~0); 12580#L680-1 [2019-12-07 18:24:03,781 INFO L796 eck$LassoCheckResult]: Loop: 12580#L680-1 assume !false; 12332#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12309#L406 assume !false; 12310#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12581#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12339#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12335#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12336#L359 assume !(0 != eval_~tmp~0); 12508#L421 start_simulation_~kernel_st~0 := 2; 14827#L287-1 start_simulation_~kernel_st~0 := 3; 14826#L431-2 assume !(0 == ~M_E~0); 14825#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14824#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14823#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14822#L446-3 assume !(0 == ~E_M~0); 14821#L451-3 assume !(0 == ~E_1~0); 14820#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14819#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14816#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14814#L210-15 assume !(1 == ~m_pc~0); 14812#L210-17 is_master_triggered_~__retres1~0 := 0; 14810#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14808#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14806#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14804#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14802#L229-15 assume !(1 == ~t1_pc~0); 14798#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 14796#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14795#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14794#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14793#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14791#L248-15 assume !(1 == ~t2_pc~0); 14789#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 14787#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14785#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14783#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14782#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14781#L267-15 assume !(1 == ~t3_pc~0); 14768#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 14767#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12307#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12308#L557-15 assume !(0 != activate_threads_~tmp___2~0); 12477#L557-17 assume !(1 == ~M_E~0); 12406#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12407#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12432#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12314#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12315#L499-3 assume !(1 == ~E_1~0); 12366#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12575#L509-3 assume !(1 == ~E_3~0); 12585#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12598#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14419#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14417#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 14414#L699 assume !(0 == start_simulation_~tmp~3); 14415#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14484#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14482#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14481#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 12239#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12240#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 12391#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 12488#L712 assume !(0 != start_simulation_~tmp___0~1); 12580#L680-1 [2019-12-07 18:24:03,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,781 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2019-12-07 18:24:03,781 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624065549] [2019-12-07 18:24:03,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:03,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:03,809 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:03,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:03,809 INFO L82 PathProgramCache]: Analyzing trace with hash -1433980996, now seen corresponding path program 1 times [2019-12-07 18:24:03,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:03,809 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763442642] [2019-12-07 18:24:03,810 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:03,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:03,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:03,825 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763442642] [2019-12-07 18:24:03,825 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:03,826 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:03,826 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102323205] [2019-12-07 18:24:03,826 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:03,826 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:03,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:03,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:03,826 INFO L87 Difference]: Start difference. First operand 3084 states and 4462 transitions. cyclomatic complexity: 1386 Second operand 3 states. [2019-12-07 18:24:03,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:03,883 INFO L93 Difference]: Finished difference Result 4667 states and 6695 transitions. [2019-12-07 18:24:03,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:03,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4667 states and 6695 transitions. [2019-12-07 18:24:03,906 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4522 [2019-12-07 18:24:03,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4667 states to 4667 states and 6695 transitions. [2019-12-07 18:24:03,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4667 [2019-12-07 18:24:03,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4667 [2019-12-07 18:24:03,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4667 states and 6695 transitions. [2019-12-07 18:24:03,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:03,938 INFO L688 BuchiCegarLoop]: Abstraction has 4667 states and 6695 transitions. [2019-12-07 18:24:03,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4667 states and 6695 transitions. [2019-12-07 18:24:03,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4667 to 4663. [2019-12-07 18:24:03,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4663 states. [2019-12-07 18:24:03,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4663 states to 4663 states and 6691 transitions. [2019-12-07 18:24:03,993 INFO L711 BuchiCegarLoop]: Abstraction has 4663 states and 6691 transitions. [2019-12-07 18:24:03,993 INFO L591 BuchiCegarLoop]: Abstraction has 4663 states and 6691 transitions. [2019-12-07 18:24:03,993 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:24:03,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4663 states and 6691 transitions. [2019-12-07 18:24:04,002 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4518 [2019-12-07 18:24:04,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:04,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:04,003 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,004 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,004 INFO L794 eck$LassoCheckResult]: Stem: 20180#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20013#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20000#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20001#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 20327#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20239#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20240#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20286#L309-1 assume !(0 == ~M_E~0); 20220#L431-1 assume !(0 == ~T1_E~0); 20221#L436-1 assume !(0 == ~T2_E~0); 20262#L441-1 assume !(0 == ~T3_E~0); 20161#L446-1 assume !(0 == ~E_M~0); 20162#L451-1 assume !(0 == ~E_1~0); 20192#L456-1 assume !(0 == ~E_2~0); 20060#L461-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20061#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20307#L210 assume !(1 == ~m_pc~0); 20308#L210-2 is_master_triggered_~__retres1~0 := 0; 20309#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20310#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20011#L533 assume !(0 != activate_threads_~tmp~1); 20012#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20129#L229 assume !(1 == ~t1_pc~0); 20003#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 20130#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20131#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20242#L541 assume !(0 != activate_threads_~tmp___0~0); 20243#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20173#L248 assume !(1 == ~t2_pc~0); 20174#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 20175#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20176#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20090#L549 assume !(0 != activate_threads_~tmp___1~0); 20091#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20344#L267 assume !(1 == ~t3_pc~0); 20345#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 20346#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20347#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20300#L557 assume !(0 != activate_threads_~tmp___2~0); 20301#L557-2 assume !(1 == ~M_E~0); 20157#L479-1 assume !(1 == ~T1_E~0); 20158#L484-1 assume !(1 == ~T2_E~0); 20212#L489-1 assume !(1 == ~T3_E~0); 20050#L494-1 assume !(1 == ~E_M~0); 20051#L499-1 assume !(1 == ~E_1~0); 20115#L504-1 assume !(1 == ~E_2~0); 20348#L509-1 assume 1 == ~E_3~0;~E_3~0 := 2; 20349#L680-1 [2019-12-07 18:24:04,004 INFO L796 eck$LassoCheckResult]: Loop: 20349#L680-1 assume !false; 21855#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 21851#L406 assume !false; 21848#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21836#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 21830#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21828#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21824#L359 assume !(0 != eval_~tmp~0); 21825#L421 start_simulation_~kernel_st~0 := 2; 22030#L287-1 start_simulation_~kernel_st~0 := 3; 22029#L431-2 assume !(0 == ~M_E~0); 22028#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22026#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22025#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22024#L446-3 assume !(0 == ~E_M~0); 22023#L451-3 assume !(0 == ~E_1~0); 22022#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22021#L461-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22019#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22017#L210-15 assume !(1 == ~m_pc~0); 22015#L210-17 is_master_triggered_~__retres1~0 := 0; 22013#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22011#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22009#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22007#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22004#L229-15 assume !(1 == ~t1_pc~0); 22001#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 21999#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21997#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 21995#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21993#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21991#L248-15 assume !(1 == ~t2_pc~0); 21989#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 21987#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21985#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 21983#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21981#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21979#L267-15 assume !(1 == ~t3_pc~0); 21977#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 21975#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21973#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21971#L557-15 assume !(0 != activate_threads_~tmp___2~0); 21969#L557-17 assume !(1 == ~M_E~0); 21163#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21967#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21965#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21963#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21961#L499-3 assume !(1 == ~E_1~0); 21959#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21958#L509-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21956#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21953#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 21949#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21947#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 21930#L699 assume !(0 == start_simulation_~tmp~3); 21928#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 21900#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 21896#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 21894#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 21892#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21890#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 21888#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 21867#L712 assume !(0 != start_simulation_~tmp___0~1); 20349#L680-1 [2019-12-07 18:24:04,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,004 INFO L82 PathProgramCache]: Analyzing trace with hash -1807097123, now seen corresponding path program 1 times [2019-12-07 18:24:04,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225640716] [2019-12-07 18:24:04,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,015 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225640716] [2019-12-07 18:24:04,015 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,015 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:04,015 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167404747] [2019-12-07 18:24:04,015 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:04,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,015 INFO L82 PathProgramCache]: Analyzing trace with hash -422863746, now seen corresponding path program 1 times [2019-12-07 18:24:04,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,016 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228907452] [2019-12-07 18:24:04,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,037 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228907452] [2019-12-07 18:24:04,037 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:24:04,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208462767] [2019-12-07 18:24:04,038 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:04,038 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:04,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:04,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:04,039 INFO L87 Difference]: Start difference. First operand 4663 states and 6691 transitions. cyclomatic complexity: 2036 Second operand 3 states. [2019-12-07 18:24:04,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:04,067 INFO L93 Difference]: Finished difference Result 3084 states and 4376 transitions. [2019-12-07 18:24:04,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:04,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3084 states and 4376 transitions. [2019-12-07 18:24:04,076 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2988 [2019-12-07 18:24:04,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3084 states to 3084 states and 4376 transitions. [2019-12-07 18:24:04,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3084 [2019-12-07 18:24:04,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3084 [2019-12-07 18:24:04,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3084 states and 4376 transitions. [2019-12-07 18:24:04,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:04,097 INFO L688 BuchiCegarLoop]: Abstraction has 3084 states and 4376 transitions. [2019-12-07 18:24:04,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states and 4376 transitions. [2019-12-07 18:24:04,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 3084. [2019-12-07 18:24:04,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3084 states. [2019-12-07 18:24:04,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3084 states to 3084 states and 4376 transitions. [2019-12-07 18:24:04,136 INFO L711 BuchiCegarLoop]: Abstraction has 3084 states and 4376 transitions. [2019-12-07 18:24:04,136 INFO L591 BuchiCegarLoop]: Abstraction has 3084 states and 4376 transitions. [2019-12-07 18:24:04,136 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:24:04,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3084 states and 4376 transitions. [2019-12-07 18:24:04,142 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2988 [2019-12-07 18:24:04,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:04,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:04,143 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,143 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,143 INFO L794 eck$LassoCheckResult]: Stem: 27920#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 27769#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27754#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27755#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 28051#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27975#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27976#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28020#L309-1 assume !(0 == ~M_E~0); 27957#L431-1 assume !(0 == ~T1_E~0); 27958#L436-1 assume !(0 == ~T2_E~0); 27996#L441-1 assume !(0 == ~T3_E~0); 27903#L446-1 assume !(0 == ~E_M~0); 27904#L451-1 assume !(0 == ~E_1~0); 27929#L456-1 assume !(0 == ~E_2~0); 27811#L461-1 assume !(0 == ~E_3~0); 27812#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27869#L210 assume !(1 == ~m_pc~0); 28026#L210-2 is_master_triggered_~__retres1~0 := 0; 28027#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28037#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27767#L533 assume !(0 != activate_threads_~tmp~1); 27768#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27877#L229 assume !(1 == ~t1_pc~0); 27759#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 27878#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27760#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27761#L541 assume !(0 != activate_threads_~tmp___0~0); 27978#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27913#L248 assume !(1 == ~t2_pc~0); 27905#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 27906#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27916#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 27841#L549 assume !(0 != activate_threads_~tmp___1~0); 27800#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27801#L267 assume !(1 == ~t3_pc~0); 28063#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 28064#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27866#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27867#L557 assume !(0 != activate_threads_~tmp___2~0); 28030#L557-2 assume !(1 == ~M_E~0); 27897#L479-1 assume !(1 == ~T1_E~0); 27898#L484-1 assume !(1 == ~T2_E~0); 27926#L489-1 assume !(1 == ~T3_E~0); 27802#L494-1 assume !(1 == ~E_M~0); 27803#L499-1 assume !(1 == ~E_1~0); 27865#L504-1 assume !(1 == ~E_2~0); 28059#L509-1 assume !(1 == ~E_3~0); 28070#L680-1 [2019-12-07 18:24:04,143 INFO L796 eck$LassoCheckResult]: Loop: 28070#L680-1 assume !false; 29937#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 28552#L406 assume !false; 29936#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28638#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28634#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28632#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 28629#L359 assume !(0 != eval_~tmp~0); 28630#L421 start_simulation_~kernel_st~0 := 2; 29394#L287-1 start_simulation_~kernel_st~0 := 3; 29392#L431-2 assume !(0 == ~M_E~0); 29390#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29388#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29386#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29384#L446-3 assume !(0 == ~E_M~0); 29382#L451-3 assume !(0 == ~E_1~0); 29381#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29379#L461-3 assume !(0 == ~E_3~0); 29378#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29377#L210-15 assume !(1 == ~m_pc~0); 29372#L210-17 is_master_triggered_~__retres1~0 := 0; 29370#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29369#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 29368#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 29367#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29366#L229-15 assume !(1 == ~t1_pc~0); 29364#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 29363#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29362#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 29361#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29360#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29359#L248-15 assume !(1 == ~t2_pc~0); 29358#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 29357#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29356#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 29355#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29354#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29353#L267-15 assume !(1 == ~t3_pc~0); 29351#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 29349#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29347#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 29345#L557-15 assume !(0 != activate_threads_~tmp___2~0); 29343#L557-17 assume !(1 == ~M_E~0); 29284#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29340#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29338#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29336#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29334#L499-3 assume !(1 == ~E_1~0); 29332#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29330#L509-3 assume !(1 == ~E_3~0); 29328#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 29324#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 29320#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29317#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 29315#L699 assume !(0 == start_simulation_~tmp~3); 27881#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27924#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 27854#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27852#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 27752#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27753#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 30112#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 30111#L712 assume !(0 != start_simulation_~tmp___0~1); 28070#L680-1 [2019-12-07 18:24:04,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,143 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2019-12-07 18:24:04,143 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,143 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908985578] [2019-12-07 18:24:04,144 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,155 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:04,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,155 INFO L82 PathProgramCache]: Analyzing trace with hash 494291706, now seen corresponding path program 1 times [2019-12-07 18:24:04,155 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049605493] [2019-12-07 18:24:04,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,174 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049605493] [2019-12-07 18:24:04,174 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:24:04,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488839157] [2019-12-07 18:24:04,175 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:04,175 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:04,175 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:24:04,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:24:04,176 INFO L87 Difference]: Start difference. First operand 3084 states and 4376 transitions. cyclomatic complexity: 1300 Second operand 5 states. [2019-12-07 18:24:04,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:04,267 INFO L93 Difference]: Finished difference Result 5360 states and 7488 transitions. [2019-12-07 18:24:04,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:24:04,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5360 states and 7488 transitions. [2019-12-07 18:24:04,282 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5216 [2019-12-07 18:24:04,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5360 states to 5360 states and 7488 transitions. [2019-12-07 18:24:04,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5360 [2019-12-07 18:24:04,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5360 [2019-12-07 18:24:04,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5360 states and 7488 transitions. [2019-12-07 18:24:04,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:04,316 INFO L688 BuchiCegarLoop]: Abstraction has 5360 states and 7488 transitions. [2019-12-07 18:24:04,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5360 states and 7488 transitions. [2019-12-07 18:24:04,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5360 to 3132. [2019-12-07 18:24:04,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3132 states. [2019-12-07 18:24:04,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3132 states to 3132 states and 4424 transitions. [2019-12-07 18:24:04,366 INFO L711 BuchiCegarLoop]: Abstraction has 3132 states and 4424 transitions. [2019-12-07 18:24:04,366 INFO L591 BuchiCegarLoop]: Abstraction has 3132 states and 4424 transitions. [2019-12-07 18:24:04,366 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:24:04,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3132 states and 4424 transitions. [2019-12-07 18:24:04,372 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3036 [2019-12-07 18:24:04,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:04,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:04,373 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,373 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,373 INFO L794 eck$LassoCheckResult]: Stem: 36386#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 36229#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36216#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36217#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 36532#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36447#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36448#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36498#L309-1 assume !(0 == ~M_E~0); 36429#L431-1 assume !(0 == ~T1_E~0); 36430#L436-1 assume !(0 == ~T2_E~0); 36468#L441-1 assume !(0 == ~T3_E~0); 36369#L446-1 assume !(0 == ~E_M~0); 36370#L451-1 assume !(0 == ~E_1~0); 36399#L456-1 assume !(0 == ~E_2~0); 36274#L461-1 assume !(0 == ~E_3~0); 36275#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36332#L210 assume !(1 == ~m_pc~0); 36502#L210-2 is_master_triggered_~__retres1~0 := 0; 36503#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36512#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 36227#L533 assume !(0 != activate_threads_~tmp~1); 36228#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36342#L229 assume !(1 == ~t1_pc~0); 36219#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 36343#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36220#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 36221#L541 assume !(0 != activate_threads_~tmp___0~0); 36450#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36381#L248 assume !(1 == ~t2_pc~0); 36371#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 36372#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36382#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 36303#L549 assume !(0 != activate_threads_~tmp___1~0); 36261#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36262#L267 assume !(1 == ~t3_pc~0); 36545#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 36546#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36330#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 36331#L557 assume !(0 != activate_threads_~tmp___2~0); 36509#L557-2 assume !(1 == ~M_E~0); 36365#L479-1 assume !(1 == ~T1_E~0); 36366#L484-1 assume !(1 == ~T2_E~0); 36396#L489-1 assume !(1 == ~T3_E~0); 36265#L494-1 assume !(1 == ~E_M~0); 36266#L499-1 assume !(1 == ~E_1~0); 36328#L504-1 assume !(1 == ~E_2~0); 36541#L509-1 assume !(1 == ~E_3~0); 36556#L680-1 [2019-12-07 18:24:04,374 INFO L796 eck$LassoCheckResult]: Loop: 36556#L680-1 assume !false; 38649#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 37853#L406 assume !false; 38643#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38641#L322 assume !(0 == ~m_st~0); 38642#L326 assume !(0 == ~t1_st~0); 38638#L330 assume !(0 == ~t2_st~0); 38640#L334 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 38637#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 36304#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 36305#L359 assume !(0 != eval_~tmp~0); 38978#L421 start_simulation_~kernel_st~0 := 2; 38976#L287-1 start_simulation_~kernel_st~0 := 3; 38974#L431-2 assume !(0 == ~M_E~0); 38972#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38970#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38968#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38966#L446-3 assume !(0 == ~E_M~0); 38964#L451-3 assume !(0 == ~E_1~0); 38962#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38960#L461-3 assume !(0 == ~E_3~0); 38958#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38956#L210-15 assume !(1 == ~m_pc~0); 38954#L210-17 is_master_triggered_~__retres1~0 := 0; 38952#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38950#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 38948#L533-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38946#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38944#L229-15 assume !(1 == ~t1_pc~0); 38940#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 38938#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38936#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 38934#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38932#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38930#L248-15 assume !(1 == ~t2_pc~0); 38928#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 38926#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38924#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 38922#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 38920#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38918#L267-15 assume !(1 == ~t3_pc~0); 38916#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 38914#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38912#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38910#L557-15 assume !(0 != activate_threads_~tmp___2~0); 38908#L557-17 assume !(1 == ~M_E~0); 38905#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38904#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38903#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38902#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38901#L499-3 assume !(1 == ~E_1~0); 38900#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38899#L509-3 assume !(1 == ~E_3~0); 38898#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38896#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 38891#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 38743#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 38738#L699 assume !(0 == start_simulation_~tmp~3); 38666#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38663#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 38660#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 38659#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 38658#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 38657#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 38653#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 38651#L712 assume !(0 != start_simulation_~tmp___0~1); 36556#L680-1 [2019-12-07 18:24:04,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,374 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2019-12-07 18:24:04,374 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,374 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587701940] [2019-12-07 18:24:04,374 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,385 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:04,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,385 INFO L82 PathProgramCache]: Analyzing trace with hash 644099896, now seen corresponding path program 1 times [2019-12-07 18:24:04,385 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,385 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430670804] [2019-12-07 18:24:04,386 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,422 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430670804] [2019-12-07 18:24:04,422 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,422 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:24:04,422 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477587868] [2019-12-07 18:24:04,423 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:04,423 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:04,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:24:04,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:24:04,423 INFO L87 Difference]: Start difference. First operand 3132 states and 4424 transitions. cyclomatic complexity: 1300 Second operand 5 states. [2019-12-07 18:24:04,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:04,540 INFO L93 Difference]: Finished difference Result 6208 states and 8703 transitions. [2019-12-07 18:24:04,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:24:04,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6208 states and 8703 transitions. [2019-12-07 18:24:04,558 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6080 [2019-12-07 18:24:04,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6208 states to 6208 states and 8703 transitions. [2019-12-07 18:24:04,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6208 [2019-12-07 18:24:04,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6208 [2019-12-07 18:24:04,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6208 states and 8703 transitions. [2019-12-07 18:24:04,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:04,592 INFO L688 BuchiCegarLoop]: Abstraction has 6208 states and 8703 transitions. [2019-12-07 18:24:04,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6208 states and 8703 transitions. [2019-12-07 18:24:04,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6208 to 3240. [2019-12-07 18:24:04,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3240 states. [2019-12-07 18:24:04,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3240 states to 3240 states and 4503 transitions. [2019-12-07 18:24:04,647 INFO L711 BuchiCegarLoop]: Abstraction has 3240 states and 4503 transitions. [2019-12-07 18:24:04,647 INFO L591 BuchiCegarLoop]: Abstraction has 3240 states and 4503 transitions. [2019-12-07 18:24:04,647 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:24:04,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3240 states and 4503 transitions. [2019-12-07 18:24:04,653 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3144 [2019-12-07 18:24:04,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:04,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:04,654 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,654 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,654 INFO L794 eck$LassoCheckResult]: Stem: 45741#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 45582#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 45567#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 45568#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 45888#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45799#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45800#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45850#L309-1 assume !(0 == ~M_E~0); 45781#L431-1 assume !(0 == ~T1_E~0); 45782#L436-1 assume !(0 == ~T2_E~0); 45822#L441-1 assume !(0 == ~T3_E~0); 45724#L446-1 assume !(0 == ~E_M~0); 45725#L451-1 assume !(0 == ~E_1~0); 45752#L456-1 assume !(0 == ~E_2~0); 45624#L461-1 assume !(0 == ~E_3~0); 45625#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45685#L210 assume !(1 == ~m_pc~0); 45857#L210-2 is_master_triggered_~__retres1~0 := 0; 45858#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45867#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 45580#L533 assume !(0 != activate_threads_~tmp~1); 45581#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45696#L229 assume !(1 == ~t1_pc~0); 45572#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 45697#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45573#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 45574#L541 assume !(0 != activate_threads_~tmp___0~0); 45802#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45734#L248 assume !(1 == ~t2_pc~0); 45726#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 45727#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45737#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45655#L549 assume !(0 != activate_threads_~tmp___1~0); 45613#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45614#L267 assume !(1 == ~t3_pc~0); 45901#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 45902#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45681#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 45682#L557 assume !(0 != activate_threads_~tmp___2~0); 45861#L557-2 assume !(1 == ~M_E~0); 45718#L479-1 assume !(1 == ~T1_E~0); 45719#L484-1 assume !(1 == ~T2_E~0); 45749#L489-1 assume !(1 == ~T3_E~0); 45615#L494-1 assume !(1 == ~E_M~0); 45616#L499-1 assume !(1 == ~E_1~0); 45680#L504-1 assume !(1 == ~E_2~0); 45899#L509-1 assume !(1 == ~E_3~0); 45915#L680-1 [2019-12-07 18:24:04,654 INFO L796 eck$LassoCheckResult]: Loop: 45915#L680-1 assume !false; 47135#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 47133#L406 assume !false; 47131#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 47122#L322 assume !(0 == ~m_st~0); 47123#L326 assume !(0 == ~t1_st~0); 47119#L330 assume !(0 == ~t2_st~0); 47120#L334 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 47121#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 46914#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 46915#L359 assume !(0 != eval_~tmp~0); 48083#L421 start_simulation_~kernel_st~0 := 2; 48082#L287-1 start_simulation_~kernel_st~0 := 3; 48081#L431-2 assume !(0 == ~M_E~0); 48080#L431-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48079#L436-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48078#L441-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48073#L446-3 assume !(0 == ~E_M~0); 48072#L451-3 assume !(0 == ~E_1~0); 48071#L456-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48070#L461-3 assume !(0 == ~E_3~0); 45692#L466-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45693#L210-15 assume !(1 == ~m_pc~0); 45846#L210-17 is_master_triggered_~__retres1~0 := 0; 47313#L221-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47311#L222-5 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 47309#L533-15 assume !(0 != activate_threads_~tmp~1); 47307#L533-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47305#L229-15 assume !(1 == ~t1_pc~0); 47301#L229-17 is_transmit1_triggered_~__retres1~1 := 0; 47299#L240-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47297#L241-5 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 47295#L541-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 47293#L541-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47291#L248-15 assume !(1 == ~t2_pc~0); 47289#L248-17 is_transmit2_triggered_~__retres1~2 := 0; 47287#L259-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47285#L260-5 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 47283#L549-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 47281#L549-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47279#L267-15 assume !(1 == ~t3_pc~0); 47277#L267-17 is_transmit3_triggered_~__retres1~3 := 0; 47275#L278-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47273#L279-5 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 47270#L557-15 assume !(0 != activate_threads_~tmp___2~0); 47267#L557-17 assume !(1 == ~M_E~0); 47264#L479-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47261#L484-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47257#L489-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47254#L494-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47251#L499-3 assume !(1 == ~E_1~0); 47248#L504-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47244#L509-3 assume !(1 == ~E_3~0); 47239#L514-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 47202#L322-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 47191#L344-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 47185#L345-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 47043#L699 assume !(0 == start_simulation_~tmp~3); 47044#L699-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 47173#L322-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 47164#L344-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 47160#L345-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 47156#L654 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47152#L661 stop_simulation_#res := stop_simulation_~__retres2~0; 47148#L662 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 47143#L712 assume !(0 != start_simulation_~tmp___0~1); 45915#L680-1 [2019-12-07 18:24:04,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2019-12-07 18:24:04,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221678406] [2019-12-07 18:24:04,655 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,665 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:04,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,666 INFO L82 PathProgramCache]: Analyzing trace with hash -727707402, now seen corresponding path program 1 times [2019-12-07 18:24:04,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90940797] [2019-12-07 18:24:04,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,680 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [90940797] [2019-12-07 18:24:04,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:04,681 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537438333] [2019-12-07 18:24:04,681 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:24:04,681 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:04,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:04,681 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:04,681 INFO L87 Difference]: Start difference. First operand 3240 states and 4503 transitions. cyclomatic complexity: 1271 Second operand 3 states. [2019-12-07 18:24:04,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:04,715 INFO L93 Difference]: Finished difference Result 4916 states and 6702 transitions. [2019-12-07 18:24:04,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:04,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4916 states and 6702 transitions. [2019-12-07 18:24:04,729 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4802 [2019-12-07 18:24:04,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4916 states to 4916 states and 6702 transitions. [2019-12-07 18:24:04,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4916 [2019-12-07 18:24:04,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4916 [2019-12-07 18:24:04,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4916 states and 6702 transitions. [2019-12-07 18:24:04,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:04,749 INFO L688 BuchiCegarLoop]: Abstraction has 4916 states and 6702 transitions. [2019-12-07 18:24:04,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4916 states and 6702 transitions. [2019-12-07 18:24:04,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4916 to 4748. [2019-12-07 18:24:04,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4748 states. [2019-12-07 18:24:04,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4748 states to 4748 states and 6482 transitions. [2019-12-07 18:24:04,796 INFO L711 BuchiCegarLoop]: Abstraction has 4748 states and 6482 transitions. [2019-12-07 18:24:04,796 INFO L591 BuchiCegarLoop]: Abstraction has 4748 states and 6482 transitions. [2019-12-07 18:24:04,796 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:24:04,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4748 states and 6482 transitions. [2019-12-07 18:24:04,805 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4634 [2019-12-07 18:24:04,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:04,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:04,806 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,806 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:04,806 INFO L794 eck$LassoCheckResult]: Stem: 53903#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 53744#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 53731#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53732#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 54043#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53958#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53959#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54009#L309-1 assume !(0 == ~M_E~0); 53938#L431-1 assume !(0 == ~T1_E~0); 53939#L436-1 assume !(0 == ~T2_E~0); 53982#L441-1 assume !(0 == ~T3_E~0); 53886#L446-1 assume !(0 == ~E_M~0); 53887#L451-1 assume !(0 == ~E_1~0); 53913#L456-1 assume !(0 == ~E_2~0); 53790#L461-1 assume !(0 == ~E_3~0); 53791#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53849#L210 assume !(1 == ~m_pc~0); 54013#L210-2 is_master_triggered_~__retres1~0 := 0; 54014#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54024#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 53742#L533 assume !(0 != activate_threads_~tmp~1); 53743#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53858#L229 assume !(1 == ~t1_pc~0); 53734#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 53859#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53735#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53736#L541 assume !(0 != activate_threads_~tmp___0~0); 53961#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53898#L248 assume !(1 == ~t2_pc~0); 53888#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 53889#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53899#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53820#L549 assume !(0 != activate_threads_~tmp___1~0); 53776#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53777#L267 assume !(1 == ~t3_pc~0); 54057#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 54058#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53847#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53848#L557 assume !(0 != activate_threads_~tmp___2~0); 54021#L557-2 assume !(1 == ~M_E~0); 53882#L479-1 assume !(1 == ~T1_E~0); 53883#L484-1 assume !(1 == ~T2_E~0); 53910#L489-1 assume !(1 == ~T3_E~0); 53780#L494-1 assume !(1 == ~E_M~0); 53781#L499-1 assume !(1 == ~E_1~0); 53845#L504-1 assume !(1 == ~E_2~0); 54053#L509-1 assume !(1 == ~E_3~0); 54067#L680-1 assume !false; 54680#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 54681#L406 [2019-12-07 18:24:04,806 INFO L796 eck$LassoCheckResult]: Loop: 54681#L406 assume !false; 54659#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 54660#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 54842#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 54839#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 54835#L359 assume 0 != eval_~tmp~0; 54829#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 54824#L367 assume !(0 != eval_~tmp_ndt_1~0); 54812#L364 assume !(0 == ~t1_st~0); 54814#L378 assume !(0 == ~t2_st~0); 54684#L392 assume !(0 == ~t3_st~0); 54681#L406 [2019-12-07 18:24:04,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,806 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2019-12-07 18:24:04,806 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,806 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407606508] [2019-12-07 18:24:04,806 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,816 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:04,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,816 INFO L82 PathProgramCache]: Analyzing trace with hash 527287816, now seen corresponding path program 1 times [2019-12-07 18:24:04,817 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,817 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187394565] [2019-12-07 18:24:04,817 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:04,821 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:04,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:04,821 INFO L82 PathProgramCache]: Analyzing trace with hash -1008144026, now seen corresponding path program 1 times [2019-12-07 18:24:04,821 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:04,821 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069621252] [2019-12-07 18:24:04,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:04,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:04,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:04,835 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069621252] [2019-12-07 18:24:04,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:04,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:04,836 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075401352] [2019-12-07 18:24:04,882 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:04,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:04,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:04,883 INFO L87 Difference]: Start difference. First operand 4748 states and 6482 transitions. cyclomatic complexity: 1746 Second operand 3 states. [2019-12-07 18:24:04,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:04,923 INFO L93 Difference]: Finished difference Result 8379 states and 11310 transitions. [2019-12-07 18:24:04,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:04,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8379 states and 11310 transitions. [2019-12-07 18:24:04,946 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8156 [2019-12-07 18:24:04,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8379 states to 8379 states and 11310 transitions. [2019-12-07 18:24:04,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8379 [2019-12-07 18:24:04,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8379 [2019-12-07 18:24:04,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8379 states and 11310 transitions. [2019-12-07 18:24:04,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:04,976 INFO L688 BuchiCegarLoop]: Abstraction has 8379 states and 11310 transitions. [2019-12-07 18:24:04,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8379 states and 11310 transitions. [2019-12-07 18:24:05,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8379 to 7931. [2019-12-07 18:24:05,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7931 states. [2019-12-07 18:24:05,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7931 states to 7931 states and 10764 transitions. [2019-12-07 18:24:05,055 INFO L711 BuchiCegarLoop]: Abstraction has 7931 states and 10764 transitions. [2019-12-07 18:24:05,055 INFO L591 BuchiCegarLoop]: Abstraction has 7931 states and 10764 transitions. [2019-12-07 18:24:05,055 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:24:05,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7931 states and 10764 transitions. [2019-12-07 18:24:05,072 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7708 [2019-12-07 18:24:05,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:05,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:05,073 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,073 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,073 INFO L794 eck$LassoCheckResult]: Stem: 67039#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 66879#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 66866#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66867#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 67182#L294-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 67209#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67601#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67600#L309-1 assume !(0 == ~M_E~0); 67599#L431-1 assume !(0 == ~T1_E~0); 67598#L436-1 assume !(0 == ~T2_E~0); 67597#L441-1 assume !(0 == ~T3_E~0); 67596#L446-1 assume !(0 == ~E_M~0); 67595#L451-1 assume !(0 == ~E_1~0); 67594#L456-1 assume !(0 == ~E_2~0); 67593#L461-1 assume !(0 == ~E_3~0); 67592#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67591#L210 assume !(1 == ~m_pc~0); 67590#L210-2 is_master_triggered_~__retres1~0 := 0; 67589#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67588#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 67587#L533 assume !(0 != activate_threads_~tmp~1); 67586#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67584#L229 assume !(1 == ~t1_pc~0); 67583#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 67582#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67581#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 67580#L541 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 67101#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 67032#L248 assume !(1 == ~t2_pc~0); 67024#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 67025#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 67035#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 66952#L549 assume !(0 != activate_threads_~tmp___1~0); 66911#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66912#L267 assume !(1 == ~t3_pc~0); 67194#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 67195#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66979#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 66980#L557 assume !(0 != activate_threads_~tmp___2~0); 67157#L557-2 assume !(1 == ~M_E~0); 67018#L479-1 assume !(1 == ~T1_E~0); 67019#L484-1 assume !(1 == ~T2_E~0); 67046#L489-1 assume !(1 == ~T3_E~0); 67068#L494-1 assume !(1 == ~E_M~0); 67560#L499-1 assume !(1 == ~E_1~0); 67559#L504-1 assume !(1 == ~E_2~0); 67205#L509-1 assume !(1 == ~E_3~0); 67206#L680-1 assume !false; 67746#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 67743#L406 [2019-12-07 18:24:05,073 INFO L796 eck$LassoCheckResult]: Loop: 67743#L406 assume !false; 67740#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 67737#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 67731#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 67730#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 67723#L359 assume 0 != eval_~tmp~0; 67721#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 67716#L367 assume !(0 != eval_~tmp_ndt_1~0); 67715#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 67470#L381 assume !(0 != eval_~tmp_ndt_2~0); 67713#L378 assume !(0 == ~t2_st~0); 67712#L392 assume !(0 == ~t3_st~0); 67743#L406 [2019-12-07 18:24:05,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,073 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2019-12-07 18:24:05,074 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,074 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787494019] [2019-12-07 18:24:05,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:05,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:05,098 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787494019] [2019-12-07 18:24:05,098 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:05,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:05,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417282406] [2019-12-07 18:24:05,098 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:24:05,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,099 INFO L82 PathProgramCache]: Analyzing trace with hash -837923902, now seen corresponding path program 1 times [2019-12-07 18:24:05,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409032809] [2019-12-07 18:24:05,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,103 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:05,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:05,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:05,151 INFO L87 Difference]: Start difference. First operand 7931 states and 10764 transitions. cyclomatic complexity: 2845 Second operand 3 states. [2019-12-07 18:24:05,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:05,171 INFO L93 Difference]: Finished difference Result 7886 states and 10704 transitions. [2019-12-07 18:24:05,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:05,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7886 states and 10704 transitions. [2019-12-07 18:24:05,199 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7708 [2019-12-07 18:24:05,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7886 states to 7886 states and 10704 transitions. [2019-12-07 18:24:05,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7886 [2019-12-07 18:24:05,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7886 [2019-12-07 18:24:05,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7886 states and 10704 transitions. [2019-12-07 18:24:05,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:05,226 INFO L688 BuchiCegarLoop]: Abstraction has 7886 states and 10704 transitions. [2019-12-07 18:24:05,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7886 states and 10704 transitions. [2019-12-07 18:24:05,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7886 to 7886. [2019-12-07 18:24:05,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7886 states. [2019-12-07 18:24:05,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7886 states to 7886 states and 10704 transitions. [2019-12-07 18:24:05,284 INFO L711 BuchiCegarLoop]: Abstraction has 7886 states and 10704 transitions. [2019-12-07 18:24:05,284 INFO L591 BuchiCegarLoop]: Abstraction has 7886 states and 10704 transitions. [2019-12-07 18:24:05,284 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 18:24:05,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7886 states and 10704 transitions. [2019-12-07 18:24:05,299 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7708 [2019-12-07 18:24:05,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:05,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:05,299 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,300 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,300 INFO L794 eck$LassoCheckResult]: Stem: 82857#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 82702#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 82687#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 82688#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 83003#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82911#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82912#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82965#L309-1 assume !(0 == ~M_E~0); 82893#L431-1 assume !(0 == ~T1_E~0); 82894#L436-1 assume !(0 == ~T2_E~0); 82934#L441-1 assume !(0 == ~T3_E~0); 82840#L446-1 assume !(0 == ~E_M~0); 82841#L451-1 assume !(0 == ~E_1~0); 82867#L456-1 assume !(0 == ~E_2~0); 82746#L461-1 assume !(0 == ~E_3~0); 82747#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82804#L210 assume !(1 == ~m_pc~0); 82971#L210-2 is_master_triggered_~__retres1~0 := 0; 82972#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 82981#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 82700#L533 assume !(0 != activate_threads_~tmp~1); 82701#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 82814#L229 assume !(1 == ~t1_pc~0); 82692#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 82815#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82693#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 82694#L541 assume !(0 != activate_threads_~tmp___0~0); 82914#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 82850#L248 assume !(1 == ~t2_pc~0); 82842#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 82843#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 82853#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 82775#L549 assume !(0 != activate_threads_~tmp___1~0); 82733#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 82734#L267 assume !(1 == ~t3_pc~0); 83011#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 83012#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 82801#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 82802#L557 assume !(0 != activate_threads_~tmp___2~0); 82975#L557-2 assume !(1 == ~M_E~0); 82834#L479-1 assume !(1 == ~T1_E~0); 82835#L484-1 assume !(1 == ~T2_E~0); 82864#L489-1 assume !(1 == ~T3_E~0); 82735#L494-1 assume !(1 == ~E_M~0); 82736#L499-1 assume !(1 == ~E_1~0); 82800#L504-1 assume !(1 == ~E_2~0); 83007#L509-1 assume !(1 == ~E_3~0); 83022#L680-1 assume !false; 84145#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 84143#L406 [2019-12-07 18:24:05,300 INFO L796 eck$LassoCheckResult]: Loop: 84143#L406 assume !false; 84141#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 84138#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 84136#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 84127#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 84121#L359 assume 0 != eval_~tmp~0; 84114#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 84108#L367 assume !(0 != eval_~tmp_ndt_1~0); 84102#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 84073#L381 assume !(0 != eval_~tmp_ndt_2~0); 84095#L378 assume !(0 == ~t2_st~0); 84148#L392 assume !(0 == ~t3_st~0); 84143#L406 [2019-12-07 18:24:05,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,300 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2019-12-07 18:24:05,300 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,300 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643219642] [2019-12-07 18:24:05,300 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,311 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,311 INFO L82 PathProgramCache]: Analyzing trace with hash -837923902, now seen corresponding path program 2 times [2019-12-07 18:24:05,311 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,311 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849654510] [2019-12-07 18:24:05,311 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,315 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,316 INFO L82 PathProgramCache]: Analyzing trace with hash -1191670748, now seen corresponding path program 1 times [2019-12-07 18:24:05,316 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,316 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669981982] [2019-12-07 18:24:05,316 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:05,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:05,332 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669981982] [2019-12-07 18:24:05,332 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:05,332 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:24:05,332 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432135333] [2019-12-07 18:24:05,382 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:05,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:05,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:05,382 INFO L87 Difference]: Start difference. First operand 7886 states and 10704 transitions. cyclomatic complexity: 2830 Second operand 3 states. [2019-12-07 18:24:05,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:05,419 INFO L93 Difference]: Finished difference Result 8666 states and 11688 transitions. [2019-12-07 18:24:05,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:05,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8666 states and 11688 transitions. [2019-12-07 18:24:05,440 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8488 [2019-12-07 18:24:05,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8666 states to 8666 states and 11688 transitions. [2019-12-07 18:24:05,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8666 [2019-12-07 18:24:05,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8666 [2019-12-07 18:24:05,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8666 states and 11688 transitions. [2019-12-07 18:24:05,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:05,462 INFO L688 BuchiCegarLoop]: Abstraction has 8666 states and 11688 transitions. [2019-12-07 18:24:05,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8666 states and 11688 transitions. [2019-12-07 18:24:05,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8666 to 8400. [2019-12-07 18:24:05,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8400 states. [2019-12-07 18:24:05,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8400 states to 8400 states and 11380 transitions. [2019-12-07 18:24:05,523 INFO L711 BuchiCegarLoop]: Abstraction has 8400 states and 11380 transitions. [2019-12-07 18:24:05,523 INFO L591 BuchiCegarLoop]: Abstraction has 8400 states and 11380 transitions. [2019-12-07 18:24:05,523 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 18:24:05,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8400 states and 11380 transitions. [2019-12-07 18:24:05,540 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8222 [2019-12-07 18:24:05,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:05,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:05,541 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,541 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,541 INFO L794 eck$LassoCheckResult]: Stem: 99420#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 99263#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 99247#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 99248#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 99566#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99481#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99482#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99534#L309-1 assume !(0 == ~M_E~0); 99461#L431-1 assume !(0 == ~T1_E~0); 99462#L436-1 assume !(0 == ~T2_E~0); 99502#L441-1 assume !(0 == ~T3_E~0); 99402#L446-1 assume !(0 == ~E_M~0); 99403#L451-1 assume !(0 == ~E_1~0); 99432#L456-1 assume !(0 == ~E_2~0); 99307#L461-1 assume !(0 == ~E_3~0); 99308#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99366#L210 assume !(1 == ~m_pc~0); 99541#L210-2 is_master_triggered_~__retres1~0 := 0; 99542#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 99550#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 99261#L533 assume !(0 != activate_threads_~tmp~1); 99262#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 99376#L229 assume !(1 == ~t1_pc~0); 99252#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 99377#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99253#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 99254#L541 assume !(0 != activate_threads_~tmp___0~0); 99484#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 99412#L248 assume !(1 == ~t2_pc~0); 99404#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 99405#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 99415#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 99336#L549 assume !(0 != activate_threads_~tmp___1~0); 99294#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 99295#L267 assume !(1 == ~t3_pc~0); 99574#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 99575#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 99363#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 99364#L557 assume !(0 != activate_threads_~tmp___2~0); 99545#L557-2 assume !(1 == ~M_E~0); 99396#L479-1 assume !(1 == ~T1_E~0); 99397#L484-1 assume !(1 == ~T2_E~0); 99429#L489-1 assume !(1 == ~T3_E~0); 99296#L494-1 assume !(1 == ~E_M~0); 99297#L499-1 assume !(1 == ~E_1~0); 99362#L504-1 assume !(1 == ~E_2~0); 99571#L509-1 assume !(1 == ~E_3~0); 99584#L680-1 assume !false; 101438#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 101432#L406 [2019-12-07 18:24:05,541 INFO L796 eck$LassoCheckResult]: Loop: 101432#L406 assume !false; 101425#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 101419#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 101413#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 101412#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 101409#L359 assume 0 != eval_~tmp~0; 101407#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 101399#L367 assume !(0 != eval_~tmp_ndt_1~0); 101301#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 101172#L381 assume !(0 != eval_~tmp_ndt_2~0); 101299#L378 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 101295#L395 assume !(0 != eval_~tmp_ndt_3~0); 101296#L392 assume !(0 == ~t3_st~0); 101432#L406 [2019-12-07 18:24:05,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,541 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2019-12-07 18:24:05,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108397479] [2019-12-07 18:24:05,542 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,550 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,551 INFO L82 PathProgramCache]: Analyzing trace with hash -205964527, now seen corresponding path program 1 times [2019-12-07 18:24:05,551 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390708152] [2019-12-07 18:24:05,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,555 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,555 INFO L82 PathProgramCache]: Analyzing trace with hash 1712785135, now seen corresponding path program 1 times [2019-12-07 18:24:05,555 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,556 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781690760] [2019-12-07 18:24:05,556 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:24:05,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:24:05,570 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781690760] [2019-12-07 18:24:05,570 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:24:05,570 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:24:05,570 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [823561401] [2019-12-07 18:24:05,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:24:05,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:24:05,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:24:05,628 INFO L87 Difference]: Start difference. First operand 8400 states and 11380 transitions. cyclomatic complexity: 2992 Second operand 3 states. [2019-12-07 18:24:05,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:24:05,669 INFO L93 Difference]: Finished difference Result 9400 states and 12638 transitions. [2019-12-07 18:24:05,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:24:05,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9400 states and 12638 transitions. [2019-12-07 18:24:05,693 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9218 [2019-12-07 18:24:05,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9400 states to 9400 states and 12638 transitions. [2019-12-07 18:24:05,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9400 [2019-12-07 18:24:05,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9400 [2019-12-07 18:24:05,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9400 states and 12638 transitions. [2019-12-07 18:24:05,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:24:05,718 INFO L688 BuchiCegarLoop]: Abstraction has 9400 states and 12638 transitions. [2019-12-07 18:24:05,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9400 states and 12638 transitions. [2019-12-07 18:24:05,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9400 to 9292. [2019-12-07 18:24:05,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9292 states. [2019-12-07 18:24:05,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9292 states to 9292 states and 12530 transitions. [2019-12-07 18:24:05,812 INFO L711 BuchiCegarLoop]: Abstraction has 9292 states and 12530 transitions. [2019-12-07 18:24:05,812 INFO L591 BuchiCegarLoop]: Abstraction has 9292 states and 12530 transitions. [2019-12-07 18:24:05,812 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 18:24:05,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9292 states and 12530 transitions. [2019-12-07 18:24:05,831 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9110 [2019-12-07 18:24:05,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:24:05,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:24:05,831 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,831 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:24:05,831 INFO L794 eck$LassoCheckResult]: Stem: 117229#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 117072#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 117057#L643 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 117058#L287 assume 1 == ~m_i~0;~m_st~0 := 0; 117384#L294-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117295#L299-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117296#L304-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117352#L309-1 assume !(0 == ~M_E~0); 117276#L431-1 assume !(0 == ~T1_E~0); 117277#L436-1 assume !(0 == ~T2_E~0); 117322#L441-1 assume !(0 == ~T3_E~0); 117211#L446-1 assume !(0 == ~E_M~0); 117212#L451-1 assume !(0 == ~E_1~0); 117243#L456-1 assume !(0 == ~E_2~0); 117116#L461-1 assume !(0 == ~E_3~0); 117117#L466-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117175#L210 assume !(1 == ~m_pc~0); 117356#L210-2 is_master_triggered_~__retres1~0 := 0; 117357#L221 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117366#L222 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 117070#L533 assume !(0 != activate_threads_~tmp~1); 117071#L533-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117186#L229 assume !(1 == ~t1_pc~0); 117060#L229-2 is_transmit1_triggered_~__retres1~1 := 0; 117187#L240 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117061#L241 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 117062#L541 assume !(0 != activate_threads_~tmp___0~0); 117299#L541-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117223#L248 assume !(1 == ~t2_pc~0); 117213#L248-2 is_transmit2_triggered_~__retres1~2 := 0; 117214#L259 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117224#L260 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 117147#L549 assume !(0 != activate_threads_~tmp___1~0); 117103#L549-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 117104#L267 assume !(1 == ~t3_pc~0); 117401#L267-2 is_transmit3_triggered_~__retres1~3 := 0; 117402#L278 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117173#L279 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 117174#L557 assume !(0 != activate_threads_~tmp___2~0); 117360#L557-2 assume !(1 == ~M_E~0); 117207#L479-1 assume !(1 == ~T1_E~0); 117208#L484-1 assume !(1 == ~T2_E~0); 117238#L489-1 assume !(1 == ~T3_E~0); 117105#L494-1 assume !(1 == ~E_M~0); 117106#L499-1 assume !(1 == ~E_1~0); 117171#L504-1 assume !(1 == ~E_2~0); 117397#L509-1 assume !(1 == ~E_3~0); 117411#L680-1 assume !false; 123224#L681 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 122934#L406 [2019-12-07 18:24:05,832 INFO L796 eck$LassoCheckResult]: Loop: 122934#L406 assume !false; 123217#L355 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 123214#L322 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 123211#L344 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 123208#L345 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 123204#L359 assume 0 != eval_~tmp~0; 123199#L359-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 123197#L367 assume !(0 != eval_~tmp_ndt_1~0); 122103#L364 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 122099#L381 assume !(0 != eval_~tmp_ndt_2~0); 122097#L378 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 122095#L395 assume !(0 != eval_~tmp_ndt_3~0); 122096#L392 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 122933#L409 assume !(0 != eval_~tmp_ndt_4~0); 122934#L406 [2019-12-07 18:24:05,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2019-12-07 18:24:05,832 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,832 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14721497] [2019-12-07 18:24:05,832 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,844 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,845 INFO L82 PathProgramCache]: Analyzing trace with hash -2089936199, now seen corresponding path program 1 times [2019-12-07 18:24:05,845 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,845 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076866438] [2019-12-07 18:24:05,845 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,849 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:05,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:24:05,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1556728475, now seen corresponding path program 1 times [2019-12-07 18:24:05,849 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:24:05,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826580064] [2019-12-07 18:24:05,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:24:05,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:24:05,861 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:24:06,191 WARN L192 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 92 [2019-12-07 18:24:06,298 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:24:06 BoogieIcfgContainer [2019-12-07 18:24:06,298 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:24:06,299 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:24:06,299 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:24:06,299 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:24:06,299 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:24:02" (3/4) ... [2019-12-07 18:24:06,302 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:24:06,348 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_9b14be87-65aa-4759-a0d4-bf9398c677bc/bin/uautomizer/witness.graphml [2019-12-07 18:24:06,348 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:24:06,349 INFO L168 Benchmark]: Toolchain (without parser) took 4595.89 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 221.2 MB). Free memory was 939.3 MB in the beginning and 1.0 GB in the end (delta: -68.9 MB). Peak memory consumption was 152.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,349 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:24:06,350 INFO L168 Benchmark]: CACSL2BoogieTranslator took 245.67 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -146.9 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,350 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:24:06,350 INFO L168 Benchmark]: Boogie Preprocessor took 33.33 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,350 INFO L168 Benchmark]: RCFGBuilder took 553.01 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.1 MB in the end (delta: 82.8 MB). Peak memory consumption was 82.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,351 INFO L168 Benchmark]: BuchiAutomizer took 3674.03 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 123.2 MB). Free memory was 998.1 MB in the beginning and 1.0 GB in the end (delta: -21.0 MB). Peak memory consumption was 102.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,351 INFO L168 Benchmark]: Witness Printer took 49.50 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:24:06,352 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 245.67 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -146.9 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 33.33 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 553.01 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.1 MB in the end (delta: 82.8 MB). Peak memory consumption was 82.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 3674.03 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 123.2 MB). Free memory was 998.1 MB in the beginning and 1.0 GB in the end (delta: -21.0 MB). Peak memory consumption was 102.2 MB. Max. memory is 11.5 GB. * Witness Printer took 49.50 ms. Allocated memory is still 1.3 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 10.8 MB). Peak memory consumption was 10.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 9292 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.6s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 1.4s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 17 MinimizatonAttempts, 6228 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 9292 states and ocurred in iteration 17. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 7937 SDtfs, 7734 SDslu, 6124 SDs, 0 SdLazy, 324 SolverSat, 169 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.2s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 354]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51e02aaa=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f683164=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a6bc08a=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@331b9472=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@64666329=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b4a4f89=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72a216ca=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38715d3f=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@560f2189=0, t1_st=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12bafe17=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2d9108e9=0, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 354]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int t3_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int t3_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int T3_E = 2; [L30] int E_M = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L39] int token ; [L41] int local ; [L725] int __retres1 ; [L638] m_i = 1 [L639] t1_i = 1 [L640] t2_i = 1 [L641] t3_i = 1 [L666] int kernel_st ; [L667] int tmp ; [L668] int tmp___0 ; [L672] kernel_st = 0 [L294] COND TRUE m_i == 1 [L295] m_st = 0 [L299] COND TRUE t1_i == 1 [L300] t1_st = 0 [L304] COND TRUE t2_i == 1 [L305] t2_st = 0 [L309] COND TRUE t3_i == 1 [L310] t3_st = 0 [L431] COND FALSE !(M_E == 0) [L436] COND FALSE !(T1_E == 0) [L441] COND FALSE !(T2_E == 0) [L446] COND FALSE !(T3_E == 0) [L451] COND FALSE !(E_M == 0) [L456] COND FALSE !(E_1 == 0) [L461] COND FALSE !(E_2 == 0) [L466] COND FALSE !(E_3 == 0) [L524] int tmp ; [L525] int tmp___0 ; [L526] int tmp___1 ; [L527] int tmp___2 ; [L207] int __retres1 ; [L210] COND FALSE !(m_pc == 1) [L220] __retres1 = 0 [L222] return (__retres1); [L531] tmp = is_master_triggered() [L533] COND FALSE !(\read(tmp)) [L226] int __retres1 ; [L229] COND FALSE !(t1_pc == 1) [L239] __retres1 = 0 [L241] return (__retres1); [L539] tmp___0 = is_transmit1_triggered() [L541] COND FALSE !(\read(tmp___0)) [L245] int __retres1 ; [L248] COND FALSE !(t2_pc == 1) [L258] __retres1 = 0 [L260] return (__retres1); [L547] tmp___1 = is_transmit2_triggered() [L549] COND FALSE !(\read(tmp___1)) [L264] int __retres1 ; [L267] COND FALSE !(t3_pc == 1) [L277] __retres1 = 0 [L279] return (__retres1); [L555] tmp___2 = is_transmit3_triggered() [L557] COND FALSE !(\read(tmp___2)) [L479] COND FALSE !(M_E == 1) [L484] COND FALSE !(T1_E == 1) [L489] COND FALSE !(T2_E == 1) [L494] COND FALSE !(T3_E == 1) [L499] COND FALSE !(E_M == 1) [L504] COND FALSE !(E_1 == 1) [L509] COND FALSE !(E_2 == 1) [L514] COND FALSE !(E_3 == 1) [L680] COND TRUE 1 [L683] kernel_st = 1 [L350] int tmp ; Loop: [L354] COND TRUE 1 [L319] int __retres1 ; [L322] COND TRUE m_st == 0 [L323] __retres1 = 1 [L345] return (__retres1); [L357] tmp = exists_runnable_thread() [L359] COND TRUE \read(tmp) [L364] COND TRUE m_st == 0 [L365] int tmp_ndt_1; [L366] tmp_ndt_1 = __VERIFIER_nondet_int() [L367] COND FALSE !(\read(tmp_ndt_1)) [L378] COND TRUE t1_st == 0 [L379] int tmp_ndt_2; [L380] tmp_ndt_2 = __VERIFIER_nondet_int() [L381] COND FALSE !(\read(tmp_ndt_2)) [L392] COND TRUE t2_st == 0 [L393] int tmp_ndt_3; [L394] tmp_ndt_3 = __VERIFIER_nondet_int() [L395] COND FALSE !(\read(tmp_ndt_3)) [L406] COND TRUE t3_st == 0 [L407] int tmp_ndt_4; [L408] tmp_ndt_4 = __VERIFIER_nondet_int() [L409] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...