./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 460c5a2466ddacef0b654abb4130c31f8265660c ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:55:01,672 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:55:01,673 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:55:01,681 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:55:01,681 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:55:01,682 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:55:01,683 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:55:01,684 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:55:01,685 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:55:01,686 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:55:01,686 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:55:01,687 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:55:01,687 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:55:01,688 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:55:01,689 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:55:01,690 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:55:01,690 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:55:01,691 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:55:01,692 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:55:01,694 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:55:01,695 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:55:01,695 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:55:01,696 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:55:01,697 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:55:01,698 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:55:01,699 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:55:01,699 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:55:01,699 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:55:01,699 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:55:01,700 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:55:01,700 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:55:01,700 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:55:01,701 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:55:01,701 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:55:01,702 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:55:01,702 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:55:01,702 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:55:01,703 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:55:01,703 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:55:01,703 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:55:01,704 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:55:01,704 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 12:55:01,715 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:55:01,715 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:55:01,716 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 12:55:01,716 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 12:55:01,716 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 12:55:01,716 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 12:55:01,717 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 12:55:01,717 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 12:55:01,718 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:55:01,719 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 12:55:01,719 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:55:01,719 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 12:55:01,719 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:55:01,719 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 12:55:01,719 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 12:55:01,720 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:55:01,720 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 12:55:01,720 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:55:01,720 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 12:55:01,720 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 12:55:01,721 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 460c5a2466ddacef0b654abb4130c31f8265660c [2019-12-07 12:55:01,820 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:55:01,830 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:55:01,833 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:55:01,834 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:55:01,835 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:55:01,835 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2019-12-07 12:55:01,882 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/data/1c998c997/e5444ee6060c45e697864da2f3280a79/FLAG0a3b275d9 [2019-12-07 12:55:02,237 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:55:02,238 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2019-12-07 12:55:02,245 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/data/1c998c997/e5444ee6060c45e697864da2f3280a79/FLAG0a3b275d9 [2019-12-07 12:55:02,254 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/data/1c998c997/e5444ee6060c45e697864da2f3280a79 [2019-12-07 12:55:02,257 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:55:02,258 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:55:02,259 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:55:02,259 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:55:02,262 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:55:02,263 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,265 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d97e9b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02, skipping insertion in model container [2019-12-07 12:55:02,265 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,271 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:55:02,296 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:55:02,456 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:55:02,460 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:55:02,488 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:55:02,501 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:55:02,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02 WrapperNode [2019-12-07 12:55:02,501 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:55:02,502 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:55:02,502 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:55:02,502 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:55:02,507 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,512 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,539 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:55:02,540 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:55:02,540 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:55:02,540 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:55:02,546 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,546 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,549 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,550 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,558 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,567 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,569 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... [2019-12-07 12:55:02,573 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:55:02,574 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:55:02,574 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:55:02,574 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:55:02,575 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:55:02,615 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:55:02,615 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:55:03,084 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:55:03,084 INFO L287 CfgBuilder]: Removed 130 assume(true) statements. [2019-12-07 12:55:03,085 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:55:03 BoogieIcfgContainer [2019-12-07 12:55:03,085 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:55:03,086 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 12:55:03,086 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 12:55:03,088 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 12:55:03,089 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:55:03,089 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:55:02" (1/3) ... [2019-12-07 12:55:03,089 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@570cbc40 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:55:03, skipping insertion in model container [2019-12-07 12:55:03,090 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:55:03,090 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:55:02" (2/3) ... [2019-12-07 12:55:03,090 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@570cbc40 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:55:03, skipping insertion in model container [2019-12-07 12:55:03,090 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:55:03,090 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:55:03" (3/3) ... [2019-12-07 12:55:03,091 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2019-12-07 12:55:03,119 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 12:55:03,119 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 12:55:03,119 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 12:55:03,119 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:55:03,119 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:55:03,119 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 12:55:03,119 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:55:03,119 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 12:55:03,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states. [2019-12-07 12:55:03,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 253 [2019-12-07 12:55:03,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,171 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,171 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,171 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 12:55:03,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states. [2019-12-07 12:55:03,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 253 [2019-12-07 12:55:03,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,184 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,185 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,192 INFO L794 eck$LassoCheckResult]: Stem: 115#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 5#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44#L631true havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 112#L275true assume !(1 == ~m_i~0);~m_st~0 := 2; 170#L282-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 182#L287-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 96#L292-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 111#L297-1true assume !(0 == ~M_E~0); 199#L419-1true assume !(0 == ~T1_E~0); 84#L424-1true assume !(0 == ~T2_E~0); 129#L429-1true assume !(0 == ~T3_E~0); 153#L434-1true assume !(0 == ~E_M~0); 15#L439-1true assume 0 == ~E_1~0;~E_1~0 := 1; 36#L444-1true assume !(0 == ~E_2~0); 237#L449-1true assume !(0 == ~E_3~0); 270#L454-1true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 105#L198true assume 1 == ~m_pc~0; 179#L199true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 106#L209true is_master_triggered_#res := is_master_triggered_~__retres1~0; 180#L210true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30#L521true assume !(0 != activate_threads_~tmp~1); 32#L521-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 291#L217true assume !(1 == ~t1_pc~0); 285#L217-2true is_transmit1_triggered_~__retres1~1 := 0; 292#L228true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40#L229true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 216#L529true assume !(0 != activate_threads_~tmp___0~0); 218#L529-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 151#L236true assume 1 == ~t2_pc~0; 91#L237true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 152#L247true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92#L248true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 220#L537true assume !(0 != activate_threads_~tmp___1~0); 228#L537-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 164#L255true assume 1 == ~t3_pc~0; 265#L256true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 165#L266true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 266#L267true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 107#L545true assume !(0 != activate_threads_~tmp___2~0); 114#L545-2true assume 1 == ~M_E~0;~M_E~0 := 2; 150#L467-1true assume !(1 == ~T1_E~0); 13#L472-1true assume !(1 == ~T2_E~0); 34#L477-1true assume !(1 == ~T3_E~0); 232#L482-1true assume !(1 == ~E_M~0); 268#L487-1true assume !(1 == ~E_1~0); 300#L492-1true assume !(1 == ~E_2~0); 166#L497-1true assume !(1 == ~E_3~0); 306#L668-1true [2019-12-07 12:55:03,193 INFO L796 eck$LassoCheckResult]: Loop: 306#L668-1true assume !false; 243#L669true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 239#L394true assume !true; 156#L409true start_simulation_~kernel_st~0 := 2; 108#L275-1true start_simulation_~kernel_st~0 := 3; 202#L419-2true assume 0 == ~M_E~0;~M_E~0 := 1; 211#L419-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 97#L424-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 138#L429-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 155#L434-3true assume !(0 == ~E_M~0); 6#L439-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L444-3true assume 0 == ~E_2~0;~E_2~0 := 1; 50#L449-3true assume 0 == ~E_3~0;~E_3~0 := 1; 250#L454-3true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87#L198-15true assume 1 == ~m_pc~0; 189#L199-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 119#L209-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 190#L210-5true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23#L521-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12#L521-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 263#L217-15true assume 1 == ~t1_pc~0; 51#L218-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 277#L228-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52#L229-5true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 178#L529-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 181#L529-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110#L236-15true assume !(1 == ~t2_pc~0); 104#L236-17true is_transmit2_triggered_~__retres1~2 := 0; 132#L247-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208#L248-5true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 47#L537-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 31#L537-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 272#L255-15true assume 1 == ~t3_pc~0; 225#L256-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 295#L266-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 227#L267-5true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 215#L545-15true assume !(0 != activate_threads_~tmp___2~0); 217#L545-17true assume 1 == ~M_E~0;~M_E~0 := 2; 154#L467-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 16#L472-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 38#L477-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 242#L482-3true assume 1 == ~E_M~0;~E_M~0 := 2; 247#L487-3true assume 1 == ~E_1~0;~E_1~0 := 2; 278#L492-3true assume 1 == ~E_2~0;~E_2~0 := 2; 157#L497-3true assume !(1 == ~E_3~0); 168#L502-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 162#L310-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 161#L332-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 255#L333-1true start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 11#L687true assume !(0 == start_simulation_~tmp~3); 3#L687-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 303#L310-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 163#L332-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 257#L333-2true stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 43#L642true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 141#L649true stop_simulation_#res := stop_simulation_~__retres2~0; 76#L650true start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 188#L700true assume !(0 != start_simulation_~tmp___0~1); 306#L668-1true [2019-12-07 12:55:03,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,199 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2019-12-07 12:55:03,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,205 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597039122] [2019-12-07 12:55:03,205 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,316 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597039122] [2019-12-07 12:55:03,317 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,317 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,318 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145053960] [2019-12-07 12:55:03,321 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,322 INFO L82 PathProgramCache]: Analyzing trace with hash 2027900336, now seen corresponding path program 1 times [2019-12-07 12:55:03,322 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,322 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453326258] [2019-12-07 12:55:03,322 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,340 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453326258] [2019-12-07 12:55:03,340 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:03,341 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674718261] [2019-12-07 12:55:03,342 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,343 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,355 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,357 INFO L87 Difference]: Start difference. First operand 308 states. Second operand 3 states. [2019-12-07 12:55:03,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,383 INFO L93 Difference]: Finished difference Result 308 states and 466 transitions. [2019-12-07 12:55:03,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 466 transitions. [2019-12-07 12:55:03,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 303 states and 461 transitions. [2019-12-07 12:55:03,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2019-12-07 12:55:03,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2019-12-07 12:55:03,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 461 transitions. [2019-12-07 12:55:03,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,397 INFO L688 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2019-12-07 12:55:03,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 461 transitions. [2019-12-07 12:55:03,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2019-12-07 12:55:03,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-12-07 12:55:03,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 461 transitions. [2019-12-07 12:55:03,427 INFO L711 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2019-12-07 12:55:03,427 INFO L591 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2019-12-07 12:55:03,427 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 12:55:03,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 461 transitions. [2019-12-07 12:55:03,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,430 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,430 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,431 INFO L794 eck$LassoCheckResult]: Stem: 830#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 629#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 630#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 696#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 826#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 878#L287-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 795#L292-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 796#L297-1 assume !(0 == ~M_E~0); 825#L419-1 assume !(0 == ~T1_E~0); 771#L424-1 assume !(0 == ~T2_E~0); 772#L429-1 assume !(0 == ~T3_E~0); 847#L434-1 assume !(0 == ~E_M~0); 650#L439-1 assume 0 == ~E_1~0;~E_1~0 := 1; 651#L444-1 assume !(0 == ~E_2~0); 682#L449-1 assume !(0 == ~E_3~0); 912#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812#L198 assume 1 == ~m_pc~0; 813#L199 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 815#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 816#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 673#L521 assume !(0 != activate_threads_~tmp~1); 674#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 679#L217 assume !(1 == ~t1_pc~0); 687#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 686#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 690#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 691#L529 assume !(0 != activate_threads_~tmp___0~0); 891#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 860#L236 assume 1 == ~t2_pc~0; 785#L237 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 786#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 789#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 790#L537 assume !(0 != activate_threads_~tmp___1~0); 896#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 870#L255 assume 1 == ~t3_pc~0; 871#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 873#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 874#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 819#L545 assume !(0 != activate_threads_~tmp___2~0); 820#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 829#L467-1 assume !(1 == ~T1_E~0); 648#L472-1 assume !(1 == ~T2_E~0); 649#L477-1 assume !(1 == ~T3_E~0); 680#L482-1 assume !(1 == ~E_M~0); 907#L487-1 assume !(1 == ~E_1~0); 927#L492-1 assume !(1 == ~E_2~0); 875#L497-1 assume !(1 == ~E_3~0); 876#L668-1 [2019-12-07 12:55:03,431 INFO L796 eck$LassoCheckResult]: Loop: 876#L668-1 assume !false; 919#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 732#L394 assume !false; 864#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 865#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 634#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 866#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 791#L347 assume !(0 != eval_~tmp~0); 792#L409 start_simulation_~kernel_st~0 := 2; 821#L275-1 start_simulation_~kernel_st~0 := 3; 822#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 888#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 797#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 798#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 855#L434-3 assume !(0 == ~E_M~0); 631#L439-3 assume 0 == ~E_1~0;~E_1~0 := 1; 632#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 665#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 704#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 778#L198-15 assume 1 == ~m_pc~0; 779#L199-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 765#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 836#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 662#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 644#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 645#L217-15 assume 1 == ~t1_pc~0; 705#L218-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 706#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 708#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 709#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 880#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 823#L236-15 assume 1 == ~t2_pc~0; 824#L237-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 811#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 849#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 699#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 675#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 676#L255-15 assume 1 == ~t3_pc~0; 898#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 899#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 901#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 889#L545-15 assume !(0 != activate_threads_~tmp___2~0); 890#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 861#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 652#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 653#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 684#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 917#L487-3 assume 1 == ~E_1~0;~E_1~0 := 2; 921#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 862#L497-3 assume !(1 == ~E_3~0); 863#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 868#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 637#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 867#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 642#L687 assume !(0 == start_simulation_~tmp~3); 625#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 626#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 641#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 869#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 694#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 695#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 755#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 756#L700 assume !(0 != start_simulation_~tmp___0~1); 876#L668-1 [2019-12-07 12:55:03,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,431 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2019-12-07 12:55:03,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351688624] [2019-12-07 12:55:03,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,454 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351688624] [2019-12-07 12:55:03,454 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,454 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653353107] [2019-12-07 12:55:03,455 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,455 INFO L82 PathProgramCache]: Analyzing trace with hash -37711328, now seen corresponding path program 1 times [2019-12-07 12:55:03,455 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,455 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884041278] [2019-12-07 12:55:03,455 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,497 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884041278] [2019-12-07 12:55:03,497 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,497 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,497 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012943333] [2019-12-07 12:55:03,497 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,498 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,498 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,498 INFO L87 Difference]: Start difference. First operand 303 states and 461 transitions. cyclomatic complexity: 159 Second operand 3 states. [2019-12-07 12:55:03,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,509 INFO L93 Difference]: Finished difference Result 303 states and 460 transitions. [2019-12-07 12:55:03,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 460 transitions. [2019-12-07 12:55:03,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 460 transitions. [2019-12-07 12:55:03,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2019-12-07 12:55:03,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2019-12-07 12:55:03,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 460 transitions. [2019-12-07 12:55:03,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,517 INFO L688 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2019-12-07 12:55:03,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 460 transitions. [2019-12-07 12:55:03,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2019-12-07 12:55:03,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-12-07 12:55:03,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 460 transitions. [2019-12-07 12:55:03,526 INFO L711 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2019-12-07 12:55:03,527 INFO L591 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2019-12-07 12:55:03,527 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 12:55:03,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 460 transitions. [2019-12-07 12:55:03,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,529 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,529 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,530 INFO L794 eck$LassoCheckResult]: Stem: 1445#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1244#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1245#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1309#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 1439#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1491#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1408#L292-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1409#L297-1 assume !(0 == ~M_E~0); 1438#L419-1 assume !(0 == ~T1_E~0); 1387#L424-1 assume !(0 == ~T2_E~0); 1388#L429-1 assume !(0 == ~T3_E~0); 1460#L434-1 assume !(0 == ~E_M~0); 1263#L439-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1264#L444-1 assume !(0 == ~E_2~0); 1295#L449-1 assume !(0 == ~E_3~0); 1525#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1425#L198 assume 1 == ~m_pc~0; 1426#L199 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1428#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1429#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1286#L521 assume !(0 != activate_threads_~tmp~1); 1287#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1292#L217 assume !(1 == ~t1_pc~0); 1300#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 1299#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1303#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1304#L529 assume !(0 != activate_threads_~tmp___0~0); 1504#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1473#L236 assume 1 == ~t2_pc~0; 1398#L237 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1399#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1403#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1404#L537 assume !(0 != activate_threads_~tmp___1~0); 1509#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1483#L255 assume 1 == ~t3_pc~0; 1484#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1486#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1487#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1432#L545 assume !(0 != activate_threads_~tmp___2~0); 1433#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1442#L467-1 assume !(1 == ~T1_E~0); 1261#L472-1 assume !(1 == ~T2_E~0); 1262#L477-1 assume !(1 == ~T3_E~0); 1293#L482-1 assume !(1 == ~E_M~0); 1520#L487-1 assume !(1 == ~E_1~0); 1540#L492-1 assume !(1 == ~E_2~0); 1488#L497-1 assume !(1 == ~E_3~0); 1489#L668-1 [2019-12-07 12:55:03,530 INFO L796 eck$LassoCheckResult]: Loop: 1489#L668-1 assume !false; 1532#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1345#L394 assume !false; 1477#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1478#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1247#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1479#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1405#L347 assume !(0 != eval_~tmp~0); 1406#L409 start_simulation_~kernel_st~0 := 2; 1434#L275-1 start_simulation_~kernel_st~0 := 3; 1435#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1501#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1410#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1411#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1469#L434-3 assume !(0 == ~E_M~0); 1242#L439-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1243#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1317#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1389#L198-15 assume 1 == ~m_pc~0; 1390#L199-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1376#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1449#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1275#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1257#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1258#L217-15 assume 1 == ~t1_pc~0; 1318#L218-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1319#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1321#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1322#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1493#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1436#L236-15 assume 1 == ~t2_pc~0; 1437#L237-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1424#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1462#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1312#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1288#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1289#L255-15 assume 1 == ~t3_pc~0; 1511#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1512#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1514#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1502#L545-15 assume !(0 != activate_threads_~tmp___2~0); 1503#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1474#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1265#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1266#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1297#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1530#L487-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1534#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1475#L497-3 assume !(1 == ~E_3~0); 1476#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1481#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1250#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1480#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1255#L687 assume !(0 == start_simulation_~tmp~3); 1238#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1239#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1254#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1482#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 1307#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1308#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 1368#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1369#L700 assume !(0 != start_simulation_~tmp___0~1); 1489#L668-1 [2019-12-07 12:55:03,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,531 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2019-12-07 12:55:03,531 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865294262] [2019-12-07 12:55:03,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,549 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865294262] [2019-12-07 12:55:03,549 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,550 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,550 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371247305] [2019-12-07 12:55:03,550 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,550 INFO L82 PathProgramCache]: Analyzing trace with hash -37711328, now seen corresponding path program 2 times [2019-12-07 12:55:03,550 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267808880] [2019-12-07 12:55:03,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267808880] [2019-12-07 12:55:03,579 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,579 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046275728] [2019-12-07 12:55:03,580 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,581 INFO L87 Difference]: Start difference. First operand 303 states and 460 transitions. cyclomatic complexity: 158 Second operand 3 states. [2019-12-07 12:55:03,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,588 INFO L93 Difference]: Finished difference Result 303 states and 459 transitions. [2019-12-07 12:55:03,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 459 transitions. [2019-12-07 12:55:03,591 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 459 transitions. [2019-12-07 12:55:03,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2019-12-07 12:55:03,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2019-12-07 12:55:03,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2019-12-07 12:55:03,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,594 INFO L688 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2019-12-07 12:55:03,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2019-12-07 12:55:03,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2019-12-07 12:55:03,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-12-07 12:55:03,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2019-12-07 12:55:03,602 INFO L711 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2019-12-07 12:55:03,602 INFO L591 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2019-12-07 12:55:03,602 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 12:55:03,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2019-12-07 12:55:03,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,605 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,605 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,605 INFO L794 eck$LassoCheckResult]: Stem: 2056#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1855#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1856#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1922#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 2052#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2104#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2021#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2022#L297-1 assume !(0 == ~M_E~0); 2051#L419-1 assume !(0 == ~T1_E~0); 1997#L424-1 assume !(0 == ~T2_E~0); 1998#L429-1 assume !(0 == ~T3_E~0); 2073#L434-1 assume !(0 == ~E_M~0); 1876#L439-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1877#L444-1 assume !(0 == ~E_2~0); 1908#L449-1 assume !(0 == ~E_3~0); 2138#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2038#L198 assume 1 == ~m_pc~0; 2039#L199 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2041#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2042#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1899#L521 assume !(0 != activate_threads_~tmp~1); 1900#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1903#L217 assume !(1 == ~t1_pc~0); 1913#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 1912#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1914#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1915#L529 assume !(0 != activate_threads_~tmp___0~0); 2117#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2086#L236 assume 1 == ~t2_pc~0; 2011#L237 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2012#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2014#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2015#L537 assume !(0 != activate_threads_~tmp___1~0); 2119#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2096#L255 assume 1 == ~t3_pc~0; 2097#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2099#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2100#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2043#L545 assume !(0 != activate_threads_~tmp___2~0); 2044#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2055#L467-1 assume !(1 == ~T1_E~0); 1872#L472-1 assume !(1 == ~T2_E~0); 1873#L477-1 assume !(1 == ~T3_E~0); 1906#L482-1 assume !(1 == ~E_M~0); 2133#L487-1 assume !(1 == ~E_1~0); 2153#L492-1 assume !(1 == ~E_2~0); 2101#L497-1 assume !(1 == ~E_3~0); 2102#L668-1 [2019-12-07 12:55:03,605 INFO L796 eck$LassoCheckResult]: Loop: 2102#L668-1 assume !false; 2145#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1958#L394 assume !false; 2090#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2091#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1860#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2092#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2016#L347 assume !(0 != eval_~tmp~0); 2017#L409 start_simulation_~kernel_st~0 := 2; 2045#L275-1 start_simulation_~kernel_st~0 := 3; 2046#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2114#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2023#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2024#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2081#L434-3 assume !(0 == ~E_M~0); 1857#L439-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1858#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1891#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1930#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2003#L198-15 assume !(1 == ~m_pc~0); 1988#L198-17 is_master_triggered_~__retres1~0 := 0; 1989#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2062#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1888#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1870#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1871#L217-15 assume 1 == ~t1_pc~0; 1931#L218-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1932#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1934#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1935#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2106#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2049#L236-15 assume 1 == ~t2_pc~0; 2050#L237-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2037#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2075#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1925#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1901#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1902#L255-15 assume 1 == ~t3_pc~0; 2124#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2125#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2128#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2115#L545-15 assume !(0 != activate_threads_~tmp___2~0); 2116#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2087#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1878#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1879#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1910#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2144#L487-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2147#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2088#L497-3 assume !(1 == ~E_3~0); 2089#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2094#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1863#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2093#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1868#L687 assume !(0 == start_simulation_~tmp~3); 1851#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1852#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1867#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2095#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 1920#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1921#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 1981#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1982#L700 assume !(0 != start_simulation_~tmp___0~1); 2102#L668-1 [2019-12-07 12:55:03,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,606 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2019-12-07 12:55:03,606 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869192386] [2019-12-07 12:55:03,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869192386] [2019-12-07 12:55:03,629 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:03,630 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048668695] [2019-12-07 12:55:03,630 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1312814017, now seen corresponding path program 1 times [2019-12-07 12:55:03,630 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,631 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409028367] [2019-12-07 12:55:03,631 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,659 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409028367] [2019-12-07 12:55:03,659 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,659 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,659 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038852184] [2019-12-07 12:55:03,659 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,660 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,660 INFO L87 Difference]: Start difference. First operand 303 states and 459 transitions. cyclomatic complexity: 157 Second operand 3 states. [2019-12-07 12:55:03,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,688 INFO L93 Difference]: Finished difference Result 303 states and 448 transitions. [2019-12-07 12:55:03,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 448 transitions. [2019-12-07 12:55:03,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 448 transitions. [2019-12-07 12:55:03,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2019-12-07 12:55:03,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2019-12-07 12:55:03,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 448 transitions. [2019-12-07 12:55:03,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,695 INFO L688 BuchiCegarLoop]: Abstraction has 303 states and 448 transitions. [2019-12-07 12:55:03,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 448 transitions. [2019-12-07 12:55:03,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2019-12-07 12:55:03,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-12-07 12:55:03,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 448 transitions. [2019-12-07 12:55:03,702 INFO L711 BuchiCegarLoop]: Abstraction has 303 states and 448 transitions. [2019-12-07 12:55:03,702 INFO L591 BuchiCegarLoop]: Abstraction has 303 states and 448 transitions. [2019-12-07 12:55:03,702 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 12:55:03,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 448 transitions. [2019-12-07 12:55:03,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2019-12-07 12:55:03,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,706 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,706 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,706 INFO L794 eck$LassoCheckResult]: Stem: 2663#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2468#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2469#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2533#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 2659#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2711#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2628#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2629#L297-1 assume !(0 == ~M_E~0); 2658#L419-1 assume !(0 == ~T1_E~0); 2604#L424-1 assume !(0 == ~T2_E~0); 2605#L429-1 assume !(0 == ~T3_E~0); 2680#L434-1 assume !(0 == ~E_M~0); 2489#L439-1 assume !(0 == ~E_1~0); 2490#L444-1 assume !(0 == ~E_2~0); 2520#L449-1 assume !(0 == ~E_3~0); 2747#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2645#L198 assume 1 == ~m_pc~0; 2646#L199 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2648#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2649#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2511#L521 assume !(0 != activate_threads_~tmp~1); 2512#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2515#L217 assume !(1 == ~t1_pc~0); 2524#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 2766#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2525#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2526#L529 assume !(0 != activate_threads_~tmp___0~0); 2724#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2693#L236 assume 1 == ~t2_pc~0; 2618#L237 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2619#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2621#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2622#L537 assume !(0 != activate_threads_~tmp___1~0); 2726#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2703#L255 assume 1 == ~t3_pc~0; 2704#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2706#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2707#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2650#L545 assume !(0 != activate_threads_~tmp___2~0); 2651#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2662#L467-1 assume !(1 == ~T1_E~0); 2485#L472-1 assume !(1 == ~T2_E~0); 2486#L477-1 assume !(1 == ~T3_E~0); 2518#L482-1 assume !(1 == ~E_M~0); 2741#L487-1 assume !(1 == ~E_1~0); 2764#L492-1 assume !(1 == ~E_2~0); 2708#L497-1 assume !(1 == ~E_3~0); 2709#L668-1 [2019-12-07 12:55:03,707 INFO L796 eck$LassoCheckResult]: Loop: 2709#L668-1 assume !false; 2754#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2565#L394 assume !false; 2697#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2698#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2473#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2699#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2623#L347 assume !(0 != eval_~tmp~0); 2624#L409 start_simulation_~kernel_st~0 := 2; 2652#L275-1 start_simulation_~kernel_st~0 := 3; 2653#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2721#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2630#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2631#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2688#L434-3 assume !(0 == ~E_M~0); 2470#L439-3 assume !(0 == ~E_1~0); 2471#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2504#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2541#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2610#L198-15 assume !(1 == ~m_pc~0); 2595#L198-17 is_master_triggered_~__retres1~0 := 0; 2596#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2669#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2501#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2483#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2484#L217-15 assume !(1 == ~t1_pc~0); 2543#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 2745#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2544#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2545#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2713#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2656#L236-15 assume 1 == ~t2_pc~0; 2657#L237-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2644#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2682#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2536#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2513#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2514#L255-15 assume 1 == ~t3_pc~0; 2732#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2733#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2736#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2722#L545-15 assume !(0 != activate_threads_~tmp___2~0); 2723#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2694#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2491#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2492#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2522#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2753#L487-3 assume !(1 == ~E_1~0); 2756#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2695#L497-3 assume !(1 == ~E_3~0); 2696#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2701#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2476#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2700#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2481#L687 assume !(0 == start_simulation_~tmp~3); 2464#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2465#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2480#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2702#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 2531#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2532#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 2588#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2589#L700 assume !(0 != start_simulation_~tmp___0~1); 2709#L668-1 [2019-12-07 12:55:03,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,707 INFO L82 PathProgramCache]: Analyzing trace with hash 989493984, now seen corresponding path program 1 times [2019-12-07 12:55:03,708 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,708 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854320733] [2019-12-07 12:55:03,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,726 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854320733] [2019-12-07 12:55:03,727 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,727 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:03,727 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055973712] [2019-12-07 12:55:03,727 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,727 INFO L82 PathProgramCache]: Analyzing trace with hash 128600346, now seen corresponding path program 1 times [2019-12-07 12:55:03,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941868573] [2019-12-07 12:55:03,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,752 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941868573] [2019-12-07 12:55:03,752 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,753 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995835563] [2019-12-07 12:55:03,753 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,753 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,753 INFO L87 Difference]: Start difference. First operand 303 states and 448 transitions. cyclomatic complexity: 146 Second operand 3 states. [2019-12-07 12:55:03,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,797 INFO L93 Difference]: Finished difference Result 547 states and 796 transitions. [2019-12-07 12:55:03,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547 states and 796 transitions. [2019-12-07 12:55:03,802 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 495 [2019-12-07 12:55:03,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547 states to 547 states and 796 transitions. [2019-12-07 12:55:03,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547 [2019-12-07 12:55:03,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547 [2019-12-07 12:55:03,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547 states and 796 transitions. [2019-12-07 12:55:03,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,809 INFO L688 BuchiCegarLoop]: Abstraction has 547 states and 796 transitions. [2019-12-07 12:55:03,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states and 796 transitions. [2019-12-07 12:55:03,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 521. [2019-12-07 12:55:03,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2019-12-07 12:55:03,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 760 transitions. [2019-12-07 12:55:03,821 INFO L711 BuchiCegarLoop]: Abstraction has 521 states and 760 transitions. [2019-12-07 12:55:03,821 INFO L591 BuchiCegarLoop]: Abstraction has 521 states and 760 transitions. [2019-12-07 12:55:03,821 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 12:55:03,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 521 states and 760 transitions. [2019-12-07 12:55:03,824 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 469 [2019-12-07 12:55:03,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,825 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,825 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,826 INFO L794 eck$LassoCheckResult]: Stem: 3519#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3327#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3328#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3391#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 3515#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3567#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3484#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3485#L297-1 assume !(0 == ~M_E~0); 3514#L419-1 assume !(0 == ~T1_E~0); 3463#L424-1 assume !(0 == ~T2_E~0); 3464#L429-1 assume !(0 == ~T3_E~0); 3535#L434-1 assume !(0 == ~E_M~0); 3347#L439-1 assume !(0 == ~E_1~0); 3348#L444-1 assume !(0 == ~E_2~0); 3378#L449-1 assume !(0 == ~E_3~0); 3618#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3502#L198 assume !(1 == ~m_pc~0); 3503#L198-2 is_master_triggered_~__retres1~0 := 0; 3504#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3505#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3369#L521 assume !(0 != activate_threads_~tmp~1); 3370#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3375#L217 assume !(1 == ~t1_pc~0); 3382#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 3638#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3385#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3386#L529 assume !(0 != activate_threads_~tmp___0~0); 3595#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3549#L236 assume 1 == ~t2_pc~0; 3473#L237 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3474#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3477#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3478#L537 assume !(0 != activate_threads_~tmp___1~0); 3600#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3559#L255 assume 1 == ~t3_pc~0; 3560#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3562#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3563#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3508#L545 assume !(0 != activate_threads_~tmp___2~0); 3509#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 3518#L467-1 assume !(1 == ~T1_E~0); 3345#L472-1 assume !(1 == ~T2_E~0); 3346#L477-1 assume !(1 == ~T3_E~0); 3376#L482-1 assume !(1 == ~E_M~0); 3612#L487-1 assume !(1 == ~E_1~0); 3635#L492-1 assume !(1 == ~E_2~0); 3564#L497-1 assume !(1 == ~E_3~0); 3565#L668-1 [2019-12-07 12:55:03,826 INFO L796 eck$LassoCheckResult]: Loop: 3565#L668-1 assume !false; 3625#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3423#L394 assume !false; 3553#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3554#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3330#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3555#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3479#L347 assume !(0 != eval_~tmp~0); 3480#L409 start_simulation_~kernel_st~0 := 2; 3510#L275-1 start_simulation_~kernel_st~0 := 3; 3511#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3591#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3486#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3487#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3542#L434-3 assume !(0 == ~E_M~0); 3325#L439-3 assume !(0 == ~E_1~0); 3326#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3362#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3399#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3465#L198-15 assume !(1 == ~m_pc~0); 3452#L198-17 is_master_triggered_~__retres1~0 := 0; 3453#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3524#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3359#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3341#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3342#L217-15 assume !(1 == ~t1_pc~0); 3401#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 3617#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3404#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3405#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3574#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3512#L236-15 assume 1 == ~t2_pc~0; 3513#L237-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3501#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3536#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3394#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3371#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3372#L255-15 assume 1 == ~t3_pc~0; 3603#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3604#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3606#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3593#L545-15 assume !(0 != activate_threads_~tmp___2~0); 3594#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3550#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3350#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3351#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3380#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3623#L487-3 assume !(1 == ~E_1~0); 3627#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3551#L497-3 assume !(1 == ~E_3~0); 3552#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3557#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3333#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3556#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3338#L687 assume !(0 == start_simulation_~tmp~3); 3339#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3722#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3719#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3716#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 3714#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3545#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 3444#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3445#L700 assume !(0 != start_simulation_~tmp___0~1); 3565#L668-1 [2019-12-07 12:55:03,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,826 INFO L82 PathProgramCache]: Analyzing trace with hash -781976991, now seen corresponding path program 1 times [2019-12-07 12:55:03,827 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,827 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749042567] [2019-12-07 12:55:03,827 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749042567] [2019-12-07 12:55:03,847 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,847 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:03,847 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202773763] [2019-12-07 12:55:03,847 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,848 INFO L82 PathProgramCache]: Analyzing trace with hash 128600346, now seen corresponding path program 2 times [2019-12-07 12:55:03,848 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,848 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808914646] [2019-12-07 12:55:03,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,870 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808914646] [2019-12-07 12:55:03,870 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:03,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255392280] [2019-12-07 12:55:03,870 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:03,871 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:03,871 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:03,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:03,871 INFO L87 Difference]: Start difference. First operand 521 states and 760 transitions. cyclomatic complexity: 241 Second operand 3 states. [2019-12-07 12:55:03,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:03,908 INFO L93 Difference]: Finished difference Result 925 states and 1337 transitions. [2019-12-07 12:55:03,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:03,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 925 states and 1337 transitions. [2019-12-07 12:55:03,922 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 868 [2019-12-07 12:55:03,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 925 states to 925 states and 1337 transitions. [2019-12-07 12:55:03,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 925 [2019-12-07 12:55:03,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 925 [2019-12-07 12:55:03,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 925 states and 1337 transitions. [2019-12-07 12:55:03,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:03,931 INFO L688 BuchiCegarLoop]: Abstraction has 925 states and 1337 transitions. [2019-12-07 12:55:03,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 925 states and 1337 transitions. [2019-12-07 12:55:03,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 925 to 921. [2019-12-07 12:55:03,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 921 states. [2019-12-07 12:55:03,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 921 states to 921 states and 1333 transitions. [2019-12-07 12:55:03,948 INFO L711 BuchiCegarLoop]: Abstraction has 921 states and 1333 transitions. [2019-12-07 12:55:03,948 INFO L591 BuchiCegarLoop]: Abstraction has 921 states and 1333 transitions. [2019-12-07 12:55:03,949 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 12:55:03,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 921 states and 1333 transitions. [2019-12-07 12:55:03,953 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 864 [2019-12-07 12:55:03,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:03,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:03,955 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,955 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:03,955 INFO L794 eck$LassoCheckResult]: Stem: 4970#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4780#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4781#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4844#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 4965#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5023#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4937#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4938#L297-1 assume !(0 == ~M_E~0); 4964#L419-1 assume !(0 == ~T1_E~0); 4918#L424-1 assume !(0 == ~T2_E~0); 4919#L429-1 assume !(0 == ~T3_E~0); 4987#L434-1 assume !(0 == ~E_M~0); 4800#L439-1 assume !(0 == ~E_1~0); 4801#L444-1 assume !(0 == ~E_2~0); 4831#L449-1 assume !(0 == ~E_3~0); 5085#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4953#L198 assume !(1 == ~m_pc~0); 4954#L198-2 is_master_triggered_~__retres1~0 := 0; 4955#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4956#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4822#L521 assume !(0 != activate_threads_~tmp~1); 4823#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4828#L217 assume !(1 == ~t1_pc~0); 4835#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 5104#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4838#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4839#L529 assume !(0 != activate_threads_~tmp___0~0); 5061#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5003#L236 assume !(1 == ~t2_pc~0); 5000#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 5001#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4935#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4936#L537 assume !(0 != activate_threads_~tmp___1~0); 5066#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5014#L255 assume 1 == ~t3_pc~0; 5015#L256 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5017#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5018#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4961#L545 assume !(0 != activate_threads_~tmp___2~0); 4962#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 4968#L467-1 assume !(1 == ~T1_E~0); 4798#L472-1 assume !(1 == ~T2_E~0); 4799#L477-1 assume !(1 == ~T3_E~0); 4829#L482-1 assume !(1 == ~E_M~0); 5078#L487-1 assume !(1 == ~E_1~0); 5102#L492-1 assume !(1 == ~E_2~0); 5019#L497-1 assume !(1 == ~E_3~0); 5020#L668-1 [2019-12-07 12:55:03,956 INFO L796 eck$LassoCheckResult]: Loop: 5020#L668-1 assume !false; 5480#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5477#L394 assume !false; 5460#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5279#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5276#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5275#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5273#L347 assume !(0 != eval_~tmp~0); 5005#L409 start_simulation_~kernel_st~0 := 2; 4957#L275-1 start_simulation_~kernel_st~0 := 3; 4958#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5048#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4939#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4940#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4996#L434-3 assume !(0 == ~E_M~0); 4778#L439-3 assume !(0 == ~E_1~0); 4779#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4815#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4854#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4920#L198-15 assume !(1 == ~m_pc~0); 4906#L198-17 is_master_triggered_~__retres1~0 := 0; 4907#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4974#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4812#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4794#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4795#L217-15 assume !(1 == ~t1_pc~0); 4853#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 5082#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4855#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4856#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5030#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4963#L236-15 assume !(1 == ~t2_pc~0); 4951#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 4952#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4988#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4847#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4824#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4825#L255-15 assume 1 == ~t3_pc~0; 5069#L256-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5070#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5072#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5059#L545-15 assume !(0 != activate_threads_~tmp___2~0); 5060#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5004#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4802#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4803#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4833#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5091#L487-3 assume !(1 == ~E_1~0); 5094#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5006#L497-3 assume !(1 == ~E_3~0); 5007#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5012#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4786#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5011#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 4791#L687 assume !(0 == start_simulation_~tmp~3); 4792#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5499#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5497#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5496#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 5495#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5494#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 5492#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5489#L700 assume !(0 != start_simulation_~tmp___0~1); 5020#L668-1 [2019-12-07 12:55:03,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,957 INFO L82 PathProgramCache]: Analyzing trace with hash 209187682, now seen corresponding path program 1 times [2019-12-07 12:55:03,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406898805] [2019-12-07 12:55:03,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:03,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:03,979 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406898805] [2019-12-07 12:55:03,979 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:03,979 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:03,979 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336038702] [2019-12-07 12:55:03,980 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:03,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:03,980 INFO L82 PathProgramCache]: Analyzing trace with hash 1047574969, now seen corresponding path program 1 times [2019-12-07 12:55:03,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:03,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565914613] [2019-12-07 12:55:03,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:03,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,003 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565914613] [2019-12-07 12:55:04,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:04,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8769815] [2019-12-07 12:55:04,004 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,004 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:04,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:04,005 INFO L87 Difference]: Start difference. First operand 921 states and 1333 transitions. cyclomatic complexity: 416 Second operand 3 states. [2019-12-07 12:55:04,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:04,048 INFO L93 Difference]: Finished difference Result 1664 states and 2392 transitions. [2019-12-07 12:55:04,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:04,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1664 states and 2392 transitions. [2019-12-07 12:55:04,059 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1592 [2019-12-07 12:55:04,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1664 states to 1664 states and 2392 transitions. [2019-12-07 12:55:04,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1664 [2019-12-07 12:55:04,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1664 [2019-12-07 12:55:04,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1664 states and 2392 transitions. [2019-12-07 12:55:04,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:04,078 INFO L688 BuchiCegarLoop]: Abstraction has 1664 states and 2392 transitions. [2019-12-07 12:55:04,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1664 states and 2392 transitions. [2019-12-07 12:55:04,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1664 to 1656. [2019-12-07 12:55:04,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1656 states. [2019-12-07 12:55:04,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1656 states to 1656 states and 2384 transitions. [2019-12-07 12:55:04,100 INFO L711 BuchiCegarLoop]: Abstraction has 1656 states and 2384 transitions. [2019-12-07 12:55:04,100 INFO L591 BuchiCegarLoop]: Abstraction has 1656 states and 2384 transitions. [2019-12-07 12:55:04,100 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 12:55:04,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1656 states and 2384 transitions. [2019-12-07 12:55:04,105 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1584 [2019-12-07 12:55:04,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:04,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:04,107 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,107 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,107 INFO L794 eck$LassoCheckResult]: Stem: 7569#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7370#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7371#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7439#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 7565#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7627#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7535#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7536#L297-1 assume !(0 == ~M_E~0); 7564#L419-1 assume !(0 == ~T1_E~0); 7514#L424-1 assume !(0 == ~T2_E~0); 7515#L429-1 assume !(0 == ~T3_E~0); 7586#L434-1 assume !(0 == ~E_M~0); 7391#L439-1 assume !(0 == ~E_1~0); 7392#L444-1 assume !(0 == ~E_2~0); 7425#L449-1 assume !(0 == ~E_3~0); 7693#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7552#L198 assume !(1 == ~m_pc~0); 7553#L198-2 is_master_triggered_~__retres1~0 := 0; 7554#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7555#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7416#L521 assume !(0 != activate_threads_~tmp~1); 7417#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7420#L217 assume !(1 == ~t1_pc~0); 7430#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 7724#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7431#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7432#L529 assume !(0 != activate_threads_~tmp___0~0); 7668#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7609#L236 assume !(1 == ~t2_pc~0); 7607#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 7608#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7527#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7528#L537 assume !(0 != activate_threads_~tmp___1~0); 7670#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7620#L255 assume !(1 == ~t3_pc~0); 7621#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 7622#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7623#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7556#L545 assume !(0 != activate_threads_~tmp___2~0); 7557#L545-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7568#L467-1 assume !(1 == ~T1_E~0); 7387#L472-1 assume !(1 == ~T2_E~0); 7388#L477-1 assume !(1 == ~T3_E~0); 7423#L482-1 assume !(1 == ~E_M~0); 7686#L487-1 assume !(1 == ~E_1~0); 7717#L492-1 assume !(1 == ~E_2~0); 7624#L497-1 assume !(1 == ~E_3~0); 7625#L668-1 [2019-12-07 12:55:04,107 INFO L796 eck$LassoCheckResult]: Loop: 7625#L668-1 assume !false; 8200#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 8198#L394 assume !false; 8196#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8090#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8078#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8073#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8066#L347 assume !(0 != eval_~tmp~0); 8067#L409 start_simulation_~kernel_st~0 := 2; 8631#L275-1 start_simulation_~kernel_st~0 := 3; 8629#L419-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8626#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8619#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8612#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8607#L434-3 assume !(0 == ~E_M~0); 8602#L439-3 assume !(0 == ~E_1~0); 8597#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8590#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8585#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8579#L198-15 assume !(1 == ~m_pc~0); 8575#L198-17 is_master_triggered_~__retres1~0 := 0; 8570#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8565#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8561#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8556#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8552#L217-15 assume !(1 == ~t1_pc~0); 8548#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 8544#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8540#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8536#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8531#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8526#L236-15 assume !(1 == ~t2_pc~0); 8520#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 8514#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8508#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8502#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8457#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8454#L255-15 assume !(1 == ~t3_pc~0); 8452#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 8450#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8448#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8446#L545-15 assume !(0 != activate_threads_~tmp___2~0); 8444#L545-17 assume 1 == ~M_E~0;~M_E~0 := 2; 8441#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8439#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8436#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8427#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8421#L487-3 assume !(1 == ~E_1~0); 8415#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8408#L497-3 assume !(1 == ~E_3~0); 8405#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8379#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8371#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8365#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 8358#L687 assume !(0 == start_simulation_~tmp~3); 8353#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8294#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8289#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8287#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 8286#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8271#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 8268#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 8265#L700 assume !(0 != start_simulation_~tmp___0~1); 7625#L668-1 [2019-12-07 12:55:04,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,108 INFO L82 PathProgramCache]: Analyzing trace with hash -1070137053, now seen corresponding path program 1 times [2019-12-07 12:55:04,108 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,108 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528843053] [2019-12-07 12:55:04,108 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,131 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528843053] [2019-12-07 12:55:04,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,132 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:04,132 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694959636] [2019-12-07 12:55:04,132 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:04,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,133 INFO L82 PathProgramCache]: Analyzing trace with hash 1686359448, now seen corresponding path program 1 times [2019-12-07 12:55:04,133 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,133 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756454526] [2019-12-07 12:55:04,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,160 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756454526] [2019-12-07 12:55:04,160 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,160 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:04,160 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067006977] [2019-12-07 12:55:04,161 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,161 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:04,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:04,161 INFO L87 Difference]: Start difference. First operand 1656 states and 2384 transitions. cyclomatic complexity: 736 Second operand 3 states. [2019-12-07 12:55:04,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:04,192 INFO L93 Difference]: Finished difference Result 3044 states and 4390 transitions. [2019-12-07 12:55:04,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:04,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3044 states and 4390 transitions. [2019-12-07 12:55:04,212 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2948 [2019-12-07 12:55:04,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3044 states to 3044 states and 4390 transitions. [2019-12-07 12:55:04,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3044 [2019-12-07 12:55:04,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3044 [2019-12-07 12:55:04,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3044 states and 4390 transitions. [2019-12-07 12:55:04,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:04,237 INFO L688 BuchiCegarLoop]: Abstraction has 3044 states and 4390 transitions. [2019-12-07 12:55:04,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3044 states and 4390 transitions. [2019-12-07 12:55:04,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3044 to 3044. [2019-12-07 12:55:04,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3044 states. [2019-12-07 12:55:04,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3044 states to 3044 states and 4390 transitions. [2019-12-07 12:55:04,274 INFO L711 BuchiCegarLoop]: Abstraction has 3044 states and 4390 transitions. [2019-12-07 12:55:04,274 INFO L591 BuchiCegarLoop]: Abstraction has 3044 states and 4390 transitions. [2019-12-07 12:55:04,274 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 12:55:04,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3044 states and 4390 transitions. [2019-12-07 12:55:04,284 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2948 [2019-12-07 12:55:04,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:04,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:04,284 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,285 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,285 INFO L794 eck$LassoCheckResult]: Stem: 12270#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12077#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12078#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12144#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 12266#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12323#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12237#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12238#L297-1 assume !(0 == ~M_E~0); 12265#L419-1 assume !(0 == ~T1_E~0); 12215#L424-1 assume !(0 == ~T2_E~0); 12216#L429-1 assume !(0 == ~T3_E~0); 12287#L434-1 assume !(0 == ~E_M~0); 12098#L439-1 assume !(0 == ~E_1~0); 12099#L444-1 assume !(0 == ~E_2~0); 12131#L449-1 assume !(0 == ~E_3~0); 12386#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12254#L198 assume !(1 == ~m_pc~0); 12255#L198-2 is_master_triggered_~__retres1~0 := 0; 12256#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12257#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12122#L521 assume !(0 != activate_threads_~tmp~1); 12123#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12126#L217 assume !(1 == ~t1_pc~0); 12135#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 12415#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12136#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12137#L529 assume !(0 != activate_threads_~tmp___0~0); 12362#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12305#L236 assume !(1 == ~t2_pc~0); 12303#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 12304#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12229#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12230#L537 assume !(0 != activate_threads_~tmp___1~0); 12364#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12316#L255 assume !(1 == ~t3_pc~0); 12317#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 12318#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12319#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12258#L545 assume !(0 != activate_threads_~tmp___2~0); 12259#L545-2 assume !(1 == ~M_E~0); 12269#L467-1 assume !(1 == ~T1_E~0); 12094#L472-1 assume !(1 == ~T2_E~0); 12095#L477-1 assume !(1 == ~T3_E~0); 12129#L482-1 assume !(1 == ~E_M~0); 12379#L487-1 assume !(1 == ~E_1~0); 12411#L492-1 assume !(1 == ~E_2~0); 12320#L497-1 assume !(1 == ~E_3~0); 12321#L668-1 [2019-12-07 12:55:04,285 INFO L796 eck$LassoCheckResult]: Loop: 12321#L668-1 assume !false; 13598#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 13485#L394 assume !false; 13586#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13580#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13576#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13573#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13569#L347 assume !(0 != eval_~tmp~0); 13567#L409 start_simulation_~kernel_st~0 := 2; 13561#L275-1 start_simulation_~kernel_st~0 := 3; 13555#L419-2 assume !(0 == ~M_E~0); 13554#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13553#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13552#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13550#L434-3 assume !(0 == ~E_M~0); 13548#L439-3 assume !(0 == ~E_1~0); 13546#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13544#L449-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13541#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13539#L198-15 assume !(1 == ~m_pc~0); 13537#L198-17 is_master_triggered_~__retres1~0 := 0; 13535#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13533#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13531#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13529#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13489#L217-15 assume !(1 == ~t1_pc~0); 13481#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 13474#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13470#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13453#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13452#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13450#L236-15 assume !(1 == ~t2_pc~0); 13445#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 13442#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13439#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13435#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13432#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13429#L255-15 assume !(1 == ~t3_pc~0); 13426#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 13424#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13421#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13417#L545-15 assume !(0 != activate_threads_~tmp___2~0); 13413#L545-17 assume !(1 == ~M_E~0); 13301#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13406#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13402#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13398#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13394#L487-3 assume !(1 == ~E_1~0); 13390#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13386#L497-3 assume !(1 == ~E_3~0); 13383#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13379#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13374#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13370#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 13365#L687 assume !(0 == start_simulation_~tmp~3); 13366#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13626#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13617#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13614#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 13613#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13612#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 13610#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 13608#L700 assume !(0 != start_simulation_~tmp___0~1); 12321#L668-1 [2019-12-07 12:55:04,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,285 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2019-12-07 12:55:04,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840674531] [2019-12-07 12:55:04,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,312 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:04,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1742005348, now seen corresponding path program 1 times [2019-12-07 12:55:04,312 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,312 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888447208] [2019-12-07 12:55:04,312 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888447208] [2019-12-07 12:55:04,329 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,329 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:04,329 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286040951] [2019-12-07 12:55:04,330 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,330 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:04,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:04,330 INFO L87 Difference]: Start difference. First operand 3044 states and 4390 transitions. cyclomatic complexity: 1354 Second operand 3 states. [2019-12-07 12:55:04,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:04,378 INFO L93 Difference]: Finished difference Result 4607 states and 6587 transitions. [2019-12-07 12:55:04,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:04,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4607 states and 6587 transitions. [2019-12-07 12:55:04,397 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4462 [2019-12-07 12:55:04,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4607 states to 4607 states and 6587 transitions. [2019-12-07 12:55:04,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4607 [2019-12-07 12:55:04,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4607 [2019-12-07 12:55:04,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4607 states and 6587 transitions. [2019-12-07 12:55:04,429 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:04,430 INFO L688 BuchiCegarLoop]: Abstraction has 4607 states and 6587 transitions. [2019-12-07 12:55:04,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4607 states and 6587 transitions. [2019-12-07 12:55:04,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4607 to 4603. [2019-12-07 12:55:04,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4603 states. [2019-12-07 12:55:04,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4603 states to 4603 states and 6583 transitions. [2019-12-07 12:55:04,488 INFO L711 BuchiCegarLoop]: Abstraction has 4603 states and 6583 transitions. [2019-12-07 12:55:04,488 INFO L591 BuchiCegarLoop]: Abstraction has 4603 states and 6583 transitions. [2019-12-07 12:55:04,488 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 12:55:04,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4603 states and 6583 transitions. [2019-12-07 12:55:04,499 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4458 [2019-12-07 12:55:04,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:04,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:04,500 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,500 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,500 INFO L794 eck$LassoCheckResult]: Stem: 19928#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 19736#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 19737#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19802#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 19922#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19990#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19893#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19894#L297-1 assume !(0 == ~M_E~0); 19921#L419-1 assume !(0 == ~T1_E~0); 19874#L424-1 assume !(0 == ~T2_E~0); 19875#L429-1 assume !(0 == ~T3_E~0); 19948#L434-1 assume !(0 == ~E_M~0); 19755#L439-1 assume !(0 == ~E_1~0); 19756#L444-1 assume !(0 == ~E_2~0); 19788#L449-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20062#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19910#L198 assume !(1 == ~m_pc~0); 19911#L198-2 is_master_triggered_~__retres1~0 := 0; 19912#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19913#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19778#L521 assume !(0 != activate_threads_~tmp~1); 19779#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20097#L217 assume !(1 == ~t1_pc~0); 19793#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 20098#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20099#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20032#L529 assume !(0 != activate_threads_~tmp___0~0); 20033#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19966#L236 assume !(1 == ~t2_pc~0); 19967#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 19968#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19969#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20043#L537 assume !(0 != activate_threads_~tmp___1~0); 20044#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19983#L255 assume !(1 == ~t3_pc~0); 19984#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 19985#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19986#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 19918#L545 assume !(0 != activate_threads_~tmp___2~0); 19919#L545-2 assume !(1 == ~M_E~0); 19965#L467-1 assume !(1 == ~T1_E~0); 19753#L472-1 assume !(1 == ~T2_E~0); 19754#L477-1 assume !(1 == ~T3_E~0); 19786#L482-1 assume !(1 == ~E_M~0); 20082#L487-1 assume !(1 == ~E_1~0); 20083#L492-1 assume !(1 == ~E_2~0); 19987#L497-1 assume 1 == ~E_3~0;~E_3~0 := 2; 19988#L668-1 [2019-12-07 12:55:04,501 INFO L796 eck$LassoCheckResult]: Loop: 19988#L668-1 assume !false; 20717#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 20712#L394 assume !false; 20707#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20701#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20694#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20689#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 20681#L347 assume !(0 != eval_~tmp~0); 20682#L409 start_simulation_~kernel_st~0 := 2; 20901#L275-1 start_simulation_~kernel_st~0 := 3; 20900#L419-2 assume !(0 == ~M_E~0); 20899#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20898#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20897#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20896#L434-3 assume !(0 == ~E_M~0); 20895#L439-3 assume !(0 == ~E_1~0); 20894#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20893#L449-3 assume !(0 == ~E_3~0); 20891#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20889#L198-15 assume !(1 == ~m_pc~0); 20887#L198-17 is_master_triggered_~__retres1~0 := 0; 20885#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20883#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20881#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20879#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20876#L217-15 assume !(1 == ~t1_pc~0); 20873#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 20871#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20869#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20866#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20863#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20860#L236-15 assume !(1 == ~t2_pc~0); 20857#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 20854#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20851#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20848#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20845#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20842#L255-15 assume !(1 == ~t3_pc~0); 20839#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 20836#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20833#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20830#L545-15 assume !(0 != activate_threads_~tmp___2~0); 20825#L545-17 assume !(1 == ~M_E~0); 20677#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20821#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20818#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20815#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20812#L487-3 assume !(1 == ~E_1~0); 20810#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20808#L497-3 assume !(1 == ~E_3~0); 20805#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20797#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20791#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20787#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 20782#L687 assume !(0 == start_simulation_~tmp~3); 20780#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20771#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20768#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20749#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 20743#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20738#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 20733#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 20728#L700 assume !(0 != start_simulation_~tmp___0~1); 19988#L668-1 [2019-12-07 12:55:04,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,501 INFO L82 PathProgramCache]: Analyzing trace with hash -1807097123, now seen corresponding path program 1 times [2019-12-07 12:55:04,501 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,501 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972610348] [2019-12-07 12:55:04,501 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,514 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972610348] [2019-12-07 12:55:04,514 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,514 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:04,514 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317622972] [2019-12-07 12:55:04,514 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:04,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,515 INFO L82 PathProgramCache]: Analyzing trace with hash 186267354, now seen corresponding path program 1 times [2019-12-07 12:55:04,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233141860] [2019-12-07 12:55:04,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,539 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233141860] [2019-12-07 12:55:04,539 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,540 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:55:04,540 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534576465] [2019-12-07 12:55:04,540 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,540 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,540 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:04,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:04,541 INFO L87 Difference]: Start difference. First operand 4603 states and 6583 transitions. cyclomatic complexity: 1988 Second operand 3 states. [2019-12-07 12:55:04,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:04,575 INFO L93 Difference]: Finished difference Result 3044 states and 4304 transitions. [2019-12-07 12:55:04,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:04,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3044 states and 4304 transitions. [2019-12-07 12:55:04,585 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2948 [2019-12-07 12:55:04,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3044 states to 3044 states and 4304 transitions. [2019-12-07 12:55:04,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3044 [2019-12-07 12:55:04,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3044 [2019-12-07 12:55:04,604 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3044 states and 4304 transitions. [2019-12-07 12:55:04,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:04,607 INFO L688 BuchiCegarLoop]: Abstraction has 3044 states and 4304 transitions. [2019-12-07 12:55:04,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3044 states and 4304 transitions. [2019-12-07 12:55:04,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3044 to 3044. [2019-12-07 12:55:04,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3044 states. [2019-12-07 12:55:04,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3044 states to 3044 states and 4304 transitions. [2019-12-07 12:55:04,643 INFO L711 BuchiCegarLoop]: Abstraction has 3044 states and 4304 transitions. [2019-12-07 12:55:04,643 INFO L591 BuchiCegarLoop]: Abstraction has 3044 states and 4304 transitions. [2019-12-07 12:55:04,643 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 12:55:04,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3044 states and 4304 transitions. [2019-12-07 12:55:04,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2948 [2019-12-07 12:55:04,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:04,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:04,650 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,650 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,650 INFO L794 eck$LassoCheckResult]: Stem: 27584#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 27392#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27393#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27457#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 27579#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27633#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27551#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27552#L297-1 assume !(0 == ~M_E~0); 27578#L419-1 assume !(0 == ~T1_E~0); 27530#L424-1 assume !(0 == ~T2_E~0); 27531#L429-1 assume !(0 == ~T3_E~0); 27599#L434-1 assume !(0 == ~E_M~0); 27412#L439-1 assume !(0 == ~E_1~0); 27413#L444-1 assume !(0 == ~E_2~0); 27444#L449-1 assume !(0 == ~E_3~0); 27692#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27567#L198 assume !(1 == ~m_pc~0); 27568#L198-2 is_master_triggered_~__retres1~0 := 0; 27569#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27570#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27435#L521 assume !(0 != activate_threads_~tmp~1); 27436#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27441#L217 assume !(1 == ~t1_pc~0); 27448#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 27717#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27451#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27452#L529 assume !(0 != activate_threads_~tmp___0~0); 27670#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27615#L236 assume !(1 == ~t2_pc~0); 27612#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 27613#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27549#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27550#L537 assume !(0 != activate_threads_~tmp___1~0); 27676#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27626#L255 assume !(1 == ~t3_pc~0); 27627#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 27628#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27629#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 27575#L545 assume !(0 != activate_threads_~tmp___2~0); 27576#L545-2 assume !(1 == ~M_E~0); 27582#L467-1 assume !(1 == ~T1_E~0); 27410#L472-1 assume !(1 == ~T2_E~0); 27411#L477-1 assume !(1 == ~T3_E~0); 27442#L482-1 assume !(1 == ~E_M~0); 27687#L487-1 assume !(1 == ~E_1~0); 27709#L492-1 assume !(1 == ~E_2~0); 27630#L497-1 assume !(1 == ~E_3~0); 27631#L668-1 [2019-12-07 12:55:04,650 INFO L796 eck$LassoCheckResult]: Loop: 27631#L668-1 assume !false; 29618#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 29327#L394 assume !false; 29615#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 29611#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 29607#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29605#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 29603#L347 assume !(0 != eval_~tmp~0); 29604#L409 start_simulation_~kernel_st~0 := 2; 30194#L275-1 start_simulation_~kernel_st~0 := 3; 30193#L419-2 assume !(0 == ~M_E~0); 30192#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30191#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30190#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30189#L434-3 assume !(0 == ~E_M~0); 30188#L439-3 assume !(0 == ~E_1~0); 30187#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30186#L449-3 assume !(0 == ~E_3~0); 30185#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30184#L198-15 assume !(1 == ~m_pc~0); 30183#L198-17 is_master_triggered_~__retres1~0 := 0; 30181#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30179#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30177#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30175#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30173#L217-15 assume !(1 == ~t1_pc~0); 30170#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 30168#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30167#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30162#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30160#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30158#L236-15 assume !(1 == ~t2_pc~0); 30157#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 30156#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30155#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30153#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30151#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30149#L255-15 assume !(1 == ~t3_pc~0); 30147#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 30145#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30142#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30140#L545-15 assume !(0 != activate_threads_~tmp___2~0); 30139#L545-17 assume !(1 == ~M_E~0); 29469#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30134#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30132#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30130#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30128#L487-3 assume !(1 == ~E_1~0); 30126#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30124#L497-3 assume !(1 == ~E_3~0); 30123#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30121#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30098#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27704#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 27403#L687 assume !(0 == start_simulation_~tmp~3); 27404#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 29634#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 29631#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29629#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 29627#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29625#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 29623#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 29621#L700 assume !(0 != start_simulation_~tmp___0~1); 27631#L668-1 [2019-12-07 12:55:04,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,650 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2019-12-07 12:55:04,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598161862] [2019-12-07 12:55:04,651 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,662 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:04,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,663 INFO L82 PathProgramCache]: Analyzing trace with hash 186267354, now seen corresponding path program 2 times [2019-12-07 12:55:04,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,663 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928189654] [2019-12-07 12:55:04,663 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,682 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928189654] [2019-12-07 12:55:04,682 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,682 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:55:04,682 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829942974] [2019-12-07 12:55:04,682 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,682 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:55:04,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:55:04,682 INFO L87 Difference]: Start difference. First operand 3044 states and 4304 transitions. cyclomatic complexity: 1268 Second operand 5 states. [2019-12-07 12:55:04,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:04,766 INFO L93 Difference]: Finished difference Result 5280 states and 7344 transitions. [2019-12-07 12:55:04,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:55:04,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5280 states and 7344 transitions. [2019-12-07 12:55:04,780 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5136 [2019-12-07 12:55:04,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5280 states to 5280 states and 7344 transitions. [2019-12-07 12:55:04,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5280 [2019-12-07 12:55:04,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5280 [2019-12-07 12:55:04,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5280 states and 7344 transitions. [2019-12-07 12:55:04,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:04,810 INFO L688 BuchiCegarLoop]: Abstraction has 5280 states and 7344 transitions. [2019-12-07 12:55:04,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5280 states and 7344 transitions. [2019-12-07 12:55:04,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5280 to 3092. [2019-12-07 12:55:04,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3092 states. [2019-12-07 12:55:04,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3092 states to 3092 states and 4352 transitions. [2019-12-07 12:55:04,852 INFO L711 BuchiCegarLoop]: Abstraction has 3092 states and 4352 transitions. [2019-12-07 12:55:04,852 INFO L591 BuchiCegarLoop]: Abstraction has 3092 states and 4352 transitions. [2019-12-07 12:55:04,852 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 12:55:04,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3092 states and 4352 transitions. [2019-12-07 12:55:04,858 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2996 [2019-12-07 12:55:04,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:04,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:04,859 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,859 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:04,859 INFO L794 eck$LassoCheckResult]: Stem: 35930#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 35732#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 35733#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35799#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 35925#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35989#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35894#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35895#L297-1 assume !(0 == ~M_E~0); 35924#L419-1 assume !(0 == ~T1_E~0); 35875#L424-1 assume !(0 == ~T2_E~0); 35876#L429-1 assume !(0 == ~T3_E~0); 35946#L434-1 assume !(0 == ~E_M~0); 35751#L439-1 assume !(0 == ~E_1~0); 35752#L444-1 assume !(0 == ~E_2~0); 35785#L449-1 assume !(0 == ~E_3~0); 36060#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35911#L198 assume !(1 == ~m_pc~0); 35912#L198-2 is_master_triggered_~__retres1~0 := 0; 35913#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35914#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 35776#L521 assume !(0 != activate_threads_~tmp~1); 35777#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35782#L217 assume !(1 == ~t1_pc~0); 35790#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 36098#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35793#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 35794#L529 assume !(0 != activate_threads_~tmp___0~0); 36038#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35967#L236 assume !(1 == ~t2_pc~0); 35963#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 35964#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35892#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35893#L537 assume !(0 != activate_threads_~tmp___1~0); 36043#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35982#L255 assume !(1 == ~t3_pc~0); 35983#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 35984#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35985#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35919#L545 assume !(0 != activate_threads_~tmp___2~0); 35920#L545-2 assume !(1 == ~M_E~0); 35928#L467-1 assume !(1 == ~T1_E~0); 35749#L472-1 assume !(1 == ~T2_E~0); 35750#L477-1 assume !(1 == ~T3_E~0); 35783#L482-1 assume !(1 == ~E_M~0); 36054#L487-1 assume !(1 == ~E_1~0); 36082#L492-1 assume !(1 == ~E_2~0); 35986#L497-1 assume !(1 == ~E_3~0); 35987#L668-1 [2019-12-07 12:55:04,859 INFO L796 eck$LassoCheckResult]: Loop: 35987#L668-1 assume !false; 37198#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 37197#L394 assume !false; 37196#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37192#L310 assume !(0 == ~m_st~0); 37193#L314 assume !(0 == ~t1_st~0); 37189#L318 assume !(0 == ~t2_st~0); 37190#L322 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 37191#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 36983#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 36984#L347 assume !(0 != eval_~tmp~0); 37321#L409 start_simulation_~kernel_st~0 := 2; 37319#L275-1 start_simulation_~kernel_st~0 := 3; 37317#L419-2 assume !(0 == ~M_E~0); 37315#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37313#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37311#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37309#L434-3 assume !(0 == ~E_M~0); 37307#L439-3 assume !(0 == ~E_1~0); 37305#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37303#L449-3 assume !(0 == ~E_3~0); 37301#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37299#L198-15 assume !(1 == ~m_pc~0); 37297#L198-17 is_master_triggered_~__retres1~0 := 0; 37295#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37293#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 37291#L521-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 37289#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37287#L217-15 assume !(1 == ~t1_pc~0); 37283#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 37281#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37279#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 37277#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 37275#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37273#L236-15 assume !(1 == ~t2_pc~0); 37271#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 37269#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37267#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 37265#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 37263#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37261#L255-15 assume !(1 == ~t3_pc~0); 37259#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 37257#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37255#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 37253#L545-15 assume !(0 != activate_threads_~tmp___2~0); 37251#L545-17 assume !(1 == ~M_E~0); 37248#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37247#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37246#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37245#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37244#L487-3 assume !(1 == ~E_1~0); 37243#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37242#L497-3 assume !(1 == ~E_3~0); 37241#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37239#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 37234#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37231#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 37227#L687 assume !(0 == start_simulation_~tmp~3); 37225#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37222#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 37219#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37217#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 37215#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37211#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 37209#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 37205#L700 assume !(0 != start_simulation_~tmp___0~1); 35987#L668-1 [2019-12-07 12:55:04,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2019-12-07 12:55:04,860 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,860 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332589150] [2019-12-07 12:55:04,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:04,871 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:04,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:04,872 INFO L82 PathProgramCache]: Analyzing trace with hash 336075544, now seen corresponding path program 1 times [2019-12-07 12:55:04,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:04,872 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59311248] [2019-12-07 12:55:04,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:04,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:04,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:04,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59311248] [2019-12-07 12:55:04,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:04,910 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:55:04,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28093025] [2019-12-07 12:55:04,910 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:04,910 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:04,910 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:55:04,910 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:55:04,911 INFO L87 Difference]: Start difference. First operand 3092 states and 4352 transitions. cyclomatic complexity: 1268 Second operand 5 states. [2019-12-07 12:55:05,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:05,024 INFO L93 Difference]: Finished difference Result 6088 states and 8487 transitions. [2019-12-07 12:55:05,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:55:05,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6088 states and 8487 transitions. [2019-12-07 12:55:05,041 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5960 [2019-12-07 12:55:05,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6088 states to 6088 states and 8487 transitions. [2019-12-07 12:55:05,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6088 [2019-12-07 12:55:05,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6088 [2019-12-07 12:55:05,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6088 states and 8487 transitions. [2019-12-07 12:55:05,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:05,070 INFO L688 BuchiCegarLoop]: Abstraction has 6088 states and 8487 transitions. [2019-12-07 12:55:05,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6088 states and 8487 transitions. [2019-12-07 12:55:05,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6088 to 3200. [2019-12-07 12:55:05,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3200 states. [2019-12-07 12:55:05,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3200 states to 3200 states and 4431 transitions. [2019-12-07 12:55:05,117 INFO L711 BuchiCegarLoop]: Abstraction has 3200 states and 4431 transitions. [2019-12-07 12:55:05,117 INFO L591 BuchiCegarLoop]: Abstraction has 3200 states and 4431 transitions. [2019-12-07 12:55:05,117 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 12:55:05,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3200 states and 4431 transitions. [2019-12-07 12:55:05,123 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3104 [2019-12-07 12:55:05,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:05,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:05,124 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,124 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,124 INFO L794 eck$LassoCheckResult]: Stem: 45126#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 44925#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44926#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44992#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 45119#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45184#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45091#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45092#L297-1 assume !(0 == ~M_E~0); 45118#L419-1 assume !(0 == ~T1_E~0); 45069#L424-1 assume !(0 == ~T2_E~0); 45070#L429-1 assume !(0 == ~T3_E~0); 45145#L434-1 assume !(0 == ~E_M~0); 44945#L439-1 assume !(0 == ~E_1~0); 44946#L444-1 assume !(0 == ~E_2~0); 44979#L449-1 assume !(0 == ~E_3~0); 45264#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45106#L198 assume !(1 == ~m_pc~0); 45107#L198-2 is_master_triggered_~__retres1~0 := 0; 45108#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45109#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 44969#L521 assume !(0 != activate_threads_~tmp~1); 44970#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44975#L217 assume !(1 == ~t1_pc~0); 44983#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 45299#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44986#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 44987#L529 assume !(0 != activate_threads_~tmp___0~0); 45240#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45163#L236 assume !(1 == ~t2_pc~0); 45160#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 45161#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45089#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 45090#L537 assume !(0 != activate_threads_~tmp___1~0); 45245#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45176#L255 assume !(1 == ~t3_pc~0); 45177#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 45178#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45179#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45114#L545 assume !(0 != activate_threads_~tmp___2~0); 45115#L545-2 assume !(1 == ~M_E~0); 45122#L467-1 assume !(1 == ~T1_E~0); 44943#L472-1 assume !(1 == ~T2_E~0); 44944#L477-1 assume !(1 == ~T3_E~0); 44976#L482-1 assume !(1 == ~E_M~0); 45258#L487-1 assume !(1 == ~E_1~0); 45289#L492-1 assume !(1 == ~E_2~0); 45180#L497-1 assume !(1 == ~E_3~0); 45181#L668-1 [2019-12-07 12:55:05,124 INFO L796 eck$LassoCheckResult]: Loop: 45181#L668-1 assume !false; 45986#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 45985#L394 assume !false; 45984#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45982#L310 assume !(0 == ~m_st~0); 45983#L314 assume !(0 == ~t1_st~0); 45981#L318 assume !(0 == ~t2_st~0); 45980#L322 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 45979#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 45814#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 45815#L347 assume !(0 != eval_~tmp~0); 45978#L409 start_simulation_~kernel_st~0 := 2; 45977#L275-1 start_simulation_~kernel_st~0 := 3; 45976#L419-2 assume !(0 == ~M_E~0); 45975#L419-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45974#L424-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45973#L429-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45972#L434-3 assume !(0 == ~E_M~0); 45971#L439-3 assume !(0 == ~E_1~0); 45970#L444-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45969#L449-3 assume !(0 == ~E_3~0); 45968#L454-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45967#L198-15 assume !(1 == ~m_pc~0); 45966#L198-17 is_master_triggered_~__retres1~0 := 0; 45965#L209-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45964#L210-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 45963#L521-15 assume !(0 != activate_threads_~tmp~1); 45962#L521-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45961#L217-15 assume !(1 == ~t1_pc~0); 45959#L217-17 is_transmit1_triggered_~__retres1~1 := 0; 45958#L228-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45957#L229-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 45956#L529-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45955#L529-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45954#L236-15 assume !(1 == ~t2_pc~0); 45953#L236-17 is_transmit2_triggered_~__retres1~2 := 0; 45952#L247-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45951#L248-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 45950#L537-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45949#L537-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45948#L255-15 assume !(1 == ~t3_pc~0); 45947#L255-17 is_transmit3_triggered_~__retres1~3 := 0; 45946#L266-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45945#L267-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45943#L545-15 assume !(0 != activate_threads_~tmp___2~0); 45941#L545-17 assume !(1 == ~M_E~0); 45872#L467-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45938#L472-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45936#L477-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45934#L482-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45932#L487-3 assume !(1 == ~E_1~0); 45930#L492-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45928#L497-3 assume !(1 == ~E_3~0); 45926#L502-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45923#L310-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45919#L332-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 45917#L333-1 start_simulation_#t~ret11 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 45914#L687 assume !(0 == start_simulation_~tmp~3); 45915#L687-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret10, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45996#L310-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 45994#L332-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 45993#L333-2 stop_simulation_#t~ret10 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret10;havoc stop_simulation_#t~ret10; 45992#L642 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45991#L649 stop_simulation_#res := stop_simulation_~__retres2~0; 45990#L650 start_simulation_#t~ret12 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 45989#L700 assume !(0 != start_simulation_~tmp___0~1); 45181#L668-1 [2019-12-07 12:55:05,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2019-12-07 12:55:05,125 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,125 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715149393] [2019-12-07 12:55:05,125 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,136 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,136 INFO L82 PathProgramCache]: Analyzing trace with hash -1035731754, now seen corresponding path program 1 times [2019-12-07 12:55:05,136 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,136 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205115946] [2019-12-07 12:55:05,137 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:05,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:05,153 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205115946] [2019-12-07 12:55:05,153 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:05,153 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:05,153 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541814829] [2019-12-07 12:55:05,154 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:55:05,154 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:05,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:05,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:05,154 INFO L87 Difference]: Start difference. First operand 3200 states and 4431 transitions. cyclomatic complexity: 1239 Second operand 3 states. [2019-12-07 12:55:05,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:05,195 INFO L93 Difference]: Finished difference Result 4876 states and 6630 transitions. [2019-12-07 12:55:05,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:05,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4876 states and 6630 transitions. [2019-12-07 12:55:05,215 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4762 [2019-12-07 12:55:05,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4876 states to 4876 states and 6630 transitions. [2019-12-07 12:55:05,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4876 [2019-12-07 12:55:05,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4876 [2019-12-07 12:55:05,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4876 states and 6630 transitions. [2019-12-07 12:55:05,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:05,232 INFO L688 BuchiCegarLoop]: Abstraction has 4876 states and 6630 transitions. [2019-12-07 12:55:05,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4876 states and 6630 transitions. [2019-12-07 12:55:05,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4876 to 4708. [2019-12-07 12:55:05,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4708 states. [2019-12-07 12:55:05,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4708 states to 4708 states and 6410 transitions. [2019-12-07 12:55:05,274 INFO L711 BuchiCegarLoop]: Abstraction has 4708 states and 6410 transitions. [2019-12-07 12:55:05,274 INFO L591 BuchiCegarLoop]: Abstraction has 4708 states and 6410 transitions. [2019-12-07 12:55:05,275 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 12:55:05,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4708 states and 6410 transitions. [2019-12-07 12:55:05,285 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4594 [2019-12-07 12:55:05,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:05,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:05,286 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,286 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,286 INFO L794 eck$LassoCheckResult]: Stem: 53200#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 53007#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 53008#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53073#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 53195#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53259#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53168#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53169#L297-1 assume !(0 == ~M_E~0); 53194#L419-1 assume !(0 == ~T1_E~0); 53149#L424-1 assume !(0 == ~T2_E~0); 53150#L429-1 assume !(0 == ~T3_E~0); 53221#L434-1 assume !(0 == ~E_M~0); 53027#L439-1 assume !(0 == ~E_1~0); 53028#L444-1 assume !(0 == ~E_2~0); 53059#L449-1 assume !(0 == ~E_3~0); 53330#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53183#L198 assume !(1 == ~m_pc~0); 53184#L198-2 is_master_triggered_~__retres1~0 := 0; 53185#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53186#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 53050#L521 assume !(0 != activate_threads_~tmp~1); 53051#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53056#L217 assume !(1 == ~t1_pc~0); 53064#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 53367#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53067#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 53068#L529 assume !(0 != activate_threads_~tmp___0~0); 53309#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53238#L236 assume !(1 == ~t2_pc~0); 53236#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 53237#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53166#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53167#L537 assume !(0 != activate_threads_~tmp___1~0); 53313#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53250#L255 assume !(1 == ~t3_pc~0); 53251#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 53252#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53253#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53191#L545 assume !(0 != activate_threads_~tmp___2~0); 53192#L545-2 assume !(1 == ~M_E~0); 53198#L467-1 assume !(1 == ~T1_E~0); 53025#L472-1 assume !(1 == ~T2_E~0); 53026#L477-1 assume !(1 == ~T3_E~0); 53057#L482-1 assume !(1 == ~E_M~0); 53325#L487-1 assume !(1 == ~E_1~0); 53356#L492-1 assume !(1 == ~E_2~0); 53254#L497-1 assume !(1 == ~E_3~0); 53255#L668-1 assume !false; 55794#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 55790#L394 [2019-12-07 12:55:05,286 INFO L796 eck$LassoCheckResult]: Loop: 55790#L394 assume !false; 55788#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 55786#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 55785#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 55784#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 55782#L347 assume 0 != eval_~tmp~0; 55780#L347-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 55777#L355 assume !(0 != eval_~tmp_ndt_1~0); 55778#L352 assume !(0 == ~t1_st~0); 55815#L366 assume !(0 == ~t2_st~0); 55797#L380 assume !(0 == ~t3_st~0); 55790#L394 [2019-12-07 12:55:05,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,286 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2019-12-07 12:55:05,286 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,287 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842263462] [2019-12-07 12:55:05,287 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,298 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,298 INFO L82 PathProgramCache]: Analyzing trace with hash 526302728, now seen corresponding path program 1 times [2019-12-07 12:55:05,298 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,298 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298959858] [2019-12-07 12:55:05,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,303 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,303 INFO L82 PathProgramCache]: Analyzing trace with hash -1009129114, now seen corresponding path program 1 times [2019-12-07 12:55:05,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,304 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103198702] [2019-12-07 12:55:05,304 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:05,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:05,320 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103198702] [2019-12-07 12:55:05,321 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:05,321 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:05,321 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72895043] [2019-12-07 12:55:05,368 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:05,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:05,368 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:05,369 INFO L87 Difference]: Start difference. First operand 4708 states and 6410 transitions. cyclomatic complexity: 1714 Second operand 3 states. [2019-12-07 12:55:05,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:05,409 INFO L93 Difference]: Finished difference Result 8299 states and 11166 transitions. [2019-12-07 12:55:05,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:05,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8299 states and 11166 transitions. [2019-12-07 12:55:05,433 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8076 [2019-12-07 12:55:05,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8299 states to 8299 states and 11166 transitions. [2019-12-07 12:55:05,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8299 [2019-12-07 12:55:05,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8299 [2019-12-07 12:55:05,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8299 states and 11166 transitions. [2019-12-07 12:55:05,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:05,461 INFO L688 BuchiCegarLoop]: Abstraction has 8299 states and 11166 transitions. [2019-12-07 12:55:05,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8299 states and 11166 transitions. [2019-12-07 12:55:05,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8299 to 7851. [2019-12-07 12:55:05,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7851 states. [2019-12-07 12:55:05,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7851 states to 7851 states and 10620 transitions. [2019-12-07 12:55:05,535 INFO L711 BuchiCegarLoop]: Abstraction has 7851 states and 10620 transitions. [2019-12-07 12:55:05,535 INFO L591 BuchiCegarLoop]: Abstraction has 7851 states and 10620 transitions. [2019-12-07 12:55:05,535 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 12:55:05,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7851 states and 10620 transitions. [2019-12-07 12:55:05,557 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7628 [2019-12-07 12:55:05,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:05,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:05,558 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,558 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,558 INFO L794 eck$LassoCheckResult]: Stem: 66217#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 66020#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 66021#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66089#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 66212#L282-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 66275#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68361#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68360#L297-1 assume !(0 == ~M_E~0); 68359#L419-1 assume !(0 == ~T1_E~0); 68358#L424-1 assume !(0 == ~T2_E~0); 68357#L429-1 assume !(0 == ~T3_E~0); 68356#L434-1 assume !(0 == ~E_M~0); 68355#L439-1 assume !(0 == ~E_1~0); 68354#L444-1 assume !(0 == ~E_2~0); 68353#L449-1 assume !(0 == ~E_3~0); 68352#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68351#L198 assume !(1 == ~m_pc~0); 68350#L198-2 is_master_triggered_~__retres1~0 := 0; 68349#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68348#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 68347#L521 assume !(0 != activate_threads_~tmp~1); 68346#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 68344#L217 assume !(1 == ~t1_pc~0); 68343#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 68342#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68341#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 68340#L529 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 66318#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66319#L236 assume !(1 == ~t2_pc~0); 68337#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 68335#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66179#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 66180#L537 assume !(0 != activate_threads_~tmp___1~0); 66336#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66337#L255 assume !(1 == ~t3_pc~0); 66391#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 66392#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66371#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 66372#L545 assume !(0 != activate_threads_~tmp___2~0); 66215#L545-2 assume !(1 == ~M_E~0); 66216#L467-1 assume !(1 == ~T1_E~0); 68292#L472-1 assume !(1 == ~T2_E~0); 68291#L477-1 assume !(1 == ~T3_E~0); 68290#L482-1 assume !(1 == ~E_M~0); 66374#L487-1 assume !(1 == ~E_1~0); 66375#L492-1 assume !(1 == ~E_2~0); 66271#L497-1 assume !(1 == ~E_3~0); 66272#L668-1 assume !false; 68526#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 68494#L394 [2019-12-07 12:55:05,558 INFO L796 eck$LassoCheckResult]: Loop: 68494#L394 assume !false; 68521#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 68518#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 68516#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 68513#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 68510#L347 assume 0 != eval_~tmp~0; 68508#L347-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 68505#L355 assume !(0 != eval_~tmp_ndt_1~0); 68503#L352 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 68191#L369 assume !(0 != eval_~tmp_ndt_2~0); 68499#L366 assume !(0 == ~t2_st~0); 68496#L380 assume !(0 == ~t3_st~0); 68494#L394 [2019-12-07 12:55:05,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,559 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2019-12-07 12:55:05,559 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,559 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882119822] [2019-12-07 12:55:05,559 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:05,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:05,570 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882119822] [2019-12-07 12:55:05,570 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:05,570 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:05,571 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259726024] [2019-12-07 12:55:05,571 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:55:05,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,571 INFO L82 PathProgramCache]: Analyzing trace with hash -868461662, now seen corresponding path program 1 times [2019-12-07 12:55:05,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,572 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107258214] [2019-12-07 12:55:05,572 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,578 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,646 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:05,646 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:05,646 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:05,647 INFO L87 Difference]: Start difference. First operand 7851 states and 10620 transitions. cyclomatic complexity: 2781 Second operand 3 states. [2019-12-07 12:55:05,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:05,660 INFO L93 Difference]: Finished difference Result 7806 states and 10560 transitions. [2019-12-07 12:55:05,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:05,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7806 states and 10560 transitions. [2019-12-07 12:55:05,681 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7628 [2019-12-07 12:55:05,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7806 states to 7806 states and 10560 transitions. [2019-12-07 12:55:05,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7806 [2019-12-07 12:55:05,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7806 [2019-12-07 12:55:05,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7806 states and 10560 transitions. [2019-12-07 12:55:05,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:05,705 INFO L688 BuchiCegarLoop]: Abstraction has 7806 states and 10560 transitions. [2019-12-07 12:55:05,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7806 states and 10560 transitions. [2019-12-07 12:55:05,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7806 to 7806. [2019-12-07 12:55:05,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7806 states. [2019-12-07 12:55:05,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7806 states to 7806 states and 10560 transitions. [2019-12-07 12:55:05,760 INFO L711 BuchiCegarLoop]: Abstraction has 7806 states and 10560 transitions. [2019-12-07 12:55:05,760 INFO L591 BuchiCegarLoop]: Abstraction has 7806 states and 10560 transitions. [2019-12-07 12:55:05,760 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 12:55:05,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7806 states and 10560 transitions. [2019-12-07 12:55:05,775 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7628 [2019-12-07 12:55:05,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:05,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:05,775 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,775 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:05,775 INFO L794 eck$LassoCheckResult]: Stem: 81879#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 81683#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 81684#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81753#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 81875#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81946#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81846#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81847#L297-1 assume !(0 == ~M_E~0); 81874#L419-1 assume !(0 == ~T1_E~0); 81826#L424-1 assume !(0 == ~T2_E~0); 81827#L429-1 assume !(0 == ~T3_E~0); 81897#L434-1 assume !(0 == ~E_M~0); 81704#L439-1 assume !(0 == ~E_1~0); 81705#L444-1 assume !(0 == ~E_2~0); 81740#L449-1 assume !(0 == ~E_3~0); 82040#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81863#L198 assume !(1 == ~m_pc~0); 81864#L198-2 is_master_triggered_~__retres1~0 := 0; 81865#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81866#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 81731#L521 assume !(0 != activate_threads_~tmp~1); 81732#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81735#L217 assume !(1 == ~t1_pc~0); 81744#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 82078#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81745#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 81746#L529 assume !(0 != activate_threads_~tmp___0~0); 82014#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81922#L236 assume !(1 == ~t2_pc~0); 81918#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 81919#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81840#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 81841#L537 assume !(0 != activate_threads_~tmp___1~0); 82017#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81937#L255 assume !(1 == ~t3_pc~0); 81938#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 81939#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81940#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 81867#L545 assume !(0 != activate_threads_~tmp___2~0); 81868#L545-2 assume !(1 == ~M_E~0); 81878#L467-1 assume !(1 == ~T1_E~0); 81700#L472-1 assume !(1 == ~T2_E~0); 81701#L477-1 assume !(1 == ~T3_E~0); 81738#L482-1 assume !(1 == ~E_M~0); 82034#L487-1 assume !(1 == ~E_1~0); 82068#L492-1 assume !(1 == ~E_2~0); 81941#L497-1 assume !(1 == ~E_3~0); 81942#L668-1 assume !false; 83171#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 83168#L394 [2019-12-07 12:55:05,776 INFO L796 eck$LassoCheckResult]: Loop: 83168#L394 assume !false; 83166#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 83163#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 83161#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 83146#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 83139#L347 assume 0 != eval_~tmp~0; 83133#L347-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 83126#L355 assume !(0 != eval_~tmp_ndt_1~0); 83120#L352 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 83103#L369 assume !(0 != eval_~tmp_ndt_2~0); 83095#L366 assume !(0 == ~t2_st~0); 83088#L380 assume !(0 == ~t3_st~0); 83168#L394 [2019-12-07 12:55:05,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,776 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2019-12-07 12:55:05,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,776 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375569482] [2019-12-07 12:55:05,776 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,785 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,786 INFO L82 PathProgramCache]: Analyzing trace with hash -868461662, now seen corresponding path program 2 times [2019-12-07 12:55:05,786 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280666533] [2019-12-07 12:55:05,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:05,790 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:05,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:05,790 INFO L82 PathProgramCache]: Analyzing trace with hash -1222208508, now seen corresponding path program 1 times [2019-12-07 12:55:05,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:05,790 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923185384] [2019-12-07 12:55:05,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:05,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:05,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:05,806 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923185384] [2019-12-07 12:55:05,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:05,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:55:05,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005785022] [2019-12-07 12:55:05,853 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:05,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:05,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:05,854 INFO L87 Difference]: Start difference. First operand 7806 states and 10560 transitions. cyclomatic complexity: 2766 Second operand 3 states. [2019-12-07 12:55:05,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:05,887 INFO L93 Difference]: Finished difference Result 8566 states and 11508 transitions. [2019-12-07 12:55:05,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:05,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8566 states and 11508 transitions. [2019-12-07 12:55:05,905 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8388 [2019-12-07 12:55:05,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8566 states to 8566 states and 11508 transitions. [2019-12-07 12:55:05,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8566 [2019-12-07 12:55:05,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8566 [2019-12-07 12:55:05,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8566 states and 11508 transitions. [2019-12-07 12:55:05,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:05,928 INFO L688 BuchiCegarLoop]: Abstraction has 8566 states and 11508 transitions. [2019-12-07 12:55:05,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8566 states and 11508 transitions. [2019-12-07 12:55:05,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8566 to 8300. [2019-12-07 12:55:05,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8300 states. [2019-12-07 12:55:05,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8300 states to 8300 states and 11200 transitions. [2019-12-07 12:55:05,988 INFO L711 BuchiCegarLoop]: Abstraction has 8300 states and 11200 transitions. [2019-12-07 12:55:05,988 INFO L591 BuchiCegarLoop]: Abstraction has 8300 states and 11200 transitions. [2019-12-07 12:55:05,988 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 12:55:05,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8300 states and 11200 transitions. [2019-12-07 12:55:06,004 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8122 [2019-12-07 12:55:06,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:06,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:06,005 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:06,005 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:06,005 INFO L794 eck$LassoCheckResult]: Stem: 98264#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 98063#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 98064#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98128#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 98260#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98327#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98230#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98231#L297-1 assume !(0 == ~M_E~0); 98259#L419-1 assume !(0 == ~T1_E~0); 98207#L424-1 assume !(0 == ~T2_E~0); 98208#L429-1 assume !(0 == ~T3_E~0); 98279#L434-1 assume !(0 == ~E_M~0); 98081#L439-1 assume !(0 == ~E_1~0); 98082#L444-1 assume !(0 == ~E_2~0); 98115#L449-1 assume !(0 == ~E_3~0); 98389#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98247#L198 assume !(1 == ~m_pc~0); 98248#L198-2 is_master_triggered_~__retres1~0 := 0; 98249#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98250#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 98106#L521 assume !(0 != activate_threads_~tmp~1); 98107#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98110#L217 assume !(1 == ~t1_pc~0); 98119#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 98429#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98120#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 98121#L529 assume !(0 != activate_threads_~tmp___0~0); 98367#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98302#L236 assume !(1 == ~t2_pc~0); 98299#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 98300#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98223#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 98224#L537 assume !(0 != activate_threads_~tmp___1~0); 98370#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98320#L255 assume !(1 == ~t3_pc~0); 98321#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 98322#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98323#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98251#L545 assume !(0 != activate_threads_~tmp___2~0); 98252#L545-2 assume !(1 == ~M_E~0); 98263#L467-1 assume !(1 == ~T1_E~0); 98077#L472-1 assume !(1 == ~T2_E~0); 98078#L477-1 assume !(1 == ~T3_E~0); 98113#L482-1 assume !(1 == ~E_M~0); 98383#L487-1 assume !(1 == ~E_1~0); 98418#L492-1 assume !(1 == ~E_2~0); 98324#L497-1 assume !(1 == ~E_3~0); 98325#L668-1 assume !false; 101213#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 100911#L394 [2019-12-07 12:55:06,006 INFO L796 eck$LassoCheckResult]: Loop: 100911#L394 assume !false; 101208#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 101203#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 101199#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 101195#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 101190#L347 assume 0 != eval_~tmp~0; 101185#L347-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 101179#L355 assume !(0 != eval_~tmp_ndt_1~0); 100977#L352 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 100970#L369 assume !(0 != eval_~tmp_ndt_2~0); 100961#L366 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 100955#L383 assume !(0 != eval_~tmp_ndt_3~0); 100948#L380 assume !(0 == ~t3_st~0); 100911#L394 [2019-12-07 12:55:06,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,006 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2019-12-07 12:55:06,006 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,006 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508699782] [2019-12-07 12:55:06,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,016 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:06,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1152635119, now seen corresponding path program 1 times [2019-12-07 12:55:06,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,016 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748549051] [2019-12-07 12:55:06,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,020 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:06,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,021 INFO L82 PathProgramCache]: Analyzing trace with hash 766114543, now seen corresponding path program 1 times [2019-12-07 12:55:06,021 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,021 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769501655] [2019-12-07 12:55:06,021 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:55:06,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:55:06,035 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769501655] [2019-12-07 12:55:06,035 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:55:06,035 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:55:06,035 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760482717] [2019-12-07 12:55:06,091 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:55:06,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:55:06,092 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:55:06,092 INFO L87 Difference]: Start difference. First operand 8300 states and 11200 transitions. cyclomatic complexity: 2912 Second operand 3 states. [2019-12-07 12:55:06,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:55:06,128 INFO L93 Difference]: Finished difference Result 9270 states and 12404 transitions. [2019-12-07 12:55:06,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:55:06,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9270 states and 12404 transitions. [2019-12-07 12:55:06,150 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9088 [2019-12-07 12:55:06,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9270 states to 9270 states and 12404 transitions. [2019-12-07 12:55:06,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9270 [2019-12-07 12:55:06,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9270 [2019-12-07 12:55:06,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9270 states and 12404 transitions. [2019-12-07 12:55:06,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:55:06,172 INFO L688 BuchiCegarLoop]: Abstraction has 9270 states and 12404 transitions. [2019-12-07 12:55:06,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9270 states and 12404 transitions. [2019-12-07 12:55:06,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9270 to 9162. [2019-12-07 12:55:06,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9162 states. [2019-12-07 12:55:06,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9162 states to 9162 states and 12296 transitions. [2019-12-07 12:55:06,233 INFO L711 BuchiCegarLoop]: Abstraction has 9162 states and 12296 transitions. [2019-12-07 12:55:06,233 INFO L591 BuchiCegarLoop]: Abstraction has 9162 states and 12296 transitions. [2019-12-07 12:55:06,233 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 12:55:06,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9162 states and 12296 transitions. [2019-12-07 12:55:06,250 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8980 [2019-12-07 12:55:06,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:55:06,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:55:06,250 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:06,250 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:55:06,250 INFO L794 eck$LassoCheckResult]: Stem: 115839#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 115641#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 115642#L631 havoc start_simulation_#t~ret11, start_simulation_#t~ret12, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 115706#L275 assume 1 == ~m_i~0;~m_st~0 := 0; 115835#L282-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115900#L287-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115804#L292-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115805#L297-1 assume !(0 == ~M_E~0); 115834#L419-1 assume !(0 == ~T1_E~0); 115786#L424-1 assume !(0 == ~T2_E~0); 115787#L429-1 assume !(0 == ~T3_E~0); 115858#L434-1 assume !(0 == ~E_M~0); 115660#L439-1 assume !(0 == ~E_1~0); 115661#L444-1 assume !(0 == ~E_2~0); 115693#L449-1 assume !(0 == ~E_3~0); 115974#L454-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 115822#L198 assume !(1 == ~m_pc~0); 115823#L198-2 is_master_triggered_~__retres1~0 := 0; 115824#L209 is_master_triggered_#res := is_master_triggered_~__retres1~0; 115825#L210 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 115684#L521 assume !(0 != activate_threads_~tmp~1); 115685#L521-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 115688#L217 assume !(1 == ~t1_pc~0); 115697#L217-2 is_transmit1_triggered_~__retres1~1 := 0; 116012#L228 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 115700#L229 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 115701#L529 assume !(0 != activate_threads_~tmp___0~0); 115950#L529-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 115878#L236 assume !(1 == ~t2_pc~0); 115874#L236-2 is_transmit2_triggered_~__retres1~2 := 0; 115875#L247 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 115798#L248 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 115799#L537 assume !(0 != activate_threads_~tmp___1~0); 115954#L537-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 115893#L255 assume !(1 == ~t3_pc~0); 115894#L255-2 is_transmit3_triggered_~__retres1~3 := 0; 115895#L266 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 115896#L267 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 115826#L545 assume !(0 != activate_threads_~tmp___2~0); 115827#L545-2 assume !(1 == ~M_E~0); 115838#L467-1 assume !(1 == ~T1_E~0); 115656#L472-1 assume !(1 == ~T2_E~0); 115657#L477-1 assume !(1 == ~T3_E~0); 115691#L482-1 assume !(1 == ~E_M~0); 115969#L487-1 assume !(1 == ~E_1~0); 116001#L492-1 assume !(1 == ~E_2~0); 115897#L497-1 assume !(1 == ~E_3~0); 115898#L668-1 assume !false; 120865#L669 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 120864#L394 [2019-12-07 12:55:06,251 INFO L796 eck$LassoCheckResult]: Loop: 120864#L394 assume !false; 120863#L343 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 120861#L310 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 120860#L332 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 120859#L333 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 120858#L347 assume 0 != eval_~tmp~0; 120856#L347-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 120853#L355 assume !(0 != eval_~tmp_ndt_1~0); 120851#L352 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 120787#L369 assume !(0 != eval_~tmp_ndt_2~0); 120849#L366 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 120491#L383 assume !(0 != eval_~tmp_ndt_3~0); 120492#L380 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 120866#L397 assume !(0 != eval_~tmp_ndt_4~0); 120864#L394 [2019-12-07 12:55:06,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,251 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2019-12-07 12:55:06,251 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,251 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572566764] [2019-12-07 12:55:06,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,284 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:06,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1371953511, now seen corresponding path program 1 times [2019-12-07 12:55:06,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56186401] [2019-12-07 12:55:06,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,290 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:06,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:55:06,291 INFO L82 PathProgramCache]: Analyzing trace with hash -2020256133, now seen corresponding path program 1 times [2019-12-07 12:55:06,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:55:06,291 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645043659] [2019-12-07 12:55:06,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:55:06,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:55:06,308 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:55:06,629 WARN L192 SmtUtils]: Spent 250.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 92 [2019-12-07 12:55:06,719 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 12:55:06 BoogieIcfgContainer [2019-12-07 12:55:06,719 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 12:55:06,719 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:55:06,719 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:55:06,719 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:55:06,719 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:55:03" (3/4) ... [2019-12-07 12:55:06,721 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 12:55:06,768 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_47a02c6a-77ec-4cb8-b03d-d60bf306d55c/bin/uautomizer/witness.graphml [2019-12-07 12:55:06,768 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:55:06,769 INFO L168 Benchmark]: Toolchain (without parser) took 4511.97 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 228.1 MB). Free memory was 946.1 MB in the beginning and 1.1 GB in the end (delta: -119.3 MB). Peak memory consumption was 108.7 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,770 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:55:06,770 INFO L168 Benchmark]: CACSL2BoogieTranslator took 242.72 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.3 MB). Free memory was 946.1 MB in the beginning and 1.1 GB in the end (delta: -134.3 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,770 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:55:06,771 INFO L168 Benchmark]: Boogie Preprocessor took 34.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,771 INFO L168 Benchmark]: RCFGBuilder took 511.74 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 992.2 MB in the end (delta: 82.8 MB). Peak memory consumption was 82.8 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,771 INFO L168 Benchmark]: BuchiAutomizer took 3632.86 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 135.8 MB). Free memory was 992.2 MB in the beginning and 1.1 GB in the end (delta: -76.0 MB). Peak memory consumption was 59.8 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,772 INFO L168 Benchmark]: Witness Printer took 49.40 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.8 MB). Peak memory consumption was 2.8 MB. Max. memory is 11.5 GB. [2019-12-07 12:55:06,774 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 242.72 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.3 MB). Free memory was 946.1 MB in the beginning and 1.1 GB in the end (delta: -134.3 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.84 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 34.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 511.74 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 992.2 MB in the end (delta: 82.8 MB). Peak memory consumption was 82.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 3632.86 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 135.8 MB). Free memory was 992.2 MB in the beginning and 1.1 GB in the end (delta: -76.0 MB). Peak memory consumption was 59.8 MB. Max. memory is 11.5 GB. * Witness Printer took 49.40 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.8 MB). Peak memory consumption was 2.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 9162 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.5s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.3s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 17 MinimizatonAttempts, 6108 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 9162 states and ocurred in iteration 17. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 7765 SDtfs, 7544 SDslu, 5998 SDs, 0 SdLazy, 324 SolverSat, 169 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 342]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e08bf70=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ce2a7f9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@8343e78=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37691ecf=0, __retres1=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6988779=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5907a937=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5fad2850=0, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@667e2cd5=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ad4f6b=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@258eed49=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@491e866e=0, t1_st=0, local=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 342]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int t3_st ; [L22] int m_i ; [L23] int t1_i ; [L24] int t2_i ; [L25] int t3_i ; [L26] int M_E = 2; [L27] int T1_E = 2; [L28] int T2_E = 2; [L29] int T3_E = 2; [L30] int E_M = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L39] int token ; [L41] int local ; [L713] int __retres1 ; [L626] m_i = 1 [L627] t1_i = 1 [L628] t2_i = 1 [L629] t3_i = 1 [L654] int kernel_st ; [L655] int tmp ; [L656] int tmp___0 ; [L660] kernel_st = 0 [L282] COND TRUE m_i == 1 [L283] m_st = 0 [L287] COND TRUE t1_i == 1 [L288] t1_st = 0 [L292] COND TRUE t2_i == 1 [L293] t2_st = 0 [L297] COND TRUE t3_i == 1 [L298] t3_st = 0 [L419] COND FALSE !(M_E == 0) [L424] COND FALSE !(T1_E == 0) [L429] COND FALSE !(T2_E == 0) [L434] COND FALSE !(T3_E == 0) [L439] COND FALSE !(E_M == 0) [L444] COND FALSE !(E_1 == 0) [L449] COND FALSE !(E_2 == 0) [L454] COND FALSE !(E_3 == 0) [L512] int tmp ; [L513] int tmp___0 ; [L514] int tmp___1 ; [L515] int tmp___2 ; [L195] int __retres1 ; [L198] COND FALSE !(m_pc == 1) [L208] __retres1 = 0 [L210] return (__retres1); [L519] tmp = is_master_triggered() [L521] COND FALSE !(\read(tmp)) [L214] int __retres1 ; [L217] COND FALSE !(t1_pc == 1) [L227] __retres1 = 0 [L229] return (__retres1); [L527] tmp___0 = is_transmit1_triggered() [L529] COND FALSE !(\read(tmp___0)) [L233] int __retres1 ; [L236] COND FALSE !(t2_pc == 1) [L246] __retres1 = 0 [L248] return (__retres1); [L535] tmp___1 = is_transmit2_triggered() [L537] COND FALSE !(\read(tmp___1)) [L252] int __retres1 ; [L255] COND FALSE !(t3_pc == 1) [L265] __retres1 = 0 [L267] return (__retres1); [L543] tmp___2 = is_transmit3_triggered() [L545] COND FALSE !(\read(tmp___2)) [L467] COND FALSE !(M_E == 1) [L472] COND FALSE !(T1_E == 1) [L477] COND FALSE !(T2_E == 1) [L482] COND FALSE !(T3_E == 1) [L487] COND FALSE !(E_M == 1) [L492] COND FALSE !(E_1 == 1) [L497] COND FALSE !(E_2 == 1) [L502] COND FALSE !(E_3 == 1) [L668] COND TRUE 1 [L671] kernel_st = 1 [L338] int tmp ; Loop: [L342] COND TRUE 1 [L307] int __retres1 ; [L310] COND TRUE m_st == 0 [L311] __retres1 = 1 [L333] return (__retres1); [L345] tmp = exists_runnable_thread() [L347] COND TRUE \read(tmp) [L352] COND TRUE m_st == 0 [L353] int tmp_ndt_1; [L354] tmp_ndt_1 = __VERIFIER_nondet_int() [L355] COND FALSE !(\read(tmp_ndt_1)) [L366] COND TRUE t1_st == 0 [L367] int tmp_ndt_2; [L368] tmp_ndt_2 = __VERIFIER_nondet_int() [L369] COND FALSE !(\read(tmp_ndt_2)) [L380] COND TRUE t2_st == 0 [L381] int tmp_ndt_3; [L382] tmp_ndt_3 = __VERIFIER_nondet_int() [L383] COND FALSE !(\read(tmp_ndt_3)) [L394] COND TRUE t3_st == 0 [L395] int tmp_ndt_4; [L396] tmp_ndt_4 = __VERIFIER_nondet_int() [L397] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...