./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0d93d749d4c7ad15cc29deef6885966e95a2d557 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 12:35:46,950 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 12:35:46,951 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 12:35:46,960 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 12:35:46,961 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 12:35:46,961 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 12:35:46,962 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 12:35:46,963 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 12:35:46,965 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 12:35:46,965 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 12:35:46,966 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 12:35:46,967 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 12:35:46,967 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 12:35:46,968 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 12:35:46,968 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 12:35:46,969 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 12:35:46,969 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 12:35:46,970 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 12:35:46,971 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 12:35:46,973 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 12:35:46,974 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 12:35:46,974 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 12:35:46,975 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 12:35:46,976 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 12:35:46,977 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 12:35:46,977 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 12:35:46,978 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 12:35:46,978 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 12:35:46,978 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 12:35:46,979 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 12:35:46,979 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 12:35:46,979 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 12:35:46,980 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 12:35:46,980 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 12:35:46,981 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 12:35:46,981 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 12:35:46,981 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 12:35:46,981 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 12:35:46,981 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 12:35:46,982 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 12:35:46,982 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 12:35:46,983 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 12:35:46,994 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 12:35:46,994 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 12:35:46,994 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 12:35:46,995 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 12:35:46,995 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 12:35:46,996 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 12:35:46,996 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 12:35:46,997 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 12:35:46,997 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 12:35:46,998 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 12:35:46,998 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 12:35:46,998 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 12:35:46,998 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 12:35:46,998 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 12:35:46,998 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 12:35:46,999 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 12:35:46,999 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0d93d749d4c7ad15cc29deef6885966e95a2d557 [2019-12-07 12:35:47,098 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 12:35:47,106 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 12:35:47,109 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 12:35:47,110 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 12:35:47,110 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 12:35:47,111 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2019-12-07 12:35:47,159 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/data/163245fcd/aca75833d31f45488287f8bd3e872279/FLAG35bab1808 [2019-12-07 12:35:47,519 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 12:35:47,519 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2019-12-07 12:35:47,526 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/data/163245fcd/aca75833d31f45488287f8bd3e872279/FLAG35bab1808 [2019-12-07 12:35:47,939 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/data/163245fcd/aca75833d31f45488287f8bd3e872279 [2019-12-07 12:35:47,943 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 12:35:47,945 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 12:35:47,946 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 12:35:47,947 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 12:35:47,951 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 12:35:47,952 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:35:47" (1/1) ... [2019-12-07 12:35:47,957 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6dfdd81d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:47, skipping insertion in model container [2019-12-07 12:35:47,957 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:35:47" (1/1) ... [2019-12-07 12:35:47,963 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 12:35:47,985 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 12:35:48,157 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:35:48,162 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 12:35:48,192 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 12:35:48,206 INFO L208 MainTranslator]: Completed translation [2019-12-07 12:35:48,206 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48 WrapperNode [2019-12-07 12:35:48,207 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 12:35:48,207 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 12:35:48,207 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 12:35:48,207 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 12:35:48,212 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,219 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,251 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 12:35:48,252 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 12:35:48,252 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 12:35:48,252 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 12:35:48,259 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,259 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,262 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,262 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,272 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,286 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,289 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... [2019-12-07 12:35:48,296 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 12:35:48,296 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 12:35:48,297 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 12:35:48,297 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 12:35:48,297 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 12:35:48,345 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 12:35:48,346 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 12:35:48,901 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 12:35:48,902 INFO L287 CfgBuilder]: Removed 161 assume(true) statements. [2019-12-07 12:35:48,903 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:35:48 BoogieIcfgContainer [2019-12-07 12:35:48,903 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 12:35:48,904 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 12:35:48,904 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 12:35:48,906 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 12:35:48,907 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:35:48,907 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:35:47" (1/3) ... [2019-12-07 12:35:48,907 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c7481c4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:35:48, skipping insertion in model container [2019-12-07 12:35:48,907 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:35:48,907 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:35:48" (2/3) ... [2019-12-07 12:35:48,908 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c7481c4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:35:48, skipping insertion in model container [2019-12-07 12:35:48,908 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 12:35:48,908 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:35:48" (3/3) ... [2019-12-07 12:35:48,909 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2019-12-07 12:35:48,937 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 12:35:48,937 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 12:35:48,937 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 12:35:48,937 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 12:35:48,937 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 12:35:48,938 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 12:35:48,938 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 12:35:48,938 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 12:35:48,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states. [2019-12-07 12:35:48,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 346 [2019-12-07 12:35:48,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:48,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,004 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,004 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,004 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 12:35:49,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states. [2019-12-07 12:35:49,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 346 [2019-12-07 12:35:49,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,015 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,015 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,021 INFO L794 eck$LassoCheckResult]: Stem: 269#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 172#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 413#L756true havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 52#L336true assume !(1 == ~m_i~0);~m_st~0 := 2; 84#L343-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 329#L348-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 116#L353-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 54#L358-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 296#L363-1true assume !(0 == ~M_E~0); 354#L504-1true assume !(0 == ~T1_E~0); 148#L509-1true assume !(0 == ~T2_E~0); 407#L514-1true assume !(0 == ~T3_E~0); 91#L519-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 337#L524-1true assume !(0 == ~E_M~0); 121#L529-1true assume !(0 == ~E_1~0); 59#L534-1true assume !(0 == ~E_2~0); 302#L539-1true assume !(0 == ~E_3~0); 7#L544-1true assume !(0 == ~E_4~0); 188#L549-1true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 220#L240true assume 1 == ~m_pc~0; 167#L241true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 222#L251true is_master_triggered_#res := is_master_triggered_~__retres1~0; 169#L252true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 298#L627true assume !(0 != activate_threads_~tmp~1); 299#L627-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53#L259true assume !(1 == ~t1_pc~0); 46#L259-2true is_transmit1_triggered_~__retres1~1 := 0; 55#L270true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 311#L271true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 415#L635true assume !(0 != activate_threads_~tmp___0~0); 403#L635-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 145#L278true assume 1 == ~t2_pc~0; 26#L279true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 146#L289true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27#L290true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3#L643true assume !(0 != activate_threads_~tmp___1~0); 4#L643-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 266#L297true assume !(1 == ~t3_pc~0); 264#L297-2true is_transmit3_triggered_~__retres1~3 := 0; 268#L308true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117#L309true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 95#L651true assume !(0 != activate_threads_~tmp___2~0); 88#L651-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 397#L316true assume 1 == ~t4_pc~0; 234#L317true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 396#L327true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 232#L328true activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 201#L659true assume !(0 != activate_threads_~tmp___3~0); 203#L659-2true assume !(1 == ~M_E~0); 120#L562-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 58#L567-1true assume !(1 == ~T2_E~0); 300#L572-1true assume !(1 == ~T3_E~0); 5#L577-1true assume !(1 == ~T4_E~0); 205#L582-1true assume !(1 == ~E_M~0); 32#L587-1true assume !(1 == ~E_1~0); 362#L592-1true assume !(1 == ~E_2~0); 142#L597-1true assume !(1 == ~E_3~0); 404#L602-1true assume 1 == ~E_4~0;~E_4~0 := 2; 249#L793-1true [2019-12-07 12:35:49,022 INFO L796 eck$LassoCheckResult]: Loop: 249#L793-1true assume !false; 96#L794true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 60#L479true assume !true; 189#L494true start_simulation_~kernel_st~0 := 2; 57#L336-1true start_simulation_~kernel_st~0 := 3; 355#L504-2true assume 0 == ~M_E~0;~M_E~0 := 1; 228#L504-4true assume !(0 == ~T1_E~0); 151#L509-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 412#L514-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 79#L519-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 313#L524-3true assume 0 == ~E_M~0;~E_M~0 := 1; 114#L529-3true assume 0 == ~E_1~0;~E_1~0 := 1; 41#L534-3true assume 0 == ~E_2~0;~E_2~0 := 1; 291#L539-3true assume 0 == ~E_3~0;~E_3~0 := 1; 74#L544-3true assume !(0 == ~E_4~0); 194#L549-3true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 198#L240-18true assume 1 == ~m_pc~0; 177#L241-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 230#L251-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 179#L252-6true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 265#L627-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 267#L627-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 335#L259-18true assume 1 == ~t1_pc~0; 308#L260-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 346#L270-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 309#L271-6true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 372#L635-18true assume !(0 != activate_threads_~tmp___0~0); 374#L635-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37#L278-18true assume !(1 == ~t2_pc~0); 35#L278-20true is_transmit2_triggered_~__retres1~2 := 0; 125#L289-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12#L290-6true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 67#L643-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 68#L643-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 256#L297-18true assume 1 == ~t3_pc~0; 112#L298-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 260#L308-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 113#L309-6true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 155#L651-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 156#L651-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 369#L316-18true assume 1 == ~t4_pc~0; 225#L317-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 385#L327-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 224#L328-6true activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 170#L659-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 171#L659-20true assume 1 == ~M_E~0;~M_E~0 := 2; 122#L562-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 39#L567-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 287#L572-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 73#L577-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 191#L582-3true assume 1 == ~E_M~0;~E_M~0 := 2; 23#L587-3true assume !(1 == ~E_1~0); 352#L592-3true assume 1 == ~E_2~0;~E_2~0 := 2; 147#L597-3true assume 1 == ~E_3~0;~E_3~0 := 2; 406#L602-3true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L607-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 83#L376-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 321#L403-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 393#L404-1true start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 366#L812true assume !(0 == start_simulation_~tmp~3); 368#L812-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 85#L376-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 326#L403-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 395#L404-2true stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 310#L767true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 36#L774true stop_simulation_#res := stop_simulation_~__retres2~0; 8#L775true start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 303#L825true assume !(0 != start_simulation_~tmp___0~1); 249#L793-1true [2019-12-07 12:35:49,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,027 INFO L82 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2019-12-07 12:35:49,033 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,033 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587480539] [2019-12-07 12:35:49,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587480539] [2019-12-07 12:35:49,140 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,140 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423409340] [2019-12-07 12:35:49,144 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,145 INFO L82 PathProgramCache]: Analyzing trace with hash 857461611, now seen corresponding path program 1 times [2019-12-07 12:35:49,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36146114] [2019-12-07 12:35:49,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,162 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36146114] [2019-12-07 12:35:49,162 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,162 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:49,163 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555550738] [2019-12-07 12:35:49,164 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,164 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,175 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,176 INFO L87 Difference]: Start difference. First operand 413 states. Second operand 3 states. [2019-12-07 12:35:49,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,204 INFO L93 Difference]: Finished difference Result 413 states and 625 transitions. [2019-12-07 12:35:49,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 625 transitions. [2019-12-07 12:35:49,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 408 states and 620 transitions. [2019-12-07 12:35:49,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2019-12-07 12:35:49,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2019-12-07 12:35:49,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 620 transitions. [2019-12-07 12:35:49,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,221 INFO L688 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2019-12-07 12:35:49,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 620 transitions. [2019-12-07 12:35:49,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2019-12-07 12:35:49,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2019-12-07 12:35:49,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 620 transitions. [2019-12-07 12:35:49,256 INFO L711 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2019-12-07 12:35:49,256 INFO L591 BuchiCegarLoop]: Abstraction has 408 states and 620 transitions. [2019-12-07 12:35:49,256 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 12:35:49,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 620 transitions. [2019-12-07 12:35:49,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,260 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,260 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,260 INFO L794 eck$LassoCheckResult]: Stem: 1186#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1098#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1099#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 930#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 931#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 978#L348-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1034#L353-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 934#L358-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 935#L363-1 assume !(0 == ~M_E~0); 1200#L504-1 assume !(0 == ~T1_E~0); 1059#L509-1 assume !(0 == ~T2_E~0); 1060#L514-1 assume !(0 == ~T3_E~0); 988#L519-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 989#L524-1 assume !(0 == ~E_M~0); 1040#L529-1 assume !(0 == ~E_1~0); 944#L534-1 assume !(0 == ~E_2~0); 945#L539-1 assume !(0 == ~E_3~0); 842#L544-1 assume !(0 == ~E_4~0); 843#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1128#L240 assume 1 == ~m_pc~0; 1091#L241 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1092#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1094#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1095#L627 assume !(0 != activate_threads_~tmp~1); 1201#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 932#L259 assume !(1 == ~t1_pc~0); 916#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 917#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 936#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1214#L635 assume !(0 != activate_threads_~tmp___0~0); 1241#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1056#L278 assume 1 == ~t2_pc~0; 886#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 887#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 889#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 835#L643 assume !(0 != activate_threads_~tmp___1~0); 836#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 837#L297 assume !(1 == ~t3_pc~0); 1038#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 1037#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1035#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 994#L651 assume !(0 != activate_threads_~tmp___2~0); 983#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 984#L316 assume 1 == ~t4_pc~0; 1162#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1163#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1161#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1136#L659 assume !(0 != activate_threads_~tmp___3~0); 1137#L659-2 assume !(1 == ~M_E~0); 1039#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 942#L567-1 assume !(1 == ~T2_E~0); 943#L572-1 assume !(1 == ~T3_E~0); 838#L577-1 assume !(1 == ~T4_E~0); 839#L582-1 assume !(1 == ~E_M~0); 893#L587-1 assume !(1 == ~E_1~0); 894#L592-1 assume !(1 == ~E_2~0); 1054#L597-1 assume !(1 == ~E_3~0); 1055#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1178#L793-1 [2019-12-07 12:35:49,261 INFO L796 eck$LassoCheckResult]: Loop: 1178#L793-1 assume !false; 995#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 946#L479 assume !false; 947#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 974#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 923#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1220#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1196#L418 assume !(0 != eval_~tmp~0); 1129#L494 start_simulation_~kernel_st~0 := 2; 940#L336-1 start_simulation_~kernel_st~0 := 3; 941#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1158#L504-4 assume !(0 == ~T1_E~0); 1064#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1065#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 970#L519-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 971#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1033#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 904#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 905#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 963#L544-3 assume !(0 == ~E_4~0); 964#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1133#L240-18 assume 1 == ~m_pc~0; 1105#L241-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1106#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1109#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1110#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1184#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1185#L259-18 assume 1 == ~t1_pc~0; 1208#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1209#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1211#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1212#L635-18 assume !(0 != activate_threads_~tmp___0~0); 1236#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 897#L278-18 assume 1 == ~t2_pc~0; 851#L279-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 852#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 854#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 855#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 954#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 955#L297-18 assume 1 == ~t3_pc~0; 1028#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1030#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1031#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1032#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1072#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1073#L316-18 assume !(1 == ~t4_pc~0); 1152#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 1151#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1149#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1096#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1097#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1041#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 900#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 901#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 961#L577-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 962#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 880#L587-3 assume !(1 == ~E_1~0); 881#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1057#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1058#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 987#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 977#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 928#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1226#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1234#L812 assume !(0 == start_simulation_~tmp~3); 949#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 979#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 938#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1230#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 1213#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 896#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 844#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 845#L825 assume !(0 != start_simulation_~tmp___0~1); 1178#L793-1 [2019-12-07 12:35:49,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,261 INFO L82 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2019-12-07 12:35:49,261 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,261 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62752061] [2019-12-07 12:35:49,261 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,287 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62752061] [2019-12-07 12:35:49,287 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,287 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,288 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379335345] [2019-12-07 12:35:49,288 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,288 INFO L82 PathProgramCache]: Analyzing trace with hash 2042923847, now seen corresponding path program 1 times [2019-12-07 12:35:49,288 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,288 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005728595] [2019-12-07 12:35:49,289 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005728595] [2019-12-07 12:35:49,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,331 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495961261] [2019-12-07 12:35:49,332 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,332 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,332 INFO L87 Difference]: Start difference. First operand 408 states and 620 transitions. cyclomatic complexity: 213 Second operand 3 states. [2019-12-07 12:35:49,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,342 INFO L93 Difference]: Finished difference Result 408 states and 619 transitions. [2019-12-07 12:35:49,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 619 transitions. [2019-12-07 12:35:49,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 619 transitions. [2019-12-07 12:35:49,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2019-12-07 12:35:49,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2019-12-07 12:35:49,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 619 transitions. [2019-12-07 12:35:49,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,352 INFO L688 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2019-12-07 12:35:49,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 619 transitions. [2019-12-07 12:35:49,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2019-12-07 12:35:49,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2019-12-07 12:35:49,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 619 transitions. [2019-12-07 12:35:49,363 INFO L711 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2019-12-07 12:35:49,363 INFO L591 BuchiCegarLoop]: Abstraction has 408 states and 619 transitions. [2019-12-07 12:35:49,363 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 12:35:49,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 619 transitions. [2019-12-07 12:35:49,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,366 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,367 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,367 INFO L794 eck$LassoCheckResult]: Stem: 2009#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1921#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1922#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1753#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 1754#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1801#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1857#L353-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1757#L358-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1758#L363-1 assume !(0 == ~M_E~0); 2023#L504-1 assume !(0 == ~T1_E~0); 1882#L509-1 assume !(0 == ~T2_E~0); 1883#L514-1 assume !(0 == ~T3_E~0); 1811#L519-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1812#L524-1 assume !(0 == ~E_M~0); 1863#L529-1 assume !(0 == ~E_1~0); 1767#L534-1 assume !(0 == ~E_2~0); 1768#L539-1 assume !(0 == ~E_3~0); 1665#L544-1 assume !(0 == ~E_4~0); 1666#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1951#L240 assume 1 == ~m_pc~0; 1914#L241 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1915#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1917#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1918#L627 assume !(0 != activate_threads_~tmp~1); 2024#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1755#L259 assume !(1 == ~t1_pc~0); 1739#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 1740#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1759#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2037#L635 assume !(0 != activate_threads_~tmp___0~0); 2064#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1879#L278 assume 1 == ~t2_pc~0; 1709#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1710#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1712#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1658#L643 assume !(0 != activate_threads_~tmp___1~0); 1659#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1660#L297 assume !(1 == ~t3_pc~0); 1861#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 1860#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1858#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1817#L651 assume !(0 != activate_threads_~tmp___2~0); 1806#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1807#L316 assume 1 == ~t4_pc~0; 1985#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1986#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1984#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1959#L659 assume !(0 != activate_threads_~tmp___3~0); 1960#L659-2 assume !(1 == ~M_E~0); 1862#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1765#L567-1 assume !(1 == ~T2_E~0); 1766#L572-1 assume !(1 == ~T3_E~0); 1661#L577-1 assume !(1 == ~T4_E~0); 1662#L582-1 assume !(1 == ~E_M~0); 1716#L587-1 assume !(1 == ~E_1~0); 1717#L592-1 assume !(1 == ~E_2~0); 1877#L597-1 assume !(1 == ~E_3~0); 1878#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2001#L793-1 [2019-12-07 12:35:49,367 INFO L796 eck$LassoCheckResult]: Loop: 2001#L793-1 assume !false; 1818#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1769#L479 assume !false; 1770#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1797#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1746#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2043#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2019#L418 assume !(0 != eval_~tmp~0); 1952#L494 start_simulation_~kernel_st~0 := 2; 1763#L336-1 start_simulation_~kernel_st~0 := 3; 1764#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1981#L504-4 assume !(0 == ~T1_E~0); 1887#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1888#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1793#L519-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1794#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1856#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1727#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1728#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1786#L544-3 assume !(0 == ~E_4~0); 1787#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1956#L240-18 assume 1 == ~m_pc~0; 1928#L241-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1929#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1932#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1933#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2007#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2008#L259-18 assume !(1 == ~t1_pc~0); 2033#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 2032#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2034#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2035#L635-18 assume !(0 != activate_threads_~tmp___0~0); 2059#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1720#L278-18 assume 1 == ~t2_pc~0; 1674#L279-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1675#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1677#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1678#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1777#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1778#L297-18 assume 1 == ~t3_pc~0; 1851#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1853#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1854#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1855#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1895#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1896#L316-18 assume 1 == ~t4_pc~0; 1973#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1974#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1972#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1919#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1920#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1864#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1723#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1724#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1784#L577-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1785#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1703#L587-3 assume !(1 == ~E_1~0); 1704#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1880#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1881#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1810#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1800#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1751#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2049#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2057#L812 assume !(0 == start_simulation_~tmp~3); 1772#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1802#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1761#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2053#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 2036#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1719#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 1667#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1668#L825 assume !(0 != start_simulation_~tmp___0~1); 2001#L793-1 [2019-12-07 12:35:49,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,368 INFO L82 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2019-12-07 12:35:49,368 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,368 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827167049] [2019-12-07 12:35:49,368 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,390 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827167049] [2019-12-07 12:35:49,390 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,390 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,390 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515100543] [2019-12-07 12:35:49,391 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,391 INFO L82 PathProgramCache]: Analyzing trace with hash 1043358087, now seen corresponding path program 1 times [2019-12-07 12:35:49,391 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,391 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74120324] [2019-12-07 12:35:49,391 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,426 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74120324] [2019-12-07 12:35:49,426 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045336472] [2019-12-07 12:35:49,427 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,427 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,428 INFO L87 Difference]: Start difference. First operand 408 states and 619 transitions. cyclomatic complexity: 212 Second operand 3 states. [2019-12-07 12:35:49,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,436 INFO L93 Difference]: Finished difference Result 408 states and 618 transitions. [2019-12-07 12:35:49,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 618 transitions. [2019-12-07 12:35:49,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 618 transitions. [2019-12-07 12:35:49,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2019-12-07 12:35:49,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2019-12-07 12:35:49,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 618 transitions. [2019-12-07 12:35:49,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,443 INFO L688 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2019-12-07 12:35:49,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 618 transitions. [2019-12-07 12:35:49,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2019-12-07 12:35:49,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2019-12-07 12:35:49,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 618 transitions. [2019-12-07 12:35:49,450 INFO L711 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2019-12-07 12:35:49,450 INFO L591 BuchiCegarLoop]: Abstraction has 408 states and 618 transitions. [2019-12-07 12:35:49,450 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 12:35:49,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 618 transitions. [2019-12-07 12:35:49,452 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,453 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,453 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,453 INFO L794 eck$LassoCheckResult]: Stem: 2832#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2744#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2745#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2576#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 2577#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2624#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2680#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2580#L358-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2581#L363-1 assume !(0 == ~M_E~0); 2846#L504-1 assume !(0 == ~T1_E~0); 2705#L509-1 assume !(0 == ~T2_E~0); 2706#L514-1 assume !(0 == ~T3_E~0); 2634#L519-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2635#L524-1 assume !(0 == ~E_M~0); 2686#L529-1 assume !(0 == ~E_1~0); 2590#L534-1 assume !(0 == ~E_2~0); 2591#L539-1 assume !(0 == ~E_3~0); 2488#L544-1 assume !(0 == ~E_4~0); 2489#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2774#L240 assume 1 == ~m_pc~0; 2737#L241 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2738#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2740#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2741#L627 assume !(0 != activate_threads_~tmp~1); 2847#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2578#L259 assume !(1 == ~t1_pc~0); 2562#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 2563#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2582#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2860#L635 assume !(0 != activate_threads_~tmp___0~0); 2887#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2702#L278 assume 1 == ~t2_pc~0; 2532#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2533#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2535#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2481#L643 assume !(0 != activate_threads_~tmp___1~0); 2482#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2483#L297 assume !(1 == ~t3_pc~0); 2684#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 2683#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2681#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2640#L651 assume !(0 != activate_threads_~tmp___2~0); 2629#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2630#L316 assume 1 == ~t4_pc~0; 2808#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2809#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2807#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2782#L659 assume !(0 != activate_threads_~tmp___3~0); 2783#L659-2 assume !(1 == ~M_E~0); 2685#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2588#L567-1 assume !(1 == ~T2_E~0); 2589#L572-1 assume !(1 == ~T3_E~0); 2484#L577-1 assume !(1 == ~T4_E~0); 2485#L582-1 assume !(1 == ~E_M~0); 2539#L587-1 assume !(1 == ~E_1~0); 2540#L592-1 assume !(1 == ~E_2~0); 2700#L597-1 assume !(1 == ~E_3~0); 2701#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2824#L793-1 [2019-12-07 12:35:49,454 INFO L796 eck$LassoCheckResult]: Loop: 2824#L793-1 assume !false; 2641#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2592#L479 assume !false; 2593#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2620#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2569#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2866#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2842#L418 assume !(0 != eval_~tmp~0); 2775#L494 start_simulation_~kernel_st~0 := 2; 2586#L336-1 start_simulation_~kernel_st~0 := 3; 2587#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2804#L504-4 assume !(0 == ~T1_E~0); 2710#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2711#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2616#L519-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2617#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2679#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2550#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2551#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2609#L544-3 assume !(0 == ~E_4~0); 2610#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2779#L240-18 assume !(1 == ~m_pc~0); 2753#L240-20 is_master_triggered_~__retres1~0 := 0; 2752#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2755#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2756#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2830#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2831#L259-18 assume 1 == ~t1_pc~0; 2854#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2855#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2857#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2858#L635-18 assume !(0 != activate_threads_~tmp___0~0); 2882#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2543#L278-18 assume 1 == ~t2_pc~0; 2497#L279-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2498#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2500#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2501#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2600#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2601#L297-18 assume 1 == ~t3_pc~0; 2674#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2676#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2677#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2678#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2718#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2719#L316-18 assume 1 == ~t4_pc~0; 2796#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2797#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2795#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2742#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2743#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2687#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2546#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2547#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2607#L577-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2608#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2526#L587-3 assume !(1 == ~E_1~0); 2527#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2703#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2704#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2633#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2623#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2574#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2872#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2880#L812 assume !(0 == start_simulation_~tmp~3); 2595#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2625#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2584#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2876#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 2859#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2542#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 2490#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2491#L825 assume !(0 != start_simulation_~tmp___0~1); 2824#L793-1 [2019-12-07 12:35:49,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,454 INFO L82 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2019-12-07 12:35:49,454 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,454 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081460041] [2019-12-07 12:35:49,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,474 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081460041] [2019-12-07 12:35:49,474 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,475 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,475 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586057296] [2019-12-07 12:35:49,475 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,475 INFO L82 PathProgramCache]: Analyzing trace with hash 1649794631, now seen corresponding path program 1 times [2019-12-07 12:35:49,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,476 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828371596] [2019-12-07 12:35:49,476 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,506 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828371596] [2019-12-07 12:35:49,506 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243882337] [2019-12-07 12:35:49,506 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,507 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,507 INFO L87 Difference]: Start difference. First operand 408 states and 618 transitions. cyclomatic complexity: 211 Second operand 3 states. [2019-12-07 12:35:49,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,515 INFO L93 Difference]: Finished difference Result 408 states and 617 transitions. [2019-12-07 12:35:49,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 617 transitions. [2019-12-07 12:35:49,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 617 transitions. [2019-12-07 12:35:49,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2019-12-07 12:35:49,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2019-12-07 12:35:49,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 617 transitions. [2019-12-07 12:35:49,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,522 INFO L688 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2019-12-07 12:35:49,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 617 transitions. [2019-12-07 12:35:49,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2019-12-07 12:35:49,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2019-12-07 12:35:49,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 617 transitions. [2019-12-07 12:35:49,528 INFO L711 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2019-12-07 12:35:49,528 INFO L591 BuchiCegarLoop]: Abstraction has 408 states and 617 transitions. [2019-12-07 12:35:49,528 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 12:35:49,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 617 transitions. [2019-12-07 12:35:49,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,531 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,531 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,532 INFO L794 eck$LassoCheckResult]: Stem: 3655#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3567#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3568#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3399#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 3400#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3448#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3503#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3403#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3404#L363-1 assume !(0 == ~M_E~0); 3669#L504-1 assume !(0 == ~T1_E~0); 3528#L509-1 assume !(0 == ~T2_E~0); 3529#L514-1 assume !(0 == ~T3_E~0); 3458#L519-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3459#L524-1 assume !(0 == ~E_M~0); 3509#L529-1 assume !(0 == ~E_1~0); 3413#L534-1 assume !(0 == ~E_2~0); 3414#L539-1 assume !(0 == ~E_3~0); 3311#L544-1 assume !(0 == ~E_4~0); 3312#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3597#L240 assume 1 == ~m_pc~0; 3560#L241 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3561#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3563#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3564#L627 assume !(0 != activate_threads_~tmp~1); 3670#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3401#L259 assume !(1 == ~t1_pc~0); 3385#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 3386#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3405#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3683#L635 assume !(0 != activate_threads_~tmp___0~0); 3710#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3525#L278 assume 1 == ~t2_pc~0; 3355#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3356#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3358#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3304#L643 assume !(0 != activate_threads_~tmp___1~0); 3305#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3306#L297 assume !(1 == ~t3_pc~0); 3507#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 3506#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3504#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3463#L651 assume !(0 != activate_threads_~tmp___2~0); 3452#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3453#L316 assume 1 == ~t4_pc~0; 3631#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3632#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3630#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3606#L659 assume !(0 != activate_threads_~tmp___3~0); 3607#L659-2 assume !(1 == ~M_E~0); 3508#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3411#L567-1 assume !(1 == ~T2_E~0); 3412#L572-1 assume !(1 == ~T3_E~0); 3309#L577-1 assume !(1 == ~T4_E~0); 3310#L582-1 assume !(1 == ~E_M~0); 3362#L587-1 assume !(1 == ~E_1~0); 3363#L592-1 assume !(1 == ~E_2~0); 3523#L597-1 assume !(1 == ~E_3~0); 3524#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3647#L793-1 [2019-12-07 12:35:49,532 INFO L796 eck$LassoCheckResult]: Loop: 3647#L793-1 assume !false; 3464#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3415#L479 assume !false; 3416#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3443#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3392#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3691#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3665#L418 assume !(0 != eval_~tmp~0); 3599#L494 start_simulation_~kernel_st~0 := 2; 3409#L336-1 start_simulation_~kernel_st~0 := 3; 3410#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3627#L504-4 assume !(0 == ~T1_E~0); 3533#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3534#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3439#L519-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3440#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3502#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3373#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3374#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3433#L544-3 assume !(0 == ~E_4~0); 3434#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3602#L240-18 assume 1 == ~m_pc~0; 3575#L241-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3576#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3578#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3579#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3653#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3654#L259-18 assume 1 == ~t1_pc~0; 3677#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3678#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3680#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3681#L635-18 assume !(0 != activate_threads_~tmp___0~0); 3705#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3366#L278-18 assume 1 == ~t2_pc~0; 3320#L279-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3321#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3323#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3324#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3423#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3424#L297-18 assume 1 == ~t3_pc~0; 3495#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3497#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3498#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3499#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3541#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3542#L316-18 assume 1 == ~t4_pc~0; 3619#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3620#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3618#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3565#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3566#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3510#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3367#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3368#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3430#L577-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3431#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3349#L587-3 assume !(1 == ~E_1~0); 3350#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3526#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3527#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3456#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3446#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3397#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3693#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3703#L812 assume !(0 == start_simulation_~tmp~3); 3418#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3447#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3407#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3697#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 3682#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3365#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 3313#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3314#L825 assume !(0 != start_simulation_~tmp___0~1); 3647#L793-1 [2019-12-07 12:35:49,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,532 INFO L82 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2019-12-07 12:35:49,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324103214] [2019-12-07 12:35:49,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,554 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324103214] [2019-12-07 12:35:49,554 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,554 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:49,554 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424870585] [2019-12-07 12:35:49,555 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,555 INFO L82 PathProgramCache]: Analyzing trace with hash -1943604440, now seen corresponding path program 1 times [2019-12-07 12:35:49,555 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459059455] [2019-12-07 12:35:49,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,590 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459059455] [2019-12-07 12:35:49,590 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,590 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,590 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287547356] [2019-12-07 12:35:49,591 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,591 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,591 INFO L87 Difference]: Start difference. First operand 408 states and 617 transitions. cyclomatic complexity: 210 Second operand 3 states. [2019-12-07 12:35:49,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,607 INFO L93 Difference]: Finished difference Result 408 states and 612 transitions. [2019-12-07 12:35:49,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 408 states and 612 transitions. [2019-12-07 12:35:49,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 408 states to 408 states and 612 transitions. [2019-12-07 12:35:49,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 408 [2019-12-07 12:35:49,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 408 [2019-12-07 12:35:49,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 408 states and 612 transitions. [2019-12-07 12:35:49,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,622 INFO L688 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2019-12-07 12:35:49,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 408 states and 612 transitions. [2019-12-07 12:35:49,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 408 to 408. [2019-12-07 12:35:49,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 408 states. [2019-12-07 12:35:49,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 612 transitions. [2019-12-07 12:35:49,629 INFO L711 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2019-12-07 12:35:49,630 INFO L591 BuchiCegarLoop]: Abstraction has 408 states and 612 transitions. [2019-12-07 12:35:49,630 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 12:35:49,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 408 states and 612 transitions. [2019-12-07 12:35:49,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2019-12-07 12:35:49,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,633 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,633 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,633 INFO L794 eck$LassoCheckResult]: Stem: 4478#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4390#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4391#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4222#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 4223#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4270#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4326#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4226#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4227#L363-1 assume !(0 == ~M_E~0); 4492#L504-1 assume !(0 == ~T1_E~0); 4351#L509-1 assume !(0 == ~T2_E~0); 4352#L514-1 assume !(0 == ~T3_E~0); 4280#L519-1 assume !(0 == ~T4_E~0); 4281#L524-1 assume !(0 == ~E_M~0); 4332#L529-1 assume !(0 == ~E_1~0); 4236#L534-1 assume !(0 == ~E_2~0); 4237#L539-1 assume !(0 == ~E_3~0); 4134#L544-1 assume !(0 == ~E_4~0); 4135#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4420#L240 assume 1 == ~m_pc~0; 4383#L241 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4384#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4386#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4387#L627 assume !(0 != activate_threads_~tmp~1); 4493#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4224#L259 assume !(1 == ~t1_pc~0); 4208#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 4209#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4228#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4506#L635 assume !(0 != activate_threads_~tmp___0~0); 4533#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4348#L278 assume 1 == ~t2_pc~0; 4178#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4179#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4181#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4127#L643 assume !(0 != activate_threads_~tmp___1~0); 4128#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4129#L297 assume !(1 == ~t3_pc~0); 4330#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 4329#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4327#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4286#L651 assume !(0 != activate_threads_~tmp___2~0); 4275#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4276#L316 assume 1 == ~t4_pc~0; 4454#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4455#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4453#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4429#L659 assume !(0 != activate_threads_~tmp___3~0); 4430#L659-2 assume !(1 == ~M_E~0); 4331#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4234#L567-1 assume !(1 == ~T2_E~0); 4235#L572-1 assume !(1 == ~T3_E~0); 4130#L577-1 assume !(1 == ~T4_E~0); 4131#L582-1 assume !(1 == ~E_M~0); 4185#L587-1 assume !(1 == ~E_1~0); 4186#L592-1 assume !(1 == ~E_2~0); 4346#L597-1 assume !(1 == ~E_3~0); 4347#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4470#L793-1 [2019-12-07 12:35:49,634 INFO L796 eck$LassoCheckResult]: Loop: 4470#L793-1 assume !false; 4287#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4238#L479 assume !false; 4239#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4266#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4215#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4512#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4488#L418 assume !(0 != eval_~tmp~0); 4421#L494 start_simulation_~kernel_st~0 := 2; 4232#L336-1 start_simulation_~kernel_st~0 := 3; 4233#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4450#L504-4 assume !(0 == ~T1_E~0); 4356#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4357#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4262#L519-3 assume !(0 == ~T4_E~0); 4263#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4325#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4196#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4197#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4255#L544-3 assume !(0 == ~E_4~0); 4256#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4425#L240-18 assume 1 == ~m_pc~0; 4397#L241-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4398#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4401#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4402#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4476#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4477#L259-18 assume 1 == ~t1_pc~0; 4500#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4501#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4503#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4504#L635-18 assume !(0 != activate_threads_~tmp___0~0); 4528#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4189#L278-18 assume !(1 == ~t2_pc~0); 4145#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 4144#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4146#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4147#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4246#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4247#L297-18 assume 1 == ~t3_pc~0; 4320#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4322#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4323#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4324#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4364#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4365#L316-18 assume 1 == ~t4_pc~0; 4442#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4443#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4441#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4388#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4389#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4333#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4192#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4193#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4253#L577-3 assume !(1 == ~T4_E~0); 4254#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4172#L587-3 assume !(1 == ~E_1~0); 4173#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4349#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4350#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4279#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4269#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4220#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4518#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 4526#L812 assume !(0 == start_simulation_~tmp~3); 4241#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4271#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4230#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4522#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 4505#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4188#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 4136#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4137#L825 assume !(0 != start_simulation_~tmp___0~1); 4470#L793-1 [2019-12-07 12:35:49,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,635 INFO L82 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2019-12-07 12:35:49,635 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,635 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492991917] [2019-12-07 12:35:49,635 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,652 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492991917] [2019-12-07 12:35:49,652 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,652 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:49,652 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882757428] [2019-12-07 12:35:49,652 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,653 INFO L82 PathProgramCache]: Analyzing trace with hash 1623110091, now seen corresponding path program 1 times [2019-12-07 12:35:49,653 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,653 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987837587] [2019-12-07 12:35:49,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,673 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987837587] [2019-12-07 12:35:49,673 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,673 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,673 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026885885] [2019-12-07 12:35:49,674 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,674 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,674 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,674 INFO L87 Difference]: Start difference. First operand 408 states and 612 transitions. cyclomatic complexity: 205 Second operand 3 states. [2019-12-07 12:35:49,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,713 INFO L93 Difference]: Finished difference Result 744 states and 1101 transitions. [2019-12-07 12:35:49,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 744 states and 1101 transitions. [2019-12-07 12:35:49,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 680 [2019-12-07 12:35:49,720 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 744 states to 744 states and 1101 transitions. [2019-12-07 12:35:49,720 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 744 [2019-12-07 12:35:49,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 744 [2019-12-07 12:35:49,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 744 states and 1101 transitions. [2019-12-07 12:35:49,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,722 INFO L688 BuchiCegarLoop]: Abstraction has 744 states and 1101 transitions. [2019-12-07 12:35:49,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 744 states and 1101 transitions. [2019-12-07 12:35:49,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 744 to 711. [2019-12-07 12:35:49,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 711 states. [2019-12-07 12:35:49,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 1055 transitions. [2019-12-07 12:35:49,731 INFO L711 BuchiCegarLoop]: Abstraction has 711 states and 1055 transitions. [2019-12-07 12:35:49,731 INFO L591 BuchiCegarLoop]: Abstraction has 711 states and 1055 transitions. [2019-12-07 12:35:49,731 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 12:35:49,731 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 711 states and 1055 transitions. [2019-12-07 12:35:49,733 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 647 [2019-12-07 12:35:49,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,734 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,734 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,734 INFO L794 eck$LassoCheckResult]: Stem: 5650#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5546#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5547#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5381#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 5382#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5430#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5485#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5385#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5386#L363-1 assume !(0 == ~M_E~0); 5667#L504-1 assume !(0 == ~T1_E~0); 5510#L509-1 assume !(0 == ~T2_E~0); 5511#L514-1 assume !(0 == ~T3_E~0); 5440#L519-1 assume !(0 == ~T4_E~0); 5441#L524-1 assume !(0 == ~E_M~0); 5491#L529-1 assume !(0 == ~E_1~0); 5395#L534-1 assume !(0 == ~E_2~0); 5396#L539-1 assume !(0 == ~E_3~0); 5293#L544-1 assume !(0 == ~E_4~0); 5294#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5576#L240 assume !(1 == ~m_pc~0); 5607#L240-2 is_master_triggered_~__retres1~0 := 0; 5611#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5542#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5543#L627 assume !(0 != activate_threads_~tmp~1); 5668#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5383#L259 assume !(1 == ~t1_pc~0); 5367#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 5368#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5387#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5681#L635 assume !(0 != activate_threads_~tmp___0~0); 5709#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5507#L278 assume 1 == ~t2_pc~0; 5337#L279 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5338#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5340#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5286#L643 assume !(0 != activate_threads_~tmp___1~0); 5287#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5288#L297 assume !(1 == ~t3_pc~0); 5489#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 5488#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5486#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5445#L651 assume !(0 != activate_threads_~tmp___2~0); 5434#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5435#L316 assume 1 == ~t4_pc~0; 5625#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5626#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5624#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5589#L659 assume !(0 != activate_threads_~tmp___3~0); 5590#L659-2 assume !(1 == ~M_E~0); 5490#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5393#L567-1 assume !(1 == ~T2_E~0); 5394#L572-1 assume !(1 == ~T3_E~0); 5289#L577-1 assume !(1 == ~T4_E~0); 5290#L582-1 assume !(1 == ~E_M~0); 5344#L587-1 assume !(1 == ~E_1~0); 5345#L592-1 assume !(1 == ~E_2~0); 5505#L597-1 assume !(1 == ~E_3~0); 5506#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5642#L793-1 [2019-12-07 12:35:49,734 INFO L796 eck$LassoCheckResult]: Loop: 5642#L793-1 assume !false; 5446#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5397#L479 assume !false; 5398#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5425#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5374#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5687#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5661#L418 assume !(0 != eval_~tmp~0); 5663#L494 start_simulation_~kernel_st~0 := 2; 5795#L336-1 start_simulation_~kernel_st~0 := 3; 5792#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5790#L504-4 assume !(0 == ~T1_E~0); 5788#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5786#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5784#L519-3 assume !(0 == ~T4_E~0); 5782#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5779#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5752#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5743#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5726#L544-3 assume !(0 == ~E_4~0); 5583#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5584#L240-18 assume !(1 == ~m_pc~0); 5586#L240-20 is_master_triggered_~__retres1~0 := 0; 5936#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5934#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5932#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5931#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5930#L259-18 assume 1 == ~t1_pc~0; 5928#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5927#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5926#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5925#L635-18 assume !(0 != activate_threads_~tmp___0~0); 5924#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5923#L278-18 assume 1 == ~t2_pc~0; 5891#L279-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5889#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5886#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5884#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5882#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5880#L297-18 assume !(1 == ~t3_pc~0); 5877#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 5875#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5872#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5870#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5868#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5866#L316-18 assume 1 == ~t4_pc~0; 5863#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5862#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5859#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5858#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5856#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5849#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5848#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5847#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5846#L577-3 assume !(1 == ~T4_E~0); 5845#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5844#L587-3 assume !(1 == ~E_1~0); 5843#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5842#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5840#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5824#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5757#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5747#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5706#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5701#L812 assume !(0 == start_simulation_~tmp~3); 5400#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5429#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5389#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5695#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 5680#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5347#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 5295#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5296#L825 assume !(0 != start_simulation_~tmp___0~1); 5642#L793-1 [2019-12-07 12:35:49,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2019-12-07 12:35:49,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439175805] [2019-12-07 12:35:49,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439175805] [2019-12-07 12:35:49,750 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:49,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747188840] [2019-12-07 12:35:49,750 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,751 INFO L82 PathProgramCache]: Analyzing trace with hash -1107099606, now seen corresponding path program 1 times [2019-12-07 12:35:49,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,751 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580310866] [2019-12-07 12:35:49,751 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,767 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580310866] [2019-12-07 12:35:49,767 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,767 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,767 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296264381] [2019-12-07 12:35:49,767 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,768 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,768 INFO L87 Difference]: Start difference. First operand 711 states and 1055 transitions. cyclomatic complexity: 346 Second operand 3 states. [2019-12-07 12:35:49,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,810 INFO L93 Difference]: Finished difference Result 1277 states and 1879 transitions. [2019-12-07 12:35:49,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1277 states and 1879 transitions. [2019-12-07 12:35:49,815 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1208 [2019-12-07 12:35:49,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1277 states to 1277 states and 1879 transitions. [2019-12-07 12:35:49,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1277 [2019-12-07 12:35:49,823 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1277 [2019-12-07 12:35:49,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1277 states and 1879 transitions. [2019-12-07 12:35:49,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,825 INFO L688 BuchiCegarLoop]: Abstraction has 1277 states and 1879 transitions. [2019-12-07 12:35:49,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1277 states and 1879 transitions. [2019-12-07 12:35:49,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1277 to 1273. [2019-12-07 12:35:49,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1273 states. [2019-12-07 12:35:49,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 1875 transitions. [2019-12-07 12:35:49,840 INFO L711 BuchiCegarLoop]: Abstraction has 1273 states and 1875 transitions. [2019-12-07 12:35:49,840 INFO L591 BuchiCegarLoop]: Abstraction has 1273 states and 1875 transitions. [2019-12-07 12:35:49,841 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 12:35:49,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1273 states and 1875 transitions. [2019-12-07 12:35:49,844 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1204 [2019-12-07 12:35:49,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,845 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,845 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,845 INFO L794 eck$LassoCheckResult]: Stem: 7657#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7550#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7551#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7377#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 7378#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7427#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7483#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7381#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7382#L363-1 assume !(0 == ~M_E~0); 7676#L504-1 assume !(0 == ~T1_E~0); 7513#L509-1 assume !(0 == ~T2_E~0); 7514#L514-1 assume !(0 == ~T3_E~0); 7437#L519-1 assume !(0 == ~T4_E~0); 7438#L524-1 assume !(0 == ~E_M~0); 7489#L529-1 assume !(0 == ~E_1~0); 7391#L534-1 assume !(0 == ~E_2~0); 7392#L539-1 assume !(0 == ~E_3~0); 7288#L544-1 assume !(0 == ~E_4~0); 7289#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7580#L240 assume !(1 == ~m_pc~0); 7611#L240-2 is_master_triggered_~__retres1~0 := 0; 7615#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7546#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7547#L627 assume !(0 != activate_threads_~tmp~1); 7677#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7379#L259 assume !(1 == ~t1_pc~0); 7363#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 7364#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7383#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7690#L635 assume !(0 != activate_threads_~tmp___0~0); 7721#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7510#L278 assume !(1 == ~t2_pc~0); 7497#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 7498#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7332#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7281#L643 assume !(0 != activate_threads_~tmp___1~0); 7282#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7283#L297 assume !(1 == ~t3_pc~0); 7487#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 7486#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7484#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7442#L651 assume !(0 != activate_threads_~tmp___2~0); 7431#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7432#L316 assume 1 == ~t4_pc~0; 7629#L317 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7630#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7628#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7594#L659 assume !(0 != activate_threads_~tmp___3~0); 7595#L659-2 assume !(1 == ~M_E~0); 7488#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7389#L567-1 assume !(1 == ~T2_E~0); 7390#L572-1 assume !(1 == ~T3_E~0); 7286#L577-1 assume !(1 == ~T4_E~0); 7287#L582-1 assume !(1 == ~E_M~0); 7338#L587-1 assume !(1 == ~E_1~0); 7339#L592-1 assume !(1 == ~E_2~0); 7508#L597-1 assume !(1 == ~E_3~0); 7509#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7646#L793-1 [2019-12-07 12:35:49,846 INFO L796 eck$LassoCheckResult]: Loop: 7646#L793-1 assume !false; 7443#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7393#L479 assume !false; 7394#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7422#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7370#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7696#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7672#L418 assume !(0 != eval_~tmp~0); 7581#L494 start_simulation_~kernel_st~0 := 2; 7387#L336-1 start_simulation_~kernel_st~0 := 3; 7388#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7625#L504-4 assume !(0 == ~T1_E~0); 7519#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7520#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7418#L519-3 assume !(0 == ~T4_E~0); 7419#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7482#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7354#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7355#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7669#L544-3 assume !(0 == ~E_4~0); 7587#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7588#L240-18 assume !(1 == ~m_pc~0); 7589#L240-20 is_master_triggered_~__retres1~0 := 0; 7590#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7561#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7562#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7655#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7656#L259-18 assume 1 == ~t1_pc~0; 7684#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7685#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7687#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7688#L635-18 assume !(0 != activate_threads_~tmp___0~0); 7713#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7344#L278-18 assume !(1 == ~t2_pc~0); 7341#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 7342#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7300#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7301#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7401#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7402#L297-18 assume 1 == ~t3_pc~0; 7477#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7479#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7480#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7481#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7527#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7528#L316-18 assume 1 == ~t4_pc~0; 7617#L317-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7618#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7616#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7548#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7549#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7490#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7347#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7348#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7408#L577-3 assume !(1 == ~T4_E~0); 7409#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7326#L587-3 assume !(1 == ~E_1~0); 7327#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7511#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7512#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7435#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7425#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7375#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7702#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 7719#L812 assume !(0 == start_simulation_~tmp~3); 8337#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7426#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7385#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7706#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 7689#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7343#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 7290#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 7291#L825 assume !(0 != start_simulation_~tmp___0~1); 7646#L793-1 [2019-12-07 12:35:49,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,846 INFO L82 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2019-12-07 12:35:49,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589788056] [2019-12-07 12:35:49,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589788056] [2019-12-07 12:35:49,861 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,861 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:49,861 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95521785] [2019-12-07 12:35:49,861 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:49,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,862 INFO L82 PathProgramCache]: Analyzing trace with hash 921541866, now seen corresponding path program 1 times [2019-12-07 12:35:49,862 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,862 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57479725] [2019-12-07 12:35:49,862 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:49,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:49,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:49,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57479725] [2019-12-07 12:35:49,878 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:49,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:49,878 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953435508] [2019-12-07 12:35:49,878 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:49,878 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:49,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:49,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:49,878 INFO L87 Difference]: Start difference. First operand 1273 states and 1875 transitions. cyclomatic complexity: 606 Second operand 3 states. [2019-12-07 12:35:49,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:49,924 INFO L93 Difference]: Finished difference Result 2324 states and 3400 transitions. [2019-12-07 12:35:49,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:49,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2324 states and 3400 transitions. [2019-12-07 12:35:49,939 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2240 [2019-12-07 12:35:49,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2324 states to 2324 states and 3400 transitions. [2019-12-07 12:35:49,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2324 [2019-12-07 12:35:49,958 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2324 [2019-12-07 12:35:49,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2324 states and 3400 transitions. [2019-12-07 12:35:49,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:49,961 INFO L688 BuchiCegarLoop]: Abstraction has 2324 states and 3400 transitions. [2019-12-07 12:35:49,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2324 states and 3400 transitions. [2019-12-07 12:35:49,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2324 to 2316. [2019-12-07 12:35:49,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2316 states. [2019-12-07 12:35:49,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2316 states to 2316 states and 3392 transitions. [2019-12-07 12:35:49,988 INFO L711 BuchiCegarLoop]: Abstraction has 2316 states and 3392 transitions. [2019-12-07 12:35:49,989 INFO L591 BuchiCegarLoop]: Abstraction has 2316 states and 3392 transitions. [2019-12-07 12:35:49,989 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 12:35:49,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2316 states and 3392 transitions. [2019-12-07 12:35:49,996 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:49,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:49,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:49,997 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,997 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:49,997 INFO L794 eck$LassoCheckResult]: Stem: 11261#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11160#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11161#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10982#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 10983#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11030#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11087#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10986#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10987#L363-1 assume !(0 == ~M_E~0); 11281#L504-1 assume !(0 == ~T1_E~0); 11120#L509-1 assume !(0 == ~T2_E~0); 11121#L514-1 assume !(0 == ~T3_E~0); 11040#L519-1 assume !(0 == ~T4_E~0); 11041#L524-1 assume !(0 == ~E_M~0); 11093#L529-1 assume !(0 == ~E_1~0); 10996#L534-1 assume !(0 == ~E_2~0); 10997#L539-1 assume !(0 == ~E_3~0); 10892#L544-1 assume !(0 == ~E_4~0); 10893#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11190#L240 assume !(1 == ~m_pc~0); 11218#L240-2 is_master_triggered_~__retres1~0 := 0; 11220#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11156#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11157#L627 assume !(0 != activate_threads_~tmp~1); 11282#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10984#L259 assume !(1 == ~t1_pc~0); 10968#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 10969#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10988#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11295#L635 assume !(0 != activate_threads_~tmp___0~0); 11344#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11117#L278 assume !(1 == ~t2_pc~0); 11103#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 11104#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10936#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10885#L643 assume !(0 != activate_threads_~tmp___1~0); 10886#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10887#L297 assume !(1 == ~t3_pc~0); 11091#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 11090#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11088#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11046#L651 assume !(0 != activate_threads_~tmp___2~0); 11035#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11036#L316 assume !(1 == ~t4_pc~0); 11343#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 11342#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11237#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11203#L659 assume !(0 != activate_threads_~tmp___3~0); 11204#L659-2 assume !(1 == ~M_E~0); 11092#L562-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10994#L567-1 assume !(1 == ~T2_E~0); 10995#L572-1 assume !(1 == ~T3_E~0); 10888#L577-1 assume !(1 == ~T4_E~0); 10889#L582-1 assume !(1 == ~E_M~0); 10943#L587-1 assume !(1 == ~E_1~0); 10944#L592-1 assume !(1 == ~E_2~0); 11114#L597-1 assume !(1 == ~E_3~0); 11115#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11345#L793-1 [2019-12-07 12:35:49,997 INFO L796 eck$LassoCheckResult]: Loop: 11345#L793-1 assume !false; 12921#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 12918#L479 assume !false; 11301#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11026#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 10975#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11302#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11276#L418 assume !(0 != eval_~tmp~0); 11278#L494 start_simulation_~kernel_st~0 := 2; 13019#L336-1 start_simulation_~kernel_st~0 := 3; 13018#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11233#L504-4 assume !(0 == ~T1_E~0); 11126#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11127#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11022#L519-3 assume !(0 == ~T4_E~0); 11023#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11086#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10956#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10957#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11015#L544-3 assume !(0 == ~E_4~0); 11016#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11198#L240-18 assume !(1 == ~m_pc~0); 11199#L240-20 is_master_triggered_~__retres1~0 := 0; 11200#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11171#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11172#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11259#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11260#L259-18 assume 1 == ~t1_pc~0; 11289#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11290#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11292#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11293#L635-18 assume !(0 != activate_threads_~tmp___0~0); 11331#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10949#L278-18 assume !(1 == ~t2_pc~0); 10946#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 10947#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10904#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10905#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11006#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11007#L297-18 assume 1 == ~t3_pc~0; 11081#L298-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11083#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11084#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11085#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11134#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11135#L316-18 assume !(1 == ~t4_pc~0); 11319#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 11320#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11224#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11158#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11159#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 11094#L562-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11095#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13059#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13058#L577-3 assume !(1 == ~T4_E~0); 11194#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10930#L587-3 assume !(1 == ~E_1~0); 10931#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11118#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11119#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11039#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11029#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 10980#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11308#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 11326#L812 assume !(0 == start_simulation_~tmp~3); 11327#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 12944#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 12938#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 12936#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 12934#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12932#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 12928#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 12926#L825 assume !(0 != start_simulation_~tmp___0~1); 11345#L793-1 [2019-12-07 12:35:49,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:49,997 INFO L82 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2019-12-07 12:35:49,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:49,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706227743] [2019-12-07 12:35:49,998 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,015 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706227743] [2019-12-07 12:35:50,015 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,015 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:50,015 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783056612] [2019-12-07 12:35:50,016 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:50,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,016 INFO L82 PathProgramCache]: Analyzing trace with hash 613102857, now seen corresponding path program 1 times [2019-12-07 12:35:50,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,016 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999766126] [2019-12-07 12:35:50,016 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,038 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999766126] [2019-12-07 12:35:50,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:50,039 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201674300] [2019-12-07 12:35:50,039 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,039 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:50,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:50,039 INFO L87 Difference]: Start difference. First operand 2316 states and 3392 transitions. cyclomatic complexity: 1084 Second operand 3 states. [2019-12-07 12:35:50,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,060 INFO L93 Difference]: Finished difference Result 2316 states and 3366 transitions. [2019-12-07 12:35:50,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:50,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2316 states and 3366 transitions. [2019-12-07 12:35:50,074 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2316 states to 2316 states and 3366 transitions. [2019-12-07 12:35:50,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2316 [2019-12-07 12:35:50,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2316 [2019-12-07 12:35:50,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2316 states and 3366 transitions. [2019-12-07 12:35:50,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:50,095 INFO L688 BuchiCegarLoop]: Abstraction has 2316 states and 3366 transitions. [2019-12-07 12:35:50,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2316 states and 3366 transitions. [2019-12-07 12:35:50,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2316 to 2316. [2019-12-07 12:35:50,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2316 states. [2019-12-07 12:35:50,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2316 states to 2316 states and 3366 transitions. [2019-12-07 12:35:50,122 INFO L711 BuchiCegarLoop]: Abstraction has 2316 states and 3366 transitions. [2019-12-07 12:35:50,123 INFO L591 BuchiCegarLoop]: Abstraction has 2316 states and 3366 transitions. [2019-12-07 12:35:50,123 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 12:35:50,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2316 states and 3366 transitions. [2019-12-07 12:35:50,129 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:50,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:50,131 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,131 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,131 INFO L794 eck$LassoCheckResult]: Stem: 15892#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 15794#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15795#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15618#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 15619#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15667#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15723#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15622#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15623#L363-1 assume !(0 == ~M_E~0); 15912#L504-1 assume !(0 == ~T1_E~0); 15757#L509-1 assume !(0 == ~T2_E~0); 15758#L514-1 assume !(0 == ~T3_E~0); 15677#L519-1 assume !(0 == ~T4_E~0); 15678#L524-1 assume !(0 == ~E_M~0); 15729#L529-1 assume !(0 == ~E_1~0); 15632#L534-1 assume !(0 == ~E_2~0); 15633#L539-1 assume !(0 == ~E_3~0); 15531#L544-1 assume !(0 == ~E_4~0); 15532#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15825#L240 assume !(1 == ~m_pc~0); 15852#L240-2 is_master_triggered_~__retres1~0 := 0; 15854#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15790#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15791#L627 assume !(0 != activate_threads_~tmp~1); 15915#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15620#L259 assume !(1 == ~t1_pc~0); 15604#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 15605#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15624#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15929#L635 assume !(0 != activate_threads_~tmp___0~0); 15981#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15754#L278 assume !(1 == ~t2_pc~0); 15740#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 15741#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15575#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15524#L643 assume !(0 != activate_threads_~tmp___1~0); 15525#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15526#L297 assume !(1 == ~t3_pc~0); 15727#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 15726#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15724#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15683#L651 assume !(0 != activate_threads_~tmp___2~0); 15672#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15673#L316 assume !(1 == ~t4_pc~0); 15980#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 15979#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15870#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15837#L659 assume !(0 != activate_threads_~tmp___3~0); 15838#L659-2 assume !(1 == ~M_E~0); 15728#L562-1 assume !(1 == ~T1_E~0); 15630#L567-1 assume !(1 == ~T2_E~0); 15631#L572-1 assume !(1 == ~T3_E~0); 15527#L577-1 assume !(1 == ~T4_E~0); 15528#L582-1 assume !(1 == ~E_M~0); 15581#L587-1 assume !(1 == ~E_1~0); 15582#L592-1 assume !(1 == ~E_2~0); 15752#L597-1 assume !(1 == ~E_3~0); 15753#L602-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15982#L793-1 [2019-12-07 12:35:50,131 INFO L796 eck$LassoCheckResult]: Loop: 15982#L793-1 assume !false; 16638#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 16531#L479 assume !false; 16635#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16633#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16627#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16626#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 16624#L418 assume !(0 != eval_~tmp~0); 16625#L494 start_simulation_~kernel_st~0 := 2; 17368#L336-1 start_simulation_~kernel_st~0 := 3; 17367#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17366#L504-4 assume !(0 == ~T1_E~0); 17365#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17363#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17361#L519-3 assume !(0 == ~T4_E~0); 17359#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17357#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17355#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17353#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17351#L544-3 assume !(0 == ~E_4~0); 17349#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17347#L240-18 assume !(1 == ~m_pc~0); 17345#L240-20 is_master_triggered_~__retres1~0 := 0; 17343#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17341#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17339#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17336#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17334#L259-18 assume 1 == ~t1_pc~0; 17331#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 17329#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17327#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17325#L635-18 assume !(0 != activate_threads_~tmp___0~0); 17322#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17320#L278-18 assume !(1 == ~t2_pc~0); 17318#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 17316#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17314#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 17312#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17309#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17307#L297-18 assume !(1 == ~t3_pc~0); 17304#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 17302#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17300#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17298#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17295#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17293#L316-18 assume !(1 == ~t4_pc~0); 17291#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 17289#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17287#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17285#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17282#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 17280#L562-3 assume !(1 == ~T1_E~0); 17278#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17276#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17274#L577-3 assume !(1 == ~T4_E~0); 17272#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17270#L587-3 assume !(1 == ~E_1~0); 17268#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17266#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17264#L602-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17262#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 17251#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 17246#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 17244#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 17239#L812 assume !(0 == start_simulation_~tmp~3); 17237#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16658#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16652#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16650#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 16647#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16645#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 16643#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 16641#L825 assume !(0 != start_simulation_~tmp___0~1); 15982#L793-1 [2019-12-07 12:35:50,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,131 INFO L82 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2019-12-07 12:35:50,131 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274259372] [2019-12-07 12:35:50,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,149 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274259372] [2019-12-07 12:35:50,149 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,149 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 12:35:50,150 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331412367] [2019-12-07 12:35:50,150 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:50,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,150 INFO L82 PathProgramCache]: Analyzing trace with hash -796692698, now seen corresponding path program 1 times [2019-12-07 12:35:50,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603810039] [2019-12-07 12:35:50,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603810039] [2019-12-07 12:35:50,165 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,166 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:50,166 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620079814] [2019-12-07 12:35:50,166 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,166 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,166 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:50,166 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:50,166 INFO L87 Difference]: Start difference. First operand 2316 states and 3366 transitions. cyclomatic complexity: 1058 Second operand 3 states. [2019-12-07 12:35:50,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,194 INFO L93 Difference]: Finished difference Result 2316 states and 3320 transitions. [2019-12-07 12:35:50,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:50,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2316 states and 3320 transitions. [2019-12-07 12:35:50,202 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2316 states to 2316 states and 3320 transitions. [2019-12-07 12:35:50,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2316 [2019-12-07 12:35:50,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2316 [2019-12-07 12:35:50,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2316 states and 3320 transitions. [2019-12-07 12:35:50,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:50,218 INFO L688 BuchiCegarLoop]: Abstraction has 2316 states and 3320 transitions. [2019-12-07 12:35:50,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2316 states and 3320 transitions. [2019-12-07 12:35:50,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2316 to 2316. [2019-12-07 12:35:50,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2316 states. [2019-12-07 12:35:50,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2316 states to 2316 states and 3320 transitions. [2019-12-07 12:35:50,242 INFO L711 BuchiCegarLoop]: Abstraction has 2316 states and 3320 transitions. [2019-12-07 12:35:50,242 INFO L591 BuchiCegarLoop]: Abstraction has 2316 states and 3320 transitions. [2019-12-07 12:35:50,242 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 12:35:50,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2316 states and 3320 transitions. [2019-12-07 12:35:50,246 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:50,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:50,247 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,247 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,247 INFO L794 eck$LassoCheckResult]: Stem: 20530#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20431#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20432#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20261#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 20262#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20309#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20366#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20265#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20266#L363-1 assume !(0 == ~M_E~0); 20549#L504-1 assume !(0 == ~T1_E~0); 20395#L509-1 assume !(0 == ~T2_E~0); 20396#L514-1 assume !(0 == ~T3_E~0); 20320#L519-1 assume !(0 == ~T4_E~0); 20321#L524-1 assume !(0 == ~E_M~0); 20372#L529-1 assume !(0 == ~E_1~0); 20275#L534-1 assume !(0 == ~E_2~0); 20276#L539-1 assume !(0 == ~E_3~0); 20170#L544-1 assume !(0 == ~E_4~0); 20171#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20462#L240 assume !(1 == ~m_pc~0); 20490#L240-2 is_master_triggered_~__retres1~0 := 0; 20492#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20427#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20428#L627 assume !(0 != activate_threads_~tmp~1); 20550#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20263#L259 assume !(1 == ~t1_pc~0); 20247#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 20248#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20267#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20563#L635 assume !(0 != activate_threads_~tmp___0~0); 20617#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20392#L278 assume !(1 == ~t2_pc~0); 20380#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 20381#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20214#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20163#L643 assume !(0 != activate_threads_~tmp___1~0); 20164#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20165#L297 assume !(1 == ~t3_pc~0); 20370#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 20369#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20367#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20326#L651 assume !(0 != activate_threads_~tmp___2~0); 20315#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20316#L316 assume !(1 == ~t4_pc~0); 20615#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 20614#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20507#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20475#L659 assume !(0 != activate_threads_~tmp___3~0); 20476#L659-2 assume !(1 == ~M_E~0); 20371#L562-1 assume !(1 == ~T1_E~0); 20273#L567-1 assume !(1 == ~T2_E~0); 20274#L572-1 assume !(1 == ~T3_E~0); 20166#L577-1 assume !(1 == ~T4_E~0); 20167#L582-1 assume !(1 == ~E_M~0); 20222#L587-1 assume !(1 == ~E_1~0); 20223#L592-1 assume !(1 == ~E_2~0); 20390#L597-1 assume !(1 == ~E_3~0); 20391#L602-1 assume !(1 == ~E_4~0); 20618#L793-1 [2019-12-07 12:35:50,248 INFO L796 eck$LassoCheckResult]: Loop: 20618#L793-1 assume !false; 21616#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 21613#L479 assume !false; 21611#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21610#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21601#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21596#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 21590#L418 assume !(0 != eval_~tmp~0); 21591#L494 start_simulation_~kernel_st~0 := 2; 22301#L336-1 start_simulation_~kernel_st~0 := 3; 22300#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22299#L504-4 assume !(0 == ~T1_E~0); 22298#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22297#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22296#L519-3 assume !(0 == ~T4_E~0); 22295#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22294#L529-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22293#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22292#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22291#L544-3 assume !(0 == ~E_4~0); 22290#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22288#L240-18 assume !(1 == ~m_pc~0); 22286#L240-20 is_master_triggered_~__retres1~0 := 0; 22284#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22282#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22280#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22277#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22275#L259-18 assume 1 == ~t1_pc~0; 22272#L260-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22270#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22268#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22266#L635-18 assume !(0 != activate_threads_~tmp___0~0); 22262#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22258#L278-18 assume !(1 == ~t2_pc~0); 22252#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 22246#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22241#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22236#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22230#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22225#L297-18 assume !(1 == ~t3_pc~0); 22219#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 22213#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22208#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22203#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22197#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22192#L316-18 assume !(1 == ~t4_pc~0); 22187#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 22183#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22179#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22174#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22168#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 22163#L562-3 assume !(1 == ~T1_E~0); 22158#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22154#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22151#L577-3 assume !(1 == ~T4_E~0); 22109#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22105#L587-3 assume !(1 == ~E_1~0); 22074#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21854#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21853#L602-3 assume !(1 == ~E_4~0); 21852#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21849#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21844#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21842#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 21798#L812 assume !(0 == start_simulation_~tmp~3); 21795#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21752#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21743#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21738#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 21734#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21729#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 21722#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 21717#L825 assume !(0 != start_simulation_~tmp___0~1); 20618#L793-1 [2019-12-07 12:35:50,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,248 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2019-12-07 12:35:50,248 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,248 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396393960] [2019-12-07 12:35:50,248 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,277 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:50,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,278 INFO L82 PathProgramCache]: Analyzing trace with hash -1807809948, now seen corresponding path program 1 times [2019-12-07 12:35:50,278 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,278 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136551925] [2019-12-07 12:35:50,278 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,293 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136551925] [2019-12-07 12:35:50,293 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,293 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:50,293 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055066744] [2019-12-07 12:35:50,293 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,293 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,293 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:50,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:50,294 INFO L87 Difference]: Start difference. First operand 2316 states and 3320 transitions. cyclomatic complexity: 1012 Second operand 3 states. [2019-12-07 12:35:50,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,360 INFO L93 Difference]: Finished difference Result 4158 states and 5886 transitions. [2019-12-07 12:35:50,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:50,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4158 states and 5886 transitions. [2019-12-07 12:35:50,373 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4008 [2019-12-07 12:35:50,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4158 states to 4158 states and 5886 transitions. [2019-12-07 12:35:50,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4158 [2019-12-07 12:35:50,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4158 [2019-12-07 12:35:50,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4158 states and 5886 transitions. [2019-12-07 12:35:50,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:50,400 INFO L688 BuchiCegarLoop]: Abstraction has 4158 states and 5886 transitions. [2019-12-07 12:35:50,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4158 states and 5886 transitions. [2019-12-07 12:35:50,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4158 to 4122. [2019-12-07 12:35:50,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4122 states. [2019-12-07 12:35:50,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4122 states to 4122 states and 5838 transitions. [2019-12-07 12:35:50,444 INFO L711 BuchiCegarLoop]: Abstraction has 4122 states and 5838 transitions. [2019-12-07 12:35:50,444 INFO L591 BuchiCegarLoop]: Abstraction has 4122 states and 5838 transitions. [2019-12-07 12:35:50,444 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 12:35:50,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4122 states and 5838 transitions. [2019-12-07 12:35:50,452 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3980 [2019-12-07 12:35:50,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:50,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:50,453 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,453 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,454 INFO L794 eck$LassoCheckResult]: Stem: 27018#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 26924#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 26925#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26742#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 26743#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26791#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26850#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26746#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26747#L363-1 assume !(0 == ~M_E~0); 27037#L504-1 assume !(0 == ~T1_E~0); 26886#L509-1 assume !(0 == ~T2_E~0); 26887#L514-1 assume !(0 == ~T3_E~0); 26800#L519-1 assume !(0 == ~T4_E~0); 26801#L524-1 assume !(0 == ~E_M~0); 26857#L529-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26858#L534-1 assume !(0 == ~E_2~0); 27043#L539-1 assume !(0 == ~E_3~0); 27044#L544-1 assume !(0 == ~E_4~0); 26954#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26955#L240 assume !(1 == ~m_pc~0); 26980#L240-2 is_master_triggered_~__retres1~0 := 0; 26983#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26984#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27038#L627 assume !(0 != activate_threads_~tmp~1); 27039#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27138#L259 assume !(1 == ~t1_pc~0); 27139#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 27076#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27056#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27057#L635 assume !(0 != activate_threads_~tmp___0~0); 27128#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26881#L278 assume !(1 == ~t2_pc~0); 26882#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 26885#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26696#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 26643#L643 assume !(0 != activate_threads_~tmp___1~0); 26644#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27151#L297 assume !(1 == ~t3_pc~0); 27149#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 27148#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27147#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 26806#L651 assume !(0 != activate_threads_~tmp___2~0); 26807#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27116#L316 assume !(1 == ~t4_pc~0); 27117#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 27115#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26995#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 26969#L659 assume !(0 != activate_threads_~tmp___3~0); 26970#L659-2 assume !(1 == ~M_E~0); 26856#L562-1 assume !(1 == ~T1_E~0); 26754#L567-1 assume !(1 == ~T2_E~0); 26755#L572-1 assume !(1 == ~T3_E~0); 26647#L577-1 assume !(1 == ~T4_E~0); 26648#L582-1 assume !(1 == ~E_M~0); 26703#L587-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26704#L592-1 assume !(1 == ~E_2~0); 26878#L597-1 assume !(1 == ~E_3~0); 26879#L602-1 assume !(1 == ~E_4~0); 27122#L793-1 [2019-12-07 12:35:50,454 INFO L796 eck$LassoCheckResult]: Loop: 27122#L793-1 assume !false; 27967#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 27964#L479 assume !false; 27963#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27962#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27957#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27956#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 27954#L418 assume !(0 != eval_~tmp~0); 27955#L494 start_simulation_~kernel_st~0 := 2; 28158#L336-1 start_simulation_~kernel_st~0 := 3; 28157#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28156#L504-4 assume !(0 == ~T1_E~0); 28155#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28154#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28152#L519-3 assume !(0 == ~T4_E~0); 28150#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28128#L529-3 assume !(0 == ~E_1~0); 28129#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28153#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28151#L544-3 assume !(0 == ~E_4~0); 28149#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28148#L240-18 assume !(1 == ~m_pc~0); 28147#L240-20 is_master_triggered_~__retres1~0 := 0; 28146#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28144#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28142#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28140#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28138#L259-18 assume !(1 == ~t1_pc~0); 28135#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 28133#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28131#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28127#L635-18 assume !(0 != activate_threads_~tmp___0~0); 28125#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28123#L278-18 assume !(1 == ~t2_pc~0); 28121#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 28119#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28117#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28115#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28113#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28111#L297-18 assume !(1 == ~t3_pc~0); 28108#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 28106#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28104#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28101#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28099#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28097#L316-18 assume !(1 == ~t4_pc~0); 28095#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 28093#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28091#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28089#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28087#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 28085#L562-3 assume !(1 == ~T1_E~0); 28083#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28081#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28079#L577-3 assume !(1 == ~T4_E~0); 28076#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28046#L587-3 assume !(1 == ~E_1~0); 28044#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28042#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28040#L602-3 assume !(1 == ~E_4~0); 28038#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28005#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28000#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27998#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 27995#L812 assume !(0 == start_simulation_~tmp~3); 27992#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27990#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27984#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27982#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 27980#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27978#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 27974#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 27972#L825 assume !(0 != start_simulation_~tmp___0~1); 27122#L793-1 [2019-12-07 12:35:50,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,454 INFO L82 PathProgramCache]: Analyzing trace with hash 1909498888, now seen corresponding path program 1 times [2019-12-07 12:35:50,454 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,454 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511283067] [2019-12-07 12:35:50,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,465 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511283067] [2019-12-07 12:35:50,465 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,465 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:50,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028501735] [2019-12-07 12:35:50,466 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:50,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,466 INFO L82 PathProgramCache]: Analyzing trace with hash -1854897467, now seen corresponding path program 1 times [2019-12-07 12:35:50,466 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,466 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921170077] [2019-12-07 12:35:50,466 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921170077] [2019-12-07 12:35:50,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:35:50,489 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787894472] [2019-12-07 12:35:50,490 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,490 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:50,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:50,490 INFO L87 Difference]: Start difference. First operand 4122 states and 5838 transitions. cyclomatic complexity: 1724 Second operand 3 states. [2019-12-07 12:35:50,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,524 INFO L93 Difference]: Finished difference Result 2316 states and 3249 transitions. [2019-12-07 12:35:50,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:50,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2316 states and 3249 transitions. [2019-12-07 12:35:50,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2316 states to 2316 states and 3249 transitions. [2019-12-07 12:35:50,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2316 [2019-12-07 12:35:50,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2316 [2019-12-07 12:35:50,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2316 states and 3249 transitions. [2019-12-07 12:35:50,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:50,544 INFO L688 BuchiCegarLoop]: Abstraction has 2316 states and 3249 transitions. [2019-12-07 12:35:50,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2316 states and 3249 transitions. [2019-12-07 12:35:50,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2316 to 2316. [2019-12-07 12:35:50,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2316 states. [2019-12-07 12:35:50,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2316 states to 2316 states and 3249 transitions. [2019-12-07 12:35:50,567 INFO L711 BuchiCegarLoop]: Abstraction has 2316 states and 3249 transitions. [2019-12-07 12:35:50,567 INFO L591 BuchiCegarLoop]: Abstraction has 2316 states and 3249 transitions. [2019-12-07 12:35:50,567 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 12:35:50,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2316 states and 3249 transitions. [2019-12-07 12:35:50,571 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2232 [2019-12-07 12:35:50,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:50,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:50,572 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,572 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,572 INFO L794 eck$LassoCheckResult]: Stem: 33455#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 33360#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 33361#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33186#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 33187#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33235#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33291#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33190#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33191#L363-1 assume !(0 == ~M_E~0); 33475#L504-1 assume !(0 == ~T1_E~0); 33323#L509-1 assume !(0 == ~T2_E~0); 33324#L514-1 assume !(0 == ~T3_E~0); 33244#L519-1 assume !(0 == ~T4_E~0); 33245#L524-1 assume !(0 == ~E_M~0); 33297#L529-1 assume !(0 == ~E_1~0); 33200#L534-1 assume !(0 == ~E_2~0); 33201#L539-1 assume !(0 == ~E_3~0); 33097#L544-1 assume !(0 == ~E_4~0); 33098#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33390#L240 assume !(1 == ~m_pc~0); 33418#L240-2 is_master_triggered_~__retres1~0 := 0; 33420#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33356#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 33357#L627 assume !(0 != activate_threads_~tmp~1); 33476#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33188#L259 assume !(1 == ~t1_pc~0); 33172#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 33173#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33192#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 33487#L635 assume !(0 != activate_threads_~tmp___0~0); 33536#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33320#L278 assume !(1 == ~t2_pc~0); 33307#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 33308#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33141#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33090#L643 assume !(0 != activate_threads_~tmp___1~0); 33091#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33092#L297 assume !(1 == ~t3_pc~0); 33295#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 33294#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33292#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33250#L651 assume !(0 != activate_threads_~tmp___2~0); 33239#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33240#L316 assume !(1 == ~t4_pc~0); 33535#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 33534#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33433#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 33403#L659 assume !(0 != activate_threads_~tmp___3~0); 33404#L659-2 assume !(1 == ~M_E~0); 33296#L562-1 assume !(1 == ~T1_E~0); 33198#L567-1 assume !(1 == ~T2_E~0); 33199#L572-1 assume !(1 == ~T3_E~0); 33093#L577-1 assume !(1 == ~T4_E~0); 33094#L582-1 assume !(1 == ~E_M~0); 33147#L587-1 assume !(1 == ~E_1~0); 33148#L592-1 assume !(1 == ~E_2~0); 33318#L597-1 assume !(1 == ~E_3~0); 33319#L602-1 assume !(1 == ~E_4~0); 33537#L793-1 [2019-12-07 12:35:50,572 INFO L796 eck$LassoCheckResult]: Loop: 33537#L793-1 assume !false; 34444#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34407#L479 assume !false; 34441#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34439#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34433#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34432#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 34430#L418 assume !(0 != eval_~tmp~0); 34431#L494 start_simulation_~kernel_st~0 := 2; 34586#L336-1 start_simulation_~kernel_st~0 := 3; 34584#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 34582#L504-4 assume !(0 == ~T1_E~0); 34580#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34578#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34576#L519-3 assume !(0 == ~T4_E~0); 34573#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34571#L529-3 assume !(0 == ~E_1~0); 34569#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34567#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34565#L544-3 assume !(0 == ~E_4~0); 34563#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34561#L240-18 assume !(1 == ~m_pc~0); 34559#L240-20 is_master_triggered_~__retres1~0 := 0; 34557#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34555#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34553#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34551#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34549#L259-18 assume !(1 == ~t1_pc~0); 34545#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 34543#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34541#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34539#L635-18 assume !(0 != activate_threads_~tmp___0~0); 34537#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34535#L278-18 assume !(1 == ~t2_pc~0); 34533#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 34531#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34529#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34527#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 34525#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34523#L297-18 assume !(1 == ~t3_pc~0); 34520#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 34518#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34516#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34514#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 34512#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34510#L316-18 assume !(1 == ~t4_pc~0); 34508#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 34507#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34506#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34505#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 34504#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 34503#L562-3 assume !(1 == ~T1_E~0); 34501#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34499#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34497#L577-3 assume !(1 == ~T4_E~0); 34495#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34493#L587-3 assume !(1 == ~E_1~0); 34491#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34488#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34486#L602-3 assume !(1 == ~E_4~0); 34484#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34479#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34474#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34472#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 34469#L812 assume !(0 == start_simulation_~tmp~3); 34466#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34464#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34458#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34456#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 34453#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34451#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 34449#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 34447#L825 assume !(0 != start_simulation_~tmp___0~1); 33537#L793-1 [2019-12-07 12:35:50,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,572 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2019-12-07 12:35:50,572 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,573 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922932575] [2019-12-07 12:35:50,573 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,588 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:50,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,588 INFO L82 PathProgramCache]: Analyzing trace with hash -1854897467, now seen corresponding path program 2 times [2019-12-07 12:35:50,588 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565949873] [2019-12-07 12:35:50,589 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,608 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565949873] [2019-12-07 12:35:50,608 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,608 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:35:50,608 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208097067] [2019-12-07 12:35:50,609 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,609 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:35:50,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:35:50,609 INFO L87 Difference]: Start difference. First operand 2316 states and 3249 transitions. cyclomatic complexity: 941 Second operand 5 states. [2019-12-07 12:35:50,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,687 INFO L93 Difference]: Finished difference Result 4088 states and 5665 transitions. [2019-12-07 12:35:50,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 12:35:50,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4088 states and 5665 transitions. [2019-12-07 12:35:50,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3980 [2019-12-07 12:35:50,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4088 states to 4088 states and 5665 transitions. [2019-12-07 12:35:50,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4088 [2019-12-07 12:35:50,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4088 [2019-12-07 12:35:50,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4088 states and 5665 transitions. [2019-12-07 12:35:50,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:50,735 INFO L688 BuchiCegarLoop]: Abstraction has 4088 states and 5665 transitions. [2019-12-07 12:35:50,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4088 states and 5665 transitions. [2019-12-07 12:35:50,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4088 to 2340. [2019-12-07 12:35:50,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2340 states. [2019-12-07 12:35:50,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2340 states to 2340 states and 3273 transitions. [2019-12-07 12:35:50,769 INFO L711 BuchiCegarLoop]: Abstraction has 2340 states and 3273 transitions. [2019-12-07 12:35:50,769 INFO L591 BuchiCegarLoop]: Abstraction has 2340 states and 3273 transitions. [2019-12-07 12:35:50,769 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 12:35:50,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2340 states and 3273 transitions. [2019-12-07 12:35:50,773 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2256 [2019-12-07 12:35:50,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:50,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:50,774 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,774 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:50,774 INFO L794 eck$LassoCheckResult]: Stem: 39903#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 39792#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 39793#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 39607#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 39608#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39656#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39714#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39611#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39612#L363-1 assume !(0 == ~M_E~0); 39926#L504-1 assume !(0 == ~T1_E~0); 39748#L509-1 assume !(0 == ~T2_E~0); 39749#L514-1 assume !(0 == ~T3_E~0); 39667#L519-1 assume !(0 == ~T4_E~0); 39668#L524-1 assume !(0 == ~E_M~0); 39720#L529-1 assume !(0 == ~E_1~0); 39621#L534-1 assume !(0 == ~E_2~0); 39622#L539-1 assume !(0 == ~E_3~0); 39517#L544-1 assume !(0 == ~E_4~0); 39518#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39822#L240 assume !(1 == ~m_pc~0); 39858#L240-2 is_master_triggered_~__retres1~0 := 0; 39861#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39786#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 39787#L627 assume !(0 != activate_threads_~tmp~1); 39927#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39609#L259 assume !(1 == ~t1_pc~0); 39592#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 39593#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39613#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 39938#L635 assume !(0 != activate_threads_~tmp___0~0); 40011#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39745#L278 assume !(1 == ~t2_pc~0); 39731#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 39732#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39561#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 39510#L643 assume !(0 != activate_threads_~tmp___1~0); 39511#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39512#L297 assume !(1 == ~t3_pc~0); 39718#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 39717#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39715#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 39673#L651 assume !(0 != activate_threads_~tmp___2~0); 39661#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39662#L316 assume !(1 == ~t4_pc~0); 40010#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 40009#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39879#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39840#L659 assume !(0 != activate_threads_~tmp___3~0); 39841#L659-2 assume !(1 == ~M_E~0); 39719#L562-1 assume !(1 == ~T1_E~0); 39619#L567-1 assume !(1 == ~T2_E~0); 39620#L572-1 assume !(1 == ~T3_E~0); 39513#L577-1 assume !(1 == ~T4_E~0); 39514#L582-1 assume !(1 == ~E_M~0); 39566#L587-1 assume !(1 == ~E_1~0); 39567#L592-1 assume !(1 == ~E_2~0); 39743#L597-1 assume !(1 == ~E_3~0); 39744#L602-1 assume !(1 == ~E_4~0); 39891#L793-1 [2019-12-07 12:35:50,774 INFO L796 eck$LassoCheckResult]: Loop: 39891#L793-1 assume !false; 39674#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 39623#L479 assume !false; 39624#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41371#L376 assume !(0 == ~m_st~0); 41367#L380 assume !(0 == ~t1_st~0); 41368#L384 assume !(0 == ~t2_st~0); 41369#L388 assume !(0 == ~t3_st~0); 41370#L392 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 39946#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 39947#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 40006#L418 assume !(0 != eval_~tmp~0); 41363#L494 start_simulation_~kernel_st~0 := 2; 41412#L336-1 start_simulation_~kernel_st~0 := 3; 41413#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 39872#L504-4 assume !(0 == ~T1_E~0); 39873#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40017#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40018#L519-3 assume !(0 == ~T4_E~0); 39941#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39942#L529-3 assume !(0 == ~E_1~0); 39583#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39584#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39641#L544-3 assume !(0 == ~E_4~0); 39642#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39837#L240-18 assume !(1 == ~m_pc~0); 39838#L240-20 is_master_triggered_~__retres1~0 := 0; 39875#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39876#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 39899#L627-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 39900#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39966#L259-18 assume !(1 == ~t1_pc~0); 39934#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 39969#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39970#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 39993#L635-18 assume !(0 != activate_threads_~tmp___0~0); 39994#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39572#L278-18 assume !(1 == ~t2_pc~0); 39573#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 41753#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41752#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 41751#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41750#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41749#L297-18 assume !(1 == ~t3_pc~0); 41747#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 41746#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41745#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 41744#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 39763#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39764#L316-18 assume !(1 == ~t4_pc~0); 39977#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 39978#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39864#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39865#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 39790#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 39791#L562-3 assume !(1 == ~T1_E~0); 39576#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39577#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39639#L577-3 assume !(1 == ~T4_E~0); 39640#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39555#L587-3 assume !(1 == ~E_1~0); 39556#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39746#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39747#L602-3 assume !(1 == ~E_4~0); 39665#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 39666#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41799#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41797#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 41790#L812 assume !(0 == start_simulation_~tmp~3); 39626#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 39657#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 39615#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 39958#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 39937#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39571#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 39519#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 39520#L825 assume !(0 != start_simulation_~tmp___0~1); 39891#L793-1 [2019-12-07 12:35:50,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,774 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2019-12-07 12:35:50,775 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131536279] [2019-12-07 12:35:50,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:50,792 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:50,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:50,793 INFO L82 PathProgramCache]: Analyzing trace with hash -400475823, now seen corresponding path program 1 times [2019-12-07 12:35:50,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:50,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41988297] [2019-12-07 12:35:50,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:50,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:50,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:50,834 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41988297] [2019-12-07 12:35:50,835 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:50,835 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 12:35:50,835 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721329136] [2019-12-07 12:35:50,835 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:50,835 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:50,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 12:35:50,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 12:35:50,836 INFO L87 Difference]: Start difference. First operand 2340 states and 3273 transitions. cyclomatic complexity: 941 Second operand 5 states. [2019-12-07 12:35:50,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:50,962 INFO L93 Difference]: Finished difference Result 4576 states and 6346 transitions. [2019-12-07 12:35:50,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 12:35:50,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4576 states and 6346 transitions. [2019-12-07 12:35:50,979 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4476 [2019-12-07 12:35:51,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4576 states to 4576 states and 6346 transitions. [2019-12-07 12:35:51,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4576 [2019-12-07 12:35:51,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4576 [2019-12-07 12:35:51,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4576 states and 6346 transitions. [2019-12-07 12:35:51,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:51,008 INFO L688 BuchiCegarLoop]: Abstraction has 4576 states and 6346 transitions. [2019-12-07 12:35:51,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4576 states and 6346 transitions. [2019-12-07 12:35:51,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4576 to 2412. [2019-12-07 12:35:51,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2412 states. [2019-12-07 12:35:51,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2412 states to 2412 states and 3324 transitions. [2019-12-07 12:35:51,039 INFO L711 BuchiCegarLoop]: Abstraction has 2412 states and 3324 transitions. [2019-12-07 12:35:51,039 INFO L591 BuchiCegarLoop]: Abstraction has 2412 states and 3324 transitions. [2019-12-07 12:35:51,039 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 12:35:51,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2412 states and 3324 transitions. [2019-12-07 12:35:51,044 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2328 [2019-12-07 12:35:51,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:51,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:51,045 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,045 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,045 INFO L794 eck$LassoCheckResult]: Stem: 46824#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 46712#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 46713#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 46536#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 46537#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46585#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46643#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46540#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46541#L363-1 assume !(0 == ~M_E~0); 46845#L504-1 assume !(0 == ~T1_E~0); 46674#L509-1 assume !(0 == ~T2_E~0); 46675#L514-1 assume !(0 == ~T3_E~0); 46596#L519-1 assume !(0 == ~T4_E~0); 46597#L524-1 assume !(0 == ~E_M~0); 46649#L529-1 assume !(0 == ~E_1~0); 46550#L534-1 assume !(0 == ~E_2~0); 46551#L539-1 assume !(0 == ~E_3~0); 46446#L544-1 assume !(0 == ~E_4~0); 46447#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46742#L240 assume !(1 == ~m_pc~0); 46778#L240-2 is_master_triggered_~__retres1~0 := 0; 46781#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46708#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 46709#L627 assume !(0 != activate_threads_~tmp~1); 46847#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46538#L259 assume !(1 == ~t1_pc~0); 46522#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 46523#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46542#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 46860#L635 assume !(0 != activate_threads_~tmp___0~0); 46915#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46671#L278 assume !(1 == ~t2_pc~0); 46658#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 46659#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46490#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 46439#L643 assume !(0 != activate_threads_~tmp___1~0); 46440#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46441#L297 assume !(1 == ~t3_pc~0); 46647#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 46646#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46644#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 46602#L651 assume !(0 != activate_threads_~tmp___2~0); 46590#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46591#L316 assume !(1 == ~t4_pc~0); 46913#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 46912#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46795#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 46756#L659 assume !(0 != activate_threads_~tmp___3~0); 46757#L659-2 assume !(1 == ~M_E~0); 46648#L562-1 assume !(1 == ~T1_E~0); 46548#L567-1 assume !(1 == ~T2_E~0); 46549#L572-1 assume !(1 == ~T3_E~0); 46442#L577-1 assume !(1 == ~T4_E~0); 46443#L582-1 assume !(1 == ~E_M~0); 46495#L587-1 assume !(1 == ~E_1~0); 46496#L592-1 assume !(1 == ~E_2~0); 46668#L597-1 assume !(1 == ~E_3~0); 46669#L602-1 assume !(1 == ~E_4~0); 46916#L793-1 [2019-12-07 12:35:51,045 INFO L796 eck$LassoCheckResult]: Loop: 46916#L793-1 assume !false; 47728#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 47131#L479 assume !false; 47727#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 47726#L376 assume !(0 == ~m_st~0); 47721#L380 assume !(0 == ~t1_st~0); 47722#L384 assume !(0 == ~t2_st~0); 47725#L388 assume !(0 == ~t3_st~0); 47723#L392 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 47724#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 47713#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 47714#L418 assume !(0 != eval_~tmp~0); 47845#L494 start_simulation_~kernel_st~0 := 2; 47844#L336-1 start_simulation_~kernel_st~0 := 3; 47843#L504-2 assume 0 == ~M_E~0;~M_E~0 := 1; 47842#L504-4 assume !(0 == ~T1_E~0); 47841#L509-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47840#L514-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47839#L519-3 assume !(0 == ~T4_E~0); 47838#L524-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47837#L529-3 assume !(0 == ~E_1~0); 47836#L534-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47835#L539-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47834#L544-3 assume !(0 == ~E_4~0); 47833#L549-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47832#L240-18 assume !(1 == ~m_pc~0); 47831#L240-20 is_master_triggered_~__retres1~0 := 0; 47830#L251-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47829#L252-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 47828#L627-18 assume !(0 != activate_threads_~tmp~1); 47827#L627-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47825#L259-18 assume !(1 == ~t1_pc~0); 47822#L259-20 is_transmit1_triggered_~__retres1~1 := 0; 47820#L270-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47818#L271-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 47816#L635-18 assume !(0 != activate_threads_~tmp___0~0); 47814#L635-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47811#L278-18 assume !(1 == ~t2_pc~0); 47809#L278-20 is_transmit2_triggered_~__retres1~2 := 0; 47807#L289-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47805#L290-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 47803#L643-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 47801#L643-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47799#L297-18 assume !(1 == ~t3_pc~0); 47796#L297-20 is_transmit3_triggered_~__retres1~3 := 0; 47794#L308-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47792#L309-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 47790#L651-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 47788#L651-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 47786#L316-18 assume !(1 == ~t4_pc~0); 47783#L316-20 is_transmit4_triggered_~__retres1~4 := 0; 47781#L327-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47779#L328-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 47777#L659-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 47775#L659-20 assume 1 == ~M_E~0;~M_E~0 := 2; 47773#L562-3 assume !(1 == ~T1_E~0); 47771#L567-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47769#L572-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47767#L577-3 assume !(1 == ~T4_E~0); 47765#L582-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47763#L587-3 assume !(1 == ~E_1~0); 47761#L592-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47759#L597-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47757#L602-3 assume !(1 == ~E_4~0); 47755#L607-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 47752#L376-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 47747#L403-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 47745#L404-1 start_simulation_#t~ret13 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 47742#L812 assume !(0 == start_simulation_~tmp~3); 47740#L812-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret12, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 47739#L376-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 47734#L403-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 47733#L404-2 stop_simulation_#t~ret12 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret12;havoc stop_simulation_#t~ret12; 47732#L767 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47731#L774 stop_simulation_#res := stop_simulation_~__retres2~0; 47730#L775 start_simulation_#t~ret14 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 47729#L825 assume !(0 != start_simulation_~tmp___0~1); 46916#L793-1 [2019-12-07 12:35:51,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,045 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2019-12-07 12:35:51,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,046 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200127004] [2019-12-07 12:35:51,046 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,058 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,058 INFO L82 PathProgramCache]: Analyzing trace with hash 1538686223, now seen corresponding path program 1 times [2019-12-07 12:35:51,058 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,058 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562401364] [2019-12-07 12:35:51,058 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:51,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:51,075 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562401364] [2019-12-07 12:35:51,075 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:51,076 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:51,076 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007752010] [2019-12-07 12:35:51,076 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 12:35:51,076 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:51,076 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:51,076 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:51,076 INFO L87 Difference]: Start difference. First operand 2412 states and 3324 transitions. cyclomatic complexity: 920 Second operand 3 states. [2019-12-07 12:35:51,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:51,105 INFO L93 Difference]: Finished difference Result 4022 states and 5466 transitions. [2019-12-07 12:35:51,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:51,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4022 states and 5466 transitions. [2019-12-07 12:35:51,115 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3920 [2019-12-07 12:35:51,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4022 states to 4022 states and 5466 transitions. [2019-12-07 12:35:51,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4022 [2019-12-07 12:35:51,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4022 [2019-12-07 12:35:51,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4022 states and 5466 transitions. [2019-12-07 12:35:51,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:51,129 INFO L688 BuchiCegarLoop]: Abstraction has 4022 states and 5466 transitions. [2019-12-07 12:35:51,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4022 states and 5466 transitions. [2019-12-07 12:35:51,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4022 to 3910. [2019-12-07 12:35:51,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3910 states. [2019-12-07 12:35:51,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3910 states to 3910 states and 5320 transitions. [2019-12-07 12:35:51,169 INFO L711 BuchiCegarLoop]: Abstraction has 3910 states and 5320 transitions. [2019-12-07 12:35:51,169 INFO L591 BuchiCegarLoop]: Abstraction has 3910 states and 5320 transitions. [2019-12-07 12:35:51,169 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 12:35:51,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3910 states and 5320 transitions. [2019-12-07 12:35:51,176 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3808 [2019-12-07 12:35:51,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:51,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:51,176 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,176 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,177 INFO L794 eck$LassoCheckResult]: Stem: 53262#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 53155#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53156#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 52978#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 52979#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53030#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53086#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52982#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52983#L363-1 assume !(0 == ~M_E~0); 53280#L504-1 assume !(0 == ~T1_E~0); 53115#L509-1 assume !(0 == ~T2_E~0); 53116#L514-1 assume !(0 == ~T3_E~0); 53040#L519-1 assume !(0 == ~T4_E~0); 53041#L524-1 assume !(0 == ~E_M~0); 53093#L529-1 assume !(0 == ~E_1~0); 52992#L534-1 assume !(0 == ~E_2~0); 52993#L539-1 assume !(0 == ~E_3~0); 52886#L544-1 assume !(0 == ~E_4~0); 52887#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53185#L240 assume !(1 == ~m_pc~0); 53223#L240-2 is_master_triggered_~__retres1~0 := 0; 53226#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53151#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 53152#L627 assume !(0 != activate_threads_~tmp~1); 53281#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52980#L259 assume !(1 == ~t1_pc~0); 52963#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 52964#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52984#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53293#L635 assume !(0 != activate_threads_~tmp___0~0); 53368#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53112#L278 assume !(1 == ~t2_pc~0); 53100#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 53101#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52930#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 52879#L643 assume !(0 != activate_threads_~tmp___1~0); 52880#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52881#L297 assume !(1 == ~t3_pc~0); 53091#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 53090#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53087#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53045#L651 assume !(0 != activate_threads_~tmp___2~0); 53034#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53035#L316 assume !(1 == ~t4_pc~0); 53364#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 53363#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53239#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53199#L659 assume !(0 != activate_threads_~tmp___3~0); 53200#L659-2 assume !(1 == ~M_E~0); 53092#L562-1 assume !(1 == ~T1_E~0); 52990#L567-1 assume !(1 == ~T2_E~0); 52991#L572-1 assume !(1 == ~T3_E~0); 52884#L577-1 assume !(1 == ~T4_E~0); 52885#L582-1 assume !(1 == ~E_M~0); 52938#L587-1 assume !(1 == ~E_1~0); 52939#L592-1 assume !(1 == ~E_2~0); 53110#L597-1 assume !(1 == ~E_3~0); 53111#L602-1 assume !(1 == ~E_4~0); 53369#L793-1 assume !false; 53881#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 53877#L479 [2019-12-07 12:35:51,177 INFO L796 eck$LassoCheckResult]: Loop: 53877#L479 assume !false; 53875#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53872#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53870#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53868#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 53866#L418 assume 0 != eval_~tmp~0; 53862#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 53859#L426 assume !(0 != eval_~tmp_ndt_1~0); 53817#L423 assume !(0 == ~t1_st~0); 53813#L437 assume !(0 == ~t2_st~0); 53792#L451 assume !(0 == ~t3_st~0); 53882#L465 assume !(0 == ~t4_st~0); 53877#L479 [2019-12-07 12:35:51,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,177 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2019-12-07 12:35:51,177 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,177 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567370977] [2019-12-07 12:35:51,177 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,189 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,190 INFO L82 PathProgramCache]: Analyzing trace with hash 1327245363, now seen corresponding path program 1 times [2019-12-07 12:35:51,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202743970] [2019-12-07 12:35:51,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,194 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,194 INFO L82 PathProgramCache]: Analyzing trace with hash -1604310376, now seen corresponding path program 1 times [2019-12-07 12:35:51,194 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,194 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673959076] [2019-12-07 12:35:51,195 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:51,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:51,215 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673959076] [2019-12-07 12:35:51,215 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:51,215 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:51,215 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633784981] [2019-12-07 12:35:51,265 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:51,265 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:51,265 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:51,265 INFO L87 Difference]: Start difference. First operand 3910 states and 5320 transitions. cyclomatic complexity: 1422 Second operand 3 states. [2019-12-07 12:35:51,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:51,299 INFO L93 Difference]: Finished difference Result 7187 states and 9698 transitions. [2019-12-07 12:35:51,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:51,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7187 states and 9698 transitions. [2019-12-07 12:35:51,319 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6988 [2019-12-07 12:35:51,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7187 states to 7187 states and 9698 transitions. [2019-12-07 12:35:51,335 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7187 [2019-12-07 12:35:51,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7187 [2019-12-07 12:35:51,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7187 states and 9698 transitions. [2019-12-07 12:35:51,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:51,343 INFO L688 BuchiCegarLoop]: Abstraction has 7187 states and 9698 transitions. [2019-12-07 12:35:51,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7187 states and 9698 transitions. [2019-12-07 12:35:51,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7187 to 6819. [2019-12-07 12:35:51,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6819 states. [2019-12-07 12:35:51,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6819 states to 6819 states and 9226 transitions. [2019-12-07 12:35:51,393 INFO L711 BuchiCegarLoop]: Abstraction has 6819 states and 9226 transitions. [2019-12-07 12:35:51,393 INFO L591 BuchiCegarLoop]: Abstraction has 6819 states and 9226 transitions. [2019-12-07 12:35:51,393 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 12:35:51,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6819 states and 9226 transitions. [2019-12-07 12:35:51,406 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6620 [2019-12-07 12:35:51,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:51,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:51,407 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,407 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,407 INFO L794 eck$LassoCheckResult]: Stem: 64379#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64264#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64265#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 64078#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 64079#L343-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 64131#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64189#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64082#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64083#L363-1 assume !(0 == ~M_E~0); 64399#L504-1 assume !(0 == ~T1_E~0); 64225#L509-1 assume !(0 == ~T2_E~0); 64226#L514-1 assume !(0 == ~T3_E~0); 64143#L519-1 assume !(0 == ~T4_E~0); 64144#L524-1 assume !(0 == ~E_M~0); 64195#L529-1 assume !(0 == ~E_1~0); 64091#L534-1 assume !(0 == ~E_2~0); 64092#L539-1 assume !(0 == ~E_3~0); 63991#L544-1 assume !(0 == ~E_4~0); 63992#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64295#L240 assume !(1 == ~m_pc~0); 64334#L240-2 is_master_triggered_~__retres1~0 := 0; 64336#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64260#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 64261#L627 assume !(0 != activate_threads_~tmp~1); 64400#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64080#L259 assume !(1 == ~t1_pc~0); 64066#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 64067#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64084#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 64411#L635 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 64486#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68111#L278 assume !(1 == ~t2_pc~0); 68110#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 68109#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68108#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 68107#L643 assume !(0 != activate_threads_~tmp___1~0); 68106#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 68105#L297 assume !(1 == ~t3_pc~0); 68103#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 68102#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 68101#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 68100#L651 assume !(0 != activate_threads_~tmp___2~0); 68099#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68098#L316 assume !(1 == ~t4_pc~0); 68097#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 68096#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 68095#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 68094#L659 assume !(0 != activate_threads_~tmp___3~0); 68093#L659-2 assume !(1 == ~M_E~0); 68092#L562-1 assume !(1 == ~T1_E~0); 68091#L567-1 assume !(1 == ~T2_E~0); 68090#L572-1 assume !(1 == ~T3_E~0); 68089#L577-1 assume !(1 == ~T4_E~0); 68088#L582-1 assume !(1 == ~E_M~0); 68087#L587-1 assume !(1 == ~E_1~0); 68086#L592-1 assume !(1 == ~E_2~0); 68084#L597-1 assume !(1 == ~E_3~0); 64477#L602-1 assume !(1 == ~E_4~0); 64478#L793-1 assume !false; 67971#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 67968#L479 [2019-12-07 12:35:51,407 INFO L796 eck$LassoCheckResult]: Loop: 67968#L479 assume !false; 67966#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 67963#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 67961#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 67959#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 67957#L418 assume 0 != eval_~tmp~0; 67953#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 67950#L426 assume !(0 != eval_~tmp_ndt_1~0); 67948#L423 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 67944#L440 assume !(0 != eval_~tmp_ndt_2~0); 67942#L437 assume !(0 == ~t2_st~0); 67940#L451 assume !(0 == ~t3_st~0); 67972#L465 assume !(0 == ~t4_st~0); 67968#L479 [2019-12-07 12:35:51,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,407 INFO L82 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2019-12-07 12:35:51,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348101930] [2019-12-07 12:35:51,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:51,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:51,418 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348101930] [2019-12-07 12:35:51,418 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:51,418 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:51,418 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569320975] [2019-12-07 12:35:51,418 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 12:35:51,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1950332302, now seen corresponding path program 1 times [2019-12-07 12:35:51,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406186697] [2019-12-07 12:35:51,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,424 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,475 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:51,475 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:51,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:51,475 INFO L87 Difference]: Start difference. First operand 6819 states and 9226 transitions. cyclomatic complexity: 2419 Second operand 3 states. [2019-12-07 12:35:51,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:51,488 INFO L93 Difference]: Finished difference Result 6762 states and 9149 transitions. [2019-12-07 12:35:51,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:51,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6762 states and 9149 transitions. [2019-12-07 12:35:51,507 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6620 [2019-12-07 12:35:51,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6762 states to 6762 states and 9149 transitions. [2019-12-07 12:35:51,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6762 [2019-12-07 12:35:51,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6762 [2019-12-07 12:35:51,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6762 states and 9149 transitions. [2019-12-07 12:35:51,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:51,525 INFO L688 BuchiCegarLoop]: Abstraction has 6762 states and 9149 transitions. [2019-12-07 12:35:51,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6762 states and 9149 transitions. [2019-12-07 12:35:51,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6762 to 6762. [2019-12-07 12:35:51,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6762 states. [2019-12-07 12:35:51,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6762 states to 6762 states and 9149 transitions. [2019-12-07 12:35:51,575 INFO L711 BuchiCegarLoop]: Abstraction has 6762 states and 9149 transitions. [2019-12-07 12:35:51,575 INFO L591 BuchiCegarLoop]: Abstraction has 6762 states and 9149 transitions. [2019-12-07 12:35:51,575 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 12:35:51,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6762 states and 9149 transitions. [2019-12-07 12:35:51,588 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6620 [2019-12-07 12:35:51,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:51,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:51,589 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,589 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,589 INFO L794 eck$LassoCheckResult]: Stem: 77954#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 77846#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77847#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 77667#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 77668#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77714#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77771#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77671#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77672#L363-1 assume !(0 == ~M_E~0); 77974#L504-1 assume !(0 == ~T1_E~0); 77807#L509-1 assume !(0 == ~T2_E~0); 77808#L514-1 assume !(0 == ~T3_E~0); 77725#L519-1 assume !(0 == ~T4_E~0); 77726#L524-1 assume !(0 == ~E_M~0); 77777#L529-1 assume !(0 == ~E_1~0); 77680#L534-1 assume !(0 == ~E_2~0); 77681#L539-1 assume !(0 == ~E_3~0); 77578#L544-1 assume !(0 == ~E_4~0); 77579#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 77878#L240 assume !(1 == ~m_pc~0); 77915#L240-2 is_master_triggered_~__retres1~0 := 0; 77917#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 77842#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 77843#L627 assume !(0 != activate_threads_~tmp~1); 77977#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77669#L259 assume !(1 == ~t1_pc~0); 77655#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 77656#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77673#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 77991#L635 assume !(0 != activate_threads_~tmp___0~0); 78057#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77804#L278 assume !(1 == ~t2_pc~0); 77789#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 77790#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77622#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 77571#L643 assume !(0 != activate_threads_~tmp___1~0); 77572#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 77573#L297 assume !(1 == ~t3_pc~0); 77775#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 77774#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77772#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 77731#L651 assume !(0 != activate_threads_~tmp___2~0); 77720#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77721#L316 assume !(1 == ~t4_pc~0); 78055#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 78054#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 77930#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 77892#L659 assume !(0 != activate_threads_~tmp___3~0); 77893#L659-2 assume !(1 == ~M_E~0); 77776#L562-1 assume !(1 == ~T1_E~0); 77678#L567-1 assume !(1 == ~T2_E~0); 77679#L572-1 assume !(1 == ~T3_E~0); 77574#L577-1 assume !(1 == ~T4_E~0); 77575#L582-1 assume !(1 == ~E_M~0); 77630#L587-1 assume !(1 == ~E_1~0); 77631#L592-1 assume !(1 == ~E_2~0); 77802#L597-1 assume !(1 == ~E_3~0); 77803#L602-1 assume !(1 == ~E_4~0); 78058#L793-1 assume !false; 81257#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 81251#L479 [2019-12-07 12:35:51,589 INFO L796 eck$LassoCheckResult]: Loop: 81251#L479 assume !false; 81243#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 81236#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 81230#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 81223#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 81215#L418 assume 0 != eval_~tmp~0; 81207#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 81202#L426 assume !(0 != eval_~tmp_ndt_1~0); 81194#L423 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 81108#L440 assume !(0 != eval_~tmp_ndt_2~0); 81188#L437 assume !(0 == ~t2_st~0); 81262#L451 assume !(0 == ~t3_st~0); 81258#L465 assume !(0 == ~t4_st~0); 81251#L479 [2019-12-07 12:35:51,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,589 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2019-12-07 12:35:51,589 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,589 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68053704] [2019-12-07 12:35:51,589 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,600 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,601 INFO L82 PathProgramCache]: Analyzing trace with hash -1950332302, now seen corresponding path program 2 times [2019-12-07 12:35:51,601 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,601 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454290102] [2019-12-07 12:35:51,601 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,605 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,605 INFO L82 PathProgramCache]: Analyzing trace with hash 1660720301, now seen corresponding path program 1 times [2019-12-07 12:35:51,605 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,605 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979747135] [2019-12-07 12:35:51,605 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:51,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:51,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979747135] [2019-12-07 12:35:51,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:51,621 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:51,621 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100308253] [2019-12-07 12:35:51,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:51,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:51,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:51,672 INFO L87 Difference]: Start difference. First operand 6762 states and 9149 transitions. cyclomatic complexity: 2399 Second operand 3 states. [2019-12-07 12:35:51,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:51,712 INFO L93 Difference]: Finished difference Result 8550 states and 11529 transitions. [2019-12-07 12:35:51,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:51,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8550 states and 11529 transitions. [2019-12-07 12:35:51,736 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8384 [2019-12-07 12:35:51,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8550 states to 8550 states and 11529 transitions. [2019-12-07 12:35:51,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8550 [2019-12-07 12:35:51,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8550 [2019-12-07 12:35:51,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8550 states and 11529 transitions. [2019-12-07 12:35:51,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:51,765 INFO L688 BuchiCegarLoop]: Abstraction has 8550 states and 11529 transitions. [2019-12-07 12:35:51,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8550 states and 11529 transitions. [2019-12-07 12:35:51,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8550 to 8286. [2019-12-07 12:35:51,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8286 states. [2019-12-07 12:35:51,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8286 states to 8286 states and 11193 transitions. [2019-12-07 12:35:51,823 INFO L711 BuchiCegarLoop]: Abstraction has 8286 states and 11193 transitions. [2019-12-07 12:35:51,823 INFO L591 BuchiCegarLoop]: Abstraction has 8286 states and 11193 transitions. [2019-12-07 12:35:51,823 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 12:35:51,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8286 states and 11193 transitions. [2019-12-07 12:35:51,839 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8120 [2019-12-07 12:35:51,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:51,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:51,840 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,840 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:51,840 INFO L794 eck$LassoCheckResult]: Stem: 93289#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93174#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93175#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 92985#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 92986#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93034#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93095#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92989#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92990#L363-1 assume !(0 == ~M_E~0); 93311#L504-1 assume !(0 == ~T1_E~0); 93136#L509-1 assume !(0 == ~T2_E~0); 93137#L514-1 assume !(0 == ~T3_E~0); 93044#L519-1 assume !(0 == ~T4_E~0); 93045#L524-1 assume !(0 == ~E_M~0); 93103#L529-1 assume !(0 == ~E_1~0); 92998#L534-1 assume !(0 == ~E_2~0); 92999#L539-1 assume !(0 == ~E_3~0); 92898#L544-1 assume !(0 == ~E_4~0); 92899#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93206#L240 assume !(1 == ~m_pc~0); 93245#L240-2 is_master_triggered_~__retres1~0 := 0; 93247#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93170#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 93171#L627 assume !(0 != activate_threads_~tmp~1); 93314#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92987#L259 assume !(1 == ~t1_pc~0); 92972#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 92973#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92991#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 93327#L635 assume !(0 != activate_threads_~tmp___0~0); 93392#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93133#L278 assume !(1 == ~t2_pc~0); 93114#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 93115#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92942#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 92891#L643 assume !(0 != activate_threads_~tmp___1~0); 92892#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 92893#L297 assume !(1 == ~t3_pc~0); 93101#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 93100#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93096#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 93051#L651 assume !(0 != activate_threads_~tmp___2~0); 93039#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93040#L316 assume !(1 == ~t4_pc~0); 93390#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 93389#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93261#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 93225#L659 assume !(0 != activate_threads_~tmp___3~0); 93226#L659-2 assume !(1 == ~M_E~0); 93102#L562-1 assume !(1 == ~T1_E~0); 92996#L567-1 assume !(1 == ~T2_E~0); 92997#L572-1 assume !(1 == ~T3_E~0); 92894#L577-1 assume !(1 == ~T4_E~0); 92895#L582-1 assume !(1 == ~E_M~0); 92949#L587-1 assume !(1 == ~E_1~0); 92950#L592-1 assume !(1 == ~E_2~0); 93130#L597-1 assume !(1 == ~E_3~0); 93131#L602-1 assume !(1 == ~E_4~0); 93393#L793-1 assume !false; 94742#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 94738#L479 [2019-12-07 12:35:51,840 INFO L796 eck$LassoCheckResult]: Loop: 94738#L479 assume !false; 94736#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 94733#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 94731#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 94730#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 94728#L418 assume 0 != eval_~tmp~0; 94724#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 94721#L426 assume !(0 != eval_~tmp_ndt_1~0); 94719#L423 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 94697#L440 assume !(0 != eval_~tmp_ndt_2~0); 94716#L437 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 94512#L454 assume !(0 != eval_~tmp_ndt_3~0); 94513#L451 assume !(0 == ~t3_st~0); 94743#L465 assume !(0 == ~t4_st~0); 94738#L479 [2019-12-07 12:35:51,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,840 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2019-12-07 12:35:51,840 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,841 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661071831] [2019-12-07 12:35:51,841 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,852 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,852 INFO L82 PathProgramCache]: Analyzing trace with hash -335443967, now seen corresponding path program 1 times [2019-12-07 12:35:51,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,852 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902187295] [2019-12-07 12:35:51,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:51,856 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:51,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:51,857 INFO L82 PathProgramCache]: Analyzing trace with hash -61962970, now seen corresponding path program 1 times [2019-12-07 12:35:51,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:51,857 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081783098] [2019-12-07 12:35:51,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:51,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:51,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:51,873 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081783098] [2019-12-07 12:35:51,873 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:51,873 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 12:35:51,873 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016201248] [2019-12-07 12:35:51,947 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:51,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:51,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:51,947 INFO L87 Difference]: Start difference. First operand 8286 states and 11193 transitions. cyclomatic complexity: 2919 Second operand 3 states. [2019-12-07 12:35:52,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:52,002 INFO L93 Difference]: Finished difference Result 14592 states and 19593 transitions. [2019-12-07 12:35:52,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:52,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14592 states and 19593 transitions. [2019-12-07 12:35:52,054 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14322 [2019-12-07 12:35:52,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14592 states to 14592 states and 19593 transitions. [2019-12-07 12:35:52,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14592 [2019-12-07 12:35:52,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14592 [2019-12-07 12:35:52,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14592 states and 19593 transitions. [2019-12-07 12:35:52,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:52,096 INFO L688 BuchiCegarLoop]: Abstraction has 14592 states and 19593 transitions. [2019-12-07 12:35:52,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14592 states and 19593 transitions. [2019-12-07 12:35:52,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14592 to 14136. [2019-12-07 12:35:52,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14136 states. [2019-12-07 12:35:52,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14136 states to 14136 states and 19041 transitions. [2019-12-07 12:35:52,199 INFO L711 BuchiCegarLoop]: Abstraction has 14136 states and 19041 transitions. [2019-12-07 12:35:52,199 INFO L591 BuchiCegarLoop]: Abstraction has 14136 states and 19041 transitions. [2019-12-07 12:35:52,199 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 12:35:52,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14136 states and 19041 transitions. [2019-12-07 12:35:52,229 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13866 [2019-12-07 12:35:52,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:52,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:52,230 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:52,230 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:52,230 INFO L794 eck$LassoCheckResult]: Stem: 116176#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 116063#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 116064#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 115869#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 115870#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115923#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115984#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115873#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115874#L363-1 assume !(0 == ~M_E~0); 116207#L504-1 assume !(0 == ~T1_E~0); 116021#L509-1 assume !(0 == ~T2_E~0); 116022#L514-1 assume !(0 == ~T3_E~0); 115934#L519-1 assume !(0 == ~T4_E~0); 115935#L524-1 assume !(0 == ~E_M~0); 115990#L529-1 assume !(0 == ~E_1~0); 115882#L534-1 assume !(0 == ~E_2~0); 115883#L539-1 assume !(0 == ~E_3~0); 115784#L544-1 assume !(0 == ~E_4~0); 115785#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 116095#L240 assume !(1 == ~m_pc~0); 116135#L240-2 is_master_triggered_~__retres1~0 := 0; 116137#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 116059#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 116060#L627 assume !(0 != activate_threads_~tmp~1); 116209#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 115871#L259 assume !(1 == ~t1_pc~0); 115856#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 115857#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 115875#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 116220#L635 assume !(0 != activate_threads_~tmp___0~0); 116296#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 116018#L278 assume !(1 == ~t2_pc~0); 116004#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 116005#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 115828#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 115777#L643 assume !(0 != activate_threads_~tmp___1~0); 115778#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 115779#L297 assume !(1 == ~t3_pc~0); 115988#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 115987#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 115985#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 115941#L651 assume !(0 != activate_threads_~tmp___2~0); 115928#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 115929#L316 assume !(1 == ~t4_pc~0); 116293#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 116292#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116153#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116114#L659 assume !(0 != activate_threads_~tmp___3~0); 116115#L659-2 assume !(1 == ~M_E~0); 115989#L562-1 assume !(1 == ~T1_E~0); 115880#L567-1 assume !(1 == ~T2_E~0); 115881#L572-1 assume !(1 == ~T3_E~0); 115780#L577-1 assume !(1 == ~T4_E~0); 115781#L582-1 assume !(1 == ~E_M~0); 115832#L587-1 assume !(1 == ~E_1~0); 115833#L592-1 assume !(1 == ~E_2~0); 116016#L597-1 assume !(1 == ~E_3~0); 116017#L602-1 assume !(1 == ~E_4~0); 116297#L793-1 assume !false; 117542#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 117538#L479 [2019-12-07 12:35:52,230 INFO L796 eck$LassoCheckResult]: Loop: 117538#L479 assume !false; 117536#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 117533#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 117531#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 117529#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 117527#L418 assume 0 != eval_~tmp~0; 117524#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 117500#L426 assume !(0 != eval_~tmp_ndt_1~0); 117447#L423 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 117441#L440 assume !(0 != eval_~tmp_ndt_2~0); 117435#L437 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 117427#L454 assume !(0 != eval_~tmp_ndt_3~0); 117428#L451 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 117546#L468 assume !(0 != eval_~tmp_ndt_4~0); 117543#L465 assume !(0 == ~t4_st~0); 117538#L479 [2019-12-07 12:35:52,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2019-12-07 12:35:52,230 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [512370406] [2019-12-07 12:35:52,231 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,243 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:52,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,244 INFO L82 PathProgramCache]: Analyzing trace with hash -1808978268, now seen corresponding path program 1 times [2019-12-07 12:35:52,244 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,244 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835449640] [2019-12-07 12:35:52,244 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,250 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:52,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,250 INFO L82 PathProgramCache]: Analyzing trace with hash -1921001953, now seen corresponding path program 1 times [2019-12-07 12:35:52,251 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,251 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73607334] [2019-12-07 12:35:52,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 12:35:52,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 12:35:52,269 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73607334] [2019-12-07 12:35:52,269 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 12:35:52,269 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 12:35:52,269 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107347026] [2019-12-07 12:35:52,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 12:35:52,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 12:35:52,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 12:35:52,345 INFO L87 Difference]: Start difference. First operand 14136 states and 19041 transitions. cyclomatic complexity: 4917 Second operand 3 states. [2019-12-07 12:35:52,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 12:35:52,395 INFO L93 Difference]: Finished difference Result 17847 states and 23911 transitions. [2019-12-07 12:35:52,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 12:35:52,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17847 states and 23911 transitions. [2019-12-07 12:35:52,440 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17521 [2019-12-07 12:35:52,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17847 states to 17847 states and 23911 transitions. [2019-12-07 12:35:52,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17847 [2019-12-07 12:35:52,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17847 [2019-12-07 12:35:52,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17847 states and 23911 transitions. [2019-12-07 12:35:52,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 12:35:52,487 INFO L688 BuchiCegarLoop]: Abstraction has 17847 states and 23911 transitions. [2019-12-07 12:35:52,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17847 states and 23911 transitions. [2019-12-07 12:35:52,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17847 to 17703. [2019-12-07 12:35:52,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17703 states. [2019-12-07 12:35:52,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17703 states to 17703 states and 23767 transitions. [2019-12-07 12:35:52,593 INFO L711 BuchiCegarLoop]: Abstraction has 17703 states and 23767 transitions. [2019-12-07 12:35:52,593 INFO L591 BuchiCegarLoop]: Abstraction has 17703 states and 23767 transitions. [2019-12-07 12:35:52,593 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 12:35:52,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17703 states and 23767 transitions. [2019-12-07 12:35:52,634 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17377 [2019-12-07 12:35:52,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 12:35:52,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 12:35:52,635 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:52,635 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 12:35:52,636 INFO L794 eck$LassoCheckResult]: Stem: 148172#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 148055#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 148056#L756 havoc start_simulation_#t~ret13, start_simulation_#t~ret14, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 147862#L336 assume 1 == ~m_i~0;~m_st~0 := 0; 147863#L343-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 147915#L348-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 147973#L353-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 147866#L358-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 147867#L363-1 assume !(0 == ~M_E~0); 148202#L504-1 assume !(0 == ~T1_E~0); 148009#L509-1 assume !(0 == ~T2_E~0); 148010#L514-1 assume !(0 == ~T3_E~0); 147926#L519-1 assume !(0 == ~T4_E~0); 147927#L524-1 assume !(0 == ~E_M~0); 147979#L529-1 assume !(0 == ~E_1~0); 147875#L534-1 assume !(0 == ~E_2~0); 147876#L539-1 assume !(0 == ~E_3~0); 147775#L544-1 assume !(0 == ~E_4~0); 147776#L549-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 148087#L240 assume !(1 == ~m_pc~0); 148129#L240-2 is_master_triggered_~__retres1~0 := 0; 148132#L251 is_master_triggered_#res := is_master_triggered_~__retres1~0; 148048#L252 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 148049#L627 assume !(0 != activate_threads_~tmp~1); 148203#L627-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 147864#L259 assume !(1 == ~t1_pc~0); 147849#L259-2 is_transmit1_triggered_~__retres1~1 := 0; 147850#L270 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 147868#L271 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 148214#L635 assume !(0 != activate_threads_~tmp___0~0); 148295#L635-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148006#L278 assume !(1 == ~t2_pc~0); 147994#L278-2 is_transmit2_triggered_~__retres1~2 := 0; 147995#L289 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 147819#L290 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 147768#L643 assume !(0 != activate_threads_~tmp___1~0); 147769#L643-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 147770#L297 assume !(1 == ~t3_pc~0); 147977#L297-2 is_transmit3_triggered_~__retres1~3 := 0; 147976#L308 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 147974#L309 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 147931#L651 assume !(0 != activate_threads_~tmp___2~0); 147920#L651-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147921#L316 assume !(1 == ~t4_pc~0); 148292#L316-2 is_transmit4_triggered_~__retres1~4 := 0; 148291#L327 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148145#L328 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 148108#L659 assume !(0 != activate_threads_~tmp___3~0); 148109#L659-2 assume !(1 == ~M_E~0); 147978#L562-1 assume !(1 == ~T1_E~0); 147873#L567-1 assume !(1 == ~T2_E~0); 147874#L572-1 assume !(1 == ~T3_E~0); 147773#L577-1 assume !(1 == ~T4_E~0); 147774#L582-1 assume !(1 == ~E_M~0); 147825#L587-1 assume !(1 == ~E_1~0); 147826#L592-1 assume !(1 == ~E_2~0); 148004#L597-1 assume !(1 == ~E_3~0); 148005#L602-1 assume !(1 == ~E_4~0); 148296#L793-1 assume !false; 161004#L794 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 149994#L479 [2019-12-07 12:35:52,636 INFO L796 eck$LassoCheckResult]: Loop: 149994#L479 assume !false; 161001#L414 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 160998#L376 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 160996#L403 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 160994#L404 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 160992#L418 assume 0 != eval_~tmp~0; 160991#L418-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 160987#L426 assume !(0 != eval_~tmp_ndt_1~0); 156075#L423 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 156071#L440 assume !(0 != eval_~tmp_ndt_2~0); 156073#L437 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 158876#L454 assume !(0 != eval_~tmp_ndt_3~0); 153331#L451 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 150001#L468 assume !(0 != eval_~tmp_ndt_4~0); 149998#L465 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 149993#L482 assume !(0 != eval_~tmp_ndt_5~0); 149994#L479 [2019-12-07 12:35:52,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2019-12-07 12:35:52,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37629611] [2019-12-07 12:35:52,637 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,650 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:52,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,651 INFO L82 PathProgramCache]: Analyzing trace with hash -243755057, now seen corresponding path program 1 times [2019-12-07 12:35:52,651 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,651 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326915494] [2019-12-07 12:35:52,651 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,656 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:52,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 12:35:52,656 INFO L82 PathProgramCache]: Analyzing trace with hash 578478004, now seen corresponding path program 1 times [2019-12-07 12:35:52,656 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 12:35:52,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113311470] [2019-12-07 12:35:52,657 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 12:35:52,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 12:35:52,673 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 12:35:53,110 WARN L192 SmtUtils]: Spent 345.00 ms on a formula simplification. DAG size of input: 167 DAG size of output: 112 [2019-12-07 12:35:53,212 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 12:35:53 BoogieIcfgContainer [2019-12-07 12:35:53,212 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 12:35:53,212 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 12:35:53,212 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 12:35:53,213 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 12:35:53,213 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:35:48" (3/4) ... [2019-12-07 12:35:53,215 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 12:35:53,259 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_a918152b-38ed-494d-8ff5-78dfb825cdb8/bin/uautomizer/witness.graphml [2019-12-07 12:35:53,260 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 12:35:53,261 INFO L168 Benchmark]: Toolchain (without parser) took 5316.39 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 243.3 MB). Free memory was 948.9 MB in the beginning and 1.1 GB in the end (delta: -110.4 MB). Peak memory consumption was 132.8 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,261 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:35:53,261 INFO L168 Benchmark]: CACSL2BoogieTranslator took 260.46 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 948.9 MB in the beginning and 1.1 GB in the end (delta: -141.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,261 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,262 INFO L168 Benchmark]: Boogie Preprocessor took 44.40 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 12:35:53,262 INFO L168 Benchmark]: RCFGBuilder took 606.84 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 991.2 MB in the end (delta: 93.6 MB). Peak memory consumption was 93.6 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,262 INFO L168 Benchmark]: BuchiAutomizer took 4308.51 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 141.6 MB). Free memory was 991.2 MB in the beginning and 1.1 GB in the end (delta: -79.6 MB). Peak memory consumption was 353.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,263 INFO L168 Benchmark]: Witness Printer took 47.17 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 11.4 MB). Peak memory consumption was 11.4 MB. Max. memory is 11.5 GB. [2019-12-07 12:35:53,264 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 260.46 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 948.9 MB in the beginning and 1.1 GB in the end (delta: -141.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.40 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 606.84 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 991.2 MB in the end (delta: 93.6 MB). Peak memory consumption was 93.6 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 4308.51 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 141.6 MB). Free memory was 991.2 MB in the beginning and 1.1 GB in the end (delta: -79.6 MB). Peak memory consumption was 353.4 MB. Max. memory is 11.5 GB. * Witness Printer took 47.17 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 11.4 MB). Peak memory consumption was 11.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 17703 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.2s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 1.8s. Construction of modules took 0.3s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 5337 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had 17703 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 12182 SDtfs, 12108 SDslu, 8350 SDs, 0 SdLazy, 366 SolverSat, 216 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 413]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f4895ae=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c883229=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@326e9664=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f5bf975=0, t4_i=1, E_3=2, t4_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1756d174=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3812f360=0, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72119db3=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f56f3b=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@75e9625e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11ea3457=0, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3299472a=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@175a7e51=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47e6e612=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 413]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int t4_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int t4_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int T4_E = 2; [L34] int E_M = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L45] int token ; [L47] int local ; [L838] int __retres1 ; [L750] m_i = 1 [L751] t1_i = 1 [L752] t2_i = 1 [L753] t3_i = 1 [L754] t4_i = 1 [L779] int kernel_st ; [L780] int tmp ; [L781] int tmp___0 ; [L785] kernel_st = 0 [L343] COND TRUE m_i == 1 [L344] m_st = 0 [L348] COND TRUE t1_i == 1 [L349] t1_st = 0 [L353] COND TRUE t2_i == 1 [L354] t2_st = 0 [L358] COND TRUE t3_i == 1 [L359] t3_st = 0 [L363] COND TRUE t4_i == 1 [L364] t4_st = 0 [L504] COND FALSE !(M_E == 0) [L509] COND FALSE !(T1_E == 0) [L514] COND FALSE !(T2_E == 0) [L519] COND FALSE !(T3_E == 0) [L524] COND FALSE !(T4_E == 0) [L529] COND FALSE !(E_M == 0) [L534] COND FALSE !(E_1 == 0) [L539] COND FALSE !(E_2 == 0) [L544] COND FALSE !(E_3 == 0) [L549] COND FALSE !(E_4 == 0) [L617] int tmp ; [L618] int tmp___0 ; [L619] int tmp___1 ; [L620] int tmp___2 ; [L621] int tmp___3 ; [L237] int __retres1 ; [L240] COND FALSE !(m_pc == 1) [L250] __retres1 = 0 [L252] return (__retres1); [L625] tmp = is_master_triggered() [L627] COND FALSE !(\read(tmp)) [L256] int __retres1 ; [L259] COND FALSE !(t1_pc == 1) [L269] __retres1 = 0 [L271] return (__retres1); [L633] tmp___0 = is_transmit1_triggered() [L635] COND FALSE !(\read(tmp___0)) [L275] int __retres1 ; [L278] COND FALSE !(t2_pc == 1) [L288] __retres1 = 0 [L290] return (__retres1); [L641] tmp___1 = is_transmit2_triggered() [L643] COND FALSE !(\read(tmp___1)) [L294] int __retres1 ; [L297] COND FALSE !(t3_pc == 1) [L307] __retres1 = 0 [L309] return (__retres1); [L649] tmp___2 = is_transmit3_triggered() [L651] COND FALSE !(\read(tmp___2)) [L313] int __retres1 ; [L316] COND FALSE !(t4_pc == 1) [L326] __retres1 = 0 [L328] return (__retres1); [L657] tmp___3 = is_transmit4_triggered() [L659] COND FALSE !(\read(tmp___3)) [L562] COND FALSE !(M_E == 1) [L567] COND FALSE !(T1_E == 1) [L572] COND FALSE !(T2_E == 1) [L577] COND FALSE !(T3_E == 1) [L582] COND FALSE !(T4_E == 1) [L587] COND FALSE !(E_M == 1) [L592] COND FALSE !(E_1 == 1) [L597] COND FALSE !(E_2 == 1) [L602] COND FALSE !(E_3 == 1) [L607] COND FALSE !(E_4 == 1) [L793] COND TRUE 1 [L796] kernel_st = 1 [L409] int tmp ; Loop: [L413] COND TRUE 1 [L373] int __retres1 ; [L376] COND TRUE m_st == 0 [L377] __retres1 = 1 [L404] return (__retres1); [L416] tmp = exists_runnable_thread() [L418] COND TRUE \read(tmp) [L423] COND TRUE m_st == 0 [L424] int tmp_ndt_1; [L425] tmp_ndt_1 = __VERIFIER_nondet_int() [L426] COND FALSE !(\read(tmp_ndt_1)) [L437] COND TRUE t1_st == 0 [L438] int tmp_ndt_2; [L439] tmp_ndt_2 = __VERIFIER_nondet_int() [L440] COND FALSE !(\read(tmp_ndt_2)) [L451] COND TRUE t2_st == 0 [L452] int tmp_ndt_3; [L453] tmp_ndt_3 = __VERIFIER_nondet_int() [L454] COND FALSE !(\read(tmp_ndt_3)) [L465] COND TRUE t3_st == 0 [L466] int tmp_ndt_4; [L467] tmp_ndt_4 = __VERIFIER_nondet_int() [L468] COND FALSE !(\read(tmp_ndt_4)) [L479] COND TRUE t4_st == 0 [L480] int tmp_ndt_5; [L481] tmp_ndt_5 = __VERIFIER_nondet_int() [L482] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...