./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5e27a879cb97b2b6600a7b4379c4e090f4fa709a .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:58:00,869 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:58:00,870 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:58:00,877 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:58:00,878 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:58:00,879 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:58:00,880 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:58:00,882 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:58:00,883 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:58:00,884 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:58:00,885 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:58:00,886 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:58:00,886 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:58:00,887 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:58:00,888 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:58:00,889 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:58:00,890 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:58:00,890 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:58:00,892 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:58:00,893 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:58:00,894 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:58:00,895 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:58:00,895 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:58:00,896 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:58:00,897 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:58:00,897 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:58:00,898 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:58:00,898 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:58:00,898 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:58:00,899 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:58:00,899 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:58:00,899 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:58:00,900 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:58:00,901 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:58:00,901 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:58:00,902 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:58:00,902 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:58:00,902 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:58:00,902 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:58:00,903 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:58:00,904 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:58:00,904 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 18:58:00,918 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:58:00,919 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:58:00,920 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:58:00,920 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:58:00,920 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:58:00,920 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:58:00,920 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:58:00,921 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:58:00,921 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:58:00,921 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:58:00,921 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:58:00,921 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:58:00,921 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:58:00,922 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:58:00,922 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:58:00,922 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:58:00,922 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:58:00,922 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:58:00,923 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:58:00,924 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:58:00,924 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:58:00,924 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:58:00,924 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:58:00,924 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:58:00,925 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:58:00,925 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:58:00,925 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:58:00,926 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:58:00,926 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5e27a879cb97b2b6600a7b4379c4e090f4fa709a [2019-12-07 18:58:01,022 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:58:01,031 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:58:01,033 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:58:01,034 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:58:01,034 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:58:01,034 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2019-12-07 18:58:01,073 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/data/ee8ca8a54/964fd48f67a94746a71b987bd225f1aa/FLAGaeb3de2f0 [2019-12-07 18:58:01,486 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:58:01,487 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2019-12-07 18:58:01,494 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/data/ee8ca8a54/964fd48f67a94746a71b987bd225f1aa/FLAGaeb3de2f0 [2019-12-07 18:58:01,859 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/data/ee8ca8a54/964fd48f67a94746a71b987bd225f1aa [2019-12-07 18:58:01,862 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:58:01,863 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:58:01,863 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:58:01,864 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:58:01,866 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:58:01,867 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:58:01" (1/1) ... [2019-12-07 18:58:01,869 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11cefb15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:01, skipping insertion in model container [2019-12-07 18:58:01,869 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:58:01" (1/1) ... [2019-12-07 18:58:01,878 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:58:01,907 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:58:02,071 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:58:02,075 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:58:02,106 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:58:02,119 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:58:02,120 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02 WrapperNode [2019-12-07 18:58:02,120 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:58:02,120 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:58:02,120 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:58:02,120 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:58:02,125 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,131 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,160 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:58:02,160 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:58:02,160 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:58:02,160 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:58:02,166 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,167 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,171 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,171 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,181 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,192 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,195 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... [2019-12-07 18:58:02,199 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:58:02,200 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:58:02,200 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:58:02,200 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:58:02,200 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:58:02,243 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:58:02,243 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:58:02,798 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:58:02,798 INFO L287 CfgBuilder]: Removed 163 assume(true) statements. [2019-12-07 18:58:02,799 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:58:02 BoogieIcfgContainer [2019-12-07 18:58:02,799 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:58:02,799 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:58:02,799 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:58:02,802 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:58:02,802 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:58:02,802 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:58:01" (1/3) ... [2019-12-07 18:58:02,803 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c327f9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:58:02, skipping insertion in model container [2019-12-07 18:58:02,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:58:02,803 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:58:02" (2/3) ... [2019-12-07 18:58:02,803 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c327f9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:58:02, skipping insertion in model container [2019-12-07 18:58:02,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:58:02,803 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:58:02" (3/3) ... [2019-12-07 18:58:02,804 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2019-12-07 18:58:02,832 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:58:02,832 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:58:02,832 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:58:02,832 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:58:02,832 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:58:02,832 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:58:02,832 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:58:02,832 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:58:02,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states. [2019-12-07 18:58:02,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 352 [2019-12-07 18:58:02,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:02,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:02,887 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:02,887 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:02,887 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:58:02,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states. [2019-12-07 18:58:02,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 352 [2019-12-07 18:58:02,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:02,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:02,898 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:02,898 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:02,904 INFO L794 eck$LassoCheckResult]: Stem: 283#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 197#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 386#L768true havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 343#L348true assume !(1 == ~m_i~0);~m_st~0 := 2; 157#L355-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 403#L360-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 82#L365-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 346#L370-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 135#L375-1true assume !(0 == ~M_E~0); 221#L516-1true assume !(0 == ~T1_E~0); 31#L521-1true assume !(0 == ~T2_E~0); 370#L526-1true assume !(0 == ~T3_E~0); 163#L531-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 414#L536-1true assume !(0 == ~E_M~0); 90#L541-1true assume !(0 == ~E_1~0); 355#L546-1true assume !(0 == ~E_2~0); 143#L551-1true assume !(0 == ~E_3~0); 56#L556-1true assume !(0 == ~E_4~0); 310#L561-1true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 195#L252true assume 1 == ~m_pc~0; 278#L253true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 196#L263true is_master_triggered_#res := is_master_triggered_~__retres1~0; 279#L264true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 266#L639true assume !(0 != activate_threads_~tmp~1); 140#L639-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 335#L271true assume !(1 == ~t1_pc~0); 348#L271-2true is_transmit1_triggered_~__retres1~1 := 0; 336#L282true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 393#L283true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 380#L647true assume !(0 != activate_threads_~tmp___0~0); 383#L647-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36#L290true assume 1 == ~t2_pc~0; 80#L291true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 37#L301true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81#L302true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60#L655true assume !(0 != activate_threads_~tmp___1~0); 53#L655-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 138#L309true assume !(1 == ~t3_pc~0); 116#L309-2true is_transmit3_triggered_~__retres1~3 := 0; 137#L320true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83#L321true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 169#L663true assume !(0 != activate_threads_~tmp___2~0); 170#L663-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 255#L328true assume 1 == ~t4_pc~0; 199#L329true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 253#L339true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 198#L340true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 318#L671true assume !(0 != activate_threads_~tmp___3~0); 307#L671-2true assume !(1 == ~M_E~0); 89#L574-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 354#L579-1true assume !(1 == ~T2_E~0); 141#L584-1true assume !(1 == ~T3_E~0); 54#L589-1true assume !(1 == ~T4_E~0); 309#L594-1true assume !(1 == ~E_M~0); 6#L599-1true assume !(1 == ~E_1~0); 228#L604-1true assume !(1 == ~E_2~0); 43#L609-1true assume !(1 == ~E_3~0); 384#L614-1true assume 1 == ~E_4~0;~E_4~0 := 2; 93#L805-1true [2019-12-07 18:58:02,905 INFO L796 eck$LassoCheckResult]: Loop: 93#L805-1true assume !false; 171#L806true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 356#L491true assume !true; 311#L506true start_simulation_~kernel_st~0 := 2; 350#L348-1true start_simulation_~kernel_st~0 := 3; 222#L516-2true assume 0 == ~M_E~0;~M_E~0 := 1; 223#L516-4true assume !(0 == ~T1_E~0); 38#L521-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 375#L526-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 166#L531-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 416#L536-3true assume 0 == ~E_M~0;~E_M~0 := 1; 92#L541-3true assume 0 == ~E_1~0;~E_1~0 := 1; 359#L546-3true assume 0 == ~E_2~0;~E_2~0 := 1; 130#L551-3true assume 0 == ~E_3~0;~E_3~0 := 1; 48#L556-3true assume !(0 == ~E_4~0); 298#L561-3true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 321#L252-18true assume 1 == ~m_pc~0; 288#L253-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 205#L263-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 289#L264-6true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 108#L639-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 111#L639-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 415#L271-18true assume 1 == ~t1_pc~0; 395#L272-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 330#L282-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 396#L283-6true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 249#L647-18true assume !(0 != activate_threads_~tmp___0~0); 234#L647-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4#L290-18true assume 1 == ~t2_pc~0; 65#L291-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16#L301-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66#L302-6true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 365#L655-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 366#L655-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 95#L309-18true assume !(1 == ~t3_pc~0); 97#L309-20true is_transmit3_triggered_~__retres1~3 := 0; 127#L320-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 182#L321-6true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 153#L663-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 147#L663-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 233#L328-18true assume !(1 == ~t4_pc~0); 224#L328-20true is_transmit4_triggered_~__retres1~4 := 0; 244#L339-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 189#L340-6true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 274#L671-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 280#L671-20true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L574-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 358#L579-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 144#L584-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 58#L589-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 313#L594-3true assume 1 == ~E_M~0;~E_M~0 := 2; 71#L599-3true assume !(1 == ~E_1~0); 219#L604-3true assume 1 == ~E_2~0;~E_2~0 := 2; 29#L609-3true assume 1 == ~E_3~0;~E_3~0 := 2; 369#L614-3true assume 1 == ~E_4~0;~E_4~0 := 2; 162#L619-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 156#L388-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 397#L415-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 378#L416-1true start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 230#L824true assume !(0 == start_simulation_~tmp~3); 232#L824-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 158#L388-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 401#L415-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 252#L416-2true stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 385#L779true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10#L786true stop_simulation_#res := stop_simulation_~__retres2~0; 59#L787true start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 268#L837true assume !(0 != start_simulation_~tmp___0~1); 93#L805-1true [2019-12-07 18:58:02,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:02,909 INFO L82 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2019-12-07 18:58:02,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:02,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083387726] [2019-12-07 18:58:02,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:02,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,019 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083387726] [2019-12-07 18:58:03,019 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,020 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,021 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364767723] [2019-12-07 18:58:03,024 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,024 INFO L82 PathProgramCache]: Analyzing trace with hash 448746186, now seen corresponding path program 1 times [2019-12-07 18:58:03,024 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,024 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508595445] [2019-12-07 18:58:03,024 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508595445] [2019-12-07 18:58:03,042 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,042 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,042 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675418575] [2019-12-07 18:58:03,043 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,044 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,055 INFO L87 Difference]: Start difference. First operand 419 states. Second operand 3 states. [2019-12-07 18:58:03,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,084 INFO L93 Difference]: Finished difference Result 419 states and 635 transitions. [2019-12-07 18:58:03,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 635 transitions. [2019-12-07 18:58:03,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 413 states and 629 transitions. [2019-12-07 18:58:03,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2019-12-07 18:58:03,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2019-12-07 18:58:03,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 629 transitions. [2019-12-07 18:58:03,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,101 INFO L688 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2019-12-07 18:58:03,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 629 transitions. [2019-12-07 18:58:03,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2019-12-07 18:58:03,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2019-12-07 18:58:03,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 629 transitions. [2019-12-07 18:58:03,135 INFO L711 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2019-12-07 18:58:03,135 INFO L591 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2019-12-07 18:58:03,135 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:58:03,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 629 transitions. [2019-12-07 18:58:03,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,140 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,140 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,140 INFO L794 eck$LassoCheckResult]: Stem: 1193#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1121#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1122#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1238#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 1076#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1077#L360-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 966#L365-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 967#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1047#L375-1 assume !(0 == ~M_E~0); 1048#L516-1 assume !(0 == ~T1_E~0); 900#L521-1 assume !(0 == ~T2_E~0); 901#L526-1 assume !(0 == ~T3_E~0); 1084#L531-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1085#L536-1 assume !(0 == ~E_M~0); 984#L541-1 assume !(0 == ~E_1~0); 985#L546-1 assume !(0 == ~E_2~0); 1055#L551-1 assume !(0 == ~E_3~0); 949#L556-1 assume !(0 == ~E_4~0); 950#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1118#L252 assume 1 == ~m_pc~0; 1119#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1100#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1120#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1184#L639 assume !(0 != activate_threads_~tmp~1); 1050#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1051#L271 assume !(1 == ~t1_pc~0); 1228#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 1230#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1231#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1254#L647 assume !(0 != activate_threads_~tmp___0~0); 1255#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 910#L290 assume 1 == ~t2_pc~0; 911#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 899#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 912#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 955#L655 assume !(0 != activate_threads_~tmp___1~0); 943#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 944#L309 assume !(1 == ~t3_pc~0); 972#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 971#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 968#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 969#L663 assume !(0 != activate_threads_~tmp___2~0); 1093#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1094#L328 assume 1 == ~t4_pc~0; 1125#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1126#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1123#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1124#L671 assume !(0 != activate_threads_~tmp___3~0); 1209#L671-2 assume !(1 == ~M_E~0); 982#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 983#L579-1 assume !(1 == ~T2_E~0); 1052#L584-1 assume !(1 == ~T3_E~0); 945#L589-1 assume !(1 == ~T4_E~0); 946#L594-1 assume !(1 == ~E_M~0); 854#L599-1 assume !(1 == ~E_1~0); 855#L604-1 assume !(1 == ~E_2~0); 925#L609-1 assume !(1 == ~E_3~0); 926#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 990#L805-1 [2019-12-07 18:58:03,140 INFO L796 eck$LassoCheckResult]: Loop: 990#L805-1 assume !false; 991#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 905#L491 assume !false; 1244#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1070#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 916#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1252#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1042#L430 assume !(0 != eval_~tmp~0); 1044#L506 start_simulation_~kernel_st~0 := 2; 1211#L348-1 start_simulation_~kernel_st~0 := 3; 1167#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1168#L516-4 assume !(0 == ~T1_E~0); 913#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 914#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1088#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1089#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 988#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1039#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 934#L556-3 assume !(0 == ~E_4~0); 935#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1205#L252-18 assume 1 == ~m_pc~0; 1198#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1137#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1138#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1016#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1017#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1022#L271-18 assume 1 == ~t1_pc~0; 1258#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1220#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1221#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1177#L647-18 assume !(0 != activate_threads_~tmp___0~0); 1171#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 849#L290-18 assume 1 == ~t2_pc~0; 850#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 866#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 872#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 962#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1246#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 994#L309-18 assume !(1 == ~t3_pc~0); 995#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 999#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1036#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1069#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1059#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1060#L328-18 assume 1 == ~t4_pc~0; 1105#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1106#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1103#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1104#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1190#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 986#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 987#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1056#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 952#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 953#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 964#L599-3 assume !(1 == ~E_1~0); 965#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 896#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 897#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1083#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1074#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 919#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1253#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1169#L824 assume !(0 == start_simulation_~tmp~3); 1170#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1078#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 891#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1180#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 1181#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 862#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 863#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 954#L837 assume !(0 != start_simulation_~tmp___0~1); 990#L805-1 [2019-12-07 18:58:03,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,141 INFO L82 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2019-12-07 18:58:03,141 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,141 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390892467] [2019-12-07 18:58:03,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,168 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390892467] [2019-12-07 18:58:03,168 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,168 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865457032] [2019-12-07 18:58:03,168 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,169 INFO L82 PathProgramCache]: Analyzing trace with hash 1477654567, now seen corresponding path program 1 times [2019-12-07 18:58:03,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158995617] [2019-12-07 18:58:03,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,213 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158995617] [2019-12-07 18:58:03,213 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,213 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,213 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113709190] [2019-12-07 18:58:03,213 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,214 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,214 INFO L87 Difference]: Start difference. First operand 413 states and 629 transitions. cyclomatic complexity: 217 Second operand 3 states. [2019-12-07 18:58:03,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,224 INFO L93 Difference]: Finished difference Result 413 states and 628 transitions. [2019-12-07 18:58:03,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 628 transitions. [2019-12-07 18:58:03,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 628 transitions. [2019-12-07 18:58:03,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2019-12-07 18:58:03,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2019-12-07 18:58:03,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 628 transitions. [2019-12-07 18:58:03,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,234 INFO L688 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2019-12-07 18:58:03,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 628 transitions. [2019-12-07 18:58:03,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2019-12-07 18:58:03,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2019-12-07 18:58:03,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 628 transitions. [2019-12-07 18:58:03,245 INFO L711 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2019-12-07 18:58:03,245 INFO L591 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2019-12-07 18:58:03,245 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:58:03,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 628 transitions. [2019-12-07 18:58:03,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,250 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,250 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,250 INFO L794 eck$LassoCheckResult]: Stem: 2026#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1954#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1955#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2071#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 1909#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1910#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1799#L365-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1800#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1880#L375-1 assume !(0 == ~M_E~0); 1881#L516-1 assume !(0 == ~T1_E~0); 1733#L521-1 assume !(0 == ~T2_E~0); 1734#L526-1 assume !(0 == ~T3_E~0); 1917#L531-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1918#L536-1 assume !(0 == ~E_M~0); 1817#L541-1 assume !(0 == ~E_1~0); 1818#L546-1 assume !(0 == ~E_2~0); 1888#L551-1 assume !(0 == ~E_3~0); 1782#L556-1 assume !(0 == ~E_4~0); 1783#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1951#L252 assume 1 == ~m_pc~0; 1952#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1933#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1953#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2017#L639 assume !(0 != activate_threads_~tmp~1); 1883#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1884#L271 assume !(1 == ~t1_pc~0); 2061#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 2063#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2064#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2087#L647 assume !(0 != activate_threads_~tmp___0~0); 2088#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1743#L290 assume 1 == ~t2_pc~0; 1744#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1732#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1745#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1788#L655 assume !(0 != activate_threads_~tmp___1~0); 1776#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1777#L309 assume !(1 == ~t3_pc~0); 1805#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 1804#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1801#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1802#L663 assume !(0 != activate_threads_~tmp___2~0); 1926#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1927#L328 assume 1 == ~t4_pc~0; 1958#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1959#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1956#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1957#L671 assume !(0 != activate_threads_~tmp___3~0); 2042#L671-2 assume !(1 == ~M_E~0); 1815#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1816#L579-1 assume !(1 == ~T2_E~0); 1885#L584-1 assume !(1 == ~T3_E~0); 1778#L589-1 assume !(1 == ~T4_E~0); 1779#L594-1 assume !(1 == ~E_M~0); 1687#L599-1 assume !(1 == ~E_1~0); 1688#L604-1 assume !(1 == ~E_2~0); 1758#L609-1 assume !(1 == ~E_3~0); 1759#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1823#L805-1 [2019-12-07 18:58:03,250 INFO L796 eck$LassoCheckResult]: Loop: 1823#L805-1 assume !false; 1824#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1738#L491 assume !false; 2077#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1903#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1749#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2085#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1875#L430 assume !(0 != eval_~tmp~0); 1877#L506 start_simulation_~kernel_st~0 := 2; 2044#L348-1 start_simulation_~kernel_st~0 := 3; 2000#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2001#L516-4 assume !(0 == ~T1_E~0); 1746#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1747#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1921#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1922#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1821#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1822#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1872#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1767#L556-3 assume !(0 == ~E_4~0); 1768#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2038#L252-18 assume !(1 == ~m_pc~0); 2032#L252-20 is_master_triggered_~__retres1~0 := 0; 1970#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1971#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1849#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1850#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1855#L271-18 assume 1 == ~t1_pc~0; 2091#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2053#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2054#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2010#L647-18 assume !(0 != activate_threads_~tmp___0~0); 2004#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1682#L290-18 assume 1 == ~t2_pc~0; 1683#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1699#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1705#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1795#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2079#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1827#L309-18 assume !(1 == ~t3_pc~0); 1828#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 1832#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1869#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1902#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1892#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1893#L328-18 assume 1 == ~t4_pc~0; 1938#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1939#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1936#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1937#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2023#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1819#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1820#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1889#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1785#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1786#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1797#L599-3 assume !(1 == ~E_1~0); 1798#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1729#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1730#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1916#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1907#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1752#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2086#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2002#L824 assume !(0 == start_simulation_~tmp~3); 2003#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1911#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1724#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2013#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 2014#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1695#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 1696#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1787#L837 assume !(0 != start_simulation_~tmp___0~1); 1823#L805-1 [2019-12-07 18:58:03,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,251 INFO L82 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2019-12-07 18:58:03,251 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,251 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131120319] [2019-12-07 18:58:03,251 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,273 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131120319] [2019-12-07 18:58:03,274 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,274 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,274 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668216733] [2019-12-07 18:58:03,274 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,275 INFO L82 PathProgramCache]: Analyzing trace with hash 776086342, now seen corresponding path program 1 times [2019-12-07 18:58:03,275 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,275 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071002799] [2019-12-07 18:58:03,275 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071002799] [2019-12-07 18:58:03,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,310 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547844652] [2019-12-07 18:58:03,311 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,311 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,312 INFO L87 Difference]: Start difference. First operand 413 states and 628 transitions. cyclomatic complexity: 216 Second operand 3 states. [2019-12-07 18:58:03,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,320 INFO L93 Difference]: Finished difference Result 413 states and 627 transitions. [2019-12-07 18:58:03,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 627 transitions. [2019-12-07 18:58:03,323 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 627 transitions. [2019-12-07 18:58:03,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2019-12-07 18:58:03,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2019-12-07 18:58:03,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 627 transitions. [2019-12-07 18:58:03,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,327 INFO L688 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2019-12-07 18:58:03,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 627 transitions. [2019-12-07 18:58:03,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2019-12-07 18:58:03,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2019-12-07 18:58:03,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 627 transitions. [2019-12-07 18:58:03,335 INFO L711 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2019-12-07 18:58:03,335 INFO L591 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2019-12-07 18:58:03,335 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:58:03,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 627 transitions. [2019-12-07 18:58:03,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,339 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,339 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,339 INFO L794 eck$LassoCheckResult]: Stem: 2859#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2787#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2788#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2904#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 2742#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2743#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2632#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2633#L370-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2713#L375-1 assume !(0 == ~M_E~0); 2714#L516-1 assume !(0 == ~T1_E~0); 2566#L521-1 assume !(0 == ~T2_E~0); 2567#L526-1 assume !(0 == ~T3_E~0); 2750#L531-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2751#L536-1 assume !(0 == ~E_M~0); 2650#L541-1 assume !(0 == ~E_1~0); 2651#L546-1 assume !(0 == ~E_2~0); 2721#L551-1 assume !(0 == ~E_3~0); 2615#L556-1 assume !(0 == ~E_4~0); 2616#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2784#L252 assume 1 == ~m_pc~0; 2785#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2766#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2786#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2850#L639 assume !(0 != activate_threads_~tmp~1); 2716#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2717#L271 assume !(1 == ~t1_pc~0); 2894#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 2896#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2897#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2920#L647 assume !(0 != activate_threads_~tmp___0~0); 2921#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2576#L290 assume 1 == ~t2_pc~0; 2577#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2565#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2578#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2621#L655 assume !(0 != activate_threads_~tmp___1~0); 2609#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2610#L309 assume !(1 == ~t3_pc~0); 2638#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 2637#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2634#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2635#L663 assume !(0 != activate_threads_~tmp___2~0); 2759#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2760#L328 assume 1 == ~t4_pc~0; 2791#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2792#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2789#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2790#L671 assume !(0 != activate_threads_~tmp___3~0); 2875#L671-2 assume !(1 == ~M_E~0); 2648#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2649#L579-1 assume !(1 == ~T2_E~0); 2718#L584-1 assume !(1 == ~T3_E~0); 2611#L589-1 assume !(1 == ~T4_E~0); 2612#L594-1 assume !(1 == ~E_M~0); 2520#L599-1 assume !(1 == ~E_1~0); 2521#L604-1 assume !(1 == ~E_2~0); 2591#L609-1 assume !(1 == ~E_3~0); 2592#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2656#L805-1 [2019-12-07 18:58:03,339 INFO L796 eck$LassoCheckResult]: Loop: 2656#L805-1 assume !false; 2657#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2571#L491 assume !false; 2910#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2736#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2582#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2918#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2708#L430 assume !(0 != eval_~tmp~0); 2710#L506 start_simulation_~kernel_st~0 := 2; 2877#L348-1 start_simulation_~kernel_st~0 := 3; 2833#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2834#L516-4 assume !(0 == ~T1_E~0); 2579#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2580#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2754#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2755#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2654#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2655#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2705#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2600#L556-3 assume !(0 == ~E_4~0); 2601#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2871#L252-18 assume 1 == ~m_pc~0; 2864#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2803#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2804#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2682#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2683#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2688#L271-18 assume 1 == ~t1_pc~0; 2924#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2886#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2887#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2843#L647-18 assume !(0 != activate_threads_~tmp___0~0); 2837#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2515#L290-18 assume 1 == ~t2_pc~0; 2516#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2532#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2538#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2628#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2912#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2660#L309-18 assume !(1 == ~t3_pc~0); 2661#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 2665#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2702#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2735#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2725#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2726#L328-18 assume 1 == ~t4_pc~0; 2771#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2772#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2769#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2770#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2856#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2652#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2653#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2722#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2618#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2619#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2630#L599-3 assume !(1 == ~E_1~0); 2631#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2562#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2563#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2749#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2740#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2585#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2919#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2835#L824 assume !(0 == start_simulation_~tmp~3); 2836#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2744#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2557#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2846#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 2847#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2528#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 2529#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2620#L837 assume !(0 != start_simulation_~tmp___0~1); 2656#L805-1 [2019-12-07 18:58:03,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2019-12-07 18:58:03,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,340 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358359596] [2019-12-07 18:58:03,340 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,359 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358359596] [2019-12-07 18:58:03,360 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,360 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,360 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180669478] [2019-12-07 18:58:03,360 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,360 INFO L82 PathProgramCache]: Analyzing trace with hash 1477654567, now seen corresponding path program 2 times [2019-12-07 18:58:03,361 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,361 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31519187] [2019-12-07 18:58:03,361 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31519187] [2019-12-07 18:58:03,392 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,392 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,392 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259518428] [2019-12-07 18:58:03,392 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,393 INFO L87 Difference]: Start difference. First operand 413 states and 627 transitions. cyclomatic complexity: 215 Second operand 3 states. [2019-12-07 18:58:03,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,400 INFO L93 Difference]: Finished difference Result 413 states and 626 transitions. [2019-12-07 18:58:03,401 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 626 transitions. [2019-12-07 18:58:03,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 626 transitions. [2019-12-07 18:58:03,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2019-12-07 18:58:03,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2019-12-07 18:58:03,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 626 transitions. [2019-12-07 18:58:03,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,407 INFO L688 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2019-12-07 18:58:03,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 626 transitions. [2019-12-07 18:58:03,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2019-12-07 18:58:03,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2019-12-07 18:58:03,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 626 transitions. [2019-12-07 18:58:03,413 INFO L711 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2019-12-07 18:58:03,413 INFO L591 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2019-12-07 18:58:03,413 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:58:03,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 626 transitions. [2019-12-07 18:58:03,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,416 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,416 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,416 INFO L794 eck$LassoCheckResult]: Stem: 3693#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3620#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3621#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3738#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 3577#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3578#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3465#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3466#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3547#L375-1 assume !(0 == ~M_E~0); 3548#L516-1 assume !(0 == ~T1_E~0); 3400#L521-1 assume !(0 == ~T2_E~0); 3401#L526-1 assume !(0 == ~T3_E~0); 3584#L531-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3585#L536-1 assume !(0 == ~E_M~0); 3483#L541-1 assume !(0 == ~E_1~0); 3484#L546-1 assume !(0 == ~E_2~0); 3554#L551-1 assume !(0 == ~E_3~0); 3448#L556-1 assume !(0 == ~E_4~0); 3449#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3617#L252 assume 1 == ~m_pc~0; 3618#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3599#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3619#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3683#L639 assume !(0 != activate_threads_~tmp~1); 3549#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3550#L271 assume !(1 == ~t1_pc~0); 3727#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 3729#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3730#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3753#L647 assume !(0 != activate_threads_~tmp___0~0); 3754#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3409#L290 assume 1 == ~t2_pc~0; 3410#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3398#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3411#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3454#L655 assume !(0 != activate_threads_~tmp___1~0); 3442#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3443#L309 assume !(1 == ~t3_pc~0); 3471#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 3470#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3467#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3468#L663 assume !(0 != activate_threads_~tmp___2~0); 3592#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3593#L328 assume 1 == ~t4_pc~0; 3624#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3625#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3622#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3623#L671 assume !(0 != activate_threads_~tmp___3~0); 3708#L671-2 assume !(1 == ~M_E~0); 3481#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3482#L579-1 assume !(1 == ~T2_E~0); 3551#L584-1 assume !(1 == ~T3_E~0); 3446#L589-1 assume !(1 == ~T4_E~0); 3447#L594-1 assume !(1 == ~E_M~0); 3353#L599-1 assume !(1 == ~E_1~0); 3354#L604-1 assume !(1 == ~E_2~0); 3424#L609-1 assume !(1 == ~E_3~0); 3425#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3491#L805-1 [2019-12-07 18:58:03,417 INFO L796 eck$LassoCheckResult]: Loop: 3491#L805-1 assume !false; 3492#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3404#L491 assume !false; 3743#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3569#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3415#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3751#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3541#L430 assume !(0 != eval_~tmp~0); 3543#L506 start_simulation_~kernel_st~0 := 2; 3710#L348-1 start_simulation_~kernel_st~0 := 3; 3666#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3667#L516-4 assume !(0 == ~T1_E~0); 3412#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3413#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3587#L531-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3588#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3487#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3488#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3537#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3433#L556-3 assume !(0 == ~E_4~0); 3434#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3704#L252-18 assume 1 == ~m_pc~0; 3696#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3636#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3637#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3515#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3516#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3521#L271-18 assume 1 == ~t1_pc~0; 3757#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3719#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3720#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3676#L647-18 assume !(0 != activate_threads_~tmp___0~0); 3670#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3348#L290-18 assume 1 == ~t2_pc~0; 3349#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3365#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3371#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3461#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3745#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3493#L309-18 assume !(1 == ~t3_pc~0); 3494#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 3498#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3534#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3568#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3558#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3559#L328-18 assume 1 == ~t4_pc~0; 3604#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3605#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3600#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3601#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3689#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3485#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3486#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3555#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3451#L589-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3452#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3463#L599-3 assume !(1 == ~E_1~0); 3464#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3395#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3396#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3582#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3573#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3418#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3752#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3668#L824 assume !(0 == start_simulation_~tmp~3); 3669#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3575#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3390#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3679#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 3680#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3361#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 3362#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3453#L837 assume !(0 != start_simulation_~tmp___0~1); 3491#L805-1 [2019-12-07 18:58:03,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,417 INFO L82 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2019-12-07 18:58:03,417 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,417 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556000329] [2019-12-07 18:58:03,417 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,439 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556000329] [2019-12-07 18:58:03,439 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,439 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,440 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325320858] [2019-12-07 18:58:03,440 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,440 INFO L82 PathProgramCache]: Analyzing trace with hash 1477654567, now seen corresponding path program 3 times [2019-12-07 18:58:03,440 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,440 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511238592] [2019-12-07 18:58:03,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,469 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511238592] [2019-12-07 18:58:03,469 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,469 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,469 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846599418] [2019-12-07 18:58:03,469 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,470 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,470 INFO L87 Difference]: Start difference. First operand 413 states and 626 transitions. cyclomatic complexity: 214 Second operand 3 states. [2019-12-07 18:58:03,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,492 INFO L93 Difference]: Finished difference Result 413 states and 621 transitions. [2019-12-07 18:58:03,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 621 transitions. [2019-12-07 18:58:03,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 621 transitions. [2019-12-07 18:58:03,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2019-12-07 18:58:03,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2019-12-07 18:58:03,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 621 transitions. [2019-12-07 18:58:03,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,498 INFO L688 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2019-12-07 18:58:03,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 621 transitions. [2019-12-07 18:58:03,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2019-12-07 18:58:03,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413 states. [2019-12-07 18:58:03,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 621 transitions. [2019-12-07 18:58:03,503 INFO L711 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2019-12-07 18:58:03,503 INFO L591 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2019-12-07 18:58:03,503 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:58:03,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 621 transitions. [2019-12-07 18:58:03,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2019-12-07 18:58:03,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,506 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,506 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,507 INFO L794 eck$LassoCheckResult]: Stem: 4525#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4453#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4454#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4570#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 4410#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4411#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4298#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4299#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4379#L375-1 assume !(0 == ~M_E~0); 4380#L516-1 assume !(0 == ~T1_E~0); 4232#L521-1 assume !(0 == ~T2_E~0); 4233#L526-1 assume !(0 == ~T3_E~0); 4416#L531-1 assume !(0 == ~T4_E~0); 4417#L536-1 assume !(0 == ~E_M~0); 4316#L541-1 assume !(0 == ~E_1~0); 4317#L546-1 assume !(0 == ~E_2~0); 4387#L551-1 assume !(0 == ~E_3~0); 4281#L556-1 assume !(0 == ~E_4~0); 4282#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4450#L252 assume 1 == ~m_pc~0; 4451#L253 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4432#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4452#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4516#L639 assume !(0 != activate_threads_~tmp~1); 4382#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4383#L271 assume !(1 == ~t1_pc~0); 4560#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 4562#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4563#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4586#L647 assume !(0 != activate_threads_~tmp___0~0); 4587#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4242#L290 assume 1 == ~t2_pc~0; 4243#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4231#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4244#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4287#L655 assume !(0 != activate_threads_~tmp___1~0); 4275#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4276#L309 assume !(1 == ~t3_pc~0); 4304#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 4303#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4300#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4301#L663 assume !(0 != activate_threads_~tmp___2~0); 4425#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4426#L328 assume 1 == ~t4_pc~0; 4457#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4458#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4455#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4456#L671 assume !(0 != activate_threads_~tmp___3~0); 4541#L671-2 assume !(1 == ~M_E~0); 4314#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4315#L579-1 assume !(1 == ~T2_E~0); 4384#L584-1 assume !(1 == ~T3_E~0); 4277#L589-1 assume !(1 == ~T4_E~0); 4278#L594-1 assume !(1 == ~E_M~0); 4186#L599-1 assume !(1 == ~E_1~0); 4187#L604-1 assume !(1 == ~E_2~0); 4257#L609-1 assume !(1 == ~E_3~0); 4258#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4322#L805-1 [2019-12-07 18:58:03,507 INFO L796 eck$LassoCheckResult]: Loop: 4322#L805-1 assume !false; 4323#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4237#L491 assume !false; 4576#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4402#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4248#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4584#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4374#L430 assume !(0 != eval_~tmp~0); 4376#L506 start_simulation_~kernel_st~0 := 2; 4543#L348-1 start_simulation_~kernel_st~0 := 3; 4499#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4500#L516-4 assume !(0 == ~T1_E~0); 4245#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4246#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4420#L531-3 assume !(0 == ~T4_E~0); 4421#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4320#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4321#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4371#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4266#L556-3 assume !(0 == ~E_4~0); 4267#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4537#L252-18 assume 1 == ~m_pc~0; 4530#L253-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4469#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4470#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4348#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4349#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4354#L271-18 assume 1 == ~t1_pc~0; 4590#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4552#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4553#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4509#L647-18 assume !(0 != activate_threads_~tmp___0~0); 4503#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4181#L290-18 assume 1 == ~t2_pc~0; 4182#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4198#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4204#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4294#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4578#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4326#L309-18 assume !(1 == ~t3_pc~0); 4327#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 4331#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4368#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4401#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4391#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4392#L328-18 assume 1 == ~t4_pc~0; 4437#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4438#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4433#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4434#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4522#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4318#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4319#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4388#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4283#L589-3 assume !(1 == ~T4_E~0); 4284#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4296#L599-3 assume !(1 == ~E_1~0); 4297#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4228#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4229#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4415#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4406#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4251#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4585#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4501#L824 assume !(0 == start_simulation_~tmp~3); 4502#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4408#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4223#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4510#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 4511#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4194#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 4195#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4286#L837 assume !(0 != start_simulation_~tmp___0~1); 4322#L805-1 [2019-12-07 18:58:03,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,507 INFO L82 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2019-12-07 18:58:03,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775205269] [2019-12-07 18:58:03,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,529 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775205269] [2019-12-07 18:58:03,529 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,529 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184433775] [2019-12-07 18:58:03,530 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,530 INFO L82 PathProgramCache]: Analyzing trace with hash 349410603, now seen corresponding path program 1 times [2019-12-07 18:58:03,530 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,530 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631426006] [2019-12-07 18:58:03,530 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,560 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631426006] [2019-12-07 18:58:03,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,560 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130385193] [2019-12-07 18:58:03,561 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,561 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,561 INFO L87 Difference]: Start difference. First operand 413 states and 621 transitions. cyclomatic complexity: 209 Second operand 3 states. [2019-12-07 18:58:03,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,609 INFO L93 Difference]: Finished difference Result 749 states and 1110 transitions. [2019-12-07 18:58:03,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 749 states and 1110 transitions. [2019-12-07 18:58:03,614 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 685 [2019-12-07 18:58:03,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 749 states to 749 states and 1110 transitions. [2019-12-07 18:58:03,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 749 [2019-12-07 18:58:03,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 749 [2019-12-07 18:58:03,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 749 states and 1110 transitions. [2019-12-07 18:58:03,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,621 INFO L688 BuchiCegarLoop]: Abstraction has 749 states and 1110 transitions. [2019-12-07 18:58:03,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states and 1110 transitions. [2019-12-07 18:58:03,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 716. [2019-12-07 18:58:03,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2019-12-07 18:58:03,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 1064 transitions. [2019-12-07 18:58:03,634 INFO L711 BuchiCegarLoop]: Abstraction has 716 states and 1064 transitions. [2019-12-07 18:58:03,634 INFO L591 BuchiCegarLoop]: Abstraction has 716 states and 1064 transitions. [2019-12-07 18:58:03,634 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:58:03,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 716 states and 1064 transitions. [2019-12-07 18:58:03,637 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2019-12-07 18:58:03,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,639 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,639 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,639 INFO L794 eck$LassoCheckResult]: Stem: 5701#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5624#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5625#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5760#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 5580#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5581#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5467#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5468#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5549#L375-1 assume !(0 == ~M_E~0); 5550#L516-1 assume !(0 == ~T1_E~0); 5401#L521-1 assume !(0 == ~T2_E~0); 5402#L526-1 assume !(0 == ~T3_E~0); 5587#L531-1 assume !(0 == ~T4_E~0); 5588#L536-1 assume !(0 == ~E_M~0); 5485#L541-1 assume !(0 == ~E_1~0); 5486#L546-1 assume !(0 == ~E_2~0); 5557#L551-1 assume !(0 == ~E_3~0); 5450#L556-1 assume !(0 == ~E_4~0); 5451#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5622#L252 assume !(1 == ~m_pc~0); 5603#L252-2 is_master_triggered_~__retres1~0 := 0; 5604#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5623#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5687#L639 assume !(0 != activate_threads_~tmp~1); 5552#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5553#L271 assume !(1 == ~t1_pc~0); 5750#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 5752#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5753#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5776#L647 assume !(0 != activate_threads_~tmp___0~0); 5777#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5411#L290 assume 1 == ~t2_pc~0; 5412#L291 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5400#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5413#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5456#L655 assume !(0 != activate_threads_~tmp___1~0); 5444#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5445#L309 assume !(1 == ~t3_pc~0); 5473#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 5472#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5469#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5470#L663 assume !(0 != activate_threads_~tmp___2~0); 5595#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5596#L328 assume 1 == ~t4_pc~0; 5628#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5629#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5626#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5627#L671 assume !(0 != activate_threads_~tmp___3~0); 5724#L671-2 assume !(1 == ~M_E~0); 5483#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5484#L579-1 assume !(1 == ~T2_E~0); 5554#L584-1 assume !(1 == ~T3_E~0); 5448#L589-1 assume !(1 == ~T4_E~0); 5449#L594-1 assume !(1 == ~E_M~0); 5355#L599-1 assume !(1 == ~E_1~0); 5356#L604-1 assume !(1 == ~E_2~0); 5426#L609-1 assume !(1 == ~E_3~0); 5427#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5493#L805-1 [2019-12-07 18:58:03,639 INFO L796 eck$LassoCheckResult]: Loop: 5493#L805-1 assume !false; 5494#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5406#L491 assume !false; 5766#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5572#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5417#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5774#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5544#L430 assume !(0 != eval_~tmp~0); 5546#L506 start_simulation_~kernel_st~0 := 2; 6030#L348-1 start_simulation_~kernel_st~0 := 3; 6026#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6025#L516-4 assume !(0 == ~T1_E~0); 6024#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6023#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6022#L531-3 assume !(0 == ~T4_E~0); 6021#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6020#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6019#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6018#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6017#L556-3 assume !(0 == ~E_4~0); 6016#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5733#L252-18 assume !(1 == ~m_pc~0); 5722#L252-20 is_master_triggered_~__retres1~0 := 0; 5642#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5643#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5518#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5519#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5524#L271-18 assume 1 == ~t1_pc~0; 5781#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5742#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5743#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5680#L647-18 assume !(0 != activate_threads_~tmp___0~0); 5674#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5350#L290-18 assume 1 == ~t2_pc~0; 5351#L291-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5367#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5373#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5463#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5768#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5495#L309-18 assume !(1 == ~t3_pc~0); 5496#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 5500#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5537#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5571#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5561#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5562#L328-18 assume 1 == ~t4_pc~0; 5609#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5610#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5605#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5606#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5696#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5487#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5488#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5558#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5453#L589-3 assume !(1 == ~T4_E~0); 5454#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5465#L599-3 assume !(1 == ~E_1~0); 5466#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5397#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5398#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5585#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5576#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5420#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5775#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5671#L824 assume !(0 == start_simulation_~tmp~3); 5673#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5578#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5392#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5681#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 5682#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5363#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 5364#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5455#L837 assume !(0 != start_simulation_~tmp___0~1); 5493#L805-1 [2019-12-07 18:58:03,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,640 INFO L82 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2019-12-07 18:58:03,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539192644] [2019-12-07 18:58:03,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539192644] [2019-12-07 18:58:03,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239298720] [2019-12-07 18:58:03,663 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,664 INFO L82 PathProgramCache]: Analyzing trace with hash -352157622, now seen corresponding path program 1 times [2019-12-07 18:58:03,664 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,664 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692737611] [2019-12-07 18:58:03,664 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692737611] [2019-12-07 18:58:03,688 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,688 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,688 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905297620] [2019-12-07 18:58:03,688 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,688 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,689 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,689 INFO L87 Difference]: Start difference. First operand 716 states and 1064 transitions. cyclomatic complexity: 350 Second operand 3 states. [2019-12-07 18:58:03,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,732 INFO L93 Difference]: Finished difference Result 1287 states and 1897 transitions. [2019-12-07 18:58:03,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1287 states and 1897 transitions. [2019-12-07 18:58:03,740 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1218 [2019-12-07 18:58:03,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1287 states to 1287 states and 1897 transitions. [2019-12-07 18:58:03,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1287 [2019-12-07 18:58:03,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1287 [2019-12-07 18:58:03,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1287 states and 1897 transitions. [2019-12-07 18:58:03,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,753 INFO L688 BuchiCegarLoop]: Abstraction has 1287 states and 1897 transitions. [2019-12-07 18:58:03,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1287 states and 1897 transitions. [2019-12-07 18:58:03,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1287 to 1283. [2019-12-07 18:58:03,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1283 states. [2019-12-07 18:58:03,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1283 states to 1283 states and 1893 transitions. [2019-12-07 18:58:03,771 INFO L711 BuchiCegarLoop]: Abstraction has 1283 states and 1893 transitions. [2019-12-07 18:58:03,771 INFO L591 BuchiCegarLoop]: Abstraction has 1283 states and 1893 transitions. [2019-12-07 18:58:03,771 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:58:03,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1283 states and 1893 transitions. [2019-12-07 18:58:03,775 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1214 [2019-12-07 18:58:03,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,776 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,776 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,776 INFO L794 eck$LassoCheckResult]: Stem: 7722#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7645#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7646#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7784#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 7602#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7603#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7488#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7489#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7570#L375-1 assume !(0 == ~M_E~0); 7571#L516-1 assume !(0 == ~T1_E~0); 7407#L521-1 assume !(0 == ~T2_E~0); 7408#L526-1 assume !(0 == ~T3_E~0); 7609#L531-1 assume !(0 == ~T4_E~0); 7610#L536-1 assume !(0 == ~E_M~0); 7506#L541-1 assume !(0 == ~E_1~0); 7507#L546-1 assume !(0 == ~E_2~0); 7578#L551-1 assume !(0 == ~E_3~0); 7455#L556-1 assume !(0 == ~E_4~0); 7456#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7643#L252 assume !(1 == ~m_pc~0); 7624#L252-2 is_master_triggered_~__retres1~0 := 0; 7625#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7644#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7707#L639 assume !(0 != activate_threads_~tmp~1); 7573#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7574#L271 assume !(1 == ~t1_pc~0); 7772#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 7774#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7775#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7803#L647 assume !(0 != activate_threads_~tmp___0~0); 7804#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7417#L290 assume !(1 == ~t2_pc~0); 7404#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 7405#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7420#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7461#L655 assume !(0 != activate_threads_~tmp___1~0); 7449#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7450#L309 assume !(1 == ~t3_pc~0); 7494#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 7493#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7490#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7491#L663 assume !(0 != activate_threads_~tmp___2~0); 7617#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7618#L328 assume 1 == ~t4_pc~0; 7649#L329 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7650#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7647#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7648#L671 assume !(0 != activate_threads_~tmp___3~0); 7746#L671-2 assume !(1 == ~M_E~0); 7504#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7505#L579-1 assume !(1 == ~T2_E~0); 7575#L584-1 assume !(1 == ~T3_E~0); 7453#L589-1 assume !(1 == ~T4_E~0); 7454#L594-1 assume !(1 == ~E_M~0); 7364#L599-1 assume !(1 == ~E_1~0); 7365#L604-1 assume !(1 == ~E_2~0); 7431#L609-1 assume !(1 == ~E_3~0); 7432#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7514#L805-1 [2019-12-07 18:58:03,776 INFO L796 eck$LassoCheckResult]: Loop: 7514#L805-1 assume !false; 7515#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7411#L491 assume !false; 7994#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7594#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7422#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7801#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7564#L430 assume !(0 != eval_~tmp~0); 7566#L506 start_simulation_~kernel_st~0 := 2; 7749#L348-1 start_simulation_~kernel_st~0 := 3; 7689#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7690#L516-4 assume !(0 == ~T1_E~0); 7418#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7419#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7612#L531-3 assume !(0 == ~T4_E~0); 7613#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7510#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7511#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7561#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7440#L556-3 assume !(0 == ~E_4~0); 7441#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7739#L252-18 assume !(1 == ~m_pc~0); 7743#L252-20 is_master_triggered_~__retres1~0 := 0; 7660#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7661#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7538#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7539#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7544#L271-18 assume 1 == ~t1_pc~0; 7808#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7764#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7765#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7700#L647-18 assume !(0 != activate_threads_~tmp___0~0); 7693#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7360#L290-18 assume !(1 == ~t2_pc~0); 7361#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 8608#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8607#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8544#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8543#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8542#L309-18 assume !(1 == ~t3_pc~0); 8540#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 8539#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8538#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8537#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8536#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8535#L328-18 assume 1 == ~t4_pc~0; 8533#L329-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8532#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8531#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8530#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8529#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 8528#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8527#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8525#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7458#L589-3 assume !(1 == ~T4_E~0); 7459#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7481#L599-3 assume !(1 == ~E_1~0); 7482#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7402#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7403#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7607#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7598#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7425#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7802#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 7691#L824 assume !(0 == start_simulation_~tmp~3); 7692#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7600#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7397#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7703#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 7704#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7371#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 7372#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7460#L837 assume !(0 != start_simulation_~tmp___0~1); 7514#L805-1 [2019-12-07 18:58:03,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,776 INFO L82 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2019-12-07 18:58:03,777 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238833167] [2019-12-07 18:58:03,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238833167] [2019-12-07 18:58:03,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,792 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106152471] [2019-12-07 18:58:03,793 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,793 INFO L82 PathProgramCache]: Analyzing trace with hash 47833577, now seen corresponding path program 1 times [2019-12-07 18:58:03,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106895072] [2019-12-07 18:58:03,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,809 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106895072] [2019-12-07 18:58:03,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,810 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509747009] [2019-12-07 18:58:03,810 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,810 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,810 INFO L87 Difference]: Start difference. First operand 1283 states and 1893 transitions. cyclomatic complexity: 614 Second operand 3 states. [2019-12-07 18:58:03,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,856 INFO L93 Difference]: Finished difference Result 2344 states and 3436 transitions. [2019-12-07 18:58:03,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2344 states and 3436 transitions. [2019-12-07 18:58:03,871 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2260 [2019-12-07 18:58:03,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2344 states to 2344 states and 3436 transitions. [2019-12-07 18:58:03,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2344 [2019-12-07 18:58:03,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2344 [2019-12-07 18:58:03,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2344 states and 3436 transitions. [2019-12-07 18:58:03,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:03,893 INFO L688 BuchiCegarLoop]: Abstraction has 2344 states and 3436 transitions. [2019-12-07 18:58:03,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2344 states and 3436 transitions. [2019-12-07 18:58:03,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2344 to 2336. [2019-12-07 18:58:03,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2336 states. [2019-12-07 18:58:03,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2336 states to 2336 states and 3428 transitions. [2019-12-07 18:58:03,930 INFO L711 BuchiCegarLoop]: Abstraction has 2336 states and 3428 transitions. [2019-12-07 18:58:03,930 INFO L591 BuchiCegarLoop]: Abstraction has 2336 states and 3428 transitions. [2019-12-07 18:58:03,930 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:58:03,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2336 states and 3428 transitions. [2019-12-07 18:58:03,937 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:03,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:03,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:03,938 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,938 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:03,938 INFO L794 eck$LassoCheckResult]: Stem: 11372#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11280#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11281#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11433#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 11235#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11236#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11119#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11120#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11205#L375-1 assume !(0 == ~M_E~0); 11206#L516-1 assume !(0 == ~T1_E~0); 11040#L521-1 assume !(0 == ~T2_E~0); 11041#L526-1 assume !(0 == ~T3_E~0); 11243#L531-1 assume !(0 == ~T4_E~0); 11244#L536-1 assume !(0 == ~E_M~0); 11137#L541-1 assume !(0 == ~E_1~0); 11138#L546-1 assume !(0 == ~E_2~0); 11214#L551-1 assume !(0 == ~E_3~0); 11088#L556-1 assume !(0 == ~E_4~0); 11089#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11278#L252 assume !(1 == ~m_pc~0); 11260#L252-2 is_master_triggered_~__retres1~0 := 0; 11261#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11279#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11357#L639 assume !(0 != activate_threads_~tmp~1); 11209#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11210#L271 assume !(1 == ~t1_pc~0); 11423#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 11425#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11426#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11452#L647 assume !(0 != activate_threads_~tmp___0~0); 11453#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11050#L290 assume !(1 == ~t2_pc~0); 11038#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 11039#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11051#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11094#L655 assume !(0 != activate_threads_~tmp___1~0); 11082#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11083#L309 assume !(1 == ~t3_pc~0); 11125#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 11124#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11121#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11122#L663 assume !(0 != activate_threads_~tmp___2~0); 11252#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11253#L328 assume !(1 == ~t4_pc~0); 11355#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 11353#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11282#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11283#L671 assume !(0 != activate_threads_~tmp___3~0); 11397#L671-2 assume !(1 == ~M_E~0); 11135#L574-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11136#L579-1 assume !(1 == ~T2_E~0); 11211#L584-1 assume !(1 == ~T3_E~0); 11084#L589-1 assume !(1 == ~T4_E~0); 11085#L594-1 assume !(1 == ~E_M~0); 10998#L599-1 assume !(1 == ~E_1~0); 10999#L604-1 assume !(1 == ~E_2~0); 11064#L609-1 assume !(1 == ~E_3~0); 11065#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11454#L805-1 [2019-12-07 18:58:03,938 INFO L796 eck$LassoCheckResult]: Loop: 11454#L805-1 assume !false; 12874#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11440#L491 assume !false; 11441#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11229#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11055#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11450#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11199#L430 assume !(0 != eval_~tmp~0); 11201#L506 start_simulation_~kernel_st~0 := 2; 13232#L348-1 start_simulation_~kernel_st~0 := 3; 13231#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13230#L516-4 assume !(0 == ~T1_E~0); 13215#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13214#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13213#L531-3 assume !(0 == ~T4_E~0); 13212#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11141#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11142#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11196#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11073#L556-3 assume !(0 == ~E_4~0); 11074#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11391#L252-18 assume !(1 == ~m_pc~0); 11394#L252-20 is_master_triggered_~__retres1~0 := 0; 11292#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11293#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11381#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13209#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13208#L271-18 assume 1 == ~t1_pc~0; 13206#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13205#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13204#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13203#L647-18 assume !(0 != activate_threads_~tmp___0~0); 11329#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10994#L290-18 assume !(1 == ~t2_pc~0); 10995#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 11008#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11014#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11107#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11444#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11147#L309-18 assume !(1 == ~t3_pc~0); 11148#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 11152#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11192#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11228#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11218#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11219#L328-18 assume !(1 == ~t4_pc~0); 11323#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 11324#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11264#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11265#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11367#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 11139#L574-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11140#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11215#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11091#L589-3 assume !(1 == ~T4_E~0); 11092#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11114#L599-3 assume !(1 == ~E_1~0); 11115#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11036#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11037#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11242#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11233#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11058#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11451#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 11327#L824 assume !(0 == start_simulation_~tmp~3); 11328#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11237#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11032#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11466#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 13018#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13017#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 13016#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 12882#L837 assume !(0 != start_simulation_~tmp___0~1); 11454#L805-1 [2019-12-07 18:58:03,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,939 INFO L82 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2019-12-07 18:58:03,939 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,939 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759257559] [2019-12-07 18:58:03,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [759257559] [2019-12-07 18:58:03,957 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,957 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:03,957 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462230329] [2019-12-07 18:58:03,958 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:03,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:03,958 INFO L82 PathProgramCache]: Analyzing trace with hash -260605432, now seen corresponding path program 1 times [2019-12-07 18:58:03,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:03,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796023781] [2019-12-07 18:58:03,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:03,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:03,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:03,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796023781] [2019-12-07 18:58:03,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:03,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:03,974 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390165032] [2019-12-07 18:58:03,975 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:03,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:03,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:03,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:03,975 INFO L87 Difference]: Start difference. First operand 2336 states and 3428 transitions. cyclomatic complexity: 1100 Second operand 3 states. [2019-12-07 18:58:03,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:03,994 INFO L93 Difference]: Finished difference Result 2336 states and 3402 transitions. [2019-12-07 18:58:03,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:03,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2336 states and 3402 transitions. [2019-12-07 18:58:04,007 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2336 states to 2336 states and 3402 transitions. [2019-12-07 18:58:04,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2336 [2019-12-07 18:58:04,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2336 [2019-12-07 18:58:04,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2336 states and 3402 transitions. [2019-12-07 18:58:04,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,027 INFO L688 BuchiCegarLoop]: Abstraction has 2336 states and 3402 transitions. [2019-12-07 18:58:04,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2336 states and 3402 transitions. [2019-12-07 18:58:04,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2336 to 2336. [2019-12-07 18:58:04,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2336 states. [2019-12-07 18:58:04,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2336 states to 2336 states and 3402 transitions. [2019-12-07 18:58:04,053 INFO L711 BuchiCegarLoop]: Abstraction has 2336 states and 3402 transitions. [2019-12-07 18:58:04,053 INFO L591 BuchiCegarLoop]: Abstraction has 2336 states and 3402 transitions. [2019-12-07 18:58:04,053 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:58:04,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2336 states and 3402 transitions. [2019-12-07 18:58:04,060 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:04,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:04,061 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,061 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,061 INFO L794 eck$LassoCheckResult]: Stem: 16051#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 15960#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15961#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16112#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 15916#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15917#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15803#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15804#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15886#L375-1 assume !(0 == ~M_E~0); 15887#L516-1 assume !(0 == ~T1_E~0); 15719#L521-1 assume !(0 == ~T2_E~0); 15720#L526-1 assume !(0 == ~T3_E~0); 15924#L531-1 assume !(0 == ~T4_E~0); 15925#L536-1 assume !(0 == ~E_M~0); 15821#L541-1 assume !(0 == ~E_1~0); 15822#L546-1 assume !(0 == ~E_2~0); 15895#L551-1 assume !(0 == ~E_3~0); 15767#L556-1 assume !(0 == ~E_4~0); 15768#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15958#L252 assume !(1 == ~m_pc~0); 15940#L252-2 is_master_triggered_~__retres1~0 := 0; 15941#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15959#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16036#L639 assume !(0 != activate_threads_~tmp~1); 15890#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15891#L271 assume !(1 == ~t1_pc~0); 16102#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 16104#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16105#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16129#L647 assume !(0 != activate_threads_~tmp___0~0); 16130#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15729#L290 assume !(1 == ~t2_pc~0); 15717#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 15718#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15730#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15773#L655 assume !(0 != activate_threads_~tmp___1~0); 15761#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15762#L309 assume !(1 == ~t3_pc~0); 15809#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 15808#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15805#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15806#L663 assume !(0 != activate_threads_~tmp___2~0); 15933#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15934#L328 assume !(1 == ~t4_pc~0); 16032#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 16030#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15962#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15963#L671 assume !(0 != activate_threads_~tmp___3~0); 16077#L671-2 assume !(1 == ~M_E~0); 15819#L574-1 assume !(1 == ~T1_E~0); 15820#L579-1 assume !(1 == ~T2_E~0); 15892#L584-1 assume !(1 == ~T3_E~0); 15763#L589-1 assume !(1 == ~T4_E~0); 15764#L594-1 assume !(1 == ~E_M~0); 15677#L599-1 assume !(1 == ~E_1~0); 15678#L604-1 assume !(1 == ~E_2~0); 15743#L609-1 assume !(1 == ~E_3~0); 15744#L614-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15827#L805-1 [2019-12-07 18:58:04,061 INFO L796 eck$LassoCheckResult]: Loop: 15827#L805-1 assume !false; 15828#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15724#L491 assume !false; 16118#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15910#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15734#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16127#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 15880#L430 assume !(0 != eval_~tmp~0); 15882#L506 start_simulation_~kernel_st~0 := 2; 18006#L348-1 start_simulation_~kernel_st~0 := 3; 18005#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18004#L516-4 assume !(0 == ~T1_E~0); 18003#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18002#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18001#L531-3 assume !(0 == ~T4_E~0); 18000#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17999#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17998#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17997#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15752#L556-3 assume !(0 == ~E_4~0); 15753#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17969#L252-18 assume !(1 == ~m_pc~0); 17968#L252-20 is_master_triggered_~__retres1~0 := 0; 17967#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17966#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15853#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15854#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15859#L271-18 assume 1 == ~t1_pc~0; 16133#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16093#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16094#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16025#L647-18 assume !(0 != activate_threads_~tmp___0~0); 16010#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15673#L290-18 assume !(1 == ~t2_pc~0); 15674#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 15689#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15694#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15783#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16121#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15831#L309-18 assume !(1 == ~t3_pc~0); 15832#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 15836#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15872#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15909#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15899#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15900#L328-18 assume !(1 == ~t4_pc~0); 16003#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 16004#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15944#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15945#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16045#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 15823#L574-3 assume !(1 == ~T1_E~0); 15824#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15896#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15770#L589-3 assume !(1 == ~T4_E~0); 15771#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15793#L599-3 assume !(1 == ~E_1~0); 15794#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15715#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15716#L614-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15923#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15914#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15737#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16128#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 16007#L824 assume !(0 == start_simulation_~tmp~3); 16009#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15918#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15711#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16028#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 16029#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15685#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 15686#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 15772#L837 assume !(0 != start_simulation_~tmp___0~1); 15827#L805-1 [2019-12-07 18:58:04,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,062 INFO L82 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2019-12-07 18:58:04,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122160264] [2019-12-07 18:58:04,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122160264] [2019-12-07 18:58:04,081 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,081 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:58:04,081 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936142783] [2019-12-07 18:58:04,081 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:04,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,082 INFO L82 PathProgramCache]: Analyzing trace with hash -41750714, now seen corresponding path program 1 times [2019-12-07 18:58:04,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,082 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511309932] [2019-12-07 18:58:04,082 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,102 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511309932] [2019-12-07 18:58:04,102 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:04,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804094617] [2019-12-07 18:58:04,103 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:04,103 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:04,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:04,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:04,103 INFO L87 Difference]: Start difference. First operand 2336 states and 3402 transitions. cyclomatic complexity: 1074 Second operand 3 states. [2019-12-07 18:58:04,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:04,135 INFO L93 Difference]: Finished difference Result 2336 states and 3356 transitions. [2019-12-07 18:58:04,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:04,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2336 states and 3356 transitions. [2019-12-07 18:58:04,143 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2336 states to 2336 states and 3356 transitions. [2019-12-07 18:58:04,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2336 [2019-12-07 18:58:04,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2336 [2019-12-07 18:58:04,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2336 states and 3356 transitions. [2019-12-07 18:58:04,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,159 INFO L688 BuchiCegarLoop]: Abstraction has 2336 states and 3356 transitions. [2019-12-07 18:58:04,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2336 states and 3356 transitions. [2019-12-07 18:58:04,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2336 to 2336. [2019-12-07 18:58:04,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2336 states. [2019-12-07 18:58:04,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2336 states to 2336 states and 3356 transitions. [2019-12-07 18:58:04,184 INFO L711 BuchiCegarLoop]: Abstraction has 2336 states and 3356 transitions. [2019-12-07 18:58:04,184 INFO L591 BuchiCegarLoop]: Abstraction has 2336 states and 3356 transitions. [2019-12-07 18:58:04,184 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:58:04,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2336 states and 3356 transitions. [2019-12-07 18:58:04,188 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:04,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:04,189 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,189 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,189 INFO L794 eck$LassoCheckResult]: Stem: 20721#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20636#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20637#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20775#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 20592#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20593#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20477#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20478#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20562#L375-1 assume !(0 == ~M_E~0); 20563#L516-1 assume !(0 == ~T1_E~0); 20402#L521-1 assume !(0 == ~T2_E~0); 20403#L526-1 assume !(0 == ~T3_E~0); 20600#L531-1 assume !(0 == ~T4_E~0); 20601#L536-1 assume !(0 == ~E_M~0); 20495#L541-1 assume !(0 == ~E_1~0); 20496#L546-1 assume !(0 == ~E_2~0); 20570#L551-1 assume !(0 == ~E_3~0); 20450#L556-1 assume !(0 == ~E_4~0); 20451#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20634#L252 assume !(1 == ~m_pc~0); 20618#L252-2 is_master_triggered_~__retres1~0 := 0; 20619#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20635#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20708#L639 assume !(0 != activate_threads_~tmp~1); 20565#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20566#L271 assume !(1 == ~t1_pc~0); 20765#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 20767#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20768#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20797#L647 assume !(0 != activate_threads_~tmp___0~0); 20798#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20412#L290 assume !(1 == ~t2_pc~0); 20400#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 20401#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20413#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20456#L655 assume !(0 != activate_threads_~tmp___1~0); 20444#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20445#L309 assume !(1 == ~t3_pc~0); 20483#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 20482#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20479#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20480#L663 assume !(0 != activate_threads_~tmp___2~0); 20609#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20610#L328 assume !(1 == ~t4_pc~0); 20705#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 20703#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20638#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20639#L671 assume !(0 != activate_threads_~tmp___3~0); 20741#L671-2 assume !(1 == ~M_E~0); 20493#L574-1 assume !(1 == ~T1_E~0); 20494#L579-1 assume !(1 == ~T2_E~0); 20567#L584-1 assume !(1 == ~T3_E~0); 20446#L589-1 assume !(1 == ~T4_E~0); 20447#L594-1 assume !(1 == ~E_M~0); 20356#L599-1 assume !(1 == ~E_1~0); 20357#L604-1 assume !(1 == ~E_2~0); 20426#L609-1 assume !(1 == ~E_3~0); 20427#L614-1 assume !(1 == ~E_4~0); 20799#L805-1 [2019-12-07 18:58:04,190 INFO L796 eck$LassoCheckResult]: Loop: 20799#L805-1 assume !false; 21573#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 21570#L491 assume !false; 21568#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21566#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21561#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21560#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 21558#L430 assume !(0 != eval_~tmp~0); 21559#L506 start_simulation_~kernel_st~0 := 2; 21736#L348-1 start_simulation_~kernel_st~0 := 3; 21735#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21734#L516-4 assume !(0 == ~T1_E~0); 21733#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21732#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21731#L531-3 assume !(0 == ~T4_E~0); 21729#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21727#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21725#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21723#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21721#L556-3 assume !(0 == ~E_4~0); 21719#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21717#L252-18 assume !(1 == ~m_pc~0); 21714#L252-20 is_master_triggered_~__retres1~0 := 0; 21712#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21710#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 21708#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21706#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21704#L271-18 assume 1 == ~t1_pc~0; 21701#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21699#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21697#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 21695#L647-18 assume !(0 != activate_threads_~tmp___0~0); 21693#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21691#L290-18 assume !(1 == ~t2_pc~0); 21688#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 21686#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21684#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21682#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21680#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21678#L309-18 assume !(1 == ~t3_pc~0); 21675#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 21673#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21671#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21669#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21667#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21665#L328-18 assume !(1 == ~t4_pc~0); 21663#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 21661#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21659#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21657#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21655#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 21653#L574-3 assume !(1 == ~T1_E~0); 21651#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21650#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21649#L589-3 assume !(1 == ~T4_E~0); 21648#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21647#L599-3 assume !(1 == ~E_1~0); 21645#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21643#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21641#L614-3 assume !(1 == ~E_4~0); 21639#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21632#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21627#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21625#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 21622#L824 assume !(0 == start_simulation_~tmp~3); 21619#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 21617#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 21611#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 21609#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 21607#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21605#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 21603#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 21601#L837 assume !(0 != start_simulation_~tmp___0~1); 20799#L805-1 [2019-12-07 18:58:04,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,190 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2019-12-07 18:58:04,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690836567] [2019-12-07 18:58:04,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,221 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:04,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,221 INFO L82 PathProgramCache]: Analyzing trace with hash -1052867964, now seen corresponding path program 1 times [2019-12-07 18:58:04,221 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,221 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3703846] [2019-12-07 18:58:04,222 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,237 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3703846] [2019-12-07 18:58:04,237 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,237 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:04,237 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614379717] [2019-12-07 18:58:04,237 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:04,237 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:04,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:04,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:04,238 INFO L87 Difference]: Start difference. First operand 2336 states and 3356 transitions. cyclomatic complexity: 1028 Second operand 3 states. [2019-12-07 18:58:04,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:04,305 INFO L93 Difference]: Finished difference Result 4198 states and 5958 transitions. [2019-12-07 18:58:04,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:04,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4198 states and 5958 transitions. [2019-12-07 18:58:04,324 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4048 [2019-12-07 18:58:04,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4198 states to 4198 states and 5958 transitions. [2019-12-07 18:58:04,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4198 [2019-12-07 18:58:04,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4198 [2019-12-07 18:58:04,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4198 states and 5958 transitions. [2019-12-07 18:58:04,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,363 INFO L688 BuchiCegarLoop]: Abstraction has 4198 states and 5958 transitions. [2019-12-07 18:58:04,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4198 states and 5958 transitions. [2019-12-07 18:58:04,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4198 to 4142. [2019-12-07 18:58:04,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4142 states. [2019-12-07 18:58:04,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4142 states to 4142 states and 5874 transitions. [2019-12-07 18:58:04,408 INFO L711 BuchiCegarLoop]: Abstraction has 4142 states and 5874 transitions. [2019-12-07 18:58:04,408 INFO L591 BuchiCegarLoop]: Abstraction has 4142 states and 5874 transitions. [2019-12-07 18:58:04,408 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:58:04,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4142 states and 5874 transitions. [2019-12-07 18:58:04,417 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4000 [2019-12-07 18:58:04,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:04,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:04,418 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,418 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,418 INFO L794 eck$LassoCheckResult]: Stem: 27307#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27194#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27195#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27375#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 27144#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27145#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27018#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27019#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27107#L375-1 assume !(0 == ~M_E~0); 27108#L516-1 assume !(0 == ~T1_E~0); 26945#L521-1 assume !(0 == ~T2_E~0); 26946#L526-1 assume !(0 == ~T3_E~0); 27151#L531-1 assume !(0 == ~T4_E~0); 27152#L536-1 assume !(0 == ~E_M~0); 27036#L541-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27037#L546-1 assume !(0 == ~E_2~0); 27118#L551-1 assume !(0 == ~E_3~0); 26994#L556-1 assume !(0 == ~E_4~0); 26995#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27442#L252 assume !(1 == ~m_pc~0); 27175#L252-2 is_master_triggered_~__retres1~0 := 0; 27176#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27193#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27440#L639 assume !(0 != activate_threads_~tmp~1); 27113#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27114#L271 assume !(1 == ~t1_pc~0); 27439#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 27363#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27364#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 27404#L647 assume !(0 != activate_threads_~tmp___0~0); 27405#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26955#L290 assume !(1 == ~t2_pc~0); 26942#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 26943#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27017#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27000#L655 assume !(0 != activate_threads_~tmp___1~0); 27001#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27111#L309 assume !(1 == ~t3_pc~0); 27024#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 27023#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27020#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 27021#L663 assume !(0 != activate_threads_~tmp___2~0); 27162#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27163#L328 assume !(1 == ~t4_pc~0); 27275#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 27446#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27196#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 27197#L671 assume !(0 != activate_threads_~tmp___3~0); 27333#L671-2 assume !(1 == ~M_E~0); 27034#L574-1 assume !(1 == ~T1_E~0); 27035#L579-1 assume !(1 == ~T2_E~0); 27115#L584-1 assume !(1 == ~T3_E~0); 26990#L589-1 assume !(1 == ~T4_E~0); 26991#L594-1 assume !(1 == ~E_M~0); 26897#L599-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26898#L604-1 assume !(1 == ~E_2~0); 26970#L609-1 assume !(1 == ~E_3~0); 26971#L614-1 assume !(1 == ~E_4~0); 27408#L805-1 [2019-12-07 18:58:04,418 INFO L796 eck$LassoCheckResult]: Loop: 27408#L805-1 assume !false; 29881#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 29878#L491 assume !false; 29877#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29876#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29871#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29870#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 29868#L430 assume !(0 != eval_~tmp~0); 29869#L506 start_simulation_~kernel_st~0 := 2; 30118#L348-1 start_simulation_~kernel_st~0 := 3; 30114#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30109#L516-4 assume !(0 == ~T1_E~0); 30105#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30101#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30097#L531-3 assume !(0 == ~T4_E~0); 30093#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30088#L541-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30085#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30082#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30079#L556-3 assume !(0 == ~E_4~0); 30076#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30074#L252-18 assume !(1 == ~m_pc~0); 30072#L252-20 is_master_triggered_~__retres1~0 := 0; 30069#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30065#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30062#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30057#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30055#L271-18 assume 1 == ~t1_pc~0; 30052#L272-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30048#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30046#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30044#L647-18 assume !(0 != activate_threads_~tmp___0~0); 30042#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30040#L290-18 assume !(1 == ~t2_pc~0); 30038#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 30036#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30034#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30032#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30030#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30028#L309-18 assume !(1 == ~t3_pc~0); 30025#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 30024#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30022#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30020#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30018#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30014#L328-18 assume !(1 == ~t4_pc~0); 30009#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 30005#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29999#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 29994#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29989#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 29984#L574-3 assume !(1 == ~T1_E~0); 29979#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29974#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29969#L589-3 assume !(1 == ~T4_E~0); 29964#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29959#L599-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29954#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29950#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29945#L614-3 assume !(1 == ~E_4~0); 29941#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29935#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29927#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29923#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 29918#L824 assume !(0 == start_simulation_~tmp~3); 29914#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29911#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29904#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29901#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 29898#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29896#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 29891#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 29887#L837 assume !(0 != start_simulation_~tmp___0~1); 27408#L805-1 [2019-12-07 18:58:04,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1909498888, now seen corresponding path program 1 times [2019-12-07 18:58:04,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366968991] [2019-12-07 18:58:04,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,431 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366968991] [2019-12-07 18:58:04,431 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,431 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:04,431 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710508075] [2019-12-07 18:58:04,431 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:04,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,432 INFO L82 PathProgramCache]: Analyzing trace with hash 535479938, now seen corresponding path program 1 times [2019-12-07 18:58:04,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952052549] [2019-12-07 18:58:04,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,473 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952052549] [2019-12-07 18:58:04,473 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,474 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:58:04,474 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583650994] [2019-12-07 18:58:04,474 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:04,474 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:04,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:04,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:04,474 INFO L87 Difference]: Start difference. First operand 4142 states and 5874 transitions. cyclomatic complexity: 1740 Second operand 3 states. [2019-12-07 18:58:04,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:04,502 INFO L93 Difference]: Finished difference Result 2336 states and 3285 transitions. [2019-12-07 18:58:04,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:04,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2336 states and 3285 transitions. [2019-12-07 18:58:04,508 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2336 states to 2336 states and 3285 transitions. [2019-12-07 18:58:04,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2336 [2019-12-07 18:58:04,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2336 [2019-12-07 18:58:04,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2336 states and 3285 transitions. [2019-12-07 18:58:04,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,521 INFO L688 BuchiCegarLoop]: Abstraction has 2336 states and 3285 transitions. [2019-12-07 18:58:04,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2336 states and 3285 transitions. [2019-12-07 18:58:04,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2336 to 2336. [2019-12-07 18:58:04,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2336 states. [2019-12-07 18:58:04,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2336 states to 2336 states and 3285 transitions. [2019-12-07 18:58:04,542 INFO L711 BuchiCegarLoop]: Abstraction has 2336 states and 3285 transitions. [2019-12-07 18:58:04,543 INFO L591 BuchiCegarLoop]: Abstraction has 2336 states and 3285 transitions. [2019-12-07 18:58:04,543 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:58:04,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2336 states and 3285 transitions. [2019-12-07 18:58:04,546 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2252 [2019-12-07 18:58:04,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:04,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:04,547 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,547 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,548 INFO L794 eck$LassoCheckResult]: Stem: 33753#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 33661#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 33662#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33809#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 33621#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33622#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33505#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33506#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33588#L375-1 assume !(0 == ~M_E~0); 33589#L516-1 assume !(0 == ~T1_E~0); 33430#L521-1 assume !(0 == ~T2_E~0); 33431#L526-1 assume !(0 == ~T3_E~0); 33628#L531-1 assume !(0 == ~T4_E~0); 33629#L536-1 assume !(0 == ~E_M~0); 33523#L541-1 assume !(0 == ~E_1~0); 33524#L546-1 assume !(0 == ~E_2~0); 33597#L551-1 assume !(0 == ~E_3~0); 33478#L556-1 assume !(0 == ~E_4~0); 33479#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33659#L252 assume !(1 == ~m_pc~0); 33643#L252-2 is_master_triggered_~__retres1~0 := 0; 33644#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33660#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 33737#L639 assume !(0 != activate_threads_~tmp~1); 33592#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33593#L271 assume !(1 == ~t1_pc~0); 33799#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 33801#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33802#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33826#L647 assume !(0 != activate_threads_~tmp___0~0); 33827#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33440#L290 assume !(1 == ~t2_pc~0); 33428#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 33429#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33441#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33484#L655 assume !(0 != activate_threads_~tmp___1~0); 33472#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33473#L309 assume !(1 == ~t3_pc~0); 33511#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 33510#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33507#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 33508#L663 assume !(0 != activate_threads_~tmp___2~0); 33637#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33638#L328 assume !(1 == ~t4_pc~0); 33733#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 33731#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33663#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33664#L671 assume !(0 != activate_threads_~tmp___3~0); 33772#L671-2 assume !(1 == ~M_E~0); 33521#L574-1 assume !(1 == ~T1_E~0); 33522#L579-1 assume !(1 == ~T2_E~0); 33594#L584-1 assume !(1 == ~T3_E~0); 33474#L589-1 assume !(1 == ~T4_E~0); 33475#L594-1 assume !(1 == ~E_M~0); 33386#L599-1 assume !(1 == ~E_1~0); 33387#L604-1 assume !(1 == ~E_2~0); 33454#L609-1 assume !(1 == ~E_3~0); 33455#L614-1 assume !(1 == ~E_4~0); 33828#L805-1 [2019-12-07 18:58:04,548 INFO L796 eck$LassoCheckResult]: Loop: 33828#L805-1 assume !false; 35077#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34692#L491 assume !false; 35076#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 35075#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 35070#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 35069#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 35067#L430 assume !(0 != eval_~tmp~0); 35068#L506 start_simulation_~kernel_st~0 := 2; 35699#L348-1 start_simulation_~kernel_st~0 := 3; 35698#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35697#L516-4 assume !(0 == ~T1_E~0); 35696#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35695#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35694#L531-3 assume !(0 == ~T4_E~0); 35693#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35691#L541-3 assume !(0 == ~E_1~0); 35689#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35687#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35685#L556-3 assume !(0 == ~E_4~0); 35683#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35681#L252-18 assume !(1 == ~m_pc~0); 35679#L252-20 is_master_triggered_~__retres1~0 := 0; 35677#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35675#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35673#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35671#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35669#L271-18 assume !(1 == ~t1_pc~0); 35666#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 35663#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35661#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35659#L647-18 assume !(0 != activate_threads_~tmp___0~0); 35657#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35655#L290-18 assume !(1 == ~t2_pc~0); 35652#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 35650#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35648#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35646#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35644#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35642#L309-18 assume !(1 == ~t3_pc~0); 35639#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 35638#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35637#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35635#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35633#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35631#L328-18 assume !(1 == ~t4_pc~0); 35629#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 35626#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35624#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35622#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 35620#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 35618#L574-3 assume !(1 == ~T1_E~0); 35616#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35614#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35612#L589-3 assume !(1 == ~T4_E~0); 35610#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35608#L599-3 assume !(1 == ~E_1~0); 35606#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35513#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35512#L614-3 assume !(1 == ~E_4~0); 35511#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33617#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33448#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33825#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 33705#L824 assume !(0 == start_simulation_~tmp~3); 33707#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33619#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33421#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33727#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 33728#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 33829#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 35079#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 35078#L837 assume !(0 != start_simulation_~tmp___0~1); 33828#L805-1 [2019-12-07 18:58:04,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,548 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2019-12-07 18:58:04,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,548 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6775119] [2019-12-07 18:58:04,548 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,565 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:04,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,565 INFO L82 PathProgramCache]: Analyzing trace with hash -1099955483, now seen corresponding path program 1 times [2019-12-07 18:58:04,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,566 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617409816] [2019-12-07 18:58:04,566 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617409816] [2019-12-07 18:58:04,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:58:04,586 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484784974] [2019-12-07 18:58:04,586 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:04,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:04,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:58:04,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:58:04,587 INFO L87 Difference]: Start difference. First operand 2336 states and 3285 transitions. cyclomatic complexity: 957 Second operand 5 states. [2019-12-07 18:58:04,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:04,657 INFO L93 Difference]: Finished difference Result 4128 states and 5737 transitions. [2019-12-07 18:58:04,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:58:04,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4128 states and 5737 transitions. [2019-12-07 18:58:04,669 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4020 [2019-12-07 18:58:04,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4128 states to 4128 states and 5737 transitions. [2019-12-07 18:58:04,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4128 [2019-12-07 18:58:04,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4128 [2019-12-07 18:58:04,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4128 states and 5737 transitions. [2019-12-07 18:58:04,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,696 INFO L688 BuchiCegarLoop]: Abstraction has 4128 states and 5737 transitions. [2019-12-07 18:58:04,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4128 states and 5737 transitions. [2019-12-07 18:58:04,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4128 to 2360. [2019-12-07 18:58:04,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2360 states. [2019-12-07 18:58:04,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2360 states to 2360 states and 3309 transitions. [2019-12-07 18:58:04,728 INFO L711 BuchiCegarLoop]: Abstraction has 2360 states and 3309 transitions. [2019-12-07 18:58:04,728 INFO L591 BuchiCegarLoop]: Abstraction has 2360 states and 3309 transitions. [2019-12-07 18:58:04,728 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:58:04,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2360 states and 3309 transitions. [2019-12-07 18:58:04,732 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2276 [2019-12-07 18:58:04,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:04,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:04,733 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,733 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:04,733 INFO L794 eck$LassoCheckResult]: Stem: 40240#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 40141#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 40142#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40301#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 40098#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40099#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39986#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39987#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40068#L375-1 assume !(0 == ~M_E~0); 40069#L516-1 assume !(0 == ~T1_E~0); 39910#L521-1 assume !(0 == ~T2_E~0); 39911#L526-1 assume !(0 == ~T3_E~0); 40106#L531-1 assume !(0 == ~T4_E~0); 40107#L536-1 assume !(0 == ~E_M~0); 40004#L541-1 assume !(0 == ~E_1~0); 40005#L546-1 assume !(0 == ~E_2~0); 40076#L551-1 assume !(0 == ~E_3~0); 39959#L556-1 assume !(0 == ~E_4~0); 39960#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40139#L252 assume !(1 == ~m_pc~0); 40123#L252-2 is_master_triggered_~__retres1~0 := 0; 40124#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40140#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 40222#L639 assume !(0 != activate_threads_~tmp~1); 40071#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40072#L271 assume !(1 == ~t1_pc~0); 40291#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 40293#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40294#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40326#L647 assume !(0 != activate_threads_~tmp___0~0); 40327#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39920#L290 assume !(1 == ~t2_pc~0); 39908#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 39909#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39921#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 39965#L655 assume !(0 != activate_threads_~tmp___1~0); 39953#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39954#L309 assume !(1 == ~t3_pc~0); 39992#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 39991#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39988#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39989#L663 assume !(0 != activate_threads_~tmp___2~0); 40115#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40116#L328 assume !(1 == ~t4_pc~0); 40218#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 40215#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40143#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40144#L671 assume !(0 != activate_threads_~tmp___3~0); 40262#L671-2 assume !(1 == ~M_E~0); 40002#L574-1 assume !(1 == ~T1_E~0); 40003#L579-1 assume !(1 == ~T2_E~0); 40073#L584-1 assume !(1 == ~T3_E~0); 39955#L589-1 assume !(1 == ~T4_E~0); 39956#L594-1 assume !(1 == ~E_M~0); 39866#L599-1 assume !(1 == ~E_1~0); 39867#L604-1 assume !(1 == ~E_2~0); 39934#L609-1 assume !(1 == ~E_3~0); 39935#L614-1 assume !(1 == ~E_4~0); 40328#L805-1 [2019-12-07 18:58:04,734 INFO L796 eck$LassoCheckResult]: Loop: 40328#L805-1 assume !false; 41949#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 41525#L491 assume !false; 41780#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41777#L388 assume !(0 == ~m_st~0); 41773#L392 assume !(0 == ~t1_st~0); 41774#L396 assume !(0 == ~t2_st~0); 41775#L400 assume !(0 == ~t3_st~0); 41776#L404 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 41771#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41743#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 41744#L430 assume !(0 != eval_~tmp~0); 41762#L506 start_simulation_~kernel_st~0 := 2; 40305#L348-1 start_simulation_~kernel_st~0 := 3; 40180#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 40181#L516-4 assume !(0 == ~T1_E~0); 39922#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39923#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40110#L531-3 assume !(0 == ~T4_E~0); 40111#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40341#L541-3 assume !(0 == ~E_1~0); 41756#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41755#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39943#L556-3 assume !(0 == ~E_4~0); 39944#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40256#L252-18 assume !(1 == ~m_pc~0); 40272#L252-20 is_master_triggered_~__retres1~0 := 0; 40152#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40153#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 40037#L639-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 40038#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40043#L271-18 assume !(1 == ~t1_pc~0); 40338#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 40339#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40335#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40209#L647-18 assume !(0 != activate_threads_~tmp___0~0); 40210#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39862#L290-18 assume !(1 == ~t2_pc~0); 39863#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 42021#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42020#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 42019#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42018#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42017#L309-18 assume 1 == ~t3_pc~0; 42016#L310-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 42014#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42013#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 42012#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42011#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42010#L328-18 assume !(1 == ~t4_pc~0); 42009#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 42008#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42007#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 42006#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 42005#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 42004#L574-3 assume !(1 == ~T1_E~0); 42003#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42002#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42001#L589-3 assume !(1 == ~T4_E~0); 42000#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41999#L599-3 assume !(1 == ~E_1~0); 41998#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41997#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41996#L614-3 assume !(1 == ~E_4~0); 41995#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41993#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41986#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41982#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 41977#L824 assume !(0 == start_simulation_~tmp~3); 41973#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 41972#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 41966#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 41963#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 41961#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41959#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 41957#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 41955#L837 assume !(0 != start_simulation_~tmp___0~1); 40328#L805-1 [2019-12-07 18:58:04,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,734 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2019-12-07 18:58:04,734 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,734 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017159673] [2019-12-07 18:58:04,734 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:04,752 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:04,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:04,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1983116434, now seen corresponding path program 1 times [2019-12-07 18:58:04,753 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:04,753 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714049776] [2019-12-07 18:58:04,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:04,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:04,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:04,795 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714049776] [2019-12-07 18:58:04,795 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:04,795 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:58:04,795 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790450295] [2019-12-07 18:58:04,796 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:04,796 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:04,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:58:04,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:58:04,796 INFO L87 Difference]: Start difference. First operand 2360 states and 3309 transitions. cyclomatic complexity: 957 Second operand 5 states. [2019-12-07 18:58:04,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:04,952 INFO L93 Difference]: Finished difference Result 4636 states and 6454 transitions. [2019-12-07 18:58:04,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:58:04,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4636 states and 6454 transitions. [2019-12-07 18:58:04,969 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4536 [2019-12-07 18:58:04,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4636 states to 4636 states and 6454 transitions. [2019-12-07 18:58:04,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4636 [2019-12-07 18:58:04,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4636 [2019-12-07 18:58:04,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4636 states and 6454 transitions. [2019-12-07 18:58:04,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:04,997 INFO L688 BuchiCegarLoop]: Abstraction has 4636 states and 6454 transitions. [2019-12-07 18:58:05,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4636 states and 6454 transitions. [2019-12-07 18:58:05,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4636 to 2432. [2019-12-07 18:58:05,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2432 states. [2019-12-07 18:58:05,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2432 states to 2432 states and 3360 transitions. [2019-12-07 18:58:05,039 INFO L711 BuchiCegarLoop]: Abstraction has 2432 states and 3360 transitions. [2019-12-07 18:58:05,039 INFO L591 BuchiCegarLoop]: Abstraction has 2432 states and 3360 transitions. [2019-12-07 18:58:05,039 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:58:05,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2432 states and 3360 transitions. [2019-12-07 18:58:05,043 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2348 [2019-12-07 18:58:05,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:05,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:05,044 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,044 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,044 INFO L794 eck$LassoCheckResult]: Stem: 47247#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 47154#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 47155#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 47316#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 47110#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47111#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46999#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47000#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47080#L375-1 assume !(0 == ~M_E~0); 47081#L516-1 assume !(0 == ~T1_E~0); 46920#L521-1 assume !(0 == ~T2_E~0); 46921#L526-1 assume !(0 == ~T3_E~0); 47118#L531-1 assume !(0 == ~T4_E~0); 47119#L536-1 assume !(0 == ~E_M~0); 47017#L541-1 assume !(0 == ~E_1~0); 47018#L546-1 assume !(0 == ~E_2~0); 47088#L551-1 assume !(0 == ~E_3~0); 46969#L556-1 assume !(0 == ~E_4~0); 46970#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47152#L252 assume !(1 == ~m_pc~0); 47136#L252-2 is_master_triggered_~__retres1~0 := 0; 47137#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47153#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 47228#L639 assume !(0 != activate_threads_~tmp~1); 47083#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47084#L271 assume !(1 == ~t1_pc~0); 47306#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 47308#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47309#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 47335#L647 assume !(0 != activate_threads_~tmp___0~0); 47336#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46930#L290 assume !(1 == ~t2_pc~0); 46918#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 46919#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46931#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 46975#L655 assume !(0 != activate_threads_~tmp___1~0); 46963#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46964#L309 assume !(1 == ~t3_pc~0); 47005#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 47004#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47001#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 47002#L663 assume !(0 != activate_threads_~tmp___2~0); 47127#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 47128#L328 assume !(1 == ~t4_pc~0); 47226#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 47224#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47156#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 47157#L671 assume !(0 != activate_threads_~tmp___3~0); 47276#L671-2 assume !(1 == ~M_E~0); 47015#L574-1 assume !(1 == ~T1_E~0); 47016#L579-1 assume !(1 == ~T2_E~0); 47085#L584-1 assume !(1 == ~T3_E~0); 46965#L589-1 assume !(1 == ~T4_E~0); 46966#L594-1 assume !(1 == ~E_M~0); 46875#L599-1 assume !(1 == ~E_1~0); 46876#L604-1 assume !(1 == ~E_2~0); 46944#L609-1 assume !(1 == ~E_3~0); 46945#L614-1 assume !(1 == ~E_4~0); 47337#L805-1 [2019-12-07 18:58:05,044 INFO L796 eck$LassoCheckResult]: Loop: 47337#L805-1 assume !false; 48095#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 48092#L491 assume !false; 48091#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 48090#L388 assume !(0 == ~m_st~0); 48085#L392 assume !(0 == ~t1_st~0); 48086#L396 assume !(0 == ~t2_st~0); 48089#L400 assume !(0 == ~t3_st~0); 48087#L404 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 48088#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48077#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 48078#L430 assume !(0 != eval_~tmp~0); 48248#L506 start_simulation_~kernel_st~0 := 2; 48247#L348-1 start_simulation_~kernel_st~0 := 3; 48246#L516-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48245#L516-4 assume !(0 == ~T1_E~0); 48244#L521-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48243#L526-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48242#L531-3 assume !(0 == ~T4_E~0); 48241#L536-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48240#L541-3 assume !(0 == ~E_1~0); 48239#L546-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48238#L551-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48237#L556-3 assume !(0 == ~E_4~0); 48236#L561-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48235#L252-18 assume !(1 == ~m_pc~0); 48234#L252-20 is_master_triggered_~__retres1~0 := 0; 48233#L263-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48232#L264-6 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 48231#L639-18 assume !(0 != activate_threads_~tmp~1); 48230#L639-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48228#L271-18 assume !(1 == ~t1_pc~0); 48225#L271-20 is_transmit1_triggered_~__retres1~1 := 0; 48223#L282-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48221#L283-6 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 48219#L647-18 assume !(0 != activate_threads_~tmp___0~0); 48217#L647-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48214#L290-18 assume !(1 == ~t2_pc~0); 48212#L290-20 is_transmit2_triggered_~__retres1~2 := 0; 48210#L301-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48208#L302-6 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48206#L655-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 48204#L655-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48202#L309-18 assume !(1 == ~t3_pc~0); 48199#L309-20 is_transmit3_triggered_~__retres1~3 := 0; 48197#L320-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48195#L321-6 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48193#L663-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48190#L663-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48187#L328-18 assume !(1 == ~t4_pc~0); 48183#L328-20 is_transmit4_triggered_~__retres1~4 := 0; 48180#L339-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48176#L340-6 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 48173#L671-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 48170#L671-20 assume 1 == ~M_E~0;~M_E~0 := 2; 48167#L574-3 assume !(1 == ~T1_E~0); 48164#L579-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48161#L584-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48158#L589-3 assume !(1 == ~T4_E~0); 48155#L594-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48152#L599-3 assume !(1 == ~E_1~0); 48149#L604-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48146#L609-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48143#L614-3 assume !(1 == ~E_4~0); 48140#L619-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 48135#L388-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 48129#L415-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48126#L416-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 48122#L824 assume !(0 == start_simulation_~tmp~3); 48119#L824-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 48117#L388-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 48111#L415-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48109#L416-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 48107#L779 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 48105#L786 stop_simulation_#res := stop_simulation_~__retres2~0; 48102#L787 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 48100#L837 assume !(0 != start_simulation_~tmp___0~1); 47337#L805-1 [2019-12-07 18:58:05,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,044 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2019-12-07 18:58:05,045 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,045 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444648625] [2019-12-07 18:58:05,045 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,057 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,057 INFO L82 PathProgramCache]: Analyzing trace with hash -2001339089, now seen corresponding path program 1 times [2019-12-07 18:58:05,057 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,057 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328555057] [2019-12-07 18:58:05,057 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:05,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:05,074 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328555057] [2019-12-07 18:58:05,074 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:05,075 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:05,075 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180719985] [2019-12-07 18:58:05,075 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:58:05,075 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:05,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:05,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:05,075 INFO L87 Difference]: Start difference. First operand 2432 states and 3360 transitions. cyclomatic complexity: 936 Second operand 3 states. [2019-12-07 18:58:05,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:05,112 INFO L93 Difference]: Finished difference Result 4042 states and 5502 transitions. [2019-12-07 18:58:05,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:05,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4042 states and 5502 transitions. [2019-12-07 18:58:05,125 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3940 [2019-12-07 18:58:05,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4042 states to 4042 states and 5502 transitions. [2019-12-07 18:58:05,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4042 [2019-12-07 18:58:05,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4042 [2019-12-07 18:58:05,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4042 states and 5502 transitions. [2019-12-07 18:58:05,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:05,142 INFO L688 BuchiCegarLoop]: Abstraction has 4042 states and 5502 transitions. [2019-12-07 18:58:05,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4042 states and 5502 transitions. [2019-12-07 18:58:05,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4042 to 3930. [2019-12-07 18:58:05,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3930 states. [2019-12-07 18:58:05,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3930 states to 3930 states and 5356 transitions. [2019-12-07 18:58:05,185 INFO L711 BuchiCegarLoop]: Abstraction has 3930 states and 5356 transitions. [2019-12-07 18:58:05,185 INFO L591 BuchiCegarLoop]: Abstraction has 3930 states and 5356 transitions. [2019-12-07 18:58:05,185 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 18:58:05,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3930 states and 5356 transitions. [2019-12-07 18:58:05,194 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3828 [2019-12-07 18:58:05,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:05,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:05,194 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,195 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,195 INFO L794 eck$LassoCheckResult]: Stem: 53731#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 53637#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53638#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53796#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 53593#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53594#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53478#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53479#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53561#L375-1 assume !(0 == ~M_E~0); 53562#L516-1 assume !(0 == ~T1_E~0); 53400#L521-1 assume !(0 == ~T2_E~0); 53401#L526-1 assume !(0 == ~T3_E~0); 53601#L531-1 assume !(0 == ~T4_E~0); 53602#L536-1 assume !(0 == ~E_M~0); 53496#L541-1 assume !(0 == ~E_1~0); 53497#L546-1 assume !(0 == ~E_2~0); 53570#L551-1 assume !(0 == ~E_3~0); 53449#L556-1 assume !(0 == ~E_4~0); 53450#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53635#L252 assume !(1 == ~m_pc~0); 53619#L252-2 is_master_triggered_~__retres1~0 := 0; 53620#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53636#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53713#L639 assume !(0 != activate_threads_~tmp~1); 53565#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53566#L271 assume !(1 == ~t1_pc~0); 53783#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 53785#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53786#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53818#L647 assume !(0 != activate_threads_~tmp___0~0); 53819#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53410#L290 assume !(1 == ~t2_pc~0); 53398#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 53399#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53411#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53455#L655 assume !(0 != activate_threads_~tmp___1~0); 53443#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53444#L309 assume !(1 == ~t3_pc~0); 53484#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 53483#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53480#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53481#L663 assume !(0 != activate_threads_~tmp___2~0); 53610#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53611#L328 assume !(1 == ~t4_pc~0); 53709#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 53707#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53639#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53640#L671 assume !(0 != activate_threads_~tmp___3~0); 53756#L671-2 assume !(1 == ~M_E~0); 53494#L574-1 assume !(1 == ~T1_E~0); 53495#L579-1 assume !(1 == ~T2_E~0); 53567#L584-1 assume !(1 == ~T3_E~0); 53445#L589-1 assume !(1 == ~T4_E~0); 53446#L594-1 assume !(1 == ~E_M~0); 53356#L599-1 assume !(1 == ~E_1~0); 53357#L604-1 assume !(1 == ~E_2~0); 53424#L609-1 assume !(1 == ~E_3~0); 53425#L614-1 assume !(1 == ~E_4~0); 53820#L805-1 assume !false; 56043#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 55980#L491 [2019-12-07 18:58:05,195 INFO L796 eck$LassoCheckResult]: Loop: 55980#L491 assume !false; 56040#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 56038#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 56036#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 56034#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 56032#L430 assume 0 != eval_~tmp~0; 56030#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 56027#L438 assume !(0 != eval_~tmp_ndt_1~0); 56024#L435 assume !(0 == ~t1_st~0); 56021#L449 assume !(0 == ~t2_st~0); 55988#L463 assume !(0 == ~t3_st~0); 55984#L477 assume !(0 == ~t4_st~0); 55980#L491 [2019-12-07 18:58:05,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2019-12-07 18:58:05,195 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,195 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551808537] [2019-12-07 18:58:05,196 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,212 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,212 INFO L82 PathProgramCache]: Analyzing trace with hash 1357783123, now seen corresponding path program 1 times [2019-12-07 18:58:05,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880536220] [2019-12-07 18:58:05,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,228 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1573772616, now seen corresponding path program 1 times [2019-12-07 18:58:05,229 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,229 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930853530] [2019-12-07 18:58:05,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:05,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:05,246 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930853530] [2019-12-07 18:58:05,246 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:05,246 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:05,246 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303424230] [2019-12-07 18:58:05,294 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:05,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:05,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:05,294 INFO L87 Difference]: Start difference. First operand 3930 states and 5356 transitions. cyclomatic complexity: 1438 Second operand 3 states. [2019-12-07 18:58:05,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:05,329 INFO L93 Difference]: Finished difference Result 7227 states and 9770 transitions. [2019-12-07 18:58:05,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:05,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7227 states and 9770 transitions. [2019-12-07 18:58:05,350 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7028 [2019-12-07 18:58:05,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7227 states to 7227 states and 9770 transitions. [2019-12-07 18:58:05,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7227 [2019-12-07 18:58:05,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7227 [2019-12-07 18:58:05,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7227 states and 9770 transitions. [2019-12-07 18:58:05,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:05,375 INFO L688 BuchiCegarLoop]: Abstraction has 7227 states and 9770 transitions. [2019-12-07 18:58:05,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7227 states and 9770 transitions. [2019-12-07 18:58:05,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7227 to 6859. [2019-12-07 18:58:05,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6859 states. [2019-12-07 18:58:05,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6859 states to 6859 states and 9298 transitions. [2019-12-07 18:58:05,432 INFO L711 BuchiCegarLoop]: Abstraction has 6859 states and 9298 transitions. [2019-12-07 18:58:05,432 INFO L591 BuchiCegarLoop]: Abstraction has 6859 states and 9298 transitions. [2019-12-07 18:58:05,432 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 18:58:05,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6859 states and 9298 transitions. [2019-12-07 18:58:05,445 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6660 [2019-12-07 18:58:05,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:05,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:05,446 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,446 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,446 INFO L794 eck$LassoCheckResult]: Stem: 64932#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64820#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64821#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65007#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 64771#L355-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 64772#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64651#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64652#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64735#L375-1 assume !(0 == ~M_E~0); 64736#L516-1 assume !(0 == ~T1_E~0); 64561#L521-1 assume !(0 == ~T2_E~0); 64562#L526-1 assume !(0 == ~T3_E~0); 64780#L531-1 assume !(0 == ~T4_E~0); 64781#L536-1 assume !(0 == ~E_M~0); 64669#L541-1 assume !(0 == ~E_1~0); 64670#L546-1 assume !(0 == ~E_2~0); 64749#L551-1 assume !(0 == ~E_3~0); 64750#L556-1 assume !(0 == ~E_4~0); 64963#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64964#L252 assume !(1 == ~m_pc~0); 64800#L252-2 is_master_triggered_~__retres1~0 := 0; 64801#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64929#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 64930#L639 assume !(0 != activate_threads_~tmp~1); 64743#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64744#L271 assume !(1 == ~t1_pc~0); 65014#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 65015#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65061#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 65062#L647 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 65049#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64571#L290 assume !(1 == ~t2_pc~0); 64572#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 64573#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64574#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64617#L655 assume !(0 != activate_threads_~tmp___1~0); 64618#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64740#L309 assume !(1 == ~t3_pc~0); 64741#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 64738#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64739#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 64789#L663 assume !(0 != activate_threads_~tmp___2~0); 64790#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64903#L328 assume !(1 == ~t4_pc~0); 64904#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 64899#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64900#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 64971#L671 assume !(0 != activate_threads_~tmp___3~0); 64972#L671-2 assume !(1 == ~M_E~0); 64667#L574-1 assume !(1 == ~T1_E~0); 64668#L579-1 assume !(1 == ~T2_E~0); 64745#L584-1 assume !(1 == ~T3_E~0); 64746#L589-1 assume !(1 == ~T4_E~0); 64961#L594-1 assume !(1 == ~E_M~0); 64962#L599-1 assume !(1 == ~E_1~0); 64869#L604-1 assume !(1 == ~E_2~0); 64870#L609-1 assume !(1 == ~E_3~0); 65052#L614-1 assume !(1 == ~E_4~0); 65053#L805-1 assume !false; 65279#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 65935#L491 [2019-12-07 18:58:05,446 INFO L796 eck$LassoCheckResult]: Loop: 65935#L491 assume !false; 65934#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 65933#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 65932#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65931#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 65930#L430 assume 0 != eval_~tmp~0; 65929#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 65927#L438 assume !(0 != eval_~tmp_ndt_1~0); 65928#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 65956#L452 assume !(0 != eval_~tmp_ndt_2~0); 65954#L449 assume !(0 == ~t2_st~0); 65939#L463 assume !(0 == ~t3_st~0); 65938#L477 assume !(0 == ~t4_st~0); 65935#L491 [2019-12-07 18:58:05,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,446 INFO L82 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2019-12-07 18:58:05,446 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,446 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64200] [2019-12-07 18:58:05,446 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:05,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:05,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64200] [2019-12-07 18:58:05,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:05,455 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:05,455 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240838795] [2019-12-07 18:58:05,456 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:58:05,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,456 INFO L82 PathProgramCache]: Analyzing trace with hash -1003661710, now seen corresponding path program 1 times [2019-12-07 18:58:05,456 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,456 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1035537428] [2019-12-07 18:58:05,456 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,460 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:05,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:05,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:05,523 INFO L87 Difference]: Start difference. First operand 6859 states and 9298 transitions. cyclomatic complexity: 2451 Second operand 3 states. [2019-12-07 18:58:05,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:05,536 INFO L93 Difference]: Finished difference Result 6802 states and 9221 transitions. [2019-12-07 18:58:05,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:05,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6802 states and 9221 transitions. [2019-12-07 18:58:05,553 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6660 [2019-12-07 18:58:05,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6802 states to 6802 states and 9221 transitions. [2019-12-07 18:58:05,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6802 [2019-12-07 18:58:05,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6802 [2019-12-07 18:58:05,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6802 states and 9221 transitions. [2019-12-07 18:58:05,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:05,573 INFO L688 BuchiCegarLoop]: Abstraction has 6802 states and 9221 transitions. [2019-12-07 18:58:05,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6802 states and 9221 transitions. [2019-12-07 18:58:05,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6802 to 6802. [2019-12-07 18:58:05,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6802 states. [2019-12-07 18:58:05,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6802 states to 6802 states and 9221 transitions. [2019-12-07 18:58:05,619 INFO L711 BuchiCegarLoop]: Abstraction has 6802 states and 9221 transitions. [2019-12-07 18:58:05,619 INFO L591 BuchiCegarLoop]: Abstraction has 6802 states and 9221 transitions. [2019-12-07 18:58:05,620 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 18:58:05,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6802 states and 9221 transitions. [2019-12-07 18:58:05,631 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6660 [2019-12-07 18:58:05,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:05,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:05,632 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,632 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,632 INFO L794 eck$LassoCheckResult]: Stem: 78564#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 78468#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 78469#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78629#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 78423#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78424#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78309#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78310#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78393#L375-1 assume !(0 == ~M_E~0); 78394#L516-1 assume !(0 == ~T1_E~0); 78229#L521-1 assume !(0 == ~T2_E~0); 78230#L526-1 assume !(0 == ~T3_E~0); 78432#L531-1 assume !(0 == ~T4_E~0); 78433#L536-1 assume !(0 == ~E_M~0); 78327#L541-1 assume !(0 == ~E_1~0); 78328#L546-1 assume !(0 == ~E_2~0); 78401#L551-1 assume !(0 == ~E_3~0); 78276#L556-1 assume !(0 == ~E_4~0); 78277#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78466#L252 assume !(1 == ~m_pc~0); 78450#L252-2 is_master_triggered_~__retres1~0 := 0; 78451#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78467#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78543#L639 assume !(0 != activate_threads_~tmp~1); 78396#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78397#L271 assume !(1 == ~t1_pc~0); 78617#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 78619#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78620#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78655#L647 assume !(0 != activate_threads_~tmp___0~0); 78656#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78239#L290 assume !(1 == ~t2_pc~0); 78227#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 78228#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78240#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78282#L655 assume !(0 != activate_threads_~tmp___1~0); 78270#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78271#L309 assume !(1 == ~t3_pc~0); 78315#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 78314#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78311#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78312#L663 assume !(0 != activate_threads_~tmp___2~0); 78441#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78442#L328 assume !(1 == ~t4_pc~0); 78539#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 78537#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78470#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78471#L671 assume !(0 != activate_threads_~tmp___3~0); 78589#L671-2 assume !(1 == ~M_E~0); 78325#L574-1 assume !(1 == ~T1_E~0); 78326#L579-1 assume !(1 == ~T2_E~0); 78398#L584-1 assume !(1 == ~T3_E~0); 78272#L589-1 assume !(1 == ~T4_E~0); 78273#L594-1 assume !(1 == ~E_M~0); 78187#L599-1 assume !(1 == ~E_1~0); 78188#L604-1 assume !(1 == ~E_2~0); 78253#L609-1 assume !(1 == ~E_3~0); 78254#L614-1 assume !(1 == ~E_4~0); 78657#L805-1 assume !false; 78996#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 78992#L491 [2019-12-07 18:58:05,632 INFO L796 eck$LassoCheckResult]: Loop: 78992#L491 assume !false; 78990#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 78988#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 78985#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 78983#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 78981#L430 assume 0 != eval_~tmp~0; 78979#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 78976#L438 assume !(0 != eval_~tmp_ndt_1~0); 78974#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 78944#L452 assume !(0 != eval_~tmp_ndt_2~0); 78972#L449 assume !(0 == ~t2_st~0); 79000#L463 assume !(0 == ~t3_st~0); 78997#L477 assume !(0 == ~t4_st~0); 78992#L491 [2019-12-07 18:58:05,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,632 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2019-12-07 18:58:05,632 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,633 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073350756] [2019-12-07 18:58:05,633 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,644 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1003661710, now seen corresponding path program 2 times [2019-12-07 18:58:05,645 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,645 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553926478] [2019-12-07 18:58:05,645 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,648 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1687576403, now seen corresponding path program 1 times [2019-12-07 18:58:05,649 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,649 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748207384] [2019-12-07 18:58:05,649 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:05,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:05,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748207384] [2019-12-07 18:58:05,665 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:05,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:05,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192327082] [2019-12-07 18:58:05,717 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:05,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:05,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:05,717 INFO L87 Difference]: Start difference. First operand 6802 states and 9221 transitions. cyclomatic complexity: 2431 Second operand 3 states. [2019-12-07 18:58:05,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:05,756 INFO L93 Difference]: Finished difference Result 8610 states and 11637 transitions. [2019-12-07 18:58:05,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:05,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8610 states and 11637 transitions. [2019-12-07 18:58:05,785 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8444 [2019-12-07 18:58:05,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8610 states to 8610 states and 11637 transitions. [2019-12-07 18:58:05,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8610 [2019-12-07 18:58:05,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8610 [2019-12-07 18:58:05,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8610 states and 11637 transitions. [2019-12-07 18:58:05,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:05,818 INFO L688 BuchiCegarLoop]: Abstraction has 8610 states and 11637 transitions. [2019-12-07 18:58:05,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8610 states and 11637 transitions. [2019-12-07 18:58:05,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8610 to 8346. [2019-12-07 18:58:05,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8346 states. [2019-12-07 18:58:05,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8346 states to 8346 states and 11301 transitions. [2019-12-07 18:58:05,875 INFO L711 BuchiCegarLoop]: Abstraction has 8346 states and 11301 transitions. [2019-12-07 18:58:05,875 INFO L591 BuchiCegarLoop]: Abstraction has 8346 states and 11301 transitions. [2019-12-07 18:58:05,875 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 18:58:05,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8346 states and 11301 transitions. [2019-12-07 18:58:05,890 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8180 [2019-12-07 18:58:05,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:05,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:05,890 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,890 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:05,891 INFO L794 eck$LassoCheckResult]: Stem: 93990#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93890#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93891#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 94069#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 93846#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93847#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93728#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93729#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93815#L375-1 assume !(0 == ~M_E~0); 93816#L516-1 assume !(0 == ~T1_E~0); 93652#L521-1 assume !(0 == ~T2_E~0); 93653#L526-1 assume !(0 == ~T3_E~0); 93854#L531-1 assume !(0 == ~T4_E~0); 93855#L536-1 assume !(0 == ~E_M~0); 93746#L541-1 assume !(0 == ~E_1~0); 93747#L546-1 assume !(0 == ~E_2~0); 93823#L551-1 assume !(0 == ~E_3~0); 93700#L556-1 assume !(0 == ~E_4~0); 93701#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93888#L252 assume !(1 == ~m_pc~0); 93872#L252-2 is_master_triggered_~__retres1~0 := 0; 93873#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93889#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 93973#L639 assume !(0 != activate_threads_~tmp~1); 93818#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93819#L271 assume !(1 == ~t1_pc~0); 94055#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 94057#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94058#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 94098#L647 assume !(0 != activate_threads_~tmp___0~0); 94099#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93662#L290 assume !(1 == ~t2_pc~0); 93650#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 93651#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93663#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 93706#L655 assume !(0 != activate_threads_~tmp___1~0); 93694#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93695#L309 assume !(1 == ~t3_pc~0); 93734#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 93733#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93730#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 93731#L663 assume !(0 != activate_threads_~tmp___2~0); 93863#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93864#L328 assume !(1 == ~t4_pc~0); 93970#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 93968#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93892#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 93893#L671 assume !(0 != activate_threads_~tmp___3~0); 94022#L671-2 assume !(1 == ~M_E~0); 93744#L574-1 assume !(1 == ~T1_E~0); 93745#L579-1 assume !(1 == ~T2_E~0); 93820#L584-1 assume !(1 == ~T3_E~0); 93696#L589-1 assume !(1 == ~T4_E~0); 93697#L594-1 assume !(1 == ~E_M~0); 93608#L599-1 assume !(1 == ~E_1~0); 93609#L604-1 assume !(1 == ~E_2~0); 93676#L609-1 assume !(1 == ~E_3~0); 93677#L614-1 assume !(1 == ~E_4~0); 94100#L805-1 assume !false; 97883#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 97879#L491 [2019-12-07 18:58:05,891 INFO L796 eck$LassoCheckResult]: Loop: 97879#L491 assume !false; 97877#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 97875#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 97871#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 97869#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 97868#L430 assume 0 != eval_~tmp~0; 97864#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 97859#L438 assume !(0 != eval_~tmp_ndt_1~0); 97857#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 97839#L452 assume !(0 != eval_~tmp_ndt_2~0); 94088#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 93658#L466 assume !(0 != eval_~tmp_ndt_3~0); 93660#L463 assume !(0 == ~t3_st~0); 97884#L477 assume !(0 == ~t4_st~0); 97879#L491 [2019-12-07 18:58:05,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,891 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2019-12-07 18:58:05,891 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,891 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573476518] [2019-12-07 18:58:05,891 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,904 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,904 INFO L82 PathProgramCache]: Analyzing trace with hash -1053426655, now seen corresponding path program 1 times [2019-12-07 18:58:05,904 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008040371] [2019-12-07 18:58:05,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:05,909 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:05,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:05,909 INFO L82 PathProgramCache]: Analyzing trace with hash -779945658, now seen corresponding path program 1 times [2019-12-07 18:58:05,909 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:05,909 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660962760] [2019-12-07 18:58:05,909 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:05,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:05,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:05,947 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660962760] [2019-12-07 18:58:05,947 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:05,947 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:58:05,948 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902483217] [2019-12-07 18:58:06,009 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:06,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:06,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:06,010 INFO L87 Difference]: Start difference. First operand 8346 states and 11301 transitions. cyclomatic complexity: 2967 Second operand 3 states. [2019-12-07 18:58:06,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:06,064 INFO L93 Difference]: Finished difference Result 14712 states and 19809 transitions. [2019-12-07 18:58:06,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:06,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14712 states and 19809 transitions. [2019-12-07 18:58:06,114 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14442 [2019-12-07 18:58:06,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14712 states to 14712 states and 19809 transitions. [2019-12-07 18:58:06,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14712 [2019-12-07 18:58:06,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14712 [2019-12-07 18:58:06,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14712 states and 19809 transitions. [2019-12-07 18:58:06,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:06,154 INFO L688 BuchiCegarLoop]: Abstraction has 14712 states and 19809 transitions. [2019-12-07 18:58:06,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14712 states and 19809 transitions. [2019-12-07 18:58:06,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14712 to 14256. [2019-12-07 18:58:06,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14256 states. [2019-12-07 18:58:06,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14256 states to 14256 states and 19257 transitions. [2019-12-07 18:58:06,252 INFO L711 BuchiCegarLoop]: Abstraction has 14256 states and 19257 transitions. [2019-12-07 18:58:06,252 INFO L591 BuchiCegarLoop]: Abstraction has 14256 states and 19257 transitions. [2019-12-07 18:58:06,252 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 18:58:06,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14256 states and 19257 transitions. [2019-12-07 18:58:06,277 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13986 [2019-12-07 18:58:06,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:06,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:06,278 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:06,278 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:06,278 INFO L794 eck$LassoCheckResult]: Stem: 117056#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 116961#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 116962#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 117127#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 116914#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116915#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116793#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116794#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116881#L375-1 assume !(0 == ~M_E~0); 116882#L516-1 assume !(0 == ~T1_E~0); 116717#L521-1 assume !(0 == ~T2_E~0); 116718#L526-1 assume !(0 == ~T3_E~0); 116923#L531-1 assume !(0 == ~T4_E~0); 116924#L536-1 assume !(0 == ~E_M~0); 116811#L541-1 assume !(0 == ~E_1~0); 116812#L546-1 assume !(0 == ~E_2~0); 116890#L551-1 assume !(0 == ~E_3~0); 116764#L556-1 assume !(0 == ~E_4~0); 116765#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 116959#L252 assume !(1 == ~m_pc~0); 116943#L252-2 is_master_triggered_~__retres1~0 := 0; 116944#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 116960#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 117038#L639 assume !(0 != activate_threads_~tmp~1); 116885#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 116886#L271 assume !(1 == ~t1_pc~0); 117115#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 117117#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117118#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 117164#L647 assume !(0 != activate_threads_~tmp___0~0); 117165#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 116728#L290 assume !(1 == ~t2_pc~0); 116715#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 116716#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 116729#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 116771#L655 assume !(0 != activate_threads_~tmp___1~0); 116758#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116759#L309 assume !(1 == ~t3_pc~0); 116799#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 116798#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 116795#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116796#L663 assume !(0 != activate_threads_~tmp___2~0); 116933#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 116934#L328 assume !(1 == ~t4_pc~0); 117031#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 117029#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116963#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 116964#L671 assume !(0 != activate_threads_~tmp___3~0); 117084#L671-2 assume !(1 == ~M_E~0); 116809#L574-1 assume !(1 == ~T1_E~0); 116810#L579-1 assume !(1 == ~T2_E~0); 116887#L584-1 assume !(1 == ~T3_E~0); 116760#L589-1 assume !(1 == ~T4_E~0); 116761#L594-1 assume !(1 == ~E_M~0); 116674#L599-1 assume !(1 == ~E_1~0); 116675#L604-1 assume !(1 == ~E_2~0); 116740#L609-1 assume !(1 == ~E_3~0); 116741#L614-1 assume !(1 == ~E_4~0); 117166#L805-1 assume !false; 120034#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 120029#L491 [2019-12-07 18:58:06,278 INFO L796 eck$LassoCheckResult]: Loop: 120029#L491 assume !false; 120027#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 120024#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 120022#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 120021#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 120019#L430 assume 0 != eval_~tmp~0; 120016#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 120013#L438 assume !(0 != eval_~tmp_ndt_1~0); 120011#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 119991#L452 assume !(0 != eval_~tmp_ndt_2~0); 120009#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 120041#L466 assume !(0 != eval_~tmp_ndt_3~0); 120039#L463 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 118616#L480 assume !(0 != eval_~tmp_ndt_4~0); 120035#L477 assume !(0 == ~t4_st~0); 120029#L491 [2019-12-07 18:58:06,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,279 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2019-12-07 18:58:06,279 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,279 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547468715] [2019-12-07 18:58:06,279 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,291 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:06,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1703362212, now seen corresponding path program 1 times [2019-12-07 18:58:06,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,291 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738471377] [2019-12-07 18:58:06,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,295 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:06,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,296 INFO L82 PathProgramCache]: Analyzing trace with hash 1591338527, now seen corresponding path program 1 times [2019-12-07 18:58:06,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,296 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685261311] [2019-12-07 18:58:06,296 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:58:06,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:58:06,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685261311] [2019-12-07 18:58:06,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:58:06,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:58:06,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308805441] [2019-12-07 18:58:06,391 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:58:06,391 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:58:06,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:58:06,391 INFO L87 Difference]: Start difference. First operand 14256 states and 19257 transitions. cyclomatic complexity: 5013 Second operand 3 states. [2019-12-07 18:58:06,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:58:06,452 INFO L93 Difference]: Finished difference Result 18027 states and 24235 transitions. [2019-12-07 18:58:06,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:58:06,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18027 states and 24235 transitions. [2019-12-07 18:58:06,504 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17701 [2019-12-07 18:58:06,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18027 states to 18027 states and 24235 transitions. [2019-12-07 18:58:06,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18027 [2019-12-07 18:58:06,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18027 [2019-12-07 18:58:06,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18027 states and 24235 transitions. [2019-12-07 18:58:06,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:58:06,549 INFO L688 BuchiCegarLoop]: Abstraction has 18027 states and 24235 transitions. [2019-12-07 18:58:06,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18027 states and 24235 transitions. [2019-12-07 18:58:06,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18027 to 17883. [2019-12-07 18:58:06,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17883 states. [2019-12-07 18:58:06,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17883 states to 17883 states and 24091 transitions. [2019-12-07 18:58:06,663 INFO L711 BuchiCegarLoop]: Abstraction has 17883 states and 24091 transitions. [2019-12-07 18:58:06,663 INFO L591 BuchiCegarLoop]: Abstraction has 17883 states and 24091 transitions. [2019-12-07 18:58:06,663 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 18:58:06,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17883 states and 24091 transitions. [2019-12-07 18:58:06,700 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17557 [2019-12-07 18:58:06,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:58:06,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:58:06,701 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:06,701 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:58:06,701 INFO L794 eck$LassoCheckResult]: Stem: 149356#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 149251#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 149252#L768 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 149433#L348 assume 1 == ~m_i~0;~m_st~0 := 0; 149203#L355-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 149204#L360-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 149079#L365-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 149080#L370-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 149167#L375-1 assume !(0 == ~M_E~0); 149168#L516-1 assume !(0 == ~T1_E~0); 149009#L521-1 assume !(0 == ~T2_E~0); 149010#L526-1 assume !(0 == ~T3_E~0); 149213#L531-1 assume !(0 == ~T4_E~0); 149214#L536-1 assume !(0 == ~E_M~0); 149097#L541-1 assume !(0 == ~E_1~0); 149098#L546-1 assume !(0 == ~E_2~0); 149174#L551-1 assume !(0 == ~E_3~0); 149053#L556-1 assume !(0 == ~E_4~0); 149054#L561-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 149249#L252 assume !(1 == ~m_pc~0); 149233#L252-2 is_master_triggered_~__retres1~0 := 0; 149234#L263 is_master_triggered_#res := is_master_triggered_~__retres1~0; 149250#L264 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 149333#L639 assume !(0 != activate_threads_~tmp~1); 149169#L639-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 149170#L271 assume !(1 == ~t1_pc~0); 149419#L271-2 is_transmit1_triggered_~__retres1~1 := 0; 149421#L282 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 149422#L283 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 149462#L647 assume !(0 != activate_threads_~tmp___0~0); 149463#L647-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 149017#L290 assume !(1 == ~t2_pc~0); 149006#L290-2 is_transmit2_triggered_~__retres1~2 := 0; 149007#L301 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 149020#L302 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 149059#L655 assume !(0 != activate_threads_~tmp___1~0); 149047#L655-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 149048#L309 assume !(1 == ~t3_pc~0); 149085#L309-2 is_transmit3_triggered_~__retres1~3 := 0; 149084#L320 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 149081#L321 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 149082#L663 assume !(0 != activate_threads_~tmp___2~0); 149222#L663-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 149223#L328 assume !(1 == ~t4_pc~0); 149327#L328-2 is_transmit4_triggered_~__retres1~4 := 0; 149326#L339 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 149253#L340 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 149254#L671 assume !(0 != activate_threads_~tmp___3~0); 149389#L671-2 assume !(1 == ~M_E~0); 149095#L574-1 assume !(1 == ~T1_E~0); 149096#L579-1 assume !(1 == ~T2_E~0); 149171#L584-1 assume !(1 == ~T3_E~0); 149051#L589-1 assume !(1 == ~T4_E~0); 149052#L594-1 assume !(1 == ~E_M~0); 148965#L599-1 assume !(1 == ~E_1~0); 148966#L604-1 assume !(1 == ~E_2~0); 149029#L609-1 assume !(1 == ~E_3~0); 149030#L614-1 assume !(1 == ~E_4~0); 149464#L805-1 assume !false; 165003#L806 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 165004#L491 [2019-12-07 18:58:06,701 INFO L796 eck$LassoCheckResult]: Loop: 165004#L491 assume !false; 166173#L426 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 166171#L388 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 166169#L415 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 166167#L416 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 161156#L430 assume 0 != eval_~tmp~0; 161154#L430-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 161153#L438 assume !(0 != eval_~tmp_ndt_1~0); 157005#L435 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 157002#L452 assume !(0 != eval_~tmp_ndt_2~0); 156999#L449 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 156996#L466 assume !(0 != eval_~tmp_ndt_3~0); 156994#L463 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 154639#L480 assume !(0 != eval_~tmp_ndt_4~0); 156993#L477 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 165024#L494 assume !(0 != eval_~tmp_ndt_5~0); 165004#L491 [2019-12-07 18:58:06,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,701 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2019-12-07 18:58:06,702 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,702 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346384367] [2019-12-07 18:58:06,702 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,716 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:06,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,716 INFO L82 PathProgramCache]: Analyzing trace with hash 1264617455, now seen corresponding path program 1 times [2019-12-07 18:58:06,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,716 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351449500] [2019-12-07 18:58:06,716 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,721 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:06,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:58:06,721 INFO L82 PathProgramCache]: Analyzing trace with hash 2086850516, now seen corresponding path program 1 times [2019-12-07 18:58:06,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:58:06,721 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763774269] [2019-12-07 18:58:06,721 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:58:06,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:58:06,738 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:58:07,183 WARN L192 SmtUtils]: Spent 344.00 ms on a formula simplification. DAG size of input: 167 DAG size of output: 112 [2019-12-07 18:58:07,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:58:07 BoogieIcfgContainer [2019-12-07 18:58:07,287 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:58:07,288 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:58:07,288 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:58:07,288 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:58:07,288 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:58:02" (3/4) ... [2019-12-07 18:58:07,290 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:58:07,336 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_60d95a51-b0ac-4896-a968-ce9ad1fe0a0e/bin/uautomizer/witness.graphml [2019-12-07 18:58:07,336 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:58:07,337 INFO L168 Benchmark]: Toolchain (without parser) took 5474.75 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 253.2 MB). Free memory was 945.1 MB in the beginning and 1.0 GB in the end (delta: -103.4 MB). Peak memory consumption was 149.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,337 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:58:07,338 INFO L168 Benchmark]: CACSL2BoogieTranslator took 256.46 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 104.9 MB). Free memory was 945.1 MB in the beginning and 1.1 GB in the end (delta: -148.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,338 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,338 INFO L168 Benchmark]: Boogie Preprocessor took 39.16 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:58:07,339 INFO L168 Benchmark]: RCFGBuilder took 599.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 989.0 MB in the end (delta: 99.0 MB). Peak memory consumption was 99.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,339 INFO L168 Benchmark]: BuchiAutomizer took 4487.92 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 148.4 MB). Free memory was 989.0 MB in the beginning and 1.1 GB in the end (delta: -71.0 MB). Peak memory consumption was 355.8 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,339 INFO L168 Benchmark]: Witness Printer took 48.47 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:58:07,341 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 256.46 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 104.9 MB). Free memory was 945.1 MB in the beginning and 1.1 GB in the end (delta: -148.2 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.92 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 39.16 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 599.58 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 989.0 MB in the end (delta: 99.0 MB). Peak memory consumption was 99.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 4487.92 ms. Allocated memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: 148.4 MB). Free memory was 989.0 MB in the beginning and 1.1 GB in the end (delta: -71.0 MB). Peak memory consumption was 355.8 MB. Max. memory is 11.5 GB. * Witness Printer took 48.47 ms. Allocated memory is still 1.3 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 17883 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.4s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 1.8s. Construction of modules took 0.3s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 20 MinimizatonAttempts, 5417 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had 17883 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 12381 SDtfs, 12325 SDslu, 8476 SDs, 0 SdLazy, 366 SolverSat, 216 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 425]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68a1ae63=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3afb13f6=0, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31279fb2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24b11f2b=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1dfa2c6f=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c0cb5b7=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ce29d13=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dbaffa0=0, t1_st=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2791c4fc=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d0c6302=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d218805=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@147d0896=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@fed6090=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 425]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int t4_st ; [L24] int m_i ; [L25] int t1_i ; [L26] int t2_i ; [L27] int t3_i ; [L28] int t4_i ; [L29] int M_E = 2; [L30] int T1_E = 2; [L31] int T2_E = 2; [L32] int T3_E = 2; [L33] int T4_E = 2; [L34] int E_M = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L45] int token ; [L47] int local ; [L850] int __retres1 ; [L762] m_i = 1 [L763] t1_i = 1 [L764] t2_i = 1 [L765] t3_i = 1 [L766] t4_i = 1 [L791] int kernel_st ; [L792] int tmp ; [L793] int tmp___0 ; [L797] kernel_st = 0 [L355] COND TRUE m_i == 1 [L356] m_st = 0 [L360] COND TRUE t1_i == 1 [L361] t1_st = 0 [L365] COND TRUE t2_i == 1 [L366] t2_st = 0 [L370] COND TRUE t3_i == 1 [L371] t3_st = 0 [L375] COND TRUE t4_i == 1 [L376] t4_st = 0 [L516] COND FALSE !(M_E == 0) [L521] COND FALSE !(T1_E == 0) [L526] COND FALSE !(T2_E == 0) [L531] COND FALSE !(T3_E == 0) [L536] COND FALSE !(T4_E == 0) [L541] COND FALSE !(E_M == 0) [L546] COND FALSE !(E_1 == 0) [L551] COND FALSE !(E_2 == 0) [L556] COND FALSE !(E_3 == 0) [L561] COND FALSE !(E_4 == 0) [L629] int tmp ; [L630] int tmp___0 ; [L631] int tmp___1 ; [L632] int tmp___2 ; [L633] int tmp___3 ; [L249] int __retres1 ; [L252] COND FALSE !(m_pc == 1) [L262] __retres1 = 0 [L264] return (__retres1); [L637] tmp = is_master_triggered() [L639] COND FALSE !(\read(tmp)) [L268] int __retres1 ; [L271] COND FALSE !(t1_pc == 1) [L281] __retres1 = 0 [L283] return (__retres1); [L645] tmp___0 = is_transmit1_triggered() [L647] COND FALSE !(\read(tmp___0)) [L287] int __retres1 ; [L290] COND FALSE !(t2_pc == 1) [L300] __retres1 = 0 [L302] return (__retres1); [L653] tmp___1 = is_transmit2_triggered() [L655] COND FALSE !(\read(tmp___1)) [L306] int __retres1 ; [L309] COND FALSE !(t3_pc == 1) [L319] __retres1 = 0 [L321] return (__retres1); [L661] tmp___2 = is_transmit3_triggered() [L663] COND FALSE !(\read(tmp___2)) [L325] int __retres1 ; [L328] COND FALSE !(t4_pc == 1) [L338] __retres1 = 0 [L340] return (__retres1); [L669] tmp___3 = is_transmit4_triggered() [L671] COND FALSE !(\read(tmp___3)) [L574] COND FALSE !(M_E == 1) [L579] COND FALSE !(T1_E == 1) [L584] COND FALSE !(T2_E == 1) [L589] COND FALSE !(T3_E == 1) [L594] COND FALSE !(T4_E == 1) [L599] COND FALSE !(E_M == 1) [L604] COND FALSE !(E_1 == 1) [L609] COND FALSE !(E_2 == 1) [L614] COND FALSE !(E_3 == 1) [L619] COND FALSE !(E_4 == 1) [L805] COND TRUE 1 [L808] kernel_st = 1 [L421] int tmp ; Loop: [L425] COND TRUE 1 [L385] int __retres1 ; [L388] COND TRUE m_st == 0 [L389] __retres1 = 1 [L416] return (__retres1); [L428] tmp = exists_runnable_thread() [L430] COND TRUE \read(tmp) [L435] COND TRUE m_st == 0 [L436] int tmp_ndt_1; [L437] tmp_ndt_1 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_1)) [L449] COND TRUE t1_st == 0 [L450] int tmp_ndt_2; [L451] tmp_ndt_2 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_2)) [L463] COND TRUE t2_st == 0 [L464] int tmp_ndt_3; [L465] tmp_ndt_3 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_3)) [L477] COND TRUE t3_st == 0 [L478] int tmp_ndt_4; [L479] tmp_ndt_4 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_4)) [L491] COND TRUE t4_st == 0 [L492] int tmp_ndt_5; [L493] tmp_ndt_5 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...