./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 75ee388caeaa04bad2057d2e7044ba2f86479f59 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:29:29,803 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:29:29,804 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:29:29,815 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:29:29,815 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:29:29,816 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:29:29,817 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:29:29,819 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:29:29,821 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:29:29,821 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:29:29,822 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:29:29,823 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:29:29,824 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:29:29,825 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:29:29,825 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:29:29,827 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:29:29,827 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:29:29,828 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:29:29,830 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:29:29,832 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:29:29,833 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:29:29,834 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:29:29,835 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:29:29,836 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:29:29,838 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:29:29,838 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:29:29,838 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:29:29,839 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:29:29,839 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:29:29,840 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:29:29,840 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:29:29,841 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:29:29,841 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:29:29,842 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:29:29,843 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:29:29,843 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:29:29,843 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:29:29,843 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:29:29,844 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:29:29,844 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:29:29,845 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:29:29,845 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 17:29:29,859 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:29:29,859 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:29:29,860 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:29:29,860 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:29:29,860 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:29:29,861 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 17:29:29,861 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 17:29:29,861 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 17:29:29,861 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 17:29:29,861 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 17:29:29,861 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 17:29:29,862 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:29:29,862 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:29:29,862 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 17:29:29,862 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:29:29,862 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:29:29,862 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:29:29,863 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 17:29:29,864 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:29:29,864 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 17:29:29,864 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:29:29,864 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:29:29,864 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 17:29:29,865 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:29:29,865 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:29:29,865 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:29:29,865 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 17:29:29,866 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 17:29:29,866 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 75ee388caeaa04bad2057d2e7044ba2f86479f59 [2019-12-07 17:29:29,964 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:29:29,973 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:29:29,976 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:29:29,976 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:29:29,977 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:29:29,977 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2019-12-07 17:29:30,014 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/data/fbb87f837/1c96fd1afce1419787fed1c6cedb6f50/FLAGa8baaac84 [2019-12-07 17:29:30,452 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:29:30,452 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2019-12-07 17:29:30,461 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/data/fbb87f837/1c96fd1afce1419787fed1c6cedb6f50/FLAGa8baaac84 [2019-12-07 17:29:30,470 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/data/fbb87f837/1c96fd1afce1419787fed1c6cedb6f50 [2019-12-07 17:29:30,472 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:29:30,473 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:29:30,474 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:29:30,474 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:29:30,476 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:29:30,477 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,478 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d97e9b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30, skipping insertion in model container [2019-12-07 17:29:30,478 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,483 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:29:30,506 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:29:30,692 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:29:30,696 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:29:30,728 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:29:30,742 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:29:30,743 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30 WrapperNode [2019-12-07 17:29:30,743 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:29:30,743 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:29:30,743 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:29:30,744 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:29:30,749 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,755 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,788 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:29:30,789 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:29:30,789 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:29:30,789 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:29:30,795 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,795 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,798 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,799 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,810 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,823 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,825 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... [2019-12-07 17:29:30,830 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:29:30,831 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:29:30,831 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:29:30,831 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:29:30,831 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 17:29:30,878 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:29:30,878 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:29:31,516 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:29:31,516 INFO L287 CfgBuilder]: Removed 196 assume(true) statements. [2019-12-07 17:29:31,517 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:29:31 BoogieIcfgContainer [2019-12-07 17:29:31,517 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:29:31,517 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 17:29:31,518 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 17:29:31,520 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 17:29:31,520 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 17:29:31,520 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 05:29:30" (1/3) ... [2019-12-07 17:29:31,521 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b534907 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 05:29:31, skipping insertion in model container [2019-12-07 17:29:31,521 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 17:29:31,521 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:29:30" (2/3) ... [2019-12-07 17:29:31,521 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b534907 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 05:29:31, skipping insertion in model container [2019-12-07 17:29:31,522 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 17:29:31,522 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:29:31" (3/3) ... [2019-12-07 17:29:31,523 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2019-12-07 17:29:31,551 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 17:29:31,551 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 17:29:31,551 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 17:29:31,551 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:29:31,551 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:29:31,551 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 17:29:31,551 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:29:31,551 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 17:29:31,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2019-12-07 17:29:31,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2019-12-07 17:29:31,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:31,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:31,611 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,611 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,611 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 17:29:31,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states. [2019-12-07 17:29:31,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2019-12-07 17:29:31,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:31,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:31,622 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,622 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,628 INFO L794 eck$LassoCheckResult]: Stem: 377#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 305#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 376#L881true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 214#L397true assume !(1 == ~m_i~0);~m_st~0 := 2; 511#L404-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 156#L409-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 429#L414-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 215#L419-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 107#L424-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 380#L429-1true assume !(0 == ~M_E~0); 121#L589-1true assume !(0 == ~T1_E~0); 384#L594-1true assume !(0 == ~T2_E~0); 7#L599-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 330#L604-1true assume !(0 == ~T4_E~0); 80#L609-1true assume !(0 == ~T5_E~0); 496#L614-1true assume !(0 == ~E_M~0); 279#L619-1true assume !(0 == ~E_1~0); 534#L624-1true assume !(0 == ~E_2~0); 164#L629-1true assume !(0 == ~E_3~0); 448#L634-1true assume !(0 == ~E_4~0); 223#L639-1true assume 0 == ~E_5~0;~E_5~0 := 1; 116#L644-1true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 407#L282true assume 1 == ~m_pc~0; 507#L283true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 408#L293true is_master_triggered_#res := is_master_triggered_~__retres1~0; 508#L294true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 460#L733true assume !(0 != activate_threads_~tmp~1); 463#L733-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69#L301true assume !(1 == ~t1_pc~0); 65#L301-2true is_transmit1_triggered_~__retres1~1 := 0; 47#L312true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 138#L313true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87#L741true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 74#L741-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 220#L320true assume 1 == ~t2_pc~0; 159#L321true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 219#L331true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 158#L332true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 371#L749true assume !(0 != activate_threads_~tmp___1~0); 372#L749-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 358#L339true assume !(1 == ~t3_pc~0); 362#L339-2true is_transmit3_triggered_~__retres1~3 := 0; 357#L350true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 325#L351true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 501#L757true assume !(0 != activate_threads_~tmp___2~0); 489#L757-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 111#L358true assume 1 == ~t4_pc~0; 434#L359true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 109#L369true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 431#L370true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 126#L765true assume !(0 != activate_threads_~tmp___3~0); 127#L765-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 255#L377true assume !(1 == ~t5_pc~0); 259#L377-2true is_transmit5_triggered_~__retres1~5 := 0; 253#L388true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70#L389true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 281#L773true assume !(0 != activate_threads_~tmp___4~0); 274#L773-2true assume !(1 == ~M_E~0); 531#L657-1true assume !(1 == ~T1_E~0); 178#L662-1true assume !(1 == ~T2_E~0); 464#L667-1true assume !(1 == ~T3_E~0); 374#L672-1true assume !(1 == ~T4_E~0); 115#L677-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 382#L682-1true assume !(1 == ~E_M~0); 3#L687-1true assume !(1 == ~E_1~0); 327#L692-1true assume !(1 == ~E_2~0); 75#L697-1true assume !(1 == ~E_3~0); 490#L702-1true assume !(1 == ~E_4~0); 275#L707-1true assume !(1 == ~E_5~0); 24#L918-1true [2019-12-07 17:29:31,629 INFO L796 eck$LassoCheckResult]: Loop: 24#L918-1true assume !false; 130#L919true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 266#L564true assume !true; 450#L579true start_simulation_~kernel_st~0 := 2; 217#L397-1true start_simulation_~kernel_st~0 := 3; 123#L589-2true assume 0 == ~M_E~0;~M_E~0 := 1; 102#L589-4true assume !(0 == ~T1_E~0); 387#L594-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 144#L599-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 319#L604-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 62#L609-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 485#L614-3true assume 0 == ~E_M~0;~E_M~0 := 1; 268#L619-3true assume 0 == ~E_1~0;~E_1~0 := 1; 525#L624-3true assume 0 == ~E_2~0;~E_2~0 := 1; 168#L629-3true assume !(0 == ~E_3~0); 453#L634-3true assume 0 == ~E_4~0;~E_4~0 := 1; 227#L639-3true assume 0 == ~E_5~0;~E_5~0 := 1; 122#L644-3true havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 521#L282-21true assume !(1 == ~m_pc~0); 532#L282-23true is_master_triggered_~__retres1~0 := 0; 396#L293-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 509#L294-7true activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 401#L733-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 403#L733-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14#L301-21true assume 1 == ~t1_pc~0; 131#L302-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38#L312-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 136#L313-7true activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40#L741-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17#L741-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 177#L320-21true assume !(1 == ~t2_pc~0); 165#L320-23true is_transmit2_triggered_~__retres1~2 := 0; 187#L331-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 296#L332-7true activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 191#L749-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 196#L749-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 326#L339-21true assume !(1 == ~t3_pc~0); 328#L339-23true is_transmit3_triggered_~__retres1~3 := 0; 350#L350-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 301#L351-7true activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 354#L757-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 337#L757-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 462#L358-21true assume !(1 == ~t4_pc~0); 466#L358-23true is_transmit4_triggered_~__retres1~4 := 0; 100#L369-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 418#L370-7true activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 479#L765-21true assume !(0 != activate_threads_~tmp___3~0); 481#L765-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 73#L377-21true assume 1 == ~t5_pc~0; 32#L378-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 247#L388-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29#L389-7true activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 252#L773-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 233#L773-23true assume 1 == ~M_E~0;~M_E~0 := 2; 522#L657-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 166#L662-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 452#L667-3true assume !(1 == ~T3_E~0); 225#L672-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 118#L677-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 383#L682-3true assume 1 == ~E_M~0;~E_M~0 := 2; 6#L687-3true assume 1 == ~E_1~0;~E_1~0 := 2; 329#L692-3true assume 1 == ~E_2~0;~E_2~0 := 2; 79#L697-3true assume 1 == ~E_3~0;~E_3~0 := 2; 493#L702-3true assume 1 == ~E_4~0;~E_4~0 := 2; 278#L707-3true assume !(1 == ~E_5~0); 533#L712-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 154#L442-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 212#L474-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 174#L475-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 180#L937true assume !(0 == start_simulation_~tmp~3); 182#L937-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 157#L442-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 213#L474-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 155#L475-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 375#L892true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 390#L899true stop_simulation_#res := stop_simulation_~__retres2~0; 498#L900true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 238#L950true assume !(0 != start_simulation_~tmp___0~1); 24#L918-1true [2019-12-07 17:29:31,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:31,633 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2019-12-07 17:29:31,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:31,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911601709] [2019-12-07 17:29:31,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:31,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:31,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:31,747 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911601709] [2019-12-07 17:29:31,747 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:31,747 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:31,749 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281977285] [2019-12-07 17:29:31,752 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:31,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:31,752 INFO L82 PathProgramCache]: Analyzing trace with hash 705629471, now seen corresponding path program 1 times [2019-12-07 17:29:31,752 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:31,753 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415675589] [2019-12-07 17:29:31,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:31,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:31,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:31,775 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415675589] [2019-12-07 17:29:31,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:31,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:31,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431434569] [2019-12-07 17:29:31,776 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:31,777 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:31,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:31,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:31,789 INFO L87 Difference]: Start difference. First operand 532 states. Second operand 3 states. [2019-12-07 17:29:31,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:31,824 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2019-12-07 17:29:31,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:31,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2019-12-07 17:29:31,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:31,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2019-12-07 17:29:31,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:31,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:31,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2019-12-07 17:29:31,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:31,847 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2019-12-07 17:29:31,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2019-12-07 17:29:31,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:31,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:31,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2019-12-07 17:29:31,886 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2019-12-07 17:29:31,886 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2019-12-07 17:29:31,886 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 17:29:31,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2019-12-07 17:29:31,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:31,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:31,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:31,894 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,894 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:31,894 INFO L794 eck$LassoCheckResult]: Stem: 1511#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1461#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1462#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1395#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 1396#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316#L409-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1317#L414-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1397#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1267#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1268#L429-1 assume !(0 == ~M_E~0); 1293#L589-1 assume !(0 == ~T1_E~0); 1294#L594-1 assume !(0 == ~T2_E~0); 1082#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1083#L604-1 assume !(0 == ~T4_E~0); 1221#L609-1 assume !(0 == ~T5_E~0); 1222#L614-1 assume !(0 == ~E_M~0); 1441#L619-1 assume !(0 == ~E_1~0); 1442#L624-1 assume !(0 == ~E_2~0); 1334#L629-1 assume !(0 == ~E_3~0); 1335#L634-1 assume !(0 == ~E_4~0); 1403#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1283#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1284#L282 assume 1 == ~m_pc~0; 1540#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1542#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1543#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1582#L733 assume !(0 != activate_threads_~tmp~1); 1583#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1203#L301 assume !(1 == ~t1_pc~0); 1196#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 1160#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1161#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1228#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1212#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1213#L320 assume 1 == ~t2_pc~0; 1321#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1322#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1319#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1320#L749 assume !(0 != activate_threads_~tmp___1~0); 1508#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1504#L339 assume !(1 == ~t3_pc~0); 1464#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 1465#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1493#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1494#L757 assume !(0 != activate_threads_~tmp___2~0); 1591#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1275#L358 assume 1 == ~t4_pc~0; 1276#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1230#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1272#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1301#L765 assume !(0 != activate_threads_~tmp___3~0); 1302#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1303#L377 assume !(1 == ~t5_pc~0); 1209#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 1208#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1205#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1206#L773 assume !(0 != activate_threads_~tmp___4~0); 1435#L773-2 assume !(1 == ~M_E~0); 1436#L657-1 assume !(1 == ~T1_E~0); 1355#L662-1 assume !(1 == ~T2_E~0); 1356#L667-1 assume !(1 == ~T3_E~0); 1509#L672-1 assume !(1 == ~T4_E~0); 1281#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1282#L682-1 assume !(1 == ~E_M~0); 1073#L687-1 assume !(1 == ~E_1~0); 1074#L692-1 assume !(1 == ~E_2~0); 1214#L697-1 assume !(1 == ~E_3~0); 1215#L702-1 assume !(1 == ~E_4~0); 1437#L707-1 assume !(1 == ~E_5~0); 1116#L918-1 [2019-12-07 17:29:31,895 INFO L796 eck$LassoCheckResult]: Loop: 1116#L918-1 assume !false; 1117#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1290#L564 assume !false; 1409#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1348#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1261#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1347#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1307#L489 assume !(0 != eval_~tmp~0); 1309#L579 start_simulation_~kernel_st~0 := 2; 1399#L397-1 start_simulation_~kernel_st~0 := 3; 1297#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L589-4 assume !(0 == ~T1_E~0); 1256#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1305#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1306#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1192#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1193#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1427#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1428#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1342#L629-3 assume !(0 == ~E_3~0); 1343#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1408#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1295#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1296#L282-21 assume 1 == ~m_pc~0; 1595#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1525#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1526#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1532#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1533#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1099#L301-21 assume !(1 == ~t1_pc~0); 1097#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 1098#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1145#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1148#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1104#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1105#L320-21 assume !(1 == ~t2_pc~0); 1336#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 1337#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1369#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1373#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1374#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1382#L339-21 assume 1 == ~t3_pc~0; 1453#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1454#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1451#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1452#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1495#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1496#L358-21 assume 1 == ~t4_pc~0; 1554#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1251#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1252#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1553#L765-21 assume !(0 != activate_threads_~tmp___3~0); 1587#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1211#L377-21 assume 1 == ~t5_pc~0; 1131#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1132#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1126#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1127#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1413#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1414#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1338#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1339#L667-3 assume !(1 == ~T3_E~0); 1406#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1287#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1288#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1080#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1081#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1219#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1220#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1439#L707-3 assume !(1 == ~E_5~0); 1440#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1313#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1264#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1349#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1350#L937 assume !(0 == start_simulation_~tmp~3); 1359#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1318#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1270#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1314#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1315#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1510#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 1517#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1418#L950 assume !(0 != start_simulation_~tmp___0~1); 1116#L918-1 [2019-12-07 17:29:31,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:31,895 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2019-12-07 17:29:31,896 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:31,896 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771554544] [2019-12-07 17:29:31,896 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:31,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:31,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:31,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771554544] [2019-12-07 17:29:31,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:31,934 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:31,934 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476111642] [2019-12-07 17:29:31,934 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:31,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:31,935 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 1 times [2019-12-07 17:29:31,935 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:31,935 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92398807] [2019-12-07 17:29:31,935 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:31,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:31,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:31,997 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92398807] [2019-12-07 17:29:31,998 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:31,998 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:31,998 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108680006] [2019-12-07 17:29:31,998 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:31,998 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:31,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:31,999 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:31,999 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand 3 states. [2019-12-07 17:29:32,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,009 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2019-12-07 17:29:32,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2019-12-07 17:29:32,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2019-12-07 17:29:32,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2019-12-07 17:29:32,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,019 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2019-12-07 17:29:32,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2019-12-07 17:29:32,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2019-12-07 17:29:32,031 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2019-12-07 17:29:32,031 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2019-12-07 17:29:32,031 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 17:29:32,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2019-12-07 17:29:32,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,034 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,035 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,035 INFO L794 eck$LassoCheckResult]: Stem: 2572#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2522#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2523#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2456#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 2457#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2378#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2379#L414-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2458#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2328#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2329#L429-1 assume !(0 == ~M_E~0); 2354#L589-1 assume !(0 == ~T1_E~0); 2355#L594-1 assume !(0 == ~T2_E~0); 2143#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2144#L604-1 assume !(0 == ~T4_E~0); 2282#L609-1 assume !(0 == ~T5_E~0); 2283#L614-1 assume !(0 == ~E_M~0); 2502#L619-1 assume !(0 == ~E_1~0); 2503#L624-1 assume !(0 == ~E_2~0); 2395#L629-1 assume !(0 == ~E_3~0); 2396#L634-1 assume !(0 == ~E_4~0); 2464#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2344#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2345#L282 assume 1 == ~m_pc~0; 2601#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2603#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2604#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2643#L733 assume !(0 != activate_threads_~tmp~1); 2644#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2264#L301 assume !(1 == ~t1_pc~0); 2257#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 2221#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2222#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2289#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2273#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2274#L320 assume 1 == ~t2_pc~0; 2382#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2383#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2380#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2381#L749 assume !(0 != activate_threads_~tmp___1~0); 2569#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2565#L339 assume !(1 == ~t3_pc~0); 2525#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 2526#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2554#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2555#L757 assume !(0 != activate_threads_~tmp___2~0); 2652#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2336#L358 assume 1 == ~t4_pc~0; 2337#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2291#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2333#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2362#L765 assume !(0 != activate_threads_~tmp___3~0); 2363#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2364#L377 assume !(1 == ~t5_pc~0); 2270#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 2269#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2266#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2267#L773 assume !(0 != activate_threads_~tmp___4~0); 2496#L773-2 assume !(1 == ~M_E~0); 2497#L657-1 assume !(1 == ~T1_E~0); 2416#L662-1 assume !(1 == ~T2_E~0); 2417#L667-1 assume !(1 == ~T3_E~0); 2570#L672-1 assume !(1 == ~T4_E~0); 2342#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2343#L682-1 assume !(1 == ~E_M~0); 2134#L687-1 assume !(1 == ~E_1~0); 2135#L692-1 assume !(1 == ~E_2~0); 2275#L697-1 assume !(1 == ~E_3~0); 2276#L702-1 assume !(1 == ~E_4~0); 2498#L707-1 assume !(1 == ~E_5~0); 2177#L918-1 [2019-12-07 17:29:32,035 INFO L796 eck$LassoCheckResult]: Loop: 2177#L918-1 assume !false; 2178#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2351#L564 assume !false; 2470#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2411#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2322#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2408#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 2368#L489 assume !(0 != eval_~tmp~0); 2370#L579 start_simulation_~kernel_st~0 := 2; 2460#L397-1 start_simulation_~kernel_st~0 := 3; 2358#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2316#L589-4 assume !(0 == ~T1_E~0); 2317#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2253#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2254#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2488#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2489#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2403#L629-3 assume !(0 == ~E_3~0); 2404#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2469#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2356#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2357#L282-21 assume 1 == ~m_pc~0; 2656#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2586#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2587#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2593#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2594#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2160#L301-21 assume 1 == ~t1_pc~0; 2161#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2159#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2206#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2209#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2165#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2166#L320-21 assume !(1 == ~t2_pc~0); 2397#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 2398#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2430#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2434#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2435#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2443#L339-21 assume 1 == ~t3_pc~0; 2514#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2515#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2512#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2513#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2556#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2557#L358-21 assume 1 == ~t4_pc~0; 2615#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2312#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2313#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2614#L765-21 assume !(0 != activate_threads_~tmp___3~0); 2648#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2272#L377-21 assume 1 == ~t5_pc~0; 2192#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2193#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2187#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2188#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2474#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2475#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2399#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2400#L667-3 assume !(1 == ~T3_E~0); 2467#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2348#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2349#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2141#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2142#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2280#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2281#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2500#L707-3 assume !(1 == ~E_5~0); 2501#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2374#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2325#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2409#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2410#L937 assume !(0 == start_simulation_~tmp~3); 2420#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2377#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2331#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2375#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2376#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2571#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 2578#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2479#L950 assume !(0 != start_simulation_~tmp___0~1); 2177#L918-1 [2019-12-07 17:29:32,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,036 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2019-12-07 17:29:32,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092230040] [2019-12-07 17:29:32,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092230040] [2019-12-07 17:29:32,061 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485217528] [2019-12-07 17:29:32,062 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1573679129, now seen corresponding path program 1 times [2019-12-07 17:29:32,062 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633737785] [2019-12-07 17:29:32,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,102 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633737785] [2019-12-07 17:29:32,102 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379016385] [2019-12-07 17:29:32,103 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,103 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,103 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand 3 states. [2019-12-07 17:29:32,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,112 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2019-12-07 17:29:32,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2019-12-07 17:29:32,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2019-12-07 17:29:32,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2019-12-07 17:29:32,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,121 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2019-12-07 17:29:32,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2019-12-07 17:29:32,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2019-12-07 17:29:32,129 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2019-12-07 17:29:32,129 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2019-12-07 17:29:32,130 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 17:29:32,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2019-12-07 17:29:32,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,133 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,133 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,133 INFO L794 eck$LassoCheckResult]: Stem: 3633#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3583#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3584#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3517#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 3518#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3439#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3440#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3519#L419-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3389#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3390#L429-1 assume !(0 == ~M_E~0); 3415#L589-1 assume !(0 == ~T1_E~0); 3416#L594-1 assume !(0 == ~T2_E~0); 3204#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3205#L604-1 assume !(0 == ~T4_E~0); 3343#L609-1 assume !(0 == ~T5_E~0); 3344#L614-1 assume !(0 == ~E_M~0); 3563#L619-1 assume !(0 == ~E_1~0); 3564#L624-1 assume !(0 == ~E_2~0); 3456#L629-1 assume !(0 == ~E_3~0); 3457#L634-1 assume !(0 == ~E_4~0); 3525#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3405#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3406#L282 assume 1 == ~m_pc~0; 3662#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3664#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3665#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3704#L733 assume !(0 != activate_threads_~tmp~1); 3705#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3325#L301 assume !(1 == ~t1_pc~0); 3318#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 3282#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3283#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3350#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3334#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3335#L320 assume 1 == ~t2_pc~0; 3443#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3444#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3441#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3442#L749 assume !(0 != activate_threads_~tmp___1~0); 3630#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3626#L339 assume !(1 == ~t3_pc~0); 3586#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 3587#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3615#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3616#L757 assume !(0 != activate_threads_~tmp___2~0); 3713#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3397#L358 assume 1 == ~t4_pc~0; 3398#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3352#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3394#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3423#L765 assume !(0 != activate_threads_~tmp___3~0); 3424#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3425#L377 assume !(1 == ~t5_pc~0); 3331#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 3330#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3327#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3328#L773 assume !(0 != activate_threads_~tmp___4~0); 3557#L773-2 assume !(1 == ~M_E~0); 3558#L657-1 assume !(1 == ~T1_E~0); 3477#L662-1 assume !(1 == ~T2_E~0); 3478#L667-1 assume !(1 == ~T3_E~0); 3631#L672-1 assume !(1 == ~T4_E~0); 3403#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3404#L682-1 assume !(1 == ~E_M~0); 3195#L687-1 assume !(1 == ~E_1~0); 3196#L692-1 assume !(1 == ~E_2~0); 3336#L697-1 assume !(1 == ~E_3~0); 3337#L702-1 assume !(1 == ~E_4~0); 3559#L707-1 assume !(1 == ~E_5~0); 3238#L918-1 [2019-12-07 17:29:32,134 INFO L796 eck$LassoCheckResult]: Loop: 3238#L918-1 assume !false; 3239#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3412#L564 assume !false; 3531#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3472#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3383#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3469#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3429#L489 assume !(0 != eval_~tmp~0); 3431#L579 start_simulation_~kernel_st~0 := 2; 3521#L397-1 start_simulation_~kernel_st~0 := 3; 3419#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3377#L589-4 assume !(0 == ~T1_E~0); 3378#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3427#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3428#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3314#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3549#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3550#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3464#L629-3 assume !(0 == ~E_3~0); 3465#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3530#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3417#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3418#L282-21 assume 1 == ~m_pc~0; 3717#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3647#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3648#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3654#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3655#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3221#L301-21 assume !(1 == ~t1_pc~0); 3219#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 3220#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3267#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3270#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3226#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3227#L320-21 assume !(1 == ~t2_pc~0); 3458#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 3459#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3491#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3495#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3496#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3504#L339-21 assume 1 == ~t3_pc~0; 3575#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3576#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3573#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3574#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3617#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3618#L358-21 assume 1 == ~t4_pc~0; 3676#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3373#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3374#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3674#L765-21 assume !(0 != activate_threads_~tmp___3~0); 3709#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3333#L377-21 assume 1 == ~t5_pc~0; 3250#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3251#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3248#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3249#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3535#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3536#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3460#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3461#L667-3 assume !(1 == ~T3_E~0); 3528#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3409#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3410#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3202#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3203#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3341#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3342#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3561#L707-3 assume !(1 == ~E_5~0); 3562#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3435#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3386#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3470#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3471#L937 assume !(0 == start_simulation_~tmp~3); 3481#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3438#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3392#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3436#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3437#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3632#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 3639#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3540#L950 assume !(0 != start_simulation_~tmp___0~1); 3238#L918-1 [2019-12-07 17:29:32,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,134 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2019-12-07 17:29:32,134 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,143 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361835441] [2019-12-07 17:29:32,144 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,169 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361835441] [2019-12-07 17:29:32,169 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,169 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,169 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833059358] [2019-12-07 17:29:32,169 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,169 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 2 times [2019-12-07 17:29:32,170 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,170 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447498219] [2019-12-07 17:29:32,170 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447498219] [2019-12-07 17:29:32,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,200 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,200 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976521243] [2019-12-07 17:29:32,201 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,201 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,201 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand 3 states. [2019-12-07 17:29:32,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,209 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2019-12-07 17:29:32,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2019-12-07 17:29:32,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2019-12-07 17:29:32,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2019-12-07 17:29:32,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,216 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2019-12-07 17:29:32,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2019-12-07 17:29:32,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2019-12-07 17:29:32,223 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2019-12-07 17:29:32,223 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2019-12-07 17:29:32,223 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 17:29:32,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2019-12-07 17:29:32,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,226 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,226 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,227 INFO L794 eck$LassoCheckResult]: Stem: 4694#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4644#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4645#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4578#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 4579#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4500#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4501#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4580#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4450#L424-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4451#L429-1 assume !(0 == ~M_E~0); 4476#L589-1 assume !(0 == ~T1_E~0); 4477#L594-1 assume !(0 == ~T2_E~0); 4265#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4266#L604-1 assume !(0 == ~T4_E~0); 4404#L609-1 assume !(0 == ~T5_E~0); 4405#L614-1 assume !(0 == ~E_M~0); 4624#L619-1 assume !(0 == ~E_1~0); 4625#L624-1 assume !(0 == ~E_2~0); 4517#L629-1 assume !(0 == ~E_3~0); 4518#L634-1 assume !(0 == ~E_4~0); 4586#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4466#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4467#L282 assume 1 == ~m_pc~0; 4723#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4725#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4726#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4765#L733 assume !(0 != activate_threads_~tmp~1); 4766#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4386#L301 assume !(1 == ~t1_pc~0); 4379#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 4346#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4347#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4411#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4395#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4396#L320 assume 1 == ~t2_pc~0; 4504#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4505#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4502#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4503#L749 assume !(0 != activate_threads_~tmp___1~0); 4691#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4687#L339 assume !(1 == ~t3_pc~0); 4647#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 4648#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4676#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4677#L757 assume !(0 != activate_threads_~tmp___2~0); 4774#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4458#L358 assume 1 == ~t4_pc~0; 4459#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4413#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4457#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4484#L765 assume !(0 != activate_threads_~tmp___3~0); 4485#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4486#L377 assume !(1 == ~t5_pc~0); 4392#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 4391#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4388#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4389#L773 assume !(0 != activate_threads_~tmp___4~0); 4618#L773-2 assume !(1 == ~M_E~0); 4619#L657-1 assume !(1 == ~T1_E~0); 4538#L662-1 assume !(1 == ~T2_E~0); 4539#L667-1 assume !(1 == ~T3_E~0); 4692#L672-1 assume !(1 == ~T4_E~0); 4464#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4465#L682-1 assume !(1 == ~E_M~0); 4256#L687-1 assume !(1 == ~E_1~0); 4257#L692-1 assume !(1 == ~E_2~0); 4397#L697-1 assume !(1 == ~E_3~0); 4398#L702-1 assume !(1 == ~E_4~0); 4621#L707-1 assume !(1 == ~E_5~0); 4299#L918-1 [2019-12-07 17:29:32,227 INFO L796 eck$LassoCheckResult]: Loop: 4299#L918-1 assume !false; 4300#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4473#L564 assume !false; 4592#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4533#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4444#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4530#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 4490#L489 assume !(0 != eval_~tmp~0); 4492#L579 start_simulation_~kernel_st~0 := 2; 4582#L397-1 start_simulation_~kernel_st~0 := 3; 4480#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4438#L589-4 assume !(0 == ~T1_E~0); 4439#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4488#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4489#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4375#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4376#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4610#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4611#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4525#L629-3 assume !(0 == ~E_3~0); 4526#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4591#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4478#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4479#L282-21 assume 1 == ~m_pc~0; 4778#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4708#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4709#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4715#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4716#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4282#L301-21 assume !(1 == ~t1_pc~0); 4280#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 4281#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4328#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4331#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4287#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4288#L320-21 assume !(1 == ~t2_pc~0); 4519#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 4520#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4552#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4556#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4557#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4565#L339-21 assume 1 == ~t3_pc~0; 4636#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4637#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4634#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4635#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4678#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4679#L358-21 assume 1 == ~t4_pc~0; 4737#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4434#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4435#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4735#L765-21 assume !(0 != activate_threads_~tmp___3~0); 4770#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4394#L377-21 assume 1 == ~t5_pc~0; 4311#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4312#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4309#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4310#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4596#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4597#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4521#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4522#L667-3 assume !(1 == ~T3_E~0); 4589#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4470#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4471#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4263#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4264#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4402#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4403#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4622#L707-3 assume !(1 == ~E_5~0); 4623#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4496#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4447#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4531#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4532#L937 assume !(0 == start_simulation_~tmp~3); 4542#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4499#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4453#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4497#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4498#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4693#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 4700#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4601#L950 assume !(0 != start_simulation_~tmp___0~1); 4299#L918-1 [2019-12-07 17:29:32,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,227 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2019-12-07 17:29:32,227 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,227 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633149941] [2019-12-07 17:29:32,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,244 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633149941] [2019-12-07 17:29:32,244 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,244 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,244 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682580432] [2019-12-07 17:29:32,244 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 3 times [2019-12-07 17:29:32,245 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,245 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484763593] [2019-12-07 17:29:32,245 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,269 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484763593] [2019-12-07 17:29:32,269 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,269 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,269 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876129464] [2019-12-07 17:29:32,270 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,270 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,270 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand 3 states. [2019-12-07 17:29:32,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,278 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2019-12-07 17:29:32,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2019-12-07 17:29:32,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2019-12-07 17:29:32,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2019-12-07 17:29:32,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,285 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2019-12-07 17:29:32,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2019-12-07 17:29:32,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2019-12-07 17:29:32,291 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2019-12-07 17:29:32,291 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2019-12-07 17:29:32,291 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 17:29:32,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2019-12-07 17:29:32,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,294 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,294 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,294 INFO L794 eck$LassoCheckResult]: Stem: 5755#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5705#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5706#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5639#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 5640#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5561#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5562#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5641#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5511#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5512#L429-1 assume !(0 == ~M_E~0); 5537#L589-1 assume !(0 == ~T1_E~0); 5538#L594-1 assume !(0 == ~T2_E~0); 5326#L599-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5327#L604-1 assume !(0 == ~T4_E~0); 5465#L609-1 assume !(0 == ~T5_E~0); 5466#L614-1 assume !(0 == ~E_M~0); 5685#L619-1 assume !(0 == ~E_1~0); 5686#L624-1 assume !(0 == ~E_2~0); 5578#L629-1 assume !(0 == ~E_3~0); 5579#L634-1 assume !(0 == ~E_4~0); 5647#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5527#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5528#L282 assume 1 == ~m_pc~0; 5784#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5786#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5787#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5826#L733 assume !(0 != activate_threads_~tmp~1); 5827#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5447#L301 assume !(1 == ~t1_pc~0); 5440#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 5407#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5408#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5472#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5456#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5457#L320 assume 1 == ~t2_pc~0; 5565#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5566#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5563#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5564#L749 assume !(0 != activate_threads_~tmp___1~0); 5752#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5748#L339 assume !(1 == ~t3_pc~0); 5708#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 5709#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5737#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5738#L757 assume !(0 != activate_threads_~tmp___2~0); 5835#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5519#L358 assume 1 == ~t4_pc~0; 5520#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5474#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5518#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5545#L765 assume !(0 != activate_threads_~tmp___3~0); 5546#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5547#L377 assume !(1 == ~t5_pc~0); 5453#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 5452#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5449#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5450#L773 assume !(0 != activate_threads_~tmp___4~0); 5679#L773-2 assume !(1 == ~M_E~0); 5680#L657-1 assume !(1 == ~T1_E~0); 5599#L662-1 assume !(1 == ~T2_E~0); 5600#L667-1 assume !(1 == ~T3_E~0); 5753#L672-1 assume !(1 == ~T4_E~0); 5525#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5526#L682-1 assume !(1 == ~E_M~0); 5317#L687-1 assume !(1 == ~E_1~0); 5318#L692-1 assume !(1 == ~E_2~0); 5458#L697-1 assume !(1 == ~E_3~0); 5459#L702-1 assume !(1 == ~E_4~0); 5682#L707-1 assume !(1 == ~E_5~0); 5360#L918-1 [2019-12-07 17:29:32,294 INFO L796 eck$LassoCheckResult]: Loop: 5360#L918-1 assume !false; 5361#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5536#L564 assume !false; 5653#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5594#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5505#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5591#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5551#L489 assume !(0 != eval_~tmp~0); 5553#L579 start_simulation_~kernel_st~0 := 2; 5643#L397-1 start_simulation_~kernel_st~0 := 3; 5541#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5499#L589-4 assume !(0 == ~T1_E~0); 5500#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5549#L599-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5550#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5436#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5437#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5671#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5672#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5586#L629-3 assume !(0 == ~E_3~0); 5587#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5652#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5539#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5540#L282-21 assume !(1 == ~m_pc~0); 5840#L282-23 is_master_triggered_~__retres1~0 := 0; 5769#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5770#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5776#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5777#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5343#L301-21 assume 1 == ~t1_pc~0; 5344#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5342#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5389#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5392#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5348#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5349#L320-21 assume !(1 == ~t2_pc~0); 5580#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 5581#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5613#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5617#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5618#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5626#L339-21 assume 1 == ~t3_pc~0; 5697#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5698#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5695#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5696#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5739#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5740#L358-21 assume 1 == ~t4_pc~0; 5798#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5495#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5496#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5796#L765-21 assume !(0 != activate_threads_~tmp___3~0); 5831#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5455#L377-21 assume 1 == ~t5_pc~0; 5372#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5373#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5370#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5371#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5657#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5658#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5582#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5583#L667-3 assume !(1 == ~T3_E~0); 5650#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5531#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5532#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5324#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5325#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5463#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5464#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5683#L707-3 assume !(1 == ~E_5~0); 5684#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5557#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5508#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5592#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5593#L937 assume !(0 == start_simulation_~tmp~3); 5603#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5560#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5514#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5558#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 5559#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5754#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 5761#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5662#L950 assume !(0 != start_simulation_~tmp___0~1); 5360#L918-1 [2019-12-07 17:29:32,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2019-12-07 17:29:32,295 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,295 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056394624] [2019-12-07 17:29:32,295 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056394624] [2019-12-07 17:29:32,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:32,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757069136] [2019-12-07 17:29:32,314 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,314 INFO L82 PathProgramCache]: Analyzing trace with hash -332805064, now seen corresponding path program 1 times [2019-12-07 17:29:32,314 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,315 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776324434] [2019-12-07 17:29:32,315 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776324434] [2019-12-07 17:29:32,344 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,344 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748837385] [2019-12-07 17:29:32,345 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,345 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand 3 states. [2019-12-07 17:29:32,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,360 INFO L93 Difference]: Finished difference Result 527 states and 790 transitions. [2019-12-07 17:29:32,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 790 transitions. [2019-12-07 17:29:32,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 790 transitions. [2019-12-07 17:29:32,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 790 transitions. [2019-12-07 17:29:32,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,367 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2019-12-07 17:29:32,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 790 transitions. [2019-12-07 17:29:32,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 790 transitions. [2019-12-07 17:29:32,373 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2019-12-07 17:29:32,373 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2019-12-07 17:29:32,373 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 17:29:32,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 790 transitions. [2019-12-07 17:29:32,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,376 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,376 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,376 INFO L794 eck$LassoCheckResult]: Stem: 6816#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6766#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6767#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6700#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 6701#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6622#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6623#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6702#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6572#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6573#L429-1 assume !(0 == ~M_E~0); 6598#L589-1 assume !(0 == ~T1_E~0); 6599#L594-1 assume !(0 == ~T2_E~0); 6387#L599-1 assume !(0 == ~T3_E~0); 6388#L604-1 assume !(0 == ~T4_E~0); 6526#L609-1 assume !(0 == ~T5_E~0); 6527#L614-1 assume !(0 == ~E_M~0); 6746#L619-1 assume !(0 == ~E_1~0); 6747#L624-1 assume !(0 == ~E_2~0); 6639#L629-1 assume !(0 == ~E_3~0); 6640#L634-1 assume !(0 == ~E_4~0); 6708#L639-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6588#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6589#L282 assume 1 == ~m_pc~0; 6845#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6847#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6848#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6887#L733 assume !(0 != activate_threads_~tmp~1); 6888#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6508#L301 assume !(1 == ~t1_pc~0); 6501#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 6468#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6469#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6533#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6517#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6518#L320 assume 1 == ~t2_pc~0; 6626#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6627#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6624#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6625#L749 assume !(0 != activate_threads_~tmp___1~0); 6813#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6809#L339 assume !(1 == ~t3_pc~0); 6769#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 6770#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6798#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6799#L757 assume !(0 != activate_threads_~tmp___2~0); 6896#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6580#L358 assume 1 == ~t4_pc~0; 6581#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6535#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6579#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6606#L765 assume !(0 != activate_threads_~tmp___3~0); 6607#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6608#L377 assume !(1 == ~t5_pc~0); 6514#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 6513#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6510#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6511#L773 assume !(0 != activate_threads_~tmp___4~0); 6740#L773-2 assume !(1 == ~M_E~0); 6741#L657-1 assume !(1 == ~T1_E~0); 6660#L662-1 assume !(1 == ~T2_E~0); 6661#L667-1 assume !(1 == ~T3_E~0); 6814#L672-1 assume !(1 == ~T4_E~0); 6586#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6587#L682-1 assume !(1 == ~E_M~0); 6378#L687-1 assume !(1 == ~E_1~0); 6379#L692-1 assume !(1 == ~E_2~0); 6519#L697-1 assume !(1 == ~E_3~0); 6520#L702-1 assume !(1 == ~E_4~0); 6743#L707-1 assume !(1 == ~E_5~0); 6421#L918-1 [2019-12-07 17:29:32,376 INFO L796 eck$LassoCheckResult]: Loop: 6421#L918-1 assume !false; 6422#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6597#L564 assume !false; 6714#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6655#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6566#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6652#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 6612#L489 assume !(0 != eval_~tmp~0); 6614#L579 start_simulation_~kernel_st~0 := 2; 6704#L397-1 start_simulation_~kernel_st~0 := 3; 6602#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6560#L589-4 assume !(0 == ~T1_E~0); 6561#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6610#L599-3 assume !(0 == ~T3_E~0); 6611#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6497#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6498#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6732#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6733#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6647#L629-3 assume !(0 == ~E_3~0); 6648#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6713#L639-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6600#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6601#L282-21 assume 1 == ~m_pc~0; 6900#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6830#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6831#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6837#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6838#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6404#L301-21 assume !(1 == ~t1_pc~0); 6402#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 6403#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6450#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6453#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6407#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6408#L320-21 assume !(1 == ~t2_pc~0); 6641#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 6642#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6674#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6678#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6679#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6687#L339-21 assume 1 == ~t3_pc~0; 6758#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6759#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6756#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6757#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6800#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6801#L358-21 assume 1 == ~t4_pc~0; 6859#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6556#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6557#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6857#L765-21 assume !(0 != activate_threads_~tmp___3~0); 6892#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6516#L377-21 assume 1 == ~t5_pc~0; 6433#L378-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6434#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6431#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6432#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6718#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6719#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6643#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6644#L667-3 assume !(1 == ~T3_E~0); 6711#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6592#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6593#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6385#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6386#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6524#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6525#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6744#L707-3 assume !(1 == ~E_5~0); 6745#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6618#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6569#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6653#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6654#L937 assume !(0 == start_simulation_~tmp~3); 6664#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6621#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6575#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6619#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 6620#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6815#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 6822#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6723#L950 assume !(0 != start_simulation_~tmp___0~1); 6421#L918-1 [2019-12-07 17:29:32,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,376 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2019-12-07 17:29:32,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,377 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30763708] [2019-12-07 17:29:32,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30763708] [2019-12-07 17:29:32,391 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,391 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:32,392 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672744077] [2019-12-07 17:29:32,392 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,392 INFO L82 PathProgramCache]: Analyzing trace with hash -710029130, now seen corresponding path program 1 times [2019-12-07 17:29:32,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253938946] [2019-12-07 17:29:32,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253938946] [2019-12-07 17:29:32,412 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,412 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:32,412 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103033002] [2019-12-07 17:29:32,412 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,413 INFO L87 Difference]: Start difference. First operand 527 states and 790 transitions. cyclomatic complexity: 264 Second operand 3 states. [2019-12-07 17:29:32,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,441 INFO L93 Difference]: Finished difference Result 527 states and 777 transitions. [2019-12-07 17:29:32,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 777 transitions. [2019-12-07 17:29:32,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 777 transitions. [2019-12-07 17:29:32,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2019-12-07 17:29:32,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2019-12-07 17:29:32,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 777 transitions. [2019-12-07 17:29:32,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,448 INFO L688 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2019-12-07 17:29:32,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 777 transitions. [2019-12-07 17:29:32,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2019-12-07 17:29:32,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 527 states. [2019-12-07 17:29:32,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 777 transitions. [2019-12-07 17:29:32,454 INFO L711 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2019-12-07 17:29:32,454 INFO L591 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2019-12-07 17:29:32,454 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 17:29:32,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 777 transitions. [2019-12-07 17:29:32,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2019-12-07 17:29:32,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,456 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,457 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,457 INFO L794 eck$LassoCheckResult]: Stem: 7877#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7827#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7828#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7756#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 7757#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7678#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7679#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7759#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7628#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7629#L429-1 assume !(0 == ~M_E~0); 7654#L589-1 assume !(0 == ~T1_E~0); 7655#L594-1 assume !(0 == ~T2_E~0); 7448#L599-1 assume !(0 == ~T3_E~0); 7449#L604-1 assume !(0 == ~T4_E~0); 7580#L609-1 assume !(0 == ~T5_E~0); 7581#L614-1 assume !(0 == ~E_M~0); 7807#L619-1 assume !(0 == ~E_1~0); 7808#L624-1 assume !(0 == ~E_2~0); 7695#L629-1 assume !(0 == ~E_3~0); 7696#L634-1 assume !(0 == ~E_4~0); 7764#L639-1 assume !(0 == ~E_5~0); 7644#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7645#L282 assume 1 == ~m_pc~0; 7906#L283 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7908#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7909#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7948#L733 assume !(0 != activate_threads_~tmp~1); 7949#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7562#L301 assume !(1 == ~t1_pc~0); 7555#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 7524#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7525#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7589#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7570#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7571#L320 assume 1 == ~t2_pc~0; 7682#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7683#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7680#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7681#L749 assume !(0 != activate_threads_~tmp___1~0); 7874#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7870#L339 assume !(1 == ~t3_pc~0); 7830#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 7831#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7859#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7860#L757 assume !(0 != activate_threads_~tmp___2~0); 7957#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7636#L358 assume 1 == ~t4_pc~0; 7637#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7591#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7635#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7662#L765 assume !(0 != activate_threads_~tmp___3~0); 7663#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7664#L377 assume !(1 == ~t5_pc~0); 7567#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 7789#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7564#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7565#L773 assume !(0 != activate_threads_~tmp___4~0); 7801#L773-2 assume !(1 == ~M_E~0); 7802#L657-1 assume !(1 == ~T1_E~0); 7716#L662-1 assume !(1 == ~T2_E~0); 7717#L667-1 assume !(1 == ~T3_E~0); 7875#L672-1 assume !(1 == ~T4_E~0); 7642#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7643#L682-1 assume !(1 == ~E_M~0); 7439#L687-1 assume !(1 == ~E_1~0); 7440#L692-1 assume !(1 == ~E_2~0); 7572#L697-1 assume !(1 == ~E_3~0); 7573#L702-1 assume !(1 == ~E_4~0); 7804#L707-1 assume !(1 == ~E_5~0); 7482#L918-1 [2019-12-07 17:29:32,457 INFO L796 eck$LassoCheckResult]: Loop: 7482#L918-1 assume !false; 7483#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7653#L564 assume !false; 7771#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7711#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7622#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7708#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7668#L489 assume !(0 != eval_~tmp~0); 7670#L579 start_simulation_~kernel_st~0 := 2; 7760#L397-1 start_simulation_~kernel_st~0 := 3; 7658#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7616#L589-4 assume !(0 == ~T1_E~0); 7617#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7666#L599-3 assume !(0 == ~T3_E~0); 7667#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7551#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7552#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7793#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7794#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7703#L629-3 assume !(0 == ~E_3~0); 7704#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7769#L639-3 assume !(0 == ~E_5~0); 7656#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7657#L282-21 assume 1 == ~m_pc~0; 7961#L283-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7891#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7892#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7898#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7899#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7465#L301-21 assume !(1 == ~t1_pc~0); 7463#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 7464#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7505#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7509#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7468#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7469#L320-21 assume !(1 == ~t2_pc~0); 7697#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 7698#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7730#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7734#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7735#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7743#L339-21 assume 1 == ~t3_pc~0; 7819#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7820#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7817#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7818#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7861#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7862#L358-21 assume 1 == ~t4_pc~0; 7920#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7612#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7613#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7918#L765-21 assume !(0 != activate_threads_~tmp___3~0); 7953#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7569#L377-21 assume !(1 == ~t5_pc~0); 7494#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 7574#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7491#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7492#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7775#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7776#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7699#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7700#L667-3 assume !(1 == ~T3_E~0); 7767#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7648#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7649#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7446#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7447#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7805#L707-3 assume !(1 == ~E_5~0); 7806#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7674#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7625#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7709#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7710#L937 assume !(0 == start_simulation_~tmp~3); 7720#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7677#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7631#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7675#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7676#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7876#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 7883#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7780#L950 assume !(0 != start_simulation_~tmp___0~1); 7482#L918-1 [2019-12-07 17:29:32,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,457 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2019-12-07 17:29:32,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170717437] [2019-12-07 17:29:32,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,471 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170717437] [2019-12-07 17:29:32,471 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,471 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:32,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217752817] [2019-12-07 17:29:32,472 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,472 INFO L82 PathProgramCache]: Analyzing trace with hash -87901101, now seen corresponding path program 1 times [2019-12-07 17:29:32,472 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,472 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599064785] [2019-12-07 17:29:32,472 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599064785] [2019-12-07 17:29:32,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:29:32,517 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1500582367] [2019-12-07 17:29:32,517 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,517 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,517 INFO L87 Difference]: Start difference. First operand 527 states and 777 transitions. cyclomatic complexity: 251 Second operand 3 states. [2019-12-07 17:29:32,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,573 INFO L93 Difference]: Finished difference Result 969 states and 1412 transitions. [2019-12-07 17:29:32,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 969 states and 1412 transitions. [2019-12-07 17:29:32,579 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 893 [2019-12-07 17:29:32,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 969 states to 969 states and 1412 transitions. [2019-12-07 17:29:32,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 969 [2019-12-07 17:29:32,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 969 [2019-12-07 17:29:32,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 969 states and 1412 transitions. [2019-12-07 17:29:32,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,589 INFO L688 BuchiCegarLoop]: Abstraction has 969 states and 1412 transitions. [2019-12-07 17:29:32,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 969 states and 1412 transitions. [2019-12-07 17:29:32,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 969 to 929. [2019-12-07 17:29:32,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 929 states. [2019-12-07 17:29:32,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 929 states to 929 states and 1357 transitions. [2019-12-07 17:29:32,607 INFO L711 BuchiCegarLoop]: Abstraction has 929 states and 1357 transitions. [2019-12-07 17:29:32,607 INFO L591 BuchiCegarLoop]: Abstraction has 929 states and 1357 transitions. [2019-12-07 17:29:32,607 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 17:29:32,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 929 states and 1357 transitions. [2019-12-07 17:29:32,611 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 853 [2019-12-07 17:29:32,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,612 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,612 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,613 INFO L794 eck$LassoCheckResult]: Stem: 9419#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9354#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9355#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9272#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 9273#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9189#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9190#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9275#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9138#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9139#L429-1 assume !(0 == ~M_E~0); 9164#L589-1 assume !(0 == ~T1_E~0); 9165#L594-1 assume !(0 == ~T2_E~0); 8956#L599-1 assume !(0 == ~T3_E~0); 8957#L604-1 assume !(0 == ~T4_E~0); 9091#L609-1 assume !(0 == ~T5_E~0); 9092#L614-1 assume !(0 == ~E_M~0); 9333#L619-1 assume !(0 == ~E_1~0); 9334#L624-1 assume !(0 == ~E_2~0); 9206#L629-1 assume !(0 == ~E_3~0); 9207#L634-1 assume !(0 == ~E_4~0); 9280#L639-1 assume !(0 == ~E_5~0); 9154#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9155#L282 assume !(1 == ~m_pc~0); 9451#L282-2 is_master_triggered_~__retres1~0 := 0; 9454#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9455#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9498#L733 assume !(0 != activate_threads_~tmp~1); 9499#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9072#L301 assume !(1 == ~t1_pc~0); 9064#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 9032#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9033#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9099#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9080#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9081#L320 assume 1 == ~t2_pc~0; 9193#L321 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9194#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9191#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9192#L749 assume !(0 != activate_threads_~tmp___1~0); 9416#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9410#L339 assume !(1 == ~t3_pc~0); 9357#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 9358#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9388#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9389#L757 assume !(0 != activate_threads_~tmp___2~0); 9512#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9146#L358 assume 1 == ~t4_pc~0; 9147#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9101#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9145#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9172#L765 assume !(0 != activate_threads_~tmp___3~0); 9173#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9174#L377 assume !(1 == ~t5_pc~0); 9078#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 9313#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9074#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9075#L773 assume !(0 != activate_threads_~tmp___4~0); 9327#L773-2 assume !(1 == ~M_E~0); 9328#L657-1 assume !(1 == ~T1_E~0); 9227#L662-1 assume !(1 == ~T2_E~0); 9228#L667-1 assume !(1 == ~T3_E~0); 9417#L672-1 assume !(1 == ~T4_E~0); 9152#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9153#L682-1 assume !(1 == ~E_M~0); 8947#L687-1 assume !(1 == ~E_1~0); 8948#L692-1 assume !(1 == ~E_2~0); 9082#L697-1 assume !(1 == ~E_3~0); 9083#L702-1 assume !(1 == ~E_4~0); 9330#L707-1 assume !(1 == ~E_5~0); 8990#L918-1 [2019-12-07 17:29:32,613 INFO L796 eck$LassoCheckResult]: Loop: 8990#L918-1 assume !false; 8991#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9176#L564 assume !false; 9316#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9220#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9132#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9542#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 9539#L489 assume !(0 != eval_~tmp~0); 9540#L579 start_simulation_~kernel_st~0 := 2; 9636#L397-1 start_simulation_~kernel_st~0 := 3; 9635#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9634#L589-4 assume !(0 == ~T1_E~0); 9424#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9177#L599-3 assume !(0 == ~T3_E~0); 9178#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9632#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9631#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9319#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9320#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9214#L629-3 assume !(0 == ~E_3~0); 9215#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9628#L639-3 assume !(0 == ~E_5~0); 9166#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9167#L282-21 assume !(1 == ~m_pc~0); 9532#L282-23 is_master_triggered_~__retres1~0 := 0; 9773#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9772#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9771#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9770#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9769#L301-21 assume !(1 == ~t1_pc~0); 9767#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 9766#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9765#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9764#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9763#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9762#L320-21 assume 1 == ~t2_pc~0; 9760#L321-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9759#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9758#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9757#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9756#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9390#L339-21 assume !(1 == ~t3_pc~0); 9392#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 9404#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9405#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9407#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9408#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9755#L358-21 assume 1 == ~t4_pc~0; 9465#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9122#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9123#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9753#L765-21 assume !(0 != activate_threads_~tmp___3~0); 9752#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9751#L377-21 assume !(1 == ~t5_pc~0); 9749#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 9307#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9308#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9748#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9296#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9297#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9210#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9211#L667-3 assume !(1 == ~T3_E~0); 9283#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9284#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9423#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8954#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8955#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9744#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9743#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9331#L707-3 assume !(1 == ~E_5~0); 9332#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9185#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9135#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9221#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9222#L937 assume !(0 == start_simulation_~tmp~3); 9231#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9801#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9796#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9794#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 9792#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9427#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 9428#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9301#L950 assume !(0 != start_simulation_~tmp___0~1); 8990#L918-1 [2019-12-07 17:29:32,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,613 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2019-12-07 17:29:32,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,614 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536005038] [2019-12-07 17:29:32,614 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,634 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536005038] [2019-12-07 17:29:32,634 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,634 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:32,634 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341325270] [2019-12-07 17:29:32,634 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,634 INFO L82 PathProgramCache]: Analyzing trace with hash -1287767118, now seen corresponding path program 1 times [2019-12-07 17:29:32,635 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,635 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351255585] [2019-12-07 17:29:32,635 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351255585] [2019-12-07 17:29:32,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,674 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:29:32,674 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723762780] [2019-12-07 17:29:32,675 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,675 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,675 INFO L87 Difference]: Start difference. First operand 929 states and 1357 transitions. cyclomatic complexity: 430 Second operand 3 states. [2019-12-07 17:29:32,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,724 INFO L93 Difference]: Finished difference Result 1685 states and 2443 transitions. [2019-12-07 17:29:32,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1685 states and 2443 transitions. [2019-12-07 17:29:32,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1604 [2019-12-07 17:29:32,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1685 states to 1685 states and 2443 transitions. [2019-12-07 17:29:32,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1685 [2019-12-07 17:29:32,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1685 [2019-12-07 17:29:32,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1685 states and 2443 transitions. [2019-12-07 17:29:32,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,749 INFO L688 BuchiCegarLoop]: Abstraction has 1685 states and 2443 transitions. [2019-12-07 17:29:32,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1685 states and 2443 transitions. [2019-12-07 17:29:32,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1685 to 1681. [2019-12-07 17:29:32,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1681 states. [2019-12-07 17:29:32,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1681 states to 1681 states and 2439 transitions. [2019-12-07 17:29:32,776 INFO L711 BuchiCegarLoop]: Abstraction has 1681 states and 2439 transitions. [2019-12-07 17:29:32,776 INFO L591 BuchiCegarLoop]: Abstraction has 1681 states and 2439 transitions. [2019-12-07 17:29:32,776 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 17:29:32,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1681 states and 2439 transitions. [2019-12-07 17:29:32,782 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1600 [2019-12-07 17:29:32,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,783 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,783 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,783 INFO L794 eck$LassoCheckResult]: Stem: 12038#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 11988#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11989#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11896#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 11897#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11815#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11816#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11898#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11765#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11766#L429-1 assume !(0 == ~M_E~0); 11791#L589-1 assume !(0 == ~T1_E~0); 11792#L594-1 assume !(0 == ~T2_E~0); 11582#L599-1 assume !(0 == ~T3_E~0); 11583#L604-1 assume !(0 == ~T4_E~0); 11717#L609-1 assume !(0 == ~T5_E~0); 11718#L614-1 assume !(0 == ~E_M~0); 11955#L619-1 assume !(0 == ~E_1~0); 11956#L624-1 assume !(0 == ~E_2~0); 11830#L629-1 assume !(0 == ~E_3~0); 11831#L634-1 assume !(0 == ~E_4~0); 11904#L639-1 assume !(0 == ~E_5~0); 11781#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11782#L282 assume !(1 == ~m_pc~0); 12066#L282-2 is_master_triggered_~__retres1~0 := 0; 12067#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12068#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12110#L733 assume !(0 != activate_threads_~tmp~1); 12111#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11698#L301 assume !(1 == ~t1_pc~0); 11691#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 11657#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11658#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11725#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11707#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11708#L320 assume !(1 == ~t2_pc~0); 11880#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 11881#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11818#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11819#L749 assume !(0 != activate_threads_~tmp___1~0); 12035#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12031#L339 assume !(1 == ~t3_pc~0); 11991#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 11992#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12020#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12021#L757 assume !(0 != activate_threads_~tmp___2~0); 12123#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11773#L358 assume 1 == ~t4_pc~0; 11774#L359 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11728#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11770#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11799#L765 assume !(0 != activate_threads_~tmp___3~0); 11800#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11801#L377 assume !(1 == ~t5_pc~0); 11703#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 11929#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11700#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11701#L773 assume !(0 != activate_threads_~tmp___4~0); 11946#L773-2 assume !(1 == ~M_E~0); 11947#L657-1 assume !(1 == ~T1_E~0); 11849#L662-1 assume !(1 == ~T2_E~0); 11850#L667-1 assume !(1 == ~T3_E~0); 12036#L672-1 assume !(1 == ~T4_E~0); 11779#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11780#L682-1 assume !(1 == ~E_M~0); 11573#L687-1 assume !(1 == ~E_1~0); 11574#L692-1 assume !(1 == ~E_2~0); 11709#L697-1 assume !(1 == ~E_3~0); 11710#L702-1 assume !(1 == ~E_4~0); 11948#L707-1 assume !(1 == ~E_5~0); 11616#L918-1 [2019-12-07 17:29:32,783 INFO L796 eck$LassoCheckResult]: Loop: 11616#L918-1 assume !false; 11617#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 11788#L564 assume !false; 11910#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11843#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11759#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11842#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 11805#L489 assume !(0 != eval_~tmp~0); 11807#L579 start_simulation_~kernel_st~0 := 2; 13244#L397-1 start_simulation_~kernel_st~0 := 3; 13243#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13242#L589-4 assume !(0 == ~T1_E~0); 13241#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13240#L599-3 assume !(0 == ~T3_E~0); 13239#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13238#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13237#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13236#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12144#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11837#L629-3 assume !(0 == ~E_3~0); 11838#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11909#L639-3 assume !(0 == ~E_5~0); 11793#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11794#L282-21 assume !(1 == ~m_pc~0); 12143#L282-23 is_master_triggered_~__retres1~0 := 0; 13253#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12133#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12058#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12059#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11599#L301-21 assume 1 == ~t1_pc~0; 11600#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11598#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11640#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11643#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11604#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11605#L320-21 assume !(1 == ~t2_pc~0); 11848#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 13230#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13229#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13228#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13154#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13152#L339-21 assume !(1 == ~t3_pc~0); 13149#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 13147#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13145#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13143#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13141#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13139#L358-21 assume 1 == ~t4_pc~0; 13136#L359-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13134#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13132#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13130#L765-21 assume !(0 != activate_threads_~tmp___3~0); 13085#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13083#L377-21 assume !(1 == ~t5_pc~0); 13080#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 13078#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13076#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13074#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13072#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 13055#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13052#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13050#L667-3 assume !(1 == ~T3_E~0); 13048#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13046#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13044#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13041#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13039#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13037#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13035#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13031#L707-3 assume !(1 == ~E_5~0); 13029#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12943#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12937#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12935#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 12931#L937 assume !(0 == start_simulation_~tmp~3); 12930#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12925#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11895#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11813#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 11814#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12037#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 12044#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11921#L950 assume !(0 != start_simulation_~tmp___0~1); 11616#L918-1 [2019-12-07 17:29:32,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,784 INFO L82 PathProgramCache]: Analyzing trace with hash -1115145540, now seen corresponding path program 1 times [2019-12-07 17:29:32,784 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,784 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092399935] [2019-12-07 17:29:32,784 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,801 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092399935] [2019-12-07 17:29:32,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:32,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106966372] [2019-12-07 17:29:32,802 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:32,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,802 INFO L82 PathProgramCache]: Analyzing trace with hash 42266354, now seen corresponding path program 1 times [2019-12-07 17:29:32,803 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,803 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196441995] [2019-12-07 17:29:32,803 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:32,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:32,851 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196441995] [2019-12-07 17:29:32,851 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:32,852 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:29:32,852 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891781722] [2019-12-07 17:29:32,852 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:32,852 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:32,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:32,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:32,852 INFO L87 Difference]: Start difference. First operand 1681 states and 2439 transitions. cyclomatic complexity: 762 Second operand 3 states. [2019-12-07 17:29:32,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:32,897 INFO L93 Difference]: Finished difference Result 3096 states and 4460 transitions. [2019-12-07 17:29:32,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:32,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3096 states and 4460 transitions. [2019-12-07 17:29:32,916 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3000 [2019-12-07 17:29:32,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3096 states to 3096 states and 4460 transitions. [2019-12-07 17:29:32,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3096 [2019-12-07 17:29:32,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3096 [2019-12-07 17:29:32,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3096 states and 4460 transitions. [2019-12-07 17:29:32,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:32,937 INFO L688 BuchiCegarLoop]: Abstraction has 3096 states and 4460 transitions. [2019-12-07 17:29:32,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3096 states and 4460 transitions. [2019-12-07 17:29:32,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3096 to 3088. [2019-12-07 17:29:32,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3088 states. [2019-12-07 17:29:32,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3088 states to 3088 states and 4452 transitions. [2019-12-07 17:29:32,972 INFO L711 BuchiCegarLoop]: Abstraction has 3088 states and 4452 transitions. [2019-12-07 17:29:32,972 INFO L591 BuchiCegarLoop]: Abstraction has 3088 states and 4452 transitions. [2019-12-07 17:29:32,972 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 17:29:32,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3088 states and 4452 transitions. [2019-12-07 17:29:32,981 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2019-12-07 17:29:32,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:32,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:32,982 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,982 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:32,982 INFO L794 eck$LassoCheckResult]: Stem: 16850#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16795#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16796#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16695#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 16696#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16608#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16609#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16697#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16554#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16555#L429-1 assume !(0 == ~M_E~0); 16579#L589-1 assume !(0 == ~T1_E~0); 16580#L594-1 assume !(0 == ~T2_E~0); 16371#L599-1 assume !(0 == ~T3_E~0); 16372#L604-1 assume !(0 == ~T4_E~0); 16507#L609-1 assume !(0 == ~T5_E~0); 16508#L614-1 assume !(0 == ~E_M~0); 16765#L619-1 assume !(0 == ~E_1~0); 16766#L624-1 assume !(0 == ~E_2~0); 16623#L629-1 assume !(0 == ~E_3~0); 16624#L634-1 assume !(0 == ~E_4~0); 16703#L639-1 assume !(0 == ~E_5~0); 16569#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16570#L282 assume !(1 == ~m_pc~0); 16880#L282-2 is_master_triggered_~__retres1~0 := 0; 16881#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16882#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16936#L733 assume !(0 != activate_threads_~tmp~1); 16937#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16489#L301 assume !(1 == ~t1_pc~0); 16481#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 16448#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16449#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16515#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16497#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16498#L320 assume !(1 == ~t2_pc~0); 16677#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 16678#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16611#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16612#L749 assume !(0 != activate_threads_~tmp___1~0); 16847#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16843#L339 assume !(1 == ~t3_pc~0); 16798#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 16799#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16828#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16829#L757 assume !(0 != activate_threads_~tmp___2~0); 16954#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16562#L358 assume !(1 == ~t4_pc~0); 16517#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 16518#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16559#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16587#L765 assume !(0 != activate_threads_~tmp___3~0); 16588#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16589#L377 assume !(1 == ~t5_pc~0); 16494#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 16737#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16491#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16492#L773 assume !(0 != activate_threads_~tmp___4~0); 16756#L773-2 assume !(1 == ~M_E~0); 16757#L657-1 assume !(1 == ~T1_E~0); 16645#L662-1 assume !(1 == ~T2_E~0); 16646#L667-1 assume !(1 == ~T3_E~0); 16848#L672-1 assume !(1 == ~T4_E~0); 16567#L677-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16568#L682-1 assume !(1 == ~E_M~0); 16362#L687-1 assume !(1 == ~E_1~0); 16363#L692-1 assume !(1 == ~E_2~0); 16499#L697-1 assume !(1 == ~E_3~0); 16500#L702-1 assume !(1 == ~E_4~0); 16758#L707-1 assume !(1 == ~E_5~0); 16759#L918-1 [2019-12-07 17:29:32,982 INFO L796 eck$LassoCheckResult]: Loop: 16759#L918-1 assume !false; 18516#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 18515#L564 assume !false; 18514#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18492#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18488#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18485#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 18480#L489 assume !(0 != eval_~tmp~0); 18481#L579 start_simulation_~kernel_st~0 := 2; 18995#L397-1 start_simulation_~kernel_st~0 := 3; 18992#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18991#L589-4 assume !(0 == ~T1_E~0); 18988#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18987#L599-3 assume !(0 == ~T3_E~0); 18984#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18981#L609-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18978#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18973#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18970#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18968#L629-3 assume !(0 == ~E_3~0); 18966#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18964#L639-3 assume !(0 == ~E_5~0); 18962#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18960#L282-21 assume !(1 == ~m_pc~0); 18956#L282-23 is_master_triggered_~__retres1~0 := 0; 18954#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18950#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18916#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18915#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18914#L301-21 assume 1 == ~t1_pc~0; 18912#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18910#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18907#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18905#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18903#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18901#L320-21 assume !(1 == ~t2_pc~0); 18900#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 18899#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18898#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18896#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18894#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18892#L339-21 assume !(1 == ~t3_pc~0); 18889#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 18887#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18885#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18883#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18881#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18879#L358-21 assume !(1 == ~t4_pc~0); 18877#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 18875#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18873#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18871#L765-21 assume !(0 != activate_threads_~tmp___3~0); 18865#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18856#L377-21 assume !(1 == ~t5_pc~0); 18852#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 18850#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18848#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18846#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 18844#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 18842#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18839#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18837#L667-3 assume !(1 == ~T3_E~0); 18835#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18833#L677-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18831#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18829#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18827#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18825#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18823#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18821#L707-3 assume !(1 == ~E_5~0); 18819#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18816#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18809#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18807#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 18798#L937 assume !(0 == start_simulation_~tmp~3); 18779#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18616#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18612#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18604#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 18602#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18600#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 18599#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 18598#L950 assume !(0 != start_simulation_~tmp___0~1); 16759#L918-1 [2019-12-07 17:29:32,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:32,983 INFO L82 PathProgramCache]: Analyzing trace with hash -335164611, now seen corresponding path program 1 times [2019-12-07 17:29:32,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:32,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370805689] [2019-12-07 17:29:32,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:32,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,003 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1370805689] [2019-12-07 17:29:33,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:33,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292372824] [2019-12-07 17:29:33,004 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:33,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,004 INFO L82 PathProgramCache]: Analyzing trace with hash -1722550255, now seen corresponding path program 1 times [2019-12-07 17:29:33,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245620998] [2019-12-07 17:29:33,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,024 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245620998] [2019-12-07 17:29:33,024 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,024 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:29:33,024 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81197885] [2019-12-07 17:29:33,024 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:33,025 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:33,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:33,025 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:33,025 INFO L87 Difference]: Start difference. First operand 3088 states and 4452 transitions. cyclomatic complexity: 1372 Second operand 3 states. [2019-12-07 17:29:33,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:33,048 INFO L93 Difference]: Finished difference Result 3088 states and 4426 transitions. [2019-12-07 17:29:33,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:33,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3088 states and 4426 transitions. [2019-12-07 17:29:33,060 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2019-12-07 17:29:33,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3088 states to 3088 states and 4426 transitions. [2019-12-07 17:29:33,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3088 [2019-12-07 17:29:33,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3088 [2019-12-07 17:29:33,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3088 states and 4426 transitions. [2019-12-07 17:29:33,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:33,080 INFO L688 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2019-12-07 17:29:33,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3088 states and 4426 transitions. [2019-12-07 17:29:33,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3088 to 3088. [2019-12-07 17:29:33,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3088 states. [2019-12-07 17:29:33,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3088 states to 3088 states and 4426 transitions. [2019-12-07 17:29:33,114 INFO L711 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2019-12-07 17:29:33,114 INFO L591 BuchiCegarLoop]: Abstraction has 3088 states and 4426 transitions. [2019-12-07 17:29:33,114 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 17:29:33,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3088 states and 4426 transitions. [2019-12-07 17:29:33,120 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2992 [2019-12-07 17:29:33,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:33,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:33,121 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,121 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,121 INFO L794 eck$LassoCheckResult]: Stem: 23007#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 22956#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22957#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22867#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 22868#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22787#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22788#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22869#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22736#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22737#L429-1 assume !(0 == ~M_E~0); 22761#L589-1 assume !(0 == ~T1_E~0); 22762#L594-1 assume !(0 == ~T2_E~0); 22556#L599-1 assume !(0 == ~T3_E~0); 22557#L604-1 assume !(0 == ~T4_E~0); 22689#L609-1 assume !(0 == ~T5_E~0); 22690#L614-1 assume !(0 == ~E_M~0); 22922#L619-1 assume !(0 == ~E_1~0); 22923#L624-1 assume !(0 == ~E_2~0); 22802#L629-1 assume !(0 == ~E_3~0); 22803#L634-1 assume !(0 == ~E_4~0); 22875#L639-1 assume !(0 == ~E_5~0); 22751#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22752#L282 assume !(1 == ~m_pc~0); 23035#L282-2 is_master_triggered_~__retres1~0 := 0; 23036#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23037#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23088#L733 assume !(0 != activate_threads_~tmp~1); 23089#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22671#L301 assume !(1 == ~t1_pc~0); 22664#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 22631#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22632#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22697#L741 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22679#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22680#L320 assume !(1 == ~t2_pc~0); 22852#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 22853#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22790#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22791#L749 assume !(0 != activate_threads_~tmp___1~0); 23004#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23000#L339 assume !(1 == ~t3_pc~0); 22959#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 22960#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22988#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22989#L757 assume !(0 != activate_threads_~tmp___2~0); 23101#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22744#L358 assume !(1 == ~t4_pc~0); 22699#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 22700#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22741#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22769#L765 assume !(0 != activate_threads_~tmp___3~0); 22770#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22771#L377 assume !(1 == ~t5_pc~0); 22676#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 22899#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22673#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22674#L773 assume !(0 != activate_threads_~tmp___4~0); 22915#L773-2 assume !(1 == ~M_E~0); 22916#L657-1 assume !(1 == ~T1_E~0); 22820#L662-1 assume !(1 == ~T2_E~0); 22821#L667-1 assume !(1 == ~T3_E~0); 23005#L672-1 assume !(1 == ~T4_E~0); 22749#L677-1 assume !(1 == ~T5_E~0); 22750#L682-1 assume !(1 == ~E_M~0); 22547#L687-1 assume !(1 == ~E_1~0); 22548#L692-1 assume !(1 == ~E_2~0); 22681#L697-1 assume !(1 == ~E_3~0); 22682#L702-1 assume !(1 == ~E_4~0); 22917#L707-1 assume !(1 == ~E_5~0); 22591#L918-1 [2019-12-07 17:29:33,121 INFO L796 eck$LassoCheckResult]: Loop: 22591#L918-1 assume !false; 22592#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 22758#L564 assume !false; 22881#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22815#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22730#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22814#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22777#L489 assume !(0 != eval_~tmp~0); 22779#L579 start_simulation_~kernel_st~0 := 2; 22871#L397-1 start_simulation_~kernel_st~0 := 3; 22765#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22724#L589-4 assume !(0 == ~T1_E~0); 22725#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22775#L599-3 assume !(0 == ~T3_E~0); 22776#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22660#L609-3 assume !(0 == ~T5_E~0); 22661#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22907#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22908#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22809#L629-3 assume !(0 == ~E_3~0); 22810#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22880#L639-3 assume !(0 == ~E_5~0); 22763#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22764#L282-21 assume !(1 == ~m_pc~0); 23123#L282-23 is_master_triggered_~__retres1~0 := 0; 23020#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23021#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23027#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23028#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22574#L301-21 assume !(1 == ~t1_pc~0); 22572#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 22573#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22615#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22618#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22579#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22580#L320-21 assume !(1 == ~t2_pc~0); 22804#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 22805#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22834#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22840#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22841#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22849#L339-21 assume 1 == ~t3_pc~0; 22948#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22949#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22946#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22947#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22990#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22991#L358-21 assume !(1 == ~t4_pc~0); 23090#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 22720#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22721#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23049#L765-21 assume !(0 != activate_threads_~tmp___3~0); 23096#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22678#L377-21 assume !(1 == ~t5_pc~0); 22606#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 22685#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22600#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22601#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22886#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 22887#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22806#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22807#L667-3 assume !(1 == ~T3_E~0); 22878#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22755#L677-3 assume !(1 == ~T5_E~0); 22756#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22554#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22555#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22687#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22688#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22920#L707-3 assume !(1 == ~E_5~0); 22921#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22784#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22733#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22816#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 22817#L937 assume !(0 == start_simulation_~tmp~3); 22824#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22789#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22739#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22785#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 22786#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23006#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 23013#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 22892#L950 assume !(0 != start_simulation_~tmp___0~1); 22591#L918-1 [2019-12-07 17:29:33,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,121 INFO L82 PathProgramCache]: Analyzing trace with hash 1439842751, now seen corresponding path program 1 times [2019-12-07 17:29:33,121 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,122 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232024859] [2019-12-07 17:29:33,122 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,158 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232024859] [2019-12-07 17:29:33,158 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,158 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:29:33,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824416076] [2019-12-07 17:29:33,159 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:33,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,159 INFO L82 PathProgramCache]: Analyzing trace with hash 672057101, now seen corresponding path program 1 times [2019-12-07 17:29:33,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428245932] [2019-12-07 17:29:33,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,179 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428245932] [2019-12-07 17:29:33,179 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,179 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:29:33,179 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256779904] [2019-12-07 17:29:33,180 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:33,180 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:33,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:29:33,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:29:33,180 INFO L87 Difference]: Start difference. First operand 3088 states and 4426 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2019-12-07 17:29:33,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:33,369 INFO L93 Difference]: Finished difference Result 8387 states and 11953 transitions. [2019-12-07 17:29:33,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:29:33,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8387 states and 11953 transitions. [2019-12-07 17:29:33,395 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8164 [2019-12-07 17:29:33,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8387 states to 8387 states and 11953 transitions. [2019-12-07 17:29:33,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8387 [2019-12-07 17:29:33,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8387 [2019-12-07 17:29:33,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8387 states and 11953 transitions. [2019-12-07 17:29:33,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:33,443 INFO L688 BuchiCegarLoop]: Abstraction has 8387 states and 11953 transitions. [2019-12-07 17:29:33,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8387 states and 11953 transitions. [2019-12-07 17:29:33,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8387 to 3247. [2019-12-07 17:29:33,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3247 states. [2019-12-07 17:29:33,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3247 states to 3247 states and 4585 transitions. [2019-12-07 17:29:33,492 INFO L711 BuchiCegarLoop]: Abstraction has 3247 states and 4585 transitions. [2019-12-07 17:29:33,492 INFO L591 BuchiCegarLoop]: Abstraction has 3247 states and 4585 transitions. [2019-12-07 17:29:33,492 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 17:29:33,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3247 states and 4585 transitions. [2019-12-07 17:29:33,498 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3148 [2019-12-07 17:29:33,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:33,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:33,499 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,499 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,499 INFO L794 eck$LassoCheckResult]: Stem: 34540#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 34487#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34488#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34398#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 34399#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34317#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34318#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34400#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34233#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34234#L429-1 assume !(0 == ~M_E~0); 34258#L589-1 assume !(0 == ~T1_E~0); 34259#L594-1 assume !(0 == ~T2_E~0); 34046#L599-1 assume !(0 == ~T3_E~0); 34047#L604-1 assume !(0 == ~T4_E~0); 34187#L609-1 assume !(0 == ~T5_E~0); 34188#L614-1 assume !(0 == ~E_M~0); 34459#L619-1 assume !(0 == ~E_1~0); 34460#L624-1 assume !(0 == ~E_2~0); 34331#L629-1 assume !(0 == ~E_3~0); 34332#L634-1 assume !(0 == ~E_4~0); 34406#L639-1 assume !(0 == ~E_5~0); 34248#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34249#L282 assume !(1 == ~m_pc~0); 34571#L282-2 is_master_triggered_~__retres1~0 := 0; 34572#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34573#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34627#L733 assume !(0 != activate_threads_~tmp~1); 34628#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34168#L301 assume !(1 == ~t1_pc~0); 34161#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 34127#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34128#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34195#L741 assume !(0 != activate_threads_~tmp___0~0); 34176#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34177#L320 assume !(1 == ~t2_pc~0); 34385#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 34386#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34319#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34320#L749 assume !(0 != activate_threads_~tmp___1~0); 34537#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34533#L339 assume !(1 == ~t3_pc~0); 34490#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 34491#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34520#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34521#L757 assume !(0 != activate_threads_~tmp___2~0); 34639#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34241#L358 assume !(1 == ~t4_pc~0); 34197#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 34198#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34238#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34267#L765 assume !(0 != activate_threads_~tmp___3~0); 34268#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34269#L377 assume !(1 == ~t5_pc~0); 34173#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 34437#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34170#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34171#L773 assume !(0 != activate_threads_~tmp___4~0); 34451#L773-2 assume !(1 == ~M_E~0); 34452#L657-1 assume !(1 == ~T1_E~0); 34352#L662-1 assume !(1 == ~T2_E~0); 34353#L667-1 assume !(1 == ~T3_E~0); 34538#L672-1 assume !(1 == ~T4_E~0); 34246#L677-1 assume !(1 == ~T5_E~0); 34247#L682-1 assume !(1 == ~E_M~0); 34037#L687-1 assume !(1 == ~E_1~0); 34038#L692-1 assume !(1 == ~E_2~0); 34178#L697-1 assume !(1 == ~E_3~0); 34179#L702-1 assume !(1 == ~E_4~0); 34453#L707-1 assume !(1 == ~E_5~0); 34454#L918-1 [2019-12-07 17:29:33,499 INFO L796 eck$LassoCheckResult]: Loop: 34454#L918-1 assume !false; 35334#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 35332#L564 assume !false; 35330#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35316#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35314#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35312#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 35309#L489 assume !(0 != eval_~tmp~0); 35310#L579 start_simulation_~kernel_st~0 := 2; 35614#L397-1 start_simulation_~kernel_st~0 := 3; 35612#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35610#L589-4 assume !(0 == ~T1_E~0); 35608#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35606#L599-3 assume !(0 == ~T3_E~0); 35603#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35601#L609-3 assume !(0 == ~T5_E~0); 35599#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35597#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35595#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35594#L629-3 assume !(0 == ~E_3~0); 35590#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35588#L639-3 assume !(0 == ~E_5~0); 35587#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35586#L282-21 assume !(1 == ~m_pc~0); 35585#L282-23 is_master_triggered_~__retres1~0 := 0; 35584#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35583#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 35582#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35581#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35580#L301-21 assume 1 == ~t1_pc~0; 35578#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35576#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35574#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35572#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35571#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35570#L320-21 assume !(1 == ~t2_pc~0); 35569#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 35568#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35567#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35566#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35565#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35564#L339-21 assume !(1 == ~t3_pc~0); 35562#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 35561#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35560#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35559#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35558#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35557#L358-21 assume !(1 == ~t4_pc~0); 35541#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 35539#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35537#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35534#L765-21 assume !(0 != activate_threads_~tmp___3~0); 35532#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35530#L377-21 assume !(1 == ~t5_pc~0); 35527#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 35525#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35523#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35520#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35518#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 35516#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35514#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35512#L667-3 assume !(1 == ~T3_E~0); 35510#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35507#L677-3 assume !(1 == ~T5_E~0); 35505#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35503#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35501#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35499#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35498#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35497#L707-3 assume !(1 == ~E_5~0); 35496#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35492#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35486#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35484#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 35480#L937 assume !(0 == start_simulation_~tmp~3); 35477#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35470#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35463#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35461#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 35460#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35459#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 35443#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 35441#L950 assume !(0 != start_simulation_~tmp___0~1); 34454#L918-1 [2019-12-07 17:29:33,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,499 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2019-12-07 17:29:33,499 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,499 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753204715] [2019-12-07 17:29:33,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:33,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:33,531 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:33,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,531 INFO L82 PathProgramCache]: Analyzing trace with hash -1586258547, now seen corresponding path program 1 times [2019-12-07 17:29:33,531 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421946405] [2019-12-07 17:29:33,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421946405] [2019-12-07 17:29:33,551 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:29:33,552 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510770400] [2019-12-07 17:29:33,552 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:33,552 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:33,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:29:33,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:29:33,552 INFO L87 Difference]: Start difference. First operand 3247 states and 4585 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2019-12-07 17:29:33,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:33,630 INFO L93 Difference]: Finished difference Result 5807 states and 8093 transitions. [2019-12-07 17:29:33,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:29:33,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5807 states and 8093 transitions. [2019-12-07 17:29:33,650 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2019-12-07 17:29:33,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5807 states to 5807 states and 8093 transitions. [2019-12-07 17:29:33,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5807 [2019-12-07 17:29:33,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5807 [2019-12-07 17:29:33,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5807 states and 8093 transitions. [2019-12-07 17:29:33,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:33,682 INFO L688 BuchiCegarLoop]: Abstraction has 5807 states and 8093 transitions. [2019-12-07 17:29:33,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5807 states and 8093 transitions. [2019-12-07 17:29:33,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5807 to 3271. [2019-12-07 17:29:33,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3271 states. [2019-12-07 17:29:33,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3271 states to 3271 states and 4609 transitions. [2019-12-07 17:29:33,729 INFO L711 BuchiCegarLoop]: Abstraction has 3271 states and 4609 transitions. [2019-12-07 17:29:33,729 INFO L591 BuchiCegarLoop]: Abstraction has 3271 states and 4609 transitions. [2019-12-07 17:29:33,729 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 17:29:33,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3271 states and 4609 transitions. [2019-12-07 17:29:33,734 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3172 [2019-12-07 17:29:33,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:33,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:33,735 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,735 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:33,735 INFO L794 eck$LassoCheckResult]: Stem: 43588#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43536#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43537#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43439#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 43440#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43359#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43360#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43443#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43300#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43301#L429-1 assume !(0 == ~M_E~0); 43325#L589-1 assume !(0 == ~T1_E~0); 43326#L594-1 assume !(0 == ~T2_E~0); 43116#L599-1 assume !(0 == ~T3_E~0); 43117#L604-1 assume !(0 == ~T4_E~0); 43254#L609-1 assume !(0 == ~T5_E~0); 43255#L614-1 assume !(0 == ~E_M~0); 43504#L619-1 assume !(0 == ~E_1~0); 43505#L624-1 assume !(0 == ~E_2~0); 43373#L629-1 assume !(0 == ~E_3~0); 43374#L634-1 assume !(0 == ~E_4~0); 43449#L639-1 assume !(0 == ~E_5~0); 43315#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43316#L282 assume !(1 == ~m_pc~0); 43622#L282-2 is_master_triggered_~__retres1~0 := 0; 43625#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43626#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 43677#L733 assume !(0 != activate_threads_~tmp~1); 43678#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43235#L301 assume !(1 == ~t1_pc~0); 43227#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 43228#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43342#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43263#L741 assume !(0 != activate_threads_~tmp___0~0); 43243#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43244#L320 assume !(1 == ~t2_pc~0); 43428#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 43429#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43361#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43362#L749 assume !(0 != activate_threads_~tmp___1~0); 43585#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43580#L339 assume !(1 == ~t3_pc~0); 43539#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 43540#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43569#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43570#L757 assume !(0 != activate_threads_~tmp___2~0); 43697#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43308#L358 assume !(1 == ~t4_pc~0); 43264#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 43265#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43307#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43333#L765 assume !(0 != activate_threads_~tmp___3~0); 43334#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43335#L377 assume !(1 == ~t5_pc~0); 43241#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 43485#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43237#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43238#L773 assume !(0 != activate_threads_~tmp___4~0); 43497#L773-2 assume !(1 == ~M_E~0); 43498#L657-1 assume !(1 == ~T1_E~0); 43393#L662-1 assume !(1 == ~T2_E~0); 43394#L667-1 assume !(1 == ~T3_E~0); 43586#L672-1 assume !(1 == ~T4_E~0); 43313#L677-1 assume !(1 == ~T5_E~0); 43314#L682-1 assume !(1 == ~E_M~0); 43107#L687-1 assume !(1 == ~E_1~0); 43108#L692-1 assume !(1 == ~E_2~0); 43245#L697-1 assume !(1 == ~E_3~0); 43246#L702-1 assume !(1 == ~E_4~0); 43499#L707-1 assume !(1 == ~E_5~0); 43500#L918-1 [2019-12-07 17:29:33,736 INFO L796 eck$LassoCheckResult]: Loop: 43500#L918-1 assume !false; 45942#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 45452#L564 assume !false; 44899#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44888#L442 assume !(0 == ~m_st~0); 44889#L446 assume !(0 == ~t1_st~0); 44892#L450 assume !(0 == ~t2_st~0); 44893#L454 assume !(0 == ~t3_st~0); 44890#L458 assume !(0 == ~t4_st~0); 44891#L462 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 43459#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43460#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 44439#L489 assume !(0 != eval_~tmp~0); 44843#L579 start_simulation_~kernel_st~0 := 2; 44842#L397-1 start_simulation_~kernel_st~0 := 3; 44841#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 44840#L589-4 assume !(0 == ~T1_E~0); 44839#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44838#L599-3 assume !(0 == ~T3_E~0); 44837#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44836#L609-3 assume !(0 == ~T5_E~0); 44835#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44834#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44833#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44832#L629-3 assume !(0 == ~E_3~0); 44831#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44830#L639-3 assume !(0 == ~E_5~0); 43327#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43328#L282-21 assume !(1 == ~m_pc~0); 43717#L282-23 is_master_triggered_~__retres1~0 := 0; 45809#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45808#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 45807#L733-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45806#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43133#L301-21 assume !(1 == ~t1_pc~0); 43134#L301-23 is_transmit1_triggered_~__retres1~1 := 0; 46102#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46103#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43182#L741-21 assume !(0 != activate_threads_~tmp___0~0); 43139#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43140#L320-21 assume !(1 == ~t2_pc~0); 43392#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 46025#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46024#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 46023#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43422#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43423#L339-21 assume 1 == ~t3_pc~0; 43528#L340-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43529#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43526#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43527#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43571#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43572#L358-21 assume !(1 == ~t4_pc~0); 46015#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 46014#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46013#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 46012#L765-21 assume !(0 != activate_threads_~tmp___3~0); 46011#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46010#L377-21 assume !(1 == ~t5_pc~0); 46008#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 46007#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46006#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 46005#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 46004#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 46003#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46002#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46001#L667-3 assume !(1 == ~T3_E~0); 46000#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45999#L677-3 assume !(1 == ~T5_E~0); 45998#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45997#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45996#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45995#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45994#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45993#L707-3 assume !(1 == ~E_5~0); 45992#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 45990#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 45981#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45976#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 45973#L937 assume !(0 == start_simulation_~tmp~3); 45971#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 45968#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 45963#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45961#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 45959#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45957#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 45956#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 45950#L950 assume !(0 != start_simulation_~tmp___0~1); 43500#L918-1 [2019-12-07 17:29:33,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,736 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2019-12-07 17:29:33,736 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,736 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318507475] [2019-12-07 17:29:33,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:33,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:33,758 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:33,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:33,759 INFO L82 PathProgramCache]: Analyzing trace with hash -486807708, now seen corresponding path program 1 times [2019-12-07 17:29:33,759 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:33,759 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234343401] [2019-12-07 17:29:33,759 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:33,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:33,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:33,808 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234343401] [2019-12-07 17:29:33,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:33,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:29:33,809 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989761150] [2019-12-07 17:29:33,809 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:33,809 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:33,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:29:33,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:29:33,809 INFO L87 Difference]: Start difference. First operand 3271 states and 4609 transitions. cyclomatic complexity: 1346 Second operand 5 states. [2019-12-07 17:29:33,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:33,947 INFO L93 Difference]: Finished difference Result 6431 states and 8996 transitions. [2019-12-07 17:29:33,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:29:33,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6431 states and 8996 transitions. [2019-12-07 17:29:33,972 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6316 [2019-12-07 17:29:33,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6431 states to 6431 states and 8996 transitions. [2019-12-07 17:29:33,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6431 [2019-12-07 17:29:33,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6431 [2019-12-07 17:29:33,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6431 states and 8996 transitions. [2019-12-07 17:29:34,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:34,003 INFO L688 BuchiCegarLoop]: Abstraction has 6431 states and 8996 transitions. [2019-12-07 17:29:34,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6431 states and 8996 transitions. [2019-12-07 17:29:34,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6431 to 3355. [2019-12-07 17:29:34,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3355 states. [2019-12-07 17:29:34,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3355 states to 3355 states and 4668 transitions. [2019-12-07 17:29:34,050 INFO L711 BuchiCegarLoop]: Abstraction has 3355 states and 4668 transitions. [2019-12-07 17:29:34,051 INFO L591 BuchiCegarLoop]: Abstraction has 3355 states and 4668 transitions. [2019-12-07 17:29:34,051 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 17:29:34,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3355 states and 4668 transitions. [2019-12-07 17:29:34,057 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3256 [2019-12-07 17:29:34,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:34,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:34,058 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,058 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,059 INFO L794 eck$LassoCheckResult]: Stem: 53318#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53261#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53262#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53162#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 53163#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53080#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53081#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53165#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53016#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53017#L429-1 assume !(0 == ~M_E~0); 53041#L589-1 assume !(0 == ~T1_E~0); 53042#L594-1 assume !(0 == ~T2_E~0); 52831#L599-1 assume !(0 == ~T3_E~0); 52832#L604-1 assume !(0 == ~T4_E~0); 52968#L609-1 assume !(0 == ~T5_E~0); 52969#L614-1 assume !(0 == ~E_M~0); 53231#L619-1 assume !(0 == ~E_1~0); 53232#L624-1 assume !(0 == ~E_2~0); 53094#L629-1 assume !(0 == ~E_3~0); 53095#L634-1 assume !(0 == ~E_4~0); 53172#L639-1 assume !(0 == ~E_5~0); 53031#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53032#L282 assume !(1 == ~m_pc~0); 53355#L282-2 is_master_triggered_~__retres1~0 := 0; 53357#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53358#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 53416#L733 assume !(0 != activate_threads_~tmp~1); 53417#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52948#L301 assume !(1 == ~t1_pc~0); 52940#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 52941#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53057#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 52976#L741 assume !(0 != activate_threads_~tmp___0~0); 52956#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52957#L320 assume !(1 == ~t2_pc~0); 53148#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 53149#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53082#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53083#L749 assume !(0 != activate_threads_~tmp___1~0); 53315#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53309#L339 assume !(1 == ~t3_pc~0); 53264#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 53265#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53293#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53294#L757 assume !(0 != activate_threads_~tmp___2~0); 53432#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53024#L358 assume !(1 == ~t4_pc~0); 52977#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 52978#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53023#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53049#L765 assume !(0 != activate_threads_~tmp___3~0); 53050#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53051#L377 assume !(1 == ~t5_pc~0); 52954#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 53201#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52950#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 52951#L773 assume !(0 != activate_threads_~tmp___4~0); 53222#L773-2 assume !(1 == ~M_E~0); 53223#L657-1 assume !(1 == ~T1_E~0); 53118#L662-1 assume !(1 == ~T2_E~0); 53119#L667-1 assume !(1 == ~T3_E~0); 53316#L672-1 assume !(1 == ~T4_E~0); 53029#L677-1 assume !(1 == ~T5_E~0); 53030#L682-1 assume !(1 == ~E_M~0); 52822#L687-1 assume !(1 == ~E_1~0); 52823#L692-1 assume !(1 == ~E_2~0); 52958#L697-1 assume !(1 == ~E_3~0); 52959#L702-1 assume !(1 == ~E_4~0); 53226#L707-1 assume !(1 == ~E_5~0); 53227#L918-1 [2019-12-07 17:29:34,059 INFO L796 eck$LassoCheckResult]: Loop: 53227#L918-1 assume !false; 54761#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 54760#L564 assume !false; 54759#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54752#L442 assume !(0 == ~m_st~0); 54753#L446 assume !(0 == ~t1_st~0); 54756#L450 assume !(0 == ~t2_st~0); 54758#L454 assume !(0 == ~t3_st~0); 54754#L458 assume !(0 == ~t4_st~0); 54755#L462 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 54757#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54237#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 54238#L489 assume !(0 != eval_~tmp~0); 54954#L579 start_simulation_~kernel_st~0 := 2; 54953#L397-1 start_simulation_~kernel_st~0 := 3; 54952#L589-2 assume 0 == ~M_E~0;~M_E~0 := 1; 54951#L589-4 assume !(0 == ~T1_E~0); 54950#L594-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54949#L599-3 assume !(0 == ~T3_E~0); 54948#L604-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54947#L609-3 assume !(0 == ~T5_E~0); 54946#L614-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54945#L619-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54944#L624-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54943#L629-3 assume !(0 == ~E_3~0); 54942#L634-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54941#L639-3 assume !(0 == ~E_5~0); 54940#L644-3 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54939#L282-21 assume !(1 == ~m_pc~0); 54938#L282-23 is_master_triggered_~__retres1~0 := 0; 54937#L293-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54936#L294-7 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 54935#L733-21 assume !(0 != activate_threads_~tmp~1); 54933#L733-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 54931#L301-21 assume 1 == ~t1_pc~0; 54928#L302-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 54925#L312-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54922#L313-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 54919#L741-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 54917#L741-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 54914#L320-21 assume !(1 == ~t2_pc~0); 54911#L320-23 is_transmit2_triggered_~__retres1~2 := 0; 54908#L331-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54905#L332-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 54903#L749-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 54901#L749-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54899#L339-21 assume !(1 == ~t3_pc~0); 54896#L339-23 is_transmit3_triggered_~__retres1~3 := 0; 54894#L350-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54892#L351-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 54890#L757-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 54888#L757-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54884#L358-21 assume !(1 == ~t4_pc~0); 54881#L358-23 is_transmit4_triggered_~__retres1~4 := 0; 54878#L369-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54875#L370-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 54872#L765-21 assume !(0 != activate_threads_~tmp___3~0); 54869#L765-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54866#L377-21 assume !(1 == ~t5_pc~0); 54861#L377-23 is_transmit5_triggered_~__retres1~5 := 0; 54857#L388-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54853#L389-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 54849#L773-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 54845#L773-23 assume 1 == ~M_E~0;~M_E~0 := 2; 54842#L657-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54839#L662-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54836#L667-3 assume !(1 == ~T3_E~0); 54833#L672-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54830#L677-3 assume !(1 == ~T5_E~0); 54827#L682-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54824#L687-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54820#L692-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54817#L697-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54814#L702-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54811#L707-3 assume !(1 == ~E_5~0); 54808#L712-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54804#L442-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54797#L474-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54794#L475-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 54790#L937 assume !(0 == start_simulation_~tmp~3); 54788#L937-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54784#L442-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54778#L474-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54776#L475-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 54774#L892 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54772#L899 stop_simulation_#res := stop_simulation_~__retres2~0; 54770#L900 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 54766#L950 assume !(0 != start_simulation_~tmp___0~1); 53227#L918-1 [2019-12-07 17:29:34,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,059 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2019-12-07 17:29:34,059 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,059 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183241651] [2019-12-07 17:29:34,059 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,078 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,078 INFO L82 PathProgramCache]: Analyzing trace with hash 2071598948, now seen corresponding path program 1 times [2019-12-07 17:29:34,079 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,079 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284010145] [2019-12-07 17:29:34,079 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:34,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:34,100 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284010145] [2019-12-07 17:29:34,100 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:34,100 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:34,100 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598194332] [2019-12-07 17:29:34,100 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 17:29:34,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:34,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:34,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:34,101 INFO L87 Difference]: Start difference. First operand 3355 states and 4668 transitions. cyclomatic complexity: 1321 Second operand 3 states. [2019-12-07 17:29:34,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:34,142 INFO L93 Difference]: Finished difference Result 5757 states and 7894 transitions. [2019-12-07 17:29:34,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:34,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5757 states and 7894 transitions. [2019-12-07 17:29:34,157 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5640 [2019-12-07 17:29:34,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5757 states to 5757 states and 7894 transitions. [2019-12-07 17:29:34,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5757 [2019-12-07 17:29:34,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5757 [2019-12-07 17:29:34,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5757 states and 7894 transitions. [2019-12-07 17:29:34,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:34,174 INFO L688 BuchiCegarLoop]: Abstraction has 5757 states and 7894 transitions. [2019-12-07 17:29:34,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5757 states and 7894 transitions. [2019-12-07 17:29:34,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5757 to 5605. [2019-12-07 17:29:34,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5605 states. [2019-12-07 17:29:34,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5605 states to 5605 states and 7694 transitions. [2019-12-07 17:29:34,217 INFO L711 BuchiCegarLoop]: Abstraction has 5605 states and 7694 transitions. [2019-12-07 17:29:34,217 INFO L591 BuchiCegarLoop]: Abstraction has 5605 states and 7694 transitions. [2019-12-07 17:29:34,217 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 17:29:34,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5605 states and 7694 transitions. [2019-12-07 17:29:34,227 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5488 [2019-12-07 17:29:34,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:34,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:34,227 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,228 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,228 INFO L794 eck$LassoCheckResult]: Stem: 62424#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 62371#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 62372#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62277#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 62278#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62195#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62196#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62280#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62133#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62134#L429-1 assume !(0 == ~M_E~0); 62159#L589-1 assume !(0 == ~T1_E~0); 62160#L594-1 assume !(0 == ~T2_E~0); 61949#L599-1 assume !(0 == ~T3_E~0); 61950#L604-1 assume !(0 == ~T4_E~0); 62086#L609-1 assume !(0 == ~T5_E~0); 62087#L614-1 assume !(0 == ~E_M~0); 62340#L619-1 assume !(0 == ~E_1~0); 62341#L624-1 assume !(0 == ~E_2~0); 62209#L629-1 assume !(0 == ~E_3~0); 62210#L634-1 assume !(0 == ~E_4~0); 62285#L639-1 assume !(0 == ~E_5~0); 62149#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62150#L282 assume !(1 == ~m_pc~0); 62454#L282-2 is_master_triggered_~__retres1~0 := 0; 62457#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62458#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 62500#L733 assume !(0 != activate_threads_~tmp~1); 62501#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62067#L301 assume !(1 == ~t1_pc~0); 62058#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 62059#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62178#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62095#L741 assume !(0 != activate_threads_~tmp___0~0); 62075#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62076#L320 assume !(1 == ~t2_pc~0); 62264#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 62265#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62197#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62198#L749 assume !(0 != activate_threads_~tmp___1~0); 62421#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62415#L339 assume !(1 == ~t3_pc~0); 62374#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 62375#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62403#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62404#L757 assume !(0 != activate_threads_~tmp___2~0); 62514#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62141#L358 assume !(1 == ~t4_pc~0); 62096#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 62097#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62140#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62167#L765 assume !(0 != activate_threads_~tmp___3~0); 62168#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62169#L377 assume !(1 == ~t5_pc~0); 62073#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 62316#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62069#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62070#L773 assume !(0 != activate_threads_~tmp___4~0); 62331#L773-2 assume !(1 == ~M_E~0); 62332#L657-1 assume !(1 == ~T1_E~0); 62230#L662-1 assume !(1 == ~T2_E~0); 62231#L667-1 assume !(1 == ~T3_E~0); 62422#L672-1 assume !(1 == ~T4_E~0); 62147#L677-1 assume !(1 == ~T5_E~0); 62148#L682-1 assume !(1 == ~E_M~0); 61940#L687-1 assume !(1 == ~E_1~0); 61941#L692-1 assume !(1 == ~E_2~0); 62077#L697-1 assume !(1 == ~E_3~0); 62078#L702-1 assume !(1 == ~E_4~0); 62335#L707-1 assume !(1 == ~E_5~0); 62336#L918-1 assume !false; 64926#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 64921#L564 [2019-12-07 17:29:34,228 INFO L796 eck$LassoCheckResult]: Loop: 64921#L564 assume !false; 64916#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 64911#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 64905#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 64900#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 64896#L489 assume 0 != eval_~tmp~0; 64891#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 64886#L497 assume !(0 != eval_~tmp_ndt_1~0); 64887#L494 assume !(0 == ~t1_st~0); 65024#L508 assume !(0 == ~t2_st~0); 65017#L522 assume !(0 == ~t3_st~0); 64949#L536 assume !(0 == ~t4_st~0); 64930#L550 assume !(0 == ~t5_st~0); 64921#L564 [2019-12-07 17:29:34,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,228 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2019-12-07 17:29:34,228 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,228 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995881865] [2019-12-07 17:29:34,228 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,243 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,243 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 1 times [2019-12-07 17:29:34,243 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,244 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712520193] [2019-12-07 17:29:34,244 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,248 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,248 INFO L82 PathProgramCache]: Analyzing trace with hash 1743073375, now seen corresponding path program 1 times [2019-12-07 17:29:34,248 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,248 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018910696] [2019-12-07 17:29:34,248 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:34,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:34,268 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018910696] [2019-12-07 17:29:34,268 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:34,268 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:34,268 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673653535] [2019-12-07 17:29:34,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:34,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:34,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:34,320 INFO L87 Difference]: Start difference. First operand 5605 states and 7694 transitions. cyclomatic complexity: 2101 Second operand 3 states. [2019-12-07 17:29:34,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:34,382 INFO L93 Difference]: Finished difference Result 10453 states and 14246 transitions. [2019-12-07 17:29:34,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:34,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 14246 transitions. [2019-12-07 17:29:34,415 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10224 [2019-12-07 17:29:34,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 14246 transitions. [2019-12-07 17:29:34,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2019-12-07 17:29:34,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2019-12-07 17:29:34,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 14246 transitions. [2019-12-07 17:29:34,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:34,452 INFO L688 BuchiCegarLoop]: Abstraction has 10453 states and 14246 transitions. [2019-12-07 17:29:34,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 14246 transitions. [2019-12-07 17:29:34,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 9973. [2019-12-07 17:29:34,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9973 states. [2019-12-07 17:29:34,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9973 states to 9973 states and 13622 transitions. [2019-12-07 17:29:34,525 INFO L711 BuchiCegarLoop]: Abstraction has 9973 states and 13622 transitions. [2019-12-07 17:29:34,525 INFO L591 BuchiCegarLoop]: Abstraction has 9973 states and 13622 transitions. [2019-12-07 17:29:34,525 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 17:29:34,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9973 states and 13622 transitions. [2019-12-07 17:29:34,543 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2019-12-07 17:29:34,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:34,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:34,544 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,544 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,544 INFO L794 eck$LassoCheckResult]: Stem: 78514#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78450#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78451#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78345#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 78346#L404-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 78261#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78262#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78347#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78198#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78199#L429-1 assume !(0 == ~M_E~0); 78223#L589-1 assume !(0 == ~T1_E~0); 78224#L594-1 assume !(0 == ~T2_E~0); 78015#L599-1 assume !(0 == ~T3_E~0); 78016#L604-1 assume !(0 == ~T4_E~0); 78153#L609-1 assume !(0 == ~T5_E~0); 78154#L614-1 assume !(0 == ~E_M~0); 78414#L619-1 assume !(0 == ~E_1~0); 78415#L624-1 assume !(0 == ~E_2~0); 78276#L629-1 assume !(0 == ~E_3~0); 78277#L634-1 assume !(0 == ~E_4~0); 78355#L639-1 assume !(0 == ~E_5~0); 78213#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78214#L282 assume !(1 == ~m_pc~0); 78546#L282-2 is_master_triggered_~__retres1~0 := 0; 78547#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78548#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78599#L733 assume !(0 != activate_threads_~tmp~1); 78600#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78135#L301 assume !(1 == ~t1_pc~0); 78128#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 78095#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78096#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78161#L741 assume !(0 != activate_threads_~tmp___0~0); 78143#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78144#L320 assume !(1 == ~t2_pc~0); 78353#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 80561#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78264#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78265#L749 assume !(0 != activate_threads_~tmp___1~0); 80551#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 80547#L339 assume !(1 == ~t3_pc~0); 80545#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 80544#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 80543#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 80542#L757 assume !(0 != activate_threads_~tmp___2~0); 78614#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78615#L358 assume !(1 == ~t4_pc~0); 80535#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 80533#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78579#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78231#L765 assume !(0 != activate_threads_~tmp___3~0); 78232#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78233#L377 assume !(1 == ~t5_pc~0); 78140#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 78384#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78137#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78138#L773 assume !(0 != activate_threads_~tmp___4~0); 78406#L773-2 assume !(1 == ~M_E~0); 78407#L657-1 assume !(1 == ~T1_E~0); 78300#L662-1 assume !(1 == ~T2_E~0); 78301#L667-1 assume !(1 == ~T3_E~0); 78512#L672-1 assume !(1 == ~T4_E~0); 78211#L677-1 assume !(1 == ~T5_E~0); 78212#L682-1 assume !(1 == ~E_M~0); 78006#L687-1 assume !(1 == ~E_1~0); 78007#L692-1 assume !(1 == ~E_2~0); 78145#L697-1 assume !(1 == ~E_3~0); 78146#L702-1 assume !(1 == ~E_4~0); 78408#L707-1 assume !(1 == ~E_5~0); 78409#L918-1 assume !false; 80587#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 80585#L564 [2019-12-07 17:29:34,544 INFO L796 eck$LassoCheckResult]: Loop: 80585#L564 assume !false; 80583#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 80580#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 80578#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 80575#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 80573#L489 assume 0 != eval_~tmp~0; 80570#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 80567#L497 assume !(0 != eval_~tmp_ndt_1~0); 80568#L494 assume !(0 == ~t1_st~0); 81676#L508 assume !(0 == ~t2_st~0); 81669#L522 assume !(0 == ~t3_st~0); 81660#L536 assume !(0 == ~t4_st~0); 80591#L550 assume !(0 == ~t5_st~0); 80585#L564 [2019-12-07 17:29:34,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,545 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2019-12-07 17:29:34,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684097912] [2019-12-07 17:29:34,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:34,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:34,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684097912] [2019-12-07 17:29:34,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:34,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:34,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554519847] [2019-12-07 17:29:34,572 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 17:29:34,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,572 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 2 times [2019-12-07 17:29:34,572 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,572 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780651646] [2019-12-07 17:29:34,572 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,576 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,618 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:34,619 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:34,619 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:34,619 INFO L87 Difference]: Start difference. First operand 9973 states and 13622 transitions. cyclomatic complexity: 3661 Second operand 3 states. [2019-12-07 17:29:34,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:34,635 INFO L93 Difference]: Finished difference Result 9901 states and 13521 transitions. [2019-12-07 17:29:34,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:34,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9901 states and 13521 transitions. [2019-12-07 17:29:34,659 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2019-12-07 17:29:34,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9901 states to 9901 states and 13521 transitions. [2019-12-07 17:29:34,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9901 [2019-12-07 17:29:34,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9901 [2019-12-07 17:29:34,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9901 states and 13521 transitions. [2019-12-07 17:29:34,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:34,687 INFO L688 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2019-12-07 17:29:34,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9901 states and 13521 transitions. [2019-12-07 17:29:34,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9901 to 9901. [2019-12-07 17:29:34,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9901 states. [2019-12-07 17:29:34,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9901 states to 9901 states and 13521 transitions. [2019-12-07 17:29:34,758 INFO L711 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2019-12-07 17:29:34,758 INFO L591 BuchiCegarLoop]: Abstraction has 9901 states and 13521 transitions. [2019-12-07 17:29:34,759 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 17:29:34,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9901 states and 13521 transitions. [2019-12-07 17:29:34,777 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9744 [2019-12-07 17:29:34,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:34,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:34,778 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,778 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:34,778 INFO L794 eck$LassoCheckResult]: Stem: 98391#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 98332#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98333#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98228#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 98229#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98139#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98140#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98230#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98079#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98080#L429-1 assume !(0 == ~M_E~0); 98103#L589-1 assume !(0 == ~T1_E~0); 98104#L594-1 assume !(0 == ~T2_E~0); 97895#L599-1 assume !(0 == ~T3_E~0); 97896#L604-1 assume !(0 == ~T4_E~0); 98034#L609-1 assume !(0 == ~T5_E~0); 98035#L614-1 assume !(0 == ~E_M~0); 98293#L619-1 assume !(0 == ~E_1~0); 98294#L624-1 assume !(0 == ~E_2~0); 98154#L629-1 assume !(0 == ~E_3~0); 98155#L634-1 assume !(0 == ~E_4~0); 98236#L639-1 assume !(0 == ~E_5~0); 98093#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98094#L282 assume !(1 == ~m_pc~0); 98422#L282-2 is_master_triggered_~__retres1~0 := 0; 98423#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98424#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 98478#L733 assume !(0 != activate_threads_~tmp~1); 98479#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98016#L301 assume !(1 == ~t1_pc~0); 98007#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 98008#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98121#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98042#L741 assume !(0 != activate_threads_~tmp___0~0); 98024#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98025#L320 assume !(1 == ~t2_pc~0); 98208#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 98209#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98142#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98143#L749 assume !(0 != activate_threads_~tmp___1~0); 98388#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98381#L339 assume !(1 == ~t3_pc~0); 98335#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 98336#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98367#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98368#L757 assume !(0 != activate_threads_~tmp___2~0); 98497#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98086#L358 assume !(1 == ~t4_pc~0); 98044#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 98045#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98083#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98112#L765 assume !(0 != activate_threads_~tmp___3~0); 98113#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98114#L377 assume !(1 == ~t5_pc~0); 98021#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 98267#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98018#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 98019#L773 assume !(0 != activate_threads_~tmp___4~0); 98285#L773-2 assume !(1 == ~M_E~0); 98286#L657-1 assume !(1 == ~T1_E~0); 98177#L662-1 assume !(1 == ~T2_E~0); 98178#L667-1 assume !(1 == ~T3_E~0); 98389#L672-1 assume !(1 == ~T4_E~0); 98091#L677-1 assume !(1 == ~T5_E~0); 98092#L682-1 assume !(1 == ~E_M~0); 97886#L687-1 assume !(1 == ~E_1~0); 97887#L692-1 assume !(1 == ~E_2~0); 98026#L697-1 assume !(1 == ~E_3~0); 98027#L702-1 assume !(1 == ~E_4~0); 98287#L707-1 assume !(1 == ~E_5~0); 98288#L918-1 assume !false; 107665#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 107663#L564 [2019-12-07 17:29:34,778 INFO L796 eck$LassoCheckResult]: Loop: 107663#L564 assume !false; 107660#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 107659#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 107562#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 107561#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 106870#L489 assume 0 != eval_~tmp~0; 106871#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 98165#L497 assume !(0 != eval_~tmp_ndt_1~0); 98167#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 102644#L511 assume !(0 != eval_~tmp_ndt_2~0); 102642#L508 assume !(0 == ~t2_st~0); 102639#L522 assume !(0 == ~t3_st~0); 102634#L536 assume !(0 == ~t4_st~0); 102632#L550 assume !(0 == ~t5_st~0); 107663#L564 [2019-12-07 17:29:34,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2019-12-07 17:29:34,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33434849] [2019-12-07 17:29:34,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,794 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,794 INFO L82 PathProgramCache]: Analyzing trace with hash 706455497, now seen corresponding path program 1 times [2019-12-07 17:29:34,795 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,795 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101081176] [2019-12-07 17:29:34,795 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:34,799 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:34,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:34,800 INFO L82 PathProgramCache]: Analyzing trace with hash 1606943435, now seen corresponding path program 1 times [2019-12-07 17:29:34,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:34,800 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661949752] [2019-12-07 17:29:34,800 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:34,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:34,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:34,821 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [661949752] [2019-12-07 17:29:34,821 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:34,821 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:34,821 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308086274] [2019-12-07 17:29:34,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:34,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:34,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:34,881 INFO L87 Difference]: Start difference. First operand 9901 states and 13521 transitions. cyclomatic complexity: 3632 Second operand 3 states. [2019-12-07 17:29:34,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:34,936 INFO L93 Difference]: Finished difference Result 12963 states and 17611 transitions. [2019-12-07 17:29:34,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:34,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12963 states and 17611 transitions. [2019-12-07 17:29:34,979 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12782 [2019-12-07 17:29:35,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12963 states to 12963 states and 17611 transitions. [2019-12-07 17:29:35,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12963 [2019-12-07 17:29:35,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12963 [2019-12-07 17:29:35,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12963 states and 17611 transitions. [2019-12-07 17:29:35,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:35,022 INFO L688 BuchiCegarLoop]: Abstraction has 12963 states and 17611 transitions. [2019-12-07 17:29:35,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12963 states and 17611 transitions. [2019-12-07 17:29:35,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12963 to 12587. [2019-12-07 17:29:35,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12587 states. [2019-12-07 17:29:35,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12587 states to 12587 states and 17123 transitions. [2019-12-07 17:29:35,113 INFO L711 BuchiCegarLoop]: Abstraction has 12587 states and 17123 transitions. [2019-12-07 17:29:35,113 INFO L591 BuchiCegarLoop]: Abstraction has 12587 states and 17123 transitions. [2019-12-07 17:29:35,113 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 17:29:35,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12587 states and 17123 transitions. [2019-12-07 17:29:35,137 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12406 [2019-12-07 17:29:35,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:35,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:35,138 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:35,138 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:35,138 INFO L794 eck$LassoCheckResult]: Stem: 121264#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 121205#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 121206#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 121114#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 121115#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121025#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121026#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121116#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120956#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120957#L429-1 assume !(0 == ~M_E~0); 120981#L589-1 assume !(0 == ~T1_E~0); 120982#L594-1 assume !(0 == ~T2_E~0); 120767#L599-1 assume !(0 == ~T3_E~0); 120768#L604-1 assume !(0 == ~T4_E~0); 120910#L609-1 assume !(0 == ~T5_E~0); 120911#L614-1 assume !(0 == ~E_M~0); 121177#L619-1 assume !(0 == ~E_1~0); 121178#L624-1 assume !(0 == ~E_2~0); 121040#L629-1 assume !(0 == ~E_3~0); 121041#L634-1 assume !(0 == ~E_4~0); 121124#L639-1 assume !(0 == ~E_5~0); 120970#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120971#L282 assume !(1 == ~m_pc~0); 121304#L282-2 is_master_triggered_~__retres1~0 := 0; 121305#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121306#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 121363#L733 assume !(0 != activate_threads_~tmp~1); 121364#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 120892#L301 assume !(1 == ~t1_pc~0); 120883#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 120884#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121004#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 120918#L741 assume !(0 != activate_threads_~tmp___0~0); 120900#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120901#L320 assume !(1 == ~t2_pc~0); 121098#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 121099#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121028#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 121029#L749 assume !(0 != activate_threads_~tmp___1~0); 121260#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121256#L339 assume !(1 == ~t3_pc~0); 121208#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 121209#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121245#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121246#L757 assume !(0 != activate_threads_~tmp___2~0); 121382#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 120963#L358 assume !(1 == ~t4_pc~0); 120920#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 120921#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120960#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 120991#L765 assume !(0 != activate_threads_~tmp___3~0); 120992#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120993#L377 assume !(1 == ~t5_pc~0); 120897#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 121152#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 120894#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 120895#L773 assume !(0 != activate_threads_~tmp___4~0); 121170#L773-2 assume !(1 == ~M_E~0); 121171#L657-1 assume !(1 == ~T1_E~0); 121064#L662-1 assume !(1 == ~T2_E~0); 121065#L667-1 assume !(1 == ~T3_E~0); 121262#L672-1 assume !(1 == ~T4_E~0); 120968#L677-1 assume !(1 == ~T5_E~0); 120969#L682-1 assume !(1 == ~E_M~0); 120758#L687-1 assume !(1 == ~E_1~0); 120759#L692-1 assume !(1 == ~E_2~0); 120902#L697-1 assume !(1 == ~E_3~0); 120903#L702-1 assume !(1 == ~E_4~0); 121172#L707-1 assume !(1 == ~E_5~0); 121173#L918-1 assume !false; 123699#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 123696#L564 [2019-12-07 17:29:35,138 INFO L796 eck$LassoCheckResult]: Loop: 123696#L564 assume !false; 123697#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 123554#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 123555#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 123548#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 123549#L489 assume 0 != eval_~tmp~0; 123543#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 123540#L497 assume !(0 != eval_~tmp_ndt_1~0); 123538#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 123404#L511 assume !(0 != eval_~tmp_ndt_2~0); 123536#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 123956#L525 assume !(0 != eval_~tmp_ndt_3~0); 123957#L522 assume !(0 == ~t3_st~0); 124081#L536 assume !(0 == ~t4_st~0); 124078#L550 assume !(0 == ~t5_st~0); 123696#L564 [2019-12-07 17:29:35,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,138 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2019-12-07 17:29:35,139 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,139 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930756256] [2019-12-07 17:29:35,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,155 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:35,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,155 INFO L82 PathProgramCache]: Analyzing trace with hash 258069692, now seen corresponding path program 1 times [2019-12-07 17:29:35,155 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641830588] [2019-12-07 17:29:35,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,160 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:35,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,161 INFO L82 PathProgramCache]: Analyzing trace with hash -1891575302, now seen corresponding path program 1 times [2019-12-07 17:29:35,161 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,161 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504716290] [2019-12-07 17:29:35,161 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:35,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:35,182 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504716290] [2019-12-07 17:29:35,182 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:35,182 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:35,182 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722157549] [2019-12-07 17:29:35,249 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:35,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:35,249 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:35,249 INFO L87 Difference]: Start difference. First operand 12587 states and 17123 transitions. cyclomatic complexity: 4548 Second operand 3 states. [2019-12-07 17:29:35,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:35,328 INFO L93 Difference]: Finished difference Result 22997 states and 31169 transitions. [2019-12-07 17:29:35,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:35,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22997 states and 31169 transitions. [2019-12-07 17:29:35,393 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22712 [2019-12-07 17:29:35,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22997 states to 22997 states and 31169 transitions. [2019-12-07 17:29:35,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22997 [2019-12-07 17:29:35,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22997 [2019-12-07 17:29:35,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22997 states and 31169 transitions. [2019-12-07 17:29:35,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:35,498 INFO L688 BuchiCegarLoop]: Abstraction has 22997 states and 31169 transitions. [2019-12-07 17:29:35,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22997 states and 31169 transitions. [2019-12-07 17:29:35,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22997 to 22205. [2019-12-07 17:29:35,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22205 states. [2019-12-07 17:29:35,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22205 states to 22205 states and 30185 transitions. [2019-12-07 17:29:35,624 INFO L711 BuchiCegarLoop]: Abstraction has 22205 states and 30185 transitions. [2019-12-07 17:29:35,624 INFO L591 BuchiCegarLoop]: Abstraction has 22205 states and 30185 transitions. [2019-12-07 17:29:35,624 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 17:29:35,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22205 states and 30185 transitions. [2019-12-07 17:29:35,664 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21920 [2019-12-07 17:29:35,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:35,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:35,665 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:35,665 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:35,665 INFO L794 eck$LassoCheckResult]: Stem: 156876#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 156804#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 156805#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 156710#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 156711#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156613#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156614#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156712#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 156547#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156548#L429-1 assume !(0 == ~M_E~0); 156571#L589-1 assume !(0 == ~T1_E~0); 156572#L594-1 assume !(0 == ~T2_E~0); 156359#L599-1 assume !(0 == ~T3_E~0); 156360#L604-1 assume !(0 == ~T4_E~0); 156499#L609-1 assume !(0 == ~T5_E~0); 156500#L614-1 assume !(0 == ~E_M~0); 156777#L619-1 assume !(0 == ~E_1~0); 156778#L624-1 assume !(0 == ~E_2~0); 156628#L629-1 assume !(0 == ~E_3~0); 156629#L634-1 assume !(0 == ~E_4~0); 156719#L639-1 assume !(0 == ~E_5~0); 156561#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156562#L282 assume !(1 == ~m_pc~0); 156919#L282-2 is_master_triggered_~__retres1~0 := 0; 156920#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156921#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 156980#L733 assume !(0 != activate_threads_~tmp~1); 156981#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156481#L301 assume !(1 == ~t1_pc~0); 156472#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 156473#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156593#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 156508#L741 assume !(0 != activate_threads_~tmp___0~0); 156489#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156490#L320 assume !(1 == ~t2_pc~0); 156691#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 156692#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156616#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156617#L749 assume !(0 != activate_threads_~tmp___1~0); 156873#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156864#L339 assume !(1 == ~t3_pc~0); 156807#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 156808#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156843#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156844#L757 assume !(0 != activate_threads_~tmp___2~0); 156997#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156554#L358 assume !(1 == ~t4_pc~0); 156511#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 156512#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156551#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 156580#L765 assume !(0 != activate_threads_~tmp___3~0); 156581#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156582#L377 assume !(1 == ~t5_pc~0); 156486#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 156750#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156483#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 156484#L773 assume !(0 != activate_threads_~tmp___4~0); 156770#L773-2 assume !(1 == ~M_E~0); 156771#L657-1 assume !(1 == ~T1_E~0); 156656#L662-1 assume !(1 == ~T2_E~0); 156657#L667-1 assume !(1 == ~T3_E~0); 156874#L672-1 assume !(1 == ~T4_E~0); 156559#L677-1 assume !(1 == ~T5_E~0); 156560#L682-1 assume !(1 == ~E_M~0); 156350#L687-1 assume !(1 == ~E_1~0); 156351#L692-1 assume !(1 == ~E_2~0); 156491#L697-1 assume !(1 == ~E_3~0); 156492#L702-1 assume !(1 == ~E_4~0); 156772#L707-1 assume !(1 == ~E_5~0); 156773#L918-1 assume !false; 159585#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 159583#L564 [2019-12-07 17:29:35,666 INFO L796 eck$LassoCheckResult]: Loop: 159583#L564 assume !false; 159581#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 159578#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 159576#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 159573#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 159571#L489 assume 0 != eval_~tmp~0; 159568#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 159565#L497 assume !(0 != eval_~tmp_ndt_1~0); 159563#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 159459#L511 assume !(0 != eval_~tmp_ndt_2~0); 159562#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 159598#L525 assume !(0 != eval_~tmp_ndt_3~0); 159596#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 159217#L539 assume !(0 != eval_~tmp_ndt_4~0); 159593#L536 assume !(0 == ~t4_st~0); 159589#L550 assume !(0 == ~t5_st~0); 159583#L564 [2019-12-07 17:29:35,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,666 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2019-12-07 17:29:35,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062720750] [2019-12-07 17:29:35,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,682 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:35,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,683 INFO L82 PathProgramCache]: Analyzing trace with hash -595166546, now seen corresponding path program 1 times [2019-12-07 17:29:35,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953250850] [2019-12-07 17:29:35,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:35,688 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:35,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:35,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1485315376, now seen corresponding path program 1 times [2019-12-07 17:29:35,688 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:35,688 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929493086] [2019-12-07 17:29:35,688 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:35,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:35,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:35,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929493086] [2019-12-07 17:29:35,706 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:35,707 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:29:35,707 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060675638] [2019-12-07 17:29:35,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:35,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:35,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:35,779 INFO L87 Difference]: Start difference. First operand 22205 states and 30185 transitions. cyclomatic complexity: 7992 Second operand 3 states. [2019-12-07 17:29:35,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:35,873 INFO L93 Difference]: Finished difference Result 29527 states and 40003 transitions. [2019-12-07 17:29:35,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:35,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29527 states and 40003 transitions. [2019-12-07 17:29:35,961 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 29186 [2019-12-07 17:29:36,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29527 states to 29527 states and 40003 transitions. [2019-12-07 17:29:36,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29527 [2019-12-07 17:29:36,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29527 [2019-12-07 17:29:36,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29527 states and 40003 transitions. [2019-12-07 17:29:36,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:36,036 INFO L688 BuchiCegarLoop]: Abstraction has 29527 states and 40003 transitions. [2019-12-07 17:29:36,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29527 states and 40003 transitions. [2019-12-07 17:29:36,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29527 to 29047. [2019-12-07 17:29:36,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29047 states. [2019-12-07 17:29:36,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29047 states to 29047 states and 39379 transitions. [2019-12-07 17:29:36,302 INFO L711 BuchiCegarLoop]: Abstraction has 29047 states and 39379 transitions. [2019-12-07 17:29:36,302 INFO L591 BuchiCegarLoop]: Abstraction has 29047 states and 39379 transitions. [2019-12-07 17:29:36,302 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 17:29:36,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29047 states and 39379 transitions. [2019-12-07 17:29:36,343 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28706 [2019-12-07 17:29:36,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:36,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:36,343 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:36,344 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:36,344 INFO L794 eck$LassoCheckResult]: Stem: 208622#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 208551#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 208552#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 208449#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 208450#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208361#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 208362#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 208452#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 208287#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 208288#L429-1 assume !(0 == ~M_E~0); 208311#L589-1 assume !(0 == ~T1_E~0); 208312#L594-1 assume !(0 == ~T2_E~0); 208099#L599-1 assume !(0 == ~T3_E~0); 208100#L604-1 assume !(0 == ~T4_E~0); 208239#L609-1 assume !(0 == ~T5_E~0); 208240#L614-1 assume !(0 == ~E_M~0); 208518#L619-1 assume !(0 == ~E_1~0); 208519#L624-1 assume !(0 == ~E_2~0); 208375#L629-1 assume !(0 == ~E_3~0); 208376#L634-1 assume !(0 == ~E_4~0); 208458#L639-1 assume !(0 == ~E_5~0); 208301#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 208302#L282 assume !(1 == ~m_pc~0); 208665#L282-2 is_master_triggered_~__retres1~0 := 0; 208668#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 208669#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 208729#L733 assume !(0 != activate_threads_~tmp~1); 208730#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 208221#L301 assume !(1 == ~t1_pc~0); 208213#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 208182#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 208183#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 208250#L741 assume !(0 != activate_threads_~tmp___0~0); 208229#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 208230#L320 assume !(1 == ~t2_pc~0); 208436#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 208437#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208363#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 208364#L749 assume !(0 != activate_threads_~tmp___1~0); 208618#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 208609#L339 assume !(1 == ~t3_pc~0); 208554#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 208555#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 208590#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 208591#L757 assume !(0 != activate_threads_~tmp___2~0); 208751#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 208294#L358 assume !(1 == ~t4_pc~0); 208251#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 208252#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 208293#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 208320#L765 assume !(0 != activate_threads_~tmp___3~0); 208321#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 208322#L377 assume !(1 == ~t5_pc~0); 208227#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 208494#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 208223#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 208224#L773 assume !(0 != activate_threads_~tmp___4~0); 208510#L773-2 assume !(1 == ~M_E~0); 208511#L657-1 assume !(1 == ~T1_E~0); 208400#L662-1 assume !(1 == ~T2_E~0); 208401#L667-1 assume !(1 == ~T3_E~0); 208619#L672-1 assume !(1 == ~T4_E~0); 208299#L677-1 assume !(1 == ~T5_E~0); 208300#L682-1 assume !(1 == ~E_M~0); 208090#L687-1 assume !(1 == ~E_1~0); 208091#L692-1 assume !(1 == ~E_2~0); 208231#L697-1 assume !(1 == ~E_3~0); 208232#L702-1 assume !(1 == ~E_4~0); 208512#L707-1 assume !(1 == ~E_5~0); 208513#L918-1 assume !false; 220502#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 220501#L564 [2019-12-07 17:29:36,344 INFO L796 eck$LassoCheckResult]: Loop: 220501#L564 assume !false; 220499#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 220497#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 220495#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 220493#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 220491#L489 assume 0 != eval_~tmp~0; 220484#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 220479#L497 assume !(0 != eval_~tmp_ndt_1~0); 220480#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 221489#L511 assume !(0 != eval_~tmp_ndt_2~0); 221484#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 221478#L525 assume !(0 != eval_~tmp_ndt_3~0); 220542#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 220536#L539 assume !(0 != eval_~tmp_ndt_4~0); 220531#L536 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 220523#L553 assume !(0 != eval_~tmp_ndt_5~0); 220506#L550 assume !(0 == ~t5_st~0); 220501#L564 [2019-12-07 17:29:36,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:36,344 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2019-12-07 17:29:36,344 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:36,344 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407190592] [2019-12-07 17:29:36,344 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:36,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:36,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:36,359 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:36,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:36,359 INFO L82 PathProgramCache]: Analyzing trace with hash -1270466089, now seen corresponding path program 1 times [2019-12-07 17:29:36,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:36,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40850640] [2019-12-07 17:29:36,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:36,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:36,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:36,363 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:36,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:36,364 INFO L82 PathProgramCache]: Analyzing trace with hash -1200035947, now seen corresponding path program 1 times [2019-12-07 17:29:36,364 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:36,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490211594] [2019-12-07 17:29:36,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:36,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:36,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:29:36,384 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490211594] [2019-12-07 17:29:36,384 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:29:36,384 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:29:36,384 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879140624] [2019-12-07 17:29:36,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:36,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:29:36,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:29:36,461 INFO L87 Difference]: Start difference. First operand 29047 states and 39379 transitions. cyclomatic complexity: 10344 Second operand 3 states. [2019-12-07 17:29:36,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:36,569 INFO L93 Difference]: Finished difference Result 50341 states and 68101 transitions. [2019-12-07 17:29:36,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:29:36,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50341 states and 68101 transitions. [2019-12-07 17:29:36,715 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49736 [2019-12-07 17:29:36,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50341 states to 50341 states and 68101 transitions. [2019-12-07 17:29:36,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50341 [2019-12-07 17:29:36,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50341 [2019-12-07 17:29:36,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50341 states and 68101 transitions. [2019-12-07 17:29:36,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 17:29:36,851 INFO L688 BuchiCegarLoop]: Abstraction has 50341 states and 68101 transitions. [2019-12-07 17:29:36,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50341 states and 68101 transitions. [2019-12-07 17:29:37,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50341 to 49909. [2019-12-07 17:29:37,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49909 states. [2019-12-07 17:29:37,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49909 states to 49909 states and 67669 transitions. [2019-12-07 17:29:37,196 INFO L711 BuchiCegarLoop]: Abstraction has 49909 states and 67669 transitions. [2019-12-07 17:29:37,196 INFO L591 BuchiCegarLoop]: Abstraction has 49909 states and 67669 transitions. [2019-12-07 17:29:37,196 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 17:29:37,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49909 states and 67669 transitions. [2019-12-07 17:29:37,384 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49304 [2019-12-07 17:29:37,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 17:29:37,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 17:29:37,384 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:37,384 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:37,385 INFO L794 eck$LassoCheckResult]: Stem: 288014#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 287944#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 287945#L881 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 287845#L397 assume 1 == ~m_i~0;~m_st~0 := 0; 287846#L404-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 287752#L409-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 287753#L414-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 287848#L419-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 287678#L424-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 287679#L429-1 assume !(0 == ~M_E~0); 287703#L589-1 assume !(0 == ~T1_E~0); 287704#L594-1 assume !(0 == ~T2_E~0); 287495#L599-1 assume !(0 == ~T3_E~0); 287496#L604-1 assume !(0 == ~T4_E~0); 287631#L609-1 assume !(0 == ~T5_E~0); 287632#L614-1 assume !(0 == ~E_M~0); 287915#L619-1 assume !(0 == ~E_1~0); 287916#L624-1 assume !(0 == ~E_2~0); 287766#L629-1 assume !(0 == ~E_3~0); 287767#L634-1 assume !(0 == ~E_4~0); 287853#L639-1 assume !(0 == ~E_5~0); 287692#L644-1 havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 287693#L282 assume !(1 == ~m_pc~0); 288054#L282-2 is_master_triggered_~__retres1~0 := 0; 288057#L293 is_master_triggered_#res := is_master_triggered_~__retres1~0; 288058#L294 activate_threads_#t~ret8 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 288120#L733 assume !(0 != activate_threads_~tmp~1); 288121#L733-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 287613#L301 assume !(1 == ~t1_pc~0); 287605#L301-2 is_transmit1_triggered_~__retres1~1 := 0; 287574#L312 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 287575#L313 activate_threads_#t~ret9 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 287640#L741 assume !(0 != activate_threads_~tmp___0~0); 287621#L741-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 287622#L320 assume !(1 == ~t2_pc~0); 287831#L320-2 is_transmit2_triggered_~__retres1~2 := 0; 287832#L331 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 287754#L332 activate_threads_#t~ret10 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 287755#L749 assume !(0 != activate_threads_~tmp___1~0); 288010#L749-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 288005#L339 assume !(1 == ~t3_pc~0); 287947#L339-2 is_transmit3_triggered_~__retres1~3 := 0; 287948#L350 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 287984#L351 activate_threads_#t~ret11 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 287985#L757 assume !(0 != activate_threads_~tmp___2~0); 288141#L757-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 287685#L358 assume !(1 == ~t4_pc~0); 287641#L358-2 is_transmit4_triggered_~__retres1~4 := 0; 287642#L369 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 287684#L370 activate_threads_#t~ret12 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 287712#L765 assume !(0 != activate_threads_~tmp___3~0); 287713#L765-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 287714#L377 assume !(1 == ~t5_pc~0); 287619#L377-2 is_transmit5_triggered_~__retres1~5 := 0; 287888#L388 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 287615#L389 activate_threads_#t~ret13 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 287616#L773 assume !(0 != activate_threads_~tmp___4~0); 287907#L773-2 assume !(1 == ~M_E~0); 287908#L657-1 assume !(1 == ~T1_E~0); 287792#L662-1 assume !(1 == ~T2_E~0); 287793#L667-1 assume !(1 == ~T3_E~0); 288012#L672-1 assume !(1 == ~T4_E~0); 287690#L677-1 assume !(1 == ~T5_E~0); 287691#L682-1 assume !(1 == ~E_M~0); 287486#L687-1 assume !(1 == ~E_1~0); 287487#L692-1 assume !(1 == ~E_2~0); 287623#L697-1 assume !(1 == ~E_3~0); 287624#L702-1 assume !(1 == ~E_4~0); 287909#L707-1 assume !(1 == ~E_5~0); 287910#L918-1 assume !false; 297696#L919 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 297692#L564 [2019-12-07 17:29:37,385 INFO L796 eck$LassoCheckResult]: Loop: 297692#L564 assume !false; 297690#L485 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 297687#L442 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 297685#L474 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 297682#L475 eval_#t~ret1 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 297680#L489 assume 0 != eval_~tmp~0; 297677#L489-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 297674#L497 assume !(0 != eval_~tmp_ndt_1~0); 297672#L494 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 297626#L511 assume !(0 != eval_~tmp_ndt_2~0); 297670#L508 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 297710#L525 assume !(0 != eval_~tmp_ndt_3~0); 297708#L522 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 297542#L539 assume !(0 != eval_~tmp_ndt_4~0); 297704#L536 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 297701#L553 assume !(0 != eval_~tmp_ndt_5~0); 297699#L550 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 296789#L567 assume !(0 != eval_~tmp_ndt_6~0); 297692#L564 [2019-12-07 17:29:37,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:37,385 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2019-12-07 17:29:37,385 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:37,385 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486460746] [2019-12-07 17:29:37,385 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:37,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,399 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:37,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:37,399 INFO L82 PathProgramCache]: Analyzing trace with hash -729747053, now seen corresponding path program 1 times [2019-12-07 17:29:37,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:37,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566154037] [2019-12-07 17:29:37,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:37,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,403 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:37,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:37,403 INFO L82 PathProgramCache]: Analyzing trace with hash 1453587349, now seen corresponding path program 1 times [2019-12-07 17:29:37,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:37,403 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935977872] [2019-12-07 17:29:37,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:37,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:29:37,420 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:29:37,874 WARN L192 SmtUtils]: Spent 359.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 [2019-12-07 17:29:38,002 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 05:29:38 BoogieIcfgContainer [2019-12-07 17:29:38,002 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 17:29:38,002 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:29:38,002 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:29:38,003 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:29:38,003 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:29:31" (3/4) ... [2019-12-07 17:29:38,005 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 17:29:38,055 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_01d4fe96-1340-46e5-90d3-887cb0c06e8b/bin/uautomizer/witness.graphml [2019-12-07 17:29:38,055 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:29:38,056 INFO L168 Benchmark]: Toolchain (without parser) took 7583.11 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 473.4 MB). Free memory was 939.3 MB in the beginning and 879.9 MB in the end (delta: 59.4 MB). Peak memory consumption was 532.9 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,056 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:29:38,056 INFO L168 Benchmark]: CACSL2BoogieTranslator took 269.57 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.9 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -145.1 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,057 INFO L168 Benchmark]: Boogie Procedure Inliner took 45.03 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,057 INFO L168 Benchmark]: Boogie Preprocessor took 41.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,057 INFO L168 Benchmark]: RCFGBuilder took 686.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 951.0 MB in the end (delta: 117.3 MB). Peak memory consumption was 117.3 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,058 INFO L168 Benchmark]: BuchiAutomizer took 6484.53 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 378.5 MB). Free memory was 951.0 MB in the beginning and 895.1 MB in the end (delta: 55.9 MB). Peak memory consumption was 434.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,058 INFO L168 Benchmark]: Witness Printer took 52.45 ms. Allocated memory is still 1.5 GB. Free memory was 895.1 MB in the beginning and 879.9 MB in the end (delta: 15.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:29:38,060 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 269.57 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 94.9 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -145.1 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 45.03 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 41.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 686.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 951.0 MB in the end (delta: 117.3 MB). Peak memory consumption was 117.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 6484.53 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 378.5 MB). Free memory was 951.0 MB in the beginning and 895.1 MB in the end (delta: 55.9 MB). Peak memory consumption was 434.4 MB. Max. memory is 11.5 GB. * Witness Printer took 52.45 ms. Allocated memory is still 1.5 GB. Free memory was 895.1 MB in the beginning and 879.9 MB in the end (delta: 15.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 49909 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.4s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.4s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 21 MinimizatonAttempts, 13516 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.0s. Biggest automaton had 49909 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17094 SDtfs, 18523 SDslu, 14213 SDs, 0 SdLazy, 479 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 484]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c55dd28=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@723621c1=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5fd680d4=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5066db59=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3ac1c116=0, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@23d1ed86=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b24baef=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b0d813a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79bbc1d9=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@63a000cf=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@443552c=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6b7631d8=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b1a786f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77a29936=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d02e566=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 484]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L963] int __retres1 ; [L874] m_i = 1 [L875] t1_i = 1 [L876] t2_i = 1 [L877] t3_i = 1 [L878] t4_i = 1 [L879] t5_i = 1 [L904] int kernel_st ; [L905] int tmp ; [L906] int tmp___0 ; [L910] kernel_st = 0 [L404] COND TRUE m_i == 1 [L405] m_st = 0 [L409] COND TRUE t1_i == 1 [L410] t1_st = 0 [L414] COND TRUE t2_i == 1 [L415] t2_st = 0 [L419] COND TRUE t3_i == 1 [L420] t3_st = 0 [L424] COND TRUE t4_i == 1 [L425] t4_st = 0 [L429] COND TRUE t5_i == 1 [L430] t5_st = 0 [L589] COND FALSE !(M_E == 0) [L594] COND FALSE !(T1_E == 0) [L599] COND FALSE !(T2_E == 0) [L604] COND FALSE !(T3_E == 0) [L609] COND FALSE !(T4_E == 0) [L614] COND FALSE !(T5_E == 0) [L619] COND FALSE !(E_M == 0) [L624] COND FALSE !(E_1 == 0) [L629] COND FALSE !(E_2 == 0) [L634] COND FALSE !(E_3 == 0) [L639] COND FALSE !(E_4 == 0) [L644] COND FALSE !(E_5 == 0) [L722] int tmp ; [L723] int tmp___0 ; [L724] int tmp___1 ; [L725] int tmp___2 ; [L726] int tmp___3 ; [L727] int tmp___4 ; [L279] int __retres1 ; [L282] COND FALSE !(m_pc == 1) [L292] __retres1 = 0 [L294] return (__retres1); [L731] tmp = is_master_triggered() [L733] COND FALSE !(\read(tmp)) [L298] int __retres1 ; [L301] COND FALSE !(t1_pc == 1) [L311] __retres1 = 0 [L313] return (__retres1); [L739] tmp___0 = is_transmit1_triggered() [L741] COND FALSE !(\read(tmp___0)) [L317] int __retres1 ; [L320] COND FALSE !(t2_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L747] tmp___1 = is_transmit2_triggered() [L749] COND FALSE !(\read(tmp___1)) [L336] int __retres1 ; [L339] COND FALSE !(t3_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L755] tmp___2 = is_transmit3_triggered() [L757] COND FALSE !(\read(tmp___2)) [L355] int __retres1 ; [L358] COND FALSE !(t4_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L763] tmp___3 = is_transmit4_triggered() [L765] COND FALSE !(\read(tmp___3)) [L374] int __retres1 ; [L377] COND FALSE !(t5_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L771] tmp___4 = is_transmit5_triggered() [L773] COND FALSE !(\read(tmp___4)) [L657] COND FALSE !(M_E == 1) [L662] COND FALSE !(T1_E == 1) [L667] COND FALSE !(T2_E == 1) [L672] COND FALSE !(T3_E == 1) [L677] COND FALSE !(T4_E == 1) [L682] COND FALSE !(T5_E == 1) [L687] COND FALSE !(E_M == 1) [L692] COND FALSE !(E_1 == 1) [L697] COND FALSE !(E_2 == 1) [L702] COND FALSE !(E_3 == 1) [L707] COND FALSE !(E_4 == 1) [L712] COND FALSE !(E_5 == 1) [L918] COND TRUE 1 [L921] kernel_st = 1 [L480] int tmp ; Loop: [L484] COND TRUE 1 [L439] int __retres1 ; [L442] COND TRUE m_st == 0 [L443] __retres1 = 1 [L475] return (__retres1); [L487] tmp = exists_runnable_thread() [L489] COND TRUE \read(tmp) [L494] COND TRUE m_st == 0 [L495] int tmp_ndt_1; [L496] tmp_ndt_1 = __VERIFIER_nondet_int() [L497] COND FALSE !(\read(tmp_ndt_1)) [L508] COND TRUE t1_st == 0 [L509] int tmp_ndt_2; [L510] tmp_ndt_2 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_2)) [L522] COND TRUE t2_st == 0 [L523] int tmp_ndt_3; [L524] tmp_ndt_3 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_3)) [L536] COND TRUE t3_st == 0 [L537] int tmp_ndt_4; [L538] tmp_ndt_4 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_4)) [L550] COND TRUE t4_st == 0 [L551] int tmp_ndt_5; [L552] tmp_ndt_5 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_5)) [L564] COND TRUE t5_st == 0 [L565] int tmp_ndt_6; [L566] tmp_ndt_6 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...