./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 27d160802d278384ef6d8db395ef2d19702d5645 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:26:17,743 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:26:17,745 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:26:17,752 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:26:17,752 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:26:17,753 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:26:17,754 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:26:17,755 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:26:17,756 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:26:17,757 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:26:17,758 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:26:17,759 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:26:17,759 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:26:17,759 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:26:17,760 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:26:17,761 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:26:17,761 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:26:17,762 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:26:17,764 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:26:17,765 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:26:17,766 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:26:17,767 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:26:17,768 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:26:17,768 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:26:17,770 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:26:17,770 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:26:17,770 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:26:17,771 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:26:17,771 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:26:17,771 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:26:17,772 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:26:17,772 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:26:17,772 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:26:17,773 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:26:17,774 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:26:17,774 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:26:17,774 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:26:17,774 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:26:17,774 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:26:17,775 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:26:17,775 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:26:17,776 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 18:26:17,786 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:26:17,786 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:26:17,787 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:26:17,787 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:26:17,787 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:26:17,787 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 18:26:17,788 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 18:26:17,788 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:26:17,789 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 18:26:17,790 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:26:17,790 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 18:26:17,790 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:26:17,790 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:26:17,790 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 18:26:17,790 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:26:17,790 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:26:17,791 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:26:17,791 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 18:26:17,791 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 18:26:17,791 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 27d160802d278384ef6d8db395ef2d19702d5645 [2019-12-07 18:26:17,890 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:26:17,899 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:26:17,901 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:26:17,902 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:26:17,902 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:26:17,902 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2019-12-07 18:26:17,942 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/data/754d17cff/930e4809653b4ce7b66b8b1654df14c9/FLAG0debb7a3e [2019-12-07 18:26:18,346 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:26:18,346 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2019-12-07 18:26:18,354 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/data/754d17cff/930e4809653b4ce7b66b8b1654df14c9/FLAG0debb7a3e [2019-12-07 18:26:18,715 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/data/754d17cff/930e4809653b4ce7b66b8b1654df14c9 [2019-12-07 18:26:18,718 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:26:18,719 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:26:18,719 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:26:18,720 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:26:18,722 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:26:18,723 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:18,725 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11cefb15 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18, skipping insertion in model container [2019-12-07 18:26:18,726 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:18,732 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:26:18,762 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:26:18,932 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:26:18,936 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:26:18,969 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:26:18,983 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:26:18,983 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18 WrapperNode [2019-12-07 18:26:18,983 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:26:18,983 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:26:18,984 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:26:18,984 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:26:18,989 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:18,995 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,030 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:26:19,030 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:26:19,030 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:26:19,030 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:26:19,037 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,037 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,040 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,040 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,052 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,065 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... [2019-12-07 18:26:19,072 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:26:19,073 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:26:19,073 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:26:19,073 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:26:19,073 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 18:26:19,117 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:26:19,117 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:26:19,756 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:26:19,756 INFO L287 CfgBuilder]: Removed 198 assume(true) statements. [2019-12-07 18:26:19,757 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:26:19 BoogieIcfgContainer [2019-12-07 18:26:19,757 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:26:19,758 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 18:26:19,758 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 18:26:19,761 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 18:26:19,761 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:26:19,761 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 06:26:18" (1/3) ... [2019-12-07 18:26:19,762 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d1a6c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:26:19, skipping insertion in model container [2019-12-07 18:26:19,762 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:26:19,763 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:26:18" (2/3) ... [2019-12-07 18:26:19,763 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d1a6c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 06:26:19, skipping insertion in model container [2019-12-07 18:26:19,763 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 18:26:19,763 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:26:19" (3/3) ... [2019-12-07 18:26:19,764 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2019-12-07 18:26:19,799 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 18:26:19,799 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 18:26:19,799 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 18:26:19,800 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:26:19,800 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:26:19,800 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 18:26:19,800 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:26:19,800 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 18:26:19,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 538 states. [2019-12-07 18:26:19,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2019-12-07 18:26:19,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:19,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:19,863 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:19,864 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:19,864 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 18:26:19,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 538 states. [2019-12-07 18:26:19,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2019-12-07 18:26:19,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:19,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:19,876 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:19,876 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:19,882 INFO L794 eck$LassoCheckResult]: Stem: 341#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 279#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 187#L893true havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 160#L409true assume !(1 == ~m_i~0);~m_st~0 := 2; 454#L416-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L421-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 497#L426-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 161#L431-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 409#L436-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 191#L441-1true assume !(0 == ~M_E~0); 427#L601-1true assume !(0 == ~T1_E~0); 194#L606-1true assume !(0 == ~T2_E~0); 90#L611-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 361#L616-1true assume !(0 == ~T4_E~0); 8#L621-1true assume !(0 == ~T5_E~0); 305#L626-1true assume !(0 == ~E_M~0); 65#L631-1true assume !(0 == ~E_1~0); 460#L636-1true assume !(0 == ~E_2~0); 236#L641-1true assume !(0 == ~E_3~0); 538#L646-1true assume !(0 == ~E_4~0); 185#L651-1true assume 0 == ~E_5~0;~E_5~0 := 1; 438#L656-1true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 484#L294true assume 1 == ~m_pc~0; 317#L295true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 509#L305true is_master_triggered_#res := is_master_triggered_~__retres1~0; 323#L306true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 531#L745true assume !(0 != activate_threads_~tmp~1); 534#L745-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 125#L313true assume !(1 == ~t1_pc~0); 134#L313-2true is_transmit1_triggered_~__retres1~1 := 0; 123#L324true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85#L325true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16#L753true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19#L753-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166#L332true assume 1 == ~t2_pc~0; 215#L333true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 165#L343true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 214#L344true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 181#L761true assume !(0 != activate_threads_~tmp___1~0); 182#L761-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 300#L351true assume !(1 == ~t3_pc~0); 284#L351-2true is_transmit3_triggered_~__retres1~3 := 0; 299#L362true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 355#L363true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 309#L769true assume !(0 != activate_threads_~tmp___2~0); 310#L769-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 415#L370true assume 1 == ~t4_pc~0; 500#L371true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 412#L381true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 498#L382true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 434#L777true assume !(0 != activate_threads_~tmp___3~0); 435#L777-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58#L389true assume !(1 == ~t5_pc~0); 38#L389-2true is_transmit5_triggered_~__retres1~5 := 0; 56#L400true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 151#L401true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 69#L785true assume !(0 != activate_threads_~tmp___4~0); 71#L785-2true assume !(1 == ~M_E~0); 457#L669-1true assume !(1 == ~T1_E~0); 235#L674-1true assume !(1 == ~T2_E~0); 535#L679-1true assume !(1 == ~T3_E~0); 184#L684-1true assume !(1 == ~T4_E~0); 437#L689-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 331#L694-1true assume !(1 == ~E_M~0); 102#L699-1true assume !(1 == ~E_1~0); 372#L704-1true assume !(1 == ~E_2~0); 3#L709-1true assume !(1 == ~E_3~0); 301#L714-1true assume !(1 == ~E_4~0); 61#L719-1true assume !(1 == ~E_5~0); 107#L930-1true [2019-12-07 18:26:19,884 INFO L796 eck$LassoCheckResult]: Loop: 107#L930-1true assume !false; 439#L931true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 67#L576true assume !true; 540#L591true start_simulation_~kernel_st~0 := 2; 163#L409-1true start_simulation_~kernel_st~0 := 3; 429#L601-2true assume 0 == ~M_E~0;~M_E~0 := 1; 432#L601-4true assume !(0 == ~T1_E~0); 197#L606-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 95#L611-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 363#L616-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L621-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 307#L626-3true assume 0 == ~E_M~0;~E_M~0 := 1; 50#L631-3true assume 0 == ~E_1~0;~E_1~0 := 1; 451#L636-3true assume 0 == ~E_2~0;~E_2~0 := 1; 224#L641-3true assume !(0 == ~E_3~0); 524#L646-3true assume 0 == ~E_4~0;~E_4~0 := 1; 175#L651-3true assume 0 == ~E_5~0;~E_5~0 := 1; 428#L656-3true havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 452#L294-21true assume !(1 == ~m_pc~0); 449#L294-23true is_master_triggered_~__retres1~0 := 0; 495#L305-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 319#L306-7true activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 469#L745-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 472#L745-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88#L313-21true assume !(1 == ~t1_pc~0); 91#L313-23true is_transmit1_triggered_~__retres1~1 := 0; 116#L324-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 444#L325-7true activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 118#L753-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 122#L753-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 234#L332-21true assume 1 == ~t2_pc~0; 209#L333-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 266#L343-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208#L344-7true activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 246#L761-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 248#L761-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 371#L351-21true assume !(1 == ~t3_pc~0); 359#L351-23true is_transmit3_triggered_~__retres1~3 := 0; 272#L362-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 333#L363-7true activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 276#L769-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 278#L769-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 533#L370-21true assume !(1 == ~t4_pc~0); 537#L370-23true is_transmit4_triggered_~__retres1~4 := 0; 401#L381-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 488#L382-7true activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 387#L777-21true assume !(0 != activate_threads_~tmp___3~0); 389#L777-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18#L389-21true assume 1 == ~t5_pc~0; 146#L390-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 29#L400-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 143#L401-7true activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34#L785-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36#L785-23true assume 1 == ~M_E~0;~M_E~0 := 2; 463#L669-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 238#L674-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 523#L679-3true assume !(1 == ~T3_E~0); 173#L684-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 424#L689-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 193#L694-3true assume 1 == ~E_M~0;~E_M~0 := 2; 89#L699-3true assume 1 == ~E_1~0;~E_1~0 := 2; 360#L704-3true assume 1 == ~E_2~0;~E_2~0 := 2; 7#L709-3true assume 1 == ~E_3~0;~E_3~0 := 2; 303#L714-3true assume 1 == ~E_4~0;~E_4~0 := 2; 64#L719-3true assume !(1 == ~E_5~0); 459#L724-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 231#L454-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 180#L486-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 230#L487-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 255#L949true assume !(0 == start_simulation_~tmp~3); 239#L949-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 213#L454-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 159#L486-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 232#L487-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 186#L904true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 476#L911true stop_simulation_#res := stop_simulation_~__retres2~0; 311#L912true start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 23#L962true assume !(0 != start_simulation_~tmp___0~1); 107#L930-1true [2019-12-07 18:26:19,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:19,889 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2019-12-07 18:26:19,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:19,895 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128531131] [2019-12-07 18:26:19,895 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:19,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,012 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128531131] [2019-12-07 18:26:20,013 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,013 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,014 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271059104] [2019-12-07 18:26:20,018 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,018 INFO L82 PathProgramCache]: Analyzing trace with hash 821686751, now seen corresponding path program 1 times [2019-12-07 18:26:20,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645282142] [2019-12-07 18:26:20,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,040 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645282142] [2019-12-07 18:26:20,040 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,041 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:20,041 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465652895] [2019-12-07 18:26:20,042 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,043 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,055 INFO L87 Difference]: Start difference. First operand 538 states. Second operand 3 states. [2019-12-07 18:26:20,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,091 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2019-12-07 18:26:20,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2019-12-07 18:26:20,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2019-12-07 18:26:20,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2019-12-07 18:26:20,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,116 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2019-12-07 18:26:20,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2019-12-07 18:26:20,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2019-12-07 18:26:20,156 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2019-12-07 18:26:20,156 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2019-12-07 18:26:20,156 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 18:26:20,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2019-12-07 18:26:20,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,163 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,163 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,163 INFO L794 eck$LassoCheckResult]: Stem: 1530#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1436#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1339#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1295#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 1296#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1382#L421-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1383#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1297#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1298#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1346#L441-1 assume !(0 == ~M_E~0); 1347#L601-1 assume !(0 == ~T1_E~0); 1349#L606-1 assume !(0 == ~T2_E~0); 1243#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1244#L616-1 assume !(0 == ~T4_E~0); 1096#L621-1 assume !(0 == ~T5_E~0); 1097#L626-1 assume !(0 == ~E_M~0); 1192#L631-1 assume !(0 == ~E_1~0); 1193#L636-1 assume !(0 == ~E_2~0); 1404#L641-1 assume !(0 == ~E_3~0); 1405#L646-1 assume !(0 == ~E_4~0); 1335#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1336#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1602#L294 assume 1 == ~m_pc~0; 1487#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1488#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1502#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1503#L745 assume !(0 != activate_threads_~tmp~1); 1616#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1282#L313 assume !(1 == ~t1_pc~0); 1237#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 1236#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1233#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1111#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1112#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1116#L332 assume 1 == ~t2_pc~0; 1307#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1305#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1306#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1329#L761 assume !(0 != activate_threads_~tmp___1~0); 1330#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1331#L351 assume !(1 == ~t3_pc~0); 1442#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 1443#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1465#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1471#L769 assume !(0 != activate_threads_~tmp___2~0); 1472#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1473#L370 assume 1 == ~t4_pc~0; 1586#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1581#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1582#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1599#L777 assume !(0 != activate_threads_~tmp___3~0); 1600#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1182#L389 assume !(1 == ~t5_pc~0); 1148#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 1149#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1181#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1201#L785 assume !(0 != activate_threads_~tmp___4~0); 1202#L785-2 assume !(1 == ~M_E~0); 1203#L669-1 assume !(1 == ~T1_E~0); 1402#L674-1 assume !(1 == ~T2_E~0); 1403#L679-1 assume !(1 == ~T3_E~0); 1333#L684-1 assume !(1 == ~T4_E~0); 1334#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1522#L694-1 assume !(1 == ~E_M~0); 1265#L699-1 assume !(1 == ~E_1~0); 1266#L704-1 assume !(1 == ~E_2~0); 1085#L709-1 assume !(1 == ~E_3~0); 1086#L714-1 assume !(1 == ~E_4~0); 1186#L719-1 assume !(1 == ~E_5~0); 1125#L930-1 [2019-12-07 18:26:20,164 INFO L796 eck$LassoCheckResult]: Loop: 1125#L930-1 assume !false; 1271#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1195#L576 assume !false; 1196#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1324#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1173#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1326#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1256#L501 assume !(0 != eval_~tmp~0); 1257#L591 start_simulation_~kernel_st~0 := 2; 1301#L409-1 start_simulation_~kernel_st~0 := 3; 1302#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1597#L601-4 assume !(0 == ~T1_E~0); 1352#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1254#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1255#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1102#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1103#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1166#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1167#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1395#L641-3 assume !(0 == ~E_3~0); 1396#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1322#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1323#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1596#L294-21 assume 1 == ~m_pc~0; 1499#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1500#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1492#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1493#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1603#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1238#L313-21 assume !(1 == ~t1_pc~0); 1239#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 1245#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1276#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1278#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1279#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1281#L332-21 assume !(1 == ~t2_pc~0); 1376#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 1375#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1372#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1373#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1411#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1412#L351-21 assume 1 == ~t3_pc~0; 1525#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1424#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1425#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1431#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1432#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1435#L370-21 assume 1 == ~t4_pc~0; 1607#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1572#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1573#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1553#L777-21 assume !(0 != activate_threads_~tmp___3~0); 1554#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1114#L389-21 assume !(1 == ~t5_pc~0); 1089#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 1090#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1134#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1143#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1144#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1146#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1406#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1407#L679-3 assume !(1 == ~T3_E~0); 1318#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1319#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1348#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1241#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1242#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1094#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1095#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1190#L719-3 assume !(1 == ~E_5~0); 1191#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1400#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1175#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1328#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1399#L949 assume !(0 == start_simulation_~tmp~3); 1408#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1384#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1179#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1294#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1337#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1338#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 1474#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1124#L962 assume !(0 != start_simulation_~tmp___0~1); 1125#L930-1 [2019-12-07 18:26:20,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,165 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2019-12-07 18:26:20,165 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,165 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808206299] [2019-12-07 18:26:20,165 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,205 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808206299] [2019-12-07 18:26:20,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,206 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204748165] [2019-12-07 18:26:20,206 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1943078903, now seen corresponding path program 1 times [2019-12-07 18:26:20,207 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955287731] [2019-12-07 18:26:20,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,264 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955287731] [2019-12-07 18:26:20,265 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,265 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921834180] [2019-12-07 18:26:20,265 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,266 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,266 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand 3 states. [2019-12-07 18:26:20,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,278 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2019-12-07 18:26:20,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2019-12-07 18:26:20,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2019-12-07 18:26:20,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2019-12-07 18:26:20,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,288 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2019-12-07 18:26:20,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2019-12-07 18:26:20,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2019-12-07 18:26:20,299 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2019-12-07 18:26:20,299 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2019-12-07 18:26:20,299 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 18:26:20,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2019-12-07 18:26:20,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,303 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,303 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,304 INFO L794 eck$LassoCheckResult]: Stem: 2601#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2507#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2410#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2366#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 2367#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2455#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2456#L426-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2368#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2369#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2417#L441-1 assume !(0 == ~M_E~0); 2418#L601-1 assume !(0 == ~T1_E~0); 2420#L606-1 assume !(0 == ~T2_E~0); 2314#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2315#L616-1 assume !(0 == ~T4_E~0); 2167#L621-1 assume !(0 == ~T5_E~0); 2168#L626-1 assume !(0 == ~E_M~0); 2263#L631-1 assume !(0 == ~E_1~0); 2264#L636-1 assume !(0 == ~E_2~0); 2475#L641-1 assume !(0 == ~E_3~0); 2476#L646-1 assume !(0 == ~E_4~0); 2406#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2407#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2673#L294 assume 1 == ~m_pc~0; 2558#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2559#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2573#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2574#L745 assume !(0 != activate_threads_~tmp~1); 2687#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2353#L313 assume !(1 == ~t1_pc~0); 2308#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 2307#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2304#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2182#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2183#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2187#L332 assume 1 == ~t2_pc~0; 2378#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2376#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2377#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2400#L761 assume !(0 != activate_threads_~tmp___1~0); 2401#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2402#L351 assume !(1 == ~t3_pc~0); 2513#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 2514#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2536#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2542#L769 assume !(0 != activate_threads_~tmp___2~0); 2543#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2544#L370 assume 1 == ~t4_pc~0; 2657#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2652#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2653#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2670#L777 assume !(0 != activate_threads_~tmp___3~0); 2671#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2254#L389 assume !(1 == ~t5_pc~0); 2221#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 2222#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2252#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2272#L785 assume !(0 != activate_threads_~tmp___4~0); 2273#L785-2 assume !(1 == ~M_E~0); 2274#L669-1 assume !(1 == ~T1_E~0); 2473#L674-1 assume !(1 == ~T2_E~0); 2474#L679-1 assume !(1 == ~T3_E~0); 2404#L684-1 assume !(1 == ~T4_E~0); 2405#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2593#L694-1 assume !(1 == ~E_M~0); 2336#L699-1 assume !(1 == ~E_1~0); 2337#L704-1 assume !(1 == ~E_2~0); 2156#L709-1 assume !(1 == ~E_3~0); 2157#L714-1 assume !(1 == ~E_4~0); 2257#L719-1 assume !(1 == ~E_5~0); 2196#L930-1 [2019-12-07 18:26:20,304 INFO L796 eck$LassoCheckResult]: Loop: 2196#L930-1 assume !false; 2342#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2266#L576 assume !false; 2267#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2395#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2244#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2397#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2327#L501 assume !(0 != eval_~tmp~0); 2328#L591 start_simulation_~kernel_st~0 := 2; 2372#L409-1 start_simulation_~kernel_st~0 := 3; 2373#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2668#L601-4 assume !(0 == ~T1_E~0); 2423#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2325#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2326#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2173#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2174#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2237#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2238#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2466#L641-3 assume !(0 == ~E_3~0); 2467#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2393#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2394#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2667#L294-21 assume 1 == ~m_pc~0; 2570#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2571#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2563#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2564#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2674#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2309#L313-21 assume !(1 == ~t1_pc~0); 2310#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 2316#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2347#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2349#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2350#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2352#L332-21 assume 1 == ~t2_pc~0; 2445#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2446#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2443#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2444#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2482#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2483#L351-21 assume 1 == ~t3_pc~0; 2596#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2495#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2496#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2502#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2503#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2506#L370-21 assume 1 == ~t4_pc~0; 2678#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2643#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2644#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2624#L777-21 assume !(0 != activate_threads_~tmp___3~0); 2625#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2185#L389-21 assume 1 == ~t5_pc~0; 2186#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2159#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2205#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2211#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2212#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2216#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2477#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2478#L679-3 assume !(1 == ~T3_E~0); 2389#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2390#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2419#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2312#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2313#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2165#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2166#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2260#L719-3 assume !(1 == ~E_5~0); 2261#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2471#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2246#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2399#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2469#L949 assume !(0 == start_simulation_~tmp~3); 2479#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2453#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2250#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2365#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2408#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2409#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 2545#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2195#L962 assume !(0 != start_simulation_~tmp___0~1); 2196#L930-1 [2019-12-07 18:26:20,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,304 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2019-12-07 18:26:20,304 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038812890] [2019-12-07 18:26:20,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038812890] [2019-12-07 18:26:20,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,331 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,332 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106042981] [2019-12-07 18:26:20,332 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,332 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 1 times [2019-12-07 18:26:20,332 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,332 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753185667] [2019-12-07 18:26:20,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753185667] [2019-12-07 18:26:20,375 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,375 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,375 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714657088] [2019-12-07 18:26:20,375 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,376 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,376 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand 3 states. [2019-12-07 18:26:20,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,389 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2019-12-07 18:26:20,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2019-12-07 18:26:20,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2019-12-07 18:26:20,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2019-12-07 18:26:20,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,401 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2019-12-07 18:26:20,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2019-12-07 18:26:20,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2019-12-07 18:26:20,412 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2019-12-07 18:26:20,412 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2019-12-07 18:26:20,413 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 18:26:20,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2019-12-07 18:26:20,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,417 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,418 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,418 INFO L794 eck$LassoCheckResult]: Stem: 3672#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3578#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3481#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3437#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 3438#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3526#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3527#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3439#L431-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3440#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3488#L441-1 assume !(0 == ~M_E~0); 3489#L601-1 assume !(0 == ~T1_E~0); 3491#L606-1 assume !(0 == ~T2_E~0); 3385#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3386#L616-1 assume !(0 == ~T4_E~0); 3238#L621-1 assume !(0 == ~T5_E~0); 3239#L626-1 assume !(0 == ~E_M~0); 3334#L631-1 assume !(0 == ~E_1~0); 3335#L636-1 assume !(0 == ~E_2~0); 3546#L641-1 assume !(0 == ~E_3~0); 3547#L646-1 assume !(0 == ~E_4~0); 3477#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3478#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3744#L294 assume 1 == ~m_pc~0; 3629#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3630#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3644#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3645#L745 assume !(0 != activate_threads_~tmp~1); 3758#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3424#L313 assume !(1 == ~t1_pc~0); 3379#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 3378#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3375#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3254#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3255#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3258#L332 assume 1 == ~t2_pc~0; 3449#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3447#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3448#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3471#L761 assume !(0 != activate_threads_~tmp___1~0); 3472#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3473#L351 assume !(1 == ~t3_pc~0); 3584#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 3585#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3607#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3613#L769 assume !(0 != activate_threads_~tmp___2~0); 3614#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3615#L370 assume 1 == ~t4_pc~0; 3728#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3725#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3726#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3741#L777 assume !(0 != activate_threads_~tmp___3~0); 3742#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3325#L389 assume !(1 == ~t5_pc~0); 3292#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 3293#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3323#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3343#L785 assume !(0 != activate_threads_~tmp___4~0); 3344#L785-2 assume !(1 == ~M_E~0); 3345#L669-1 assume !(1 == ~T1_E~0); 3544#L674-1 assume !(1 == ~T2_E~0); 3545#L679-1 assume !(1 == ~T3_E~0); 3475#L684-1 assume !(1 == ~T4_E~0); 3476#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3664#L694-1 assume !(1 == ~E_M~0); 3407#L699-1 assume !(1 == ~E_1~0); 3408#L704-1 assume !(1 == ~E_2~0); 3227#L709-1 assume !(1 == ~E_3~0); 3228#L714-1 assume !(1 == ~E_4~0); 3330#L719-1 assume !(1 == ~E_5~0); 3267#L930-1 [2019-12-07 18:26:20,418 INFO L796 eck$LassoCheckResult]: Loop: 3267#L930-1 assume !false; 3413#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3337#L576 assume !false; 3338#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3466#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3315#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3468#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3398#L501 assume !(0 != eval_~tmp~0); 3399#L591 start_simulation_~kernel_st~0 := 2; 3443#L409-1 start_simulation_~kernel_st~0 := 3; 3444#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3739#L601-4 assume !(0 == ~T1_E~0); 3494#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3396#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3397#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3244#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3245#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3308#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3309#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3537#L641-3 assume !(0 == ~E_3~0); 3538#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3464#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3465#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3738#L294-21 assume 1 == ~m_pc~0; 3641#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3642#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3634#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3635#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3745#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3380#L313-21 assume !(1 == ~t1_pc~0); 3381#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 3387#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3418#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3420#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3421#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3423#L332-21 assume 1 == ~t2_pc~0; 3516#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3517#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3514#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3515#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3553#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3554#L351-21 assume 1 == ~t3_pc~0; 3667#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3566#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3567#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3573#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3574#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3577#L370-21 assume 1 == ~t4_pc~0; 3749#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3714#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3715#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3695#L777-21 assume !(0 != activate_threads_~tmp___3~0); 3696#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3256#L389-21 assume 1 == ~t5_pc~0; 3257#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3230#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3276#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3285#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3286#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3288#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3548#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3549#L679-3 assume !(1 == ~T3_E~0); 3460#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3461#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3490#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3383#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3384#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3236#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3237#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3332#L719-3 assume !(1 == ~E_5~0); 3333#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3542#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3317#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3470#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3540#L949 assume !(0 == start_simulation_~tmp~3); 3550#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3524#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3321#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3436#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 3479#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3480#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 3616#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 3266#L962 assume !(0 != start_simulation_~tmp___0~1); 3267#L930-1 [2019-12-07 18:26:20,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,419 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2019-12-07 18:26:20,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195240417] [2019-12-07 18:26:20,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195240417] [2019-12-07 18:26:20,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,455 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534993337] [2019-12-07 18:26:20,456 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,457 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 2 times [2019-12-07 18:26:20,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166455828] [2019-12-07 18:26:20,458 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,490 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166455828] [2019-12-07 18:26:20,490 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,490 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,490 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964514929] [2019-12-07 18:26:20,491 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,491 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand 3 states. [2019-12-07 18:26:20,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,498 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2019-12-07 18:26:20,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2019-12-07 18:26:20,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2019-12-07 18:26:20,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2019-12-07 18:26:20,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,505 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2019-12-07 18:26:20,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2019-12-07 18:26:20,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2019-12-07 18:26:20,511 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2019-12-07 18:26:20,511 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2019-12-07 18:26:20,512 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 18:26:20,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2019-12-07 18:26:20,513 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,514 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,515 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,515 INFO L794 eck$LassoCheckResult]: Stem: 4743#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4649#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4552#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4508#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 4509#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4597#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4598#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4510#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4511#L436-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4559#L441-1 assume !(0 == ~M_E~0); 4560#L601-1 assume !(0 == ~T1_E~0); 4562#L606-1 assume !(0 == ~T2_E~0); 4456#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4457#L616-1 assume !(0 == ~T4_E~0); 4309#L621-1 assume !(0 == ~T5_E~0); 4310#L626-1 assume !(0 == ~E_M~0); 4405#L631-1 assume !(0 == ~E_1~0); 4406#L636-1 assume !(0 == ~E_2~0); 4617#L641-1 assume !(0 == ~E_3~0); 4618#L646-1 assume !(0 == ~E_4~0); 4548#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4549#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4815#L294 assume 1 == ~m_pc~0; 4700#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4701#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4715#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4716#L745 assume !(0 != activate_threads_~tmp~1); 4829#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4495#L313 assume !(1 == ~t1_pc~0); 4450#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 4449#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4446#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4325#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4326#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4329#L332 assume 1 == ~t2_pc~0; 4520#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4518#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4519#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4542#L761 assume !(0 != activate_threads_~tmp___1~0); 4543#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4544#L351 assume !(1 == ~t3_pc~0); 4655#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 4656#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4678#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4684#L769 assume !(0 != activate_threads_~tmp___2~0); 4685#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4686#L370 assume 1 == ~t4_pc~0; 4799#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4796#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4797#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4812#L777 assume !(0 != activate_threads_~tmp___3~0); 4813#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4396#L389 assume !(1 == ~t5_pc~0); 4363#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 4364#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4394#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4414#L785 assume !(0 != activate_threads_~tmp___4~0); 4415#L785-2 assume !(1 == ~M_E~0); 4416#L669-1 assume !(1 == ~T1_E~0); 4615#L674-1 assume !(1 == ~T2_E~0); 4616#L679-1 assume !(1 == ~T3_E~0); 4546#L684-1 assume !(1 == ~T4_E~0); 4547#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4735#L694-1 assume !(1 == ~E_M~0); 4478#L699-1 assume !(1 == ~E_1~0); 4479#L704-1 assume !(1 == ~E_2~0); 4298#L709-1 assume !(1 == ~E_3~0); 4299#L714-1 assume !(1 == ~E_4~0); 4401#L719-1 assume !(1 == ~E_5~0); 4338#L930-1 [2019-12-07 18:26:20,515 INFO L796 eck$LassoCheckResult]: Loop: 4338#L930-1 assume !false; 4484#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4408#L576 assume !false; 4409#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4537#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4386#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4539#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4469#L501 assume !(0 != eval_~tmp~0); 4470#L591 start_simulation_~kernel_st~0 := 2; 4514#L409-1 start_simulation_~kernel_st~0 := 3; 4515#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4810#L601-4 assume !(0 == ~T1_E~0); 4565#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4467#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4468#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4315#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4316#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4379#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4380#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4608#L641-3 assume !(0 == ~E_3~0); 4609#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4535#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4536#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4809#L294-21 assume 1 == ~m_pc~0; 4712#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4713#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4705#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4706#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4816#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4451#L313-21 assume !(1 == ~t1_pc~0); 4452#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 4458#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4489#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4491#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4492#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4494#L332-21 assume 1 == ~t2_pc~0; 4587#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4588#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4585#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4586#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4624#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4625#L351-21 assume 1 == ~t3_pc~0; 4737#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4637#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4638#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4644#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4645#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4648#L370-21 assume 1 == ~t4_pc~0; 4820#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4785#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4786#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4766#L777-21 assume !(0 != activate_threads_~tmp___3~0); 4767#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4327#L389-21 assume 1 == ~t5_pc~0; 4328#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4301#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4347#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4356#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4357#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4359#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4619#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4620#L679-3 assume !(1 == ~T3_E~0); 4531#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4532#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4561#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4454#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4455#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4307#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4308#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4403#L719-3 assume !(1 == ~E_5~0); 4404#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4613#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4388#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4541#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4611#L949 assume !(0 == start_simulation_~tmp~3); 4621#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4595#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4392#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4507#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 4550#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4551#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 4687#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4337#L962 assume !(0 != start_simulation_~tmp___0~1); 4338#L930-1 [2019-12-07 18:26:20,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,515 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2019-12-07 18:26:20,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488824804] [2019-12-07 18:26:20,515 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,531 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488824804] [2019-12-07 18:26:20,531 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,532 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,532 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12101111] [2019-12-07 18:26:20,532 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,532 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 3 times [2019-12-07 18:26:20,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137423745] [2019-12-07 18:26:20,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137423745] [2019-12-07 18:26:20,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,558 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293462945] [2019-12-07 18:26:20,558 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,558 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,559 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand 3 states. [2019-12-07 18:26:20,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,565 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2019-12-07 18:26:20,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2019-12-07 18:26:20,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2019-12-07 18:26:20,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2019-12-07 18:26:20,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,572 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2019-12-07 18:26:20,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2019-12-07 18:26:20,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2019-12-07 18:26:20,578 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2019-12-07 18:26:20,578 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2019-12-07 18:26:20,579 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 18:26:20,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2019-12-07 18:26:20,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,581 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,581 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,581 INFO L794 eck$LassoCheckResult]: Stem: 5814#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5720#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5623#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5579#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 5580#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5668#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5669#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5583#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5584#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5630#L441-1 assume !(0 == ~M_E~0); 5631#L601-1 assume !(0 == ~T1_E~0); 5633#L606-1 assume !(0 == ~T2_E~0); 5527#L611-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5528#L616-1 assume !(0 == ~T4_E~0); 5380#L621-1 assume !(0 == ~T5_E~0); 5381#L626-1 assume !(0 == ~E_M~0); 5476#L631-1 assume !(0 == ~E_1~0); 5477#L636-1 assume !(0 == ~E_2~0); 5688#L641-1 assume !(0 == ~E_3~0); 5689#L646-1 assume !(0 == ~E_4~0); 5619#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5620#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5886#L294 assume 1 == ~m_pc~0; 5771#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5772#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5786#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5787#L745 assume !(0 != activate_threads_~tmp~1); 5900#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5566#L313 assume !(1 == ~t1_pc~0); 5521#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 5520#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5517#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5396#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5397#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5400#L332 assume 1 == ~t2_pc~0; 5591#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5589#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5590#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5613#L761 assume !(0 != activate_threads_~tmp___1~0); 5614#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5615#L351 assume !(1 == ~t3_pc~0); 5726#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 5727#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5749#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5755#L769 assume !(0 != activate_threads_~tmp___2~0); 5756#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5757#L370 assume 1 == ~t4_pc~0; 5870#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5867#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5868#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5883#L777 assume !(0 != activate_threads_~tmp___3~0); 5884#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5467#L389 assume !(1 == ~t5_pc~0); 5434#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 5435#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5465#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5485#L785 assume !(0 != activate_threads_~tmp___4~0); 5486#L785-2 assume !(1 == ~M_E~0); 5487#L669-1 assume !(1 == ~T1_E~0); 5686#L674-1 assume !(1 == ~T2_E~0); 5687#L679-1 assume !(1 == ~T3_E~0); 5617#L684-1 assume !(1 == ~T4_E~0); 5618#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5806#L694-1 assume !(1 == ~E_M~0); 5549#L699-1 assume !(1 == ~E_1~0); 5550#L704-1 assume !(1 == ~E_2~0); 5369#L709-1 assume !(1 == ~E_3~0); 5370#L714-1 assume !(1 == ~E_4~0); 5472#L719-1 assume !(1 == ~E_5~0); 5409#L930-1 [2019-12-07 18:26:20,582 INFO L796 eck$LassoCheckResult]: Loop: 5409#L930-1 assume !false; 5555#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5479#L576 assume !false; 5480#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5608#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5457#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5610#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5540#L501 assume !(0 != eval_~tmp~0); 5541#L591 start_simulation_~kernel_st~0 := 2; 5585#L409-1 start_simulation_~kernel_st~0 := 3; 5586#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5881#L601-4 assume !(0 == ~T1_E~0); 5636#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5538#L611-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5539#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5386#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5387#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5450#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5451#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5679#L641-3 assume !(0 == ~E_3~0); 5680#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5606#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5607#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5880#L294-21 assume 1 == ~m_pc~0; 5783#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5784#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5776#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5777#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5887#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5522#L313-21 assume !(1 == ~t1_pc~0); 5523#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 5529#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5560#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5561#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5562#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5565#L332-21 assume 1 == ~t2_pc~0; 5658#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5659#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5656#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5657#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5695#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5696#L351-21 assume 1 == ~t3_pc~0; 5808#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5708#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5709#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5715#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5716#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5719#L370-21 assume 1 == ~t4_pc~0; 5891#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5856#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5857#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5837#L777-21 assume !(0 != activate_threads_~tmp___3~0); 5838#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5398#L389-21 assume 1 == ~t5_pc~0; 5399#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5372#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5418#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5427#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5428#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5430#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5690#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5691#L679-3 assume !(1 == ~T3_E~0); 5602#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5603#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5632#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5525#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5526#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5378#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5379#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5474#L719-3 assume !(1 == ~E_5~0); 5475#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5684#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5459#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5612#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5682#L949 assume !(0 == start_simulation_~tmp~3); 5692#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5666#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5463#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5578#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5621#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5622#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 5758#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5408#L962 assume !(0 != start_simulation_~tmp___0~1); 5409#L930-1 [2019-12-07 18:26:20,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,582 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2019-12-07 18:26:20,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822665511] [2019-12-07 18:26:20,582 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822665511] [2019-12-07 18:26:20,600 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,600 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:20,600 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167994880] [2019-12-07 18:26:20,600 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,600 INFO L82 PathProgramCache]: Analyzing trace with hash 567388409, now seen corresponding path program 4 times [2019-12-07 18:26:20,600 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,600 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114135768] [2019-12-07 18:26:20,601 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114135768] [2019-12-07 18:26:20,621 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,621 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,621 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069699294] [2019-12-07 18:26:20,621 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,621 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,622 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand 3 states. [2019-12-07 18:26:20,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,633 INFO L93 Difference]: Finished difference Result 532 states and 799 transitions. [2019-12-07 18:26:20,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 799 transitions. [2019-12-07 18:26:20,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 799 transitions. [2019-12-07 18:26:20,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 799 transitions. [2019-12-07 18:26:20,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,640 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2019-12-07 18:26:20,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 799 transitions. [2019-12-07 18:26:20,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 799 transitions. [2019-12-07 18:26:20,646 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2019-12-07 18:26:20,646 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2019-12-07 18:26:20,646 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 18:26:20,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 799 transitions. [2019-12-07 18:26:20,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,649 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,649 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,649 INFO L794 eck$LassoCheckResult]: Stem: 6885#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6791#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6694#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6650#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 6651#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6739#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6740#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6654#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6655#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6701#L441-1 assume !(0 == ~M_E~0); 6702#L601-1 assume !(0 == ~T1_E~0); 6704#L606-1 assume !(0 == ~T2_E~0); 6599#L611-1 assume !(0 == ~T3_E~0); 6600#L616-1 assume !(0 == ~T4_E~0); 6451#L621-1 assume !(0 == ~T5_E~0); 6452#L626-1 assume !(0 == ~E_M~0); 6547#L631-1 assume !(0 == ~E_1~0); 6548#L636-1 assume !(0 == ~E_2~0); 6759#L641-1 assume !(0 == ~E_3~0); 6760#L646-1 assume !(0 == ~E_4~0); 6690#L651-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6691#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6957#L294 assume 1 == ~m_pc~0; 6842#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6843#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6857#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6858#L745 assume !(0 != activate_threads_~tmp~1); 6971#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6637#L313 assume !(1 == ~t1_pc~0); 6592#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 6591#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6588#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6467#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6468#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6471#L332 assume 1 == ~t2_pc~0; 6662#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6660#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6661#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6684#L761 assume !(0 != activate_threads_~tmp___1~0); 6685#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6686#L351 assume !(1 == ~t3_pc~0); 6797#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 6798#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6820#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6826#L769 assume !(0 != activate_threads_~tmp___2~0); 6827#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6828#L370 assume 1 == ~t4_pc~0; 6941#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6938#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6939#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6954#L777 assume !(0 != activate_threads_~tmp___3~0); 6955#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6538#L389 assume !(1 == ~t5_pc~0); 6505#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 6506#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6536#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6556#L785 assume !(0 != activate_threads_~tmp___4~0); 6557#L785-2 assume !(1 == ~M_E~0); 6558#L669-1 assume !(1 == ~T1_E~0); 6757#L674-1 assume !(1 == ~T2_E~0); 6758#L679-1 assume !(1 == ~T3_E~0); 6688#L684-1 assume !(1 == ~T4_E~0); 6689#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6877#L694-1 assume !(1 == ~E_M~0); 6620#L699-1 assume !(1 == ~E_1~0); 6621#L704-1 assume !(1 == ~E_2~0); 6440#L709-1 assume !(1 == ~E_3~0); 6441#L714-1 assume !(1 == ~E_4~0); 6543#L719-1 assume !(1 == ~E_5~0); 6480#L930-1 [2019-12-07 18:26:20,649 INFO L796 eck$LassoCheckResult]: Loop: 6480#L930-1 assume !false; 6626#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6550#L576 assume !false; 6551#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6680#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6528#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6681#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6611#L501 assume !(0 != eval_~tmp~0); 6612#L591 start_simulation_~kernel_st~0 := 2; 6656#L409-1 start_simulation_~kernel_st~0 := 3; 6657#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6952#L601-4 assume !(0 == ~T1_E~0); 6707#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6609#L611-3 assume !(0 == ~T3_E~0); 6610#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6457#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6458#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6521#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6522#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6750#L641-3 assume !(0 == ~E_3~0); 6751#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6677#L651-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6678#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6951#L294-21 assume 1 == ~m_pc~0; 6854#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6855#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6847#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6848#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6958#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6593#L313-21 assume !(1 == ~t1_pc~0); 6594#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 6598#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6631#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6632#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6633#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6636#L332-21 assume 1 == ~t2_pc~0; 6729#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6730#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6727#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6728#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6766#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6767#L351-21 assume !(1 == ~t3_pc~0); 6880#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 6779#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6780#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6786#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6787#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6790#L370-21 assume 1 == ~t4_pc~0; 6962#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6927#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6928#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6908#L777-21 assume !(0 != activate_threads_~tmp___3~0); 6909#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6469#L389-21 assume 1 == ~t5_pc~0; 6470#L390-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6443#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6489#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6498#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6499#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6501#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6761#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6762#L679-3 assume !(1 == ~T3_E~0); 6673#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6674#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6703#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6596#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6597#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6449#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6450#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6545#L719-3 assume !(1 == ~E_5~0); 6546#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6755#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6530#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6683#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6753#L949 assume !(0 == start_simulation_~tmp~3); 6763#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6737#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6534#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6649#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 6692#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6693#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 6829#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6479#L962 assume !(0 != start_simulation_~tmp___0~1); 6480#L930-1 [2019-12-07 18:26:20,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,650 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2019-12-07 18:26:20,650 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,650 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711381357] [2019-12-07 18:26:20,650 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711381357] [2019-12-07 18:26:20,665 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,665 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:20,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672733241] [2019-12-07 18:26:20,666 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,666 INFO L82 PathProgramCache]: Analyzing trace with hash 320331798, now seen corresponding path program 1 times [2019-12-07 18:26:20,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,667 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577977377] [2019-12-07 18:26:20,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,693 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577977377] [2019-12-07 18:26:20,693 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,693 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:20,693 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73919636] [2019-12-07 18:26:20,694 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,694 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,694 INFO L87 Difference]: Start difference. First operand 532 states and 799 transitions. cyclomatic complexity: 268 Second operand 3 states. [2019-12-07 18:26:20,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,724 INFO L93 Difference]: Finished difference Result 532 states and 786 transitions. [2019-12-07 18:26:20,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 786 transitions. [2019-12-07 18:26:20,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 786 transitions. [2019-12-07 18:26:20,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2019-12-07 18:26:20,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2019-12-07 18:26:20,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 786 transitions. [2019-12-07 18:26:20,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,730 INFO L688 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2019-12-07 18:26:20,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 786 transitions. [2019-12-07 18:26:20,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2019-12-07 18:26:20,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 532 states. [2019-12-07 18:26:20,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 786 transitions. [2019-12-07 18:26:20,737 INFO L711 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2019-12-07 18:26:20,737 INFO L591 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2019-12-07 18:26:20,737 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 18:26:20,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 786 transitions. [2019-12-07 18:26:20,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2019-12-07 18:26:20,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,739 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,739 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,739 INFO L794 eck$LassoCheckResult]: Stem: 7956#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7862#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7765#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7721#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 7722#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7810#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7811#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7725#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7726#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7772#L441-1 assume !(0 == ~M_E~0); 7773#L601-1 assume !(0 == ~T1_E~0); 7775#L606-1 assume !(0 == ~T2_E~0); 7670#L611-1 assume !(0 == ~T3_E~0); 7671#L616-1 assume !(0 == ~T4_E~0); 7523#L621-1 assume !(0 == ~T5_E~0); 7524#L626-1 assume !(0 == ~E_M~0); 7618#L631-1 assume !(0 == ~E_1~0); 7619#L636-1 assume !(0 == ~E_2~0); 7830#L641-1 assume !(0 == ~E_3~0); 7831#L646-1 assume !(0 == ~E_4~0); 7761#L651-1 assume !(0 == ~E_5~0); 7762#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8028#L294 assume 1 == ~m_pc~0; 7915#L295 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7916#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7928#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7929#L745 assume !(0 != activate_threads_~tmp~1); 8042#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7708#L313 assume !(1 == ~t1_pc~0); 7663#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 7662#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7659#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7538#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7539#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7542#L332 assume 1 == ~t2_pc~0; 7733#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7731#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7732#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7755#L761 assume !(0 != activate_threads_~tmp___1~0); 7756#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7757#L351 assume !(1 == ~t3_pc~0); 7868#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 7869#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7891#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7897#L769 assume !(0 != activate_threads_~tmp___2~0); 7898#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7899#L370 assume 1 == ~t4_pc~0; 8012#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8009#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8010#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8025#L777 assume !(0 != activate_threads_~tmp___3~0); 8026#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7609#L389 assume !(1 == ~t5_pc~0); 7576#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 7577#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7607#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7627#L785 assume !(0 != activate_threads_~tmp___4~0); 7628#L785-2 assume !(1 == ~M_E~0); 7629#L669-1 assume !(1 == ~T1_E~0); 7828#L674-1 assume !(1 == ~T2_E~0); 7829#L679-1 assume !(1 == ~T3_E~0); 7759#L684-1 assume !(1 == ~T4_E~0); 7760#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7948#L694-1 assume !(1 == ~E_M~0); 7691#L699-1 assume !(1 == ~E_1~0); 7692#L704-1 assume !(1 == ~E_2~0); 7511#L709-1 assume !(1 == ~E_3~0); 7512#L714-1 assume !(1 == ~E_4~0); 7614#L719-1 assume !(1 == ~E_5~0); 7551#L930-1 [2019-12-07 18:26:20,740 INFO L796 eck$LassoCheckResult]: Loop: 7551#L930-1 assume !false; 7697#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7621#L576 assume !false; 7622#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7751#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7599#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7752#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7682#L501 assume !(0 != eval_~tmp~0); 7683#L591 start_simulation_~kernel_st~0 := 2; 7727#L409-1 start_simulation_~kernel_st~0 := 3; 7728#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8023#L601-4 assume !(0 == ~T1_E~0); 7778#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7680#L611-3 assume !(0 == ~T3_E~0); 7681#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7528#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7529#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7592#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7593#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7821#L641-3 assume !(0 == ~E_3~0); 7822#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7748#L651-3 assume !(0 == ~E_5~0); 7749#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8022#L294-21 assume 1 == ~m_pc~0; 7925#L295-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7926#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7918#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7919#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8029#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7664#L313-21 assume !(1 == ~t1_pc~0); 7665#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 7669#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7702#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7703#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7704#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7707#L332-21 assume 1 == ~t2_pc~0; 7800#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7801#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7798#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7799#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7837#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7838#L351-21 assume 1 == ~t3_pc~0; 7950#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7850#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7851#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7857#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7858#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7861#L370-21 assume 1 == ~t4_pc~0; 8033#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7998#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7999#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7979#L777-21 assume !(0 != activate_threads_~tmp___3~0); 7980#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7540#L389-21 assume !(1 == ~t5_pc~0); 7515#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 7516#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7560#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7569#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7570#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7572#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7832#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7833#L679-3 assume !(1 == ~T3_E~0); 7744#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7745#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7774#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7667#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7668#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7520#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7521#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7616#L719-3 assume !(1 == ~E_5~0); 7617#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7826#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7601#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7754#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7824#L949 assume !(0 == start_simulation_~tmp~3); 7834#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7808#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7605#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7720#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7763#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7764#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 7900#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7550#L962 assume !(0 != start_simulation_~tmp___0~1); 7551#L930-1 [2019-12-07 18:26:20,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,740 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2019-12-07 18:26:20,740 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,740 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931495078] [2019-12-07 18:26:20,740 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,753 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931495078] [2019-12-07 18:26:20,753 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,754 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:20,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [155714173] [2019-12-07 18:26:20,754 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,754 INFO L82 PathProgramCache]: Analyzing trace with hash -1196993068, now seen corresponding path program 1 times [2019-12-07 18:26:20,754 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,754 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309480653] [2019-12-07 18:26:20,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,798 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309480653] [2019-12-07 18:26:20,798 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,798 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:26:20,798 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860687476] [2019-12-07 18:26:20,799 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,799 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,799 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,799 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,799 INFO L87 Difference]: Start difference. First operand 532 states and 786 transitions. cyclomatic complexity: 255 Second operand 3 states. [2019-12-07 18:26:20,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,852 INFO L93 Difference]: Finished difference Result 974 states and 1421 transitions. [2019-12-07 18:26:20,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 974 states and 1421 transitions. [2019-12-07 18:26:20,858 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 898 [2019-12-07 18:26:20,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 974 states to 974 states and 1421 transitions. [2019-12-07 18:26:20,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 974 [2019-12-07 18:26:20,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 974 [2019-12-07 18:26:20,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 974 states and 1421 transitions. [2019-12-07 18:26:20,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:20,868 INFO L688 BuchiCegarLoop]: Abstraction has 974 states and 1421 transitions. [2019-12-07 18:26:20,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 974 states and 1421 transitions. [2019-12-07 18:26:20,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 974 to 934. [2019-12-07 18:26:20,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2019-12-07 18:26:20,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1366 transitions. [2019-12-07 18:26:20,881 INFO L711 BuchiCegarLoop]: Abstraction has 934 states and 1366 transitions. [2019-12-07 18:26:20,881 INFO L591 BuchiCegarLoop]: Abstraction has 934 states and 1366 transitions. [2019-12-07 18:26:20,881 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 18:26:20,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 934 states and 1366 transitions. [2019-12-07 18:26:20,884 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 858 [2019-12-07 18:26:20,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:20,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:20,885 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,885 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:20,885 INFO L794 eck$LassoCheckResult]: Stem: 9475#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9383#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9285#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9241#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 9242#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9330#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9331#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9245#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9246#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9292#L441-1 assume !(0 == ~M_E~0); 9293#L601-1 assume !(0 == ~T1_E~0); 9295#L606-1 assume !(0 == ~T2_E~0); 9189#L611-1 assume !(0 == ~T3_E~0); 9190#L616-1 assume !(0 == ~T4_E~0); 9041#L621-1 assume !(0 == ~T5_E~0); 9042#L626-1 assume !(0 == ~E_M~0); 9136#L631-1 assume !(0 == ~E_1~0); 9137#L636-1 assume !(0 == ~E_2~0); 9350#L641-1 assume !(0 == ~E_3~0); 9351#L646-1 assume !(0 == ~E_4~0); 9281#L651-1 assume !(0 == ~E_5~0); 9282#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9552#L294 assume !(1 == ~m_pc~0); 9568#L294-2 is_master_triggered_~__retres1~0 := 0; 9580#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9449#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9450#L745 assume !(0 != activate_threads_~tmp~1); 9584#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9227#L313 assume !(1 == ~t1_pc~0); 9182#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 9181#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9179#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9056#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9057#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9060#L332 assume 1 == ~t2_pc~0; 9253#L333 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9251#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9252#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9275#L761 assume !(0 != activate_threads_~tmp___1~0); 9276#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9277#L351 assume !(1 == ~t3_pc~0); 9389#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 9390#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9412#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9418#L769 assume !(0 != activate_threads_~tmp___2~0); 9419#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9420#L370 assume 1 == ~t4_pc~0; 9536#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9534#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9535#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9549#L777 assume !(0 != activate_threads_~tmp___3~0); 9550#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9127#L389 assume !(1 == ~t5_pc~0); 9094#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 9095#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9125#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9145#L785 assume !(0 != activate_threads_~tmp___4~0); 9146#L785-2 assume !(1 == ~M_E~0); 9147#L669-1 assume !(1 == ~T1_E~0); 9348#L674-1 assume !(1 == ~T2_E~0); 9349#L679-1 assume !(1 == ~T3_E~0); 9279#L684-1 assume !(1 == ~T4_E~0); 9280#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9466#L694-1 assume !(1 == ~E_M~0); 9210#L699-1 assume !(1 == ~E_1~0); 9211#L704-1 assume !(1 == ~E_2~0); 9029#L709-1 assume !(1 == ~E_3~0); 9030#L714-1 assume !(1 == ~E_4~0); 9132#L719-1 assume !(1 == ~E_5~0); 9069#L930-1 [2019-12-07 18:26:20,885 INFO L796 eck$LassoCheckResult]: Loop: 9069#L930-1 assume !false; 9216#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9139#L576 assume !false; 9140#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9271#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9117#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9272#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9201#L501 assume !(0 != eval_~tmp~0); 9202#L591 start_simulation_~kernel_st~0 := 2; 9247#L409-1 start_simulation_~kernel_st~0 := 3; 9248#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9547#L601-4 assume !(0 == ~T1_E~0); 9298#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9199#L611-3 assume !(0 == ~T3_E~0); 9200#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9046#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9047#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9110#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9111#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9341#L641-3 assume !(0 == ~E_3~0); 9342#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9268#L651-3 assume !(0 == ~E_5~0); 9269#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9546#L294-21 assume !(1 == ~m_pc~0); 9554#L294-23 is_master_triggered_~__retres1~0 := 0; 9555#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9436#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9437#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9562#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9183#L313-21 assume !(1 == ~t1_pc~0); 9184#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 9188#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9221#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9222#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9223#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9226#L332-21 assume 1 == ~t2_pc~0; 9320#L333-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9321#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9318#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9319#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9357#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9358#L351-21 assume 1 == ~t3_pc~0; 9468#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9371#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9372#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9378#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9379#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9382#L370-21 assume !(1 == ~t4_pc~0); 9585#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 9923#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9922#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9921#L777-21 assume !(0 != activate_threads_~tmp___3~0); 9920#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9919#L389-21 assume !(1 == ~t5_pc~0); 9917#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 9916#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9914#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9913#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9912#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9911#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9910#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9909#L679-3 assume !(1 == ~T3_E~0); 9908#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9907#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9906#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9905#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9488#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9038#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9039#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9134#L719-3 assume !(1 == ~E_5~0); 9135#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9346#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9119#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9274#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9345#L949 assume !(0 == start_simulation_~tmp~3); 9354#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9328#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9123#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9240#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9283#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9284#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 9421#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9068#L962 assume !(0 != start_simulation_~tmp___0~1); 9069#L930-1 [2019-12-07 18:26:20,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,885 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2019-12-07 18:26:20,886 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,886 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734704199] [2019-12-07 18:26:20,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734704199] [2019-12-07 18:26:20,904 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:20,904 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124864582] [2019-12-07 18:26:20,905 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:20,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:20,905 INFO L82 PathProgramCache]: Analyzing trace with hash -573326574, now seen corresponding path program 1 times [2019-12-07 18:26:20,905 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:20,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873304129] [2019-12-07 18:26:20,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:20,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:20,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873304129] [2019-12-07 18:26:20,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:20,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:20,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138407956] [2019-12-07 18:26:20,932 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:20,932 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:20,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:20,932 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:20,933 INFO L87 Difference]: Start difference. First operand 934 states and 1366 transitions. cyclomatic complexity: 434 Second operand 3 states. [2019-12-07 18:26:20,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:20,975 INFO L93 Difference]: Finished difference Result 1695 states and 2461 transitions. [2019-12-07 18:26:20,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:20,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1695 states and 2461 transitions. [2019-12-07 18:26:20,985 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1614 [2019-12-07 18:26:20,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1695 states to 1695 states and 2461 transitions. [2019-12-07 18:26:20,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1695 [2019-12-07 18:26:20,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1695 [2019-12-07 18:26:20,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1695 states and 2461 transitions. [2019-12-07 18:26:21,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:21,001 INFO L688 BuchiCegarLoop]: Abstraction has 1695 states and 2461 transitions. [2019-12-07 18:26:21,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1695 states and 2461 transitions. [2019-12-07 18:26:21,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1695 to 1691. [2019-12-07 18:26:21,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1691 states. [2019-12-07 18:26:21,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 1691 states and 2457 transitions. [2019-12-07 18:26:21,027 INFO L711 BuchiCegarLoop]: Abstraction has 1691 states and 2457 transitions. [2019-12-07 18:26:21,028 INFO L591 BuchiCegarLoop]: Abstraction has 1691 states and 2457 transitions. [2019-12-07 18:26:21,028 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 18:26:21,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1691 states and 2457 transitions. [2019-12-07 18:26:21,033 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1610 [2019-12-07 18:26:21,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:21,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:21,034 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,034 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,034 INFO L794 eck$LassoCheckResult]: Stem: 12119#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12028#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11922#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11879#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 11880#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11965#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11966#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11881#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11882#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11928#L441-1 assume !(0 == ~M_E~0); 11929#L601-1 assume !(0 == ~T1_E~0); 11932#L606-1 assume !(0 == ~T2_E~0); 11826#L611-1 assume !(0 == ~T3_E~0); 11827#L616-1 assume !(0 == ~T4_E~0); 11678#L621-1 assume !(0 == ~T5_E~0); 11679#L626-1 assume !(0 == ~E_M~0); 11775#L631-1 assume !(0 == ~E_1~0); 11776#L636-1 assume !(0 == ~E_2~0); 11993#L641-1 assume !(0 == ~E_3~0); 11994#L646-1 assume !(0 == ~E_4~0); 11918#L651-1 assume !(0 == ~E_5~0); 11919#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12194#L294 assume !(1 == ~m_pc~0); 12212#L294-2 is_master_triggered_~__retres1~0 := 0; 12223#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12090#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12091#L745 assume !(0 != activate_threads_~tmp~1); 12226#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11865#L313 assume !(1 == ~t1_pc~0); 11820#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 11819#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11816#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11693#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11694#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11698#L332 assume !(1 == ~t2_pc~0); 11891#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 11889#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11890#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11912#L761 assume !(0 != activate_threads_~tmp___1~0); 11913#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11914#L351 assume !(1 == ~t3_pc~0); 12034#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 12035#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12056#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12062#L769 assume !(0 != activate_threads_~tmp___2~0); 12063#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12064#L370 assume 1 == ~t4_pc~0; 12178#L371 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12173#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12174#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12191#L777 assume !(0 != activate_threads_~tmp___3~0); 12192#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11764#L389 assume !(1 == ~t5_pc~0); 11730#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 11731#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11760#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11783#L785 assume !(0 != activate_threads_~tmp___4~0); 11784#L785-2 assume !(1 == ~M_E~0); 11786#L669-1 assume !(1 == ~T1_E~0); 11991#L674-1 assume !(1 == ~T2_E~0); 11992#L679-1 assume !(1 == ~T3_E~0); 11916#L684-1 assume !(1 == ~T4_E~0); 11917#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12110#L694-1 assume !(1 == ~E_M~0); 11848#L699-1 assume !(1 == ~E_1~0); 11849#L704-1 assume !(1 == ~E_2~0); 11667#L709-1 assume !(1 == ~E_3~0); 11668#L714-1 assume !(1 == ~E_4~0); 11768#L719-1 assume !(1 == ~E_5~0); 11769#L930-1 [2019-12-07 18:26:21,035 INFO L796 eck$LassoCheckResult]: Loop: 11769#L930-1 assume !false; 12479#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12477#L576 assume !false; 12475#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12463#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12461#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12375#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12346#L501 assume !(0 != eval_~tmp~0); 12228#L591 start_simulation_~kernel_st~0 := 2; 11885#L409-1 start_simulation_~kernel_st~0 := 3; 11886#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12189#L601-4 assume !(0 == ~T1_E~0); 11935#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11837#L611-3 assume !(0 == ~T3_E~0); 11838#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11684#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11685#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11748#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11749#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11980#L641-3 assume !(0 == ~E_3~0); 11981#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11905#L651-3 assume !(0 == ~E_5~0); 11906#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12188#L294-21 assume !(1 == ~m_pc~0); 12195#L294-23 is_master_triggered_~__retres1~0 := 0; 12196#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12080#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12081#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12205#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11821#L313-21 assume !(1 == ~t1_pc~0); 11822#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 11828#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11859#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11860#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11861#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11864#L332-21 assume !(1 == ~t2_pc~0); 11990#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 11995#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11955#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11956#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12001#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12002#L351-21 assume 1 == ~t3_pc~0; 12114#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12016#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12017#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12023#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12024#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12027#L370-21 assume 1 == ~t4_pc~0; 12214#L371-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12164#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12165#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12145#L777-21 assume !(0 != activate_threads_~tmp___3~0); 12146#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11696#L389-21 assume !(1 == ~t5_pc~0); 11671#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 11672#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11716#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11722#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11723#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 11727#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11996#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11997#L679-3 assume !(1 == ~T3_E~0); 11901#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11902#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11931#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11824#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11825#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11676#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11677#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11773#L719-3 assume !(1 == ~E_5~0); 11774#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11987#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11757#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11911#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 11986#L949 assume !(0 == start_simulation_~tmp~3); 11998#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11967#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 11762#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11878#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 12591#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12590#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 12589#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 12588#L962 assume !(0 != start_simulation_~tmp___0~1); 11769#L930-1 [2019-12-07 18:26:21,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,035 INFO L82 PathProgramCache]: Analyzing trace with hash -1115145540, now seen corresponding path program 1 times [2019-12-07 18:26:21,035 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,035 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829159430] [2019-12-07 18:26:21,035 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829159430] [2019-12-07 18:26:21,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:21,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838506511] [2019-12-07 18:26:21,053 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:21,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,053 INFO L82 PathProgramCache]: Analyzing trace with hash -1670642542, now seen corresponding path program 1 times [2019-12-07 18:26:21,053 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,054 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850506619] [2019-12-07 18:26:21,054 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850506619] [2019-12-07 18:26:21,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,091 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:26:21,101 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34918589] [2019-12-07 18:26:21,101 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:21,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:21,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:21,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:21,102 INFO L87 Difference]: Start difference. First operand 1691 states and 2457 transitions. cyclomatic complexity: 770 Second operand 3 states. [2019-12-07 18:26:21,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:21,147 INFO L93 Difference]: Finished difference Result 3116 states and 4496 transitions. [2019-12-07 18:26:21,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:21,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3116 states and 4496 transitions. [2019-12-07 18:26:21,165 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3020 [2019-12-07 18:26:21,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3116 states to 3116 states and 4496 transitions. [2019-12-07 18:26:21,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3116 [2019-12-07 18:26:21,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3116 [2019-12-07 18:26:21,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3116 states and 4496 transitions. [2019-12-07 18:26:21,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:21,192 INFO L688 BuchiCegarLoop]: Abstraction has 3116 states and 4496 transitions. [2019-12-07 18:26:21,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3116 states and 4496 transitions. [2019-12-07 18:26:21,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3116 to 3108. [2019-12-07 18:26:21,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3108 states. [2019-12-07 18:26:21,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3108 states to 3108 states and 4488 transitions. [2019-12-07 18:26:21,228 INFO L711 BuchiCegarLoop]: Abstraction has 3108 states and 4488 transitions. [2019-12-07 18:26:21,228 INFO L591 BuchiCegarLoop]: Abstraction has 3108 states and 4488 transitions. [2019-12-07 18:26:21,228 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 18:26:21,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3108 states and 4488 transitions. [2019-12-07 18:26:21,237 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2019-12-07 18:26:21,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:21,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:21,238 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,238 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,238 INFO L794 eck$LassoCheckResult]: Stem: 16962#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16871#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16755#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16711#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 16712#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16798#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16799#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16713#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16714#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16761#L441-1 assume !(0 == ~M_E~0); 16762#L601-1 assume !(0 == ~T1_E~0); 16765#L606-1 assume !(0 == ~T2_E~0); 16648#L611-1 assume !(0 == ~T3_E~0); 16649#L616-1 assume !(0 == ~T4_E~0); 16497#L621-1 assume !(0 == ~T5_E~0); 16498#L626-1 assume !(0 == ~E_M~0); 16596#L631-1 assume !(0 == ~E_1~0); 16597#L636-1 assume !(0 == ~E_2~0); 16827#L641-1 assume !(0 == ~E_3~0); 16828#L646-1 assume !(0 == ~E_4~0); 16751#L651-1 assume !(0 == ~E_5~0); 16752#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17038#L294 assume !(1 == ~m_pc~0); 17054#L294-2 is_master_triggered_~__retres1~0 := 0; 17071#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16933#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16934#L745 assume !(0 != activate_threads_~tmp~1); 17077#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16690#L313 assume !(1 == ~t1_pc~0); 16642#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 16641#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16638#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16513#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16514#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16518#L332 assume !(1 == ~t2_pc~0); 16723#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 16721#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16722#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16745#L761 assume !(0 != activate_threads_~tmp___1~0); 16746#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16747#L351 assume !(1 == ~t3_pc~0); 16877#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 16878#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16899#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16905#L769 assume !(0 != activate_threads_~tmp___2~0); 16906#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16907#L370 assume !(1 == ~t4_pc~0); 17023#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 17018#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17019#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17035#L777 assume !(0 != activate_threads_~tmp___3~0); 17036#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16585#L389 assume !(1 == ~t5_pc~0); 16550#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 16551#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16581#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16605#L785 assume !(0 != activate_threads_~tmp___4~0); 16606#L785-2 assume !(1 == ~M_E~0); 16607#L669-1 assume !(1 == ~T1_E~0); 16825#L674-1 assume !(1 == ~T2_E~0); 16826#L679-1 assume !(1 == ~T3_E~0); 16749#L684-1 assume !(1 == ~T4_E~0); 16750#L689-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16953#L694-1 assume !(1 == ~E_M~0); 16670#L699-1 assume !(1 == ~E_1~0); 16671#L704-1 assume !(1 == ~E_2~0); 16486#L709-1 assume !(1 == ~E_3~0); 16487#L714-1 assume !(1 == ~E_4~0); 16589#L719-1 assume !(1 == ~E_5~0); 16590#L930-1 [2019-12-07 18:26:21,238 INFO L796 eck$LassoCheckResult]: Loop: 16590#L930-1 assume !false; 18615#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 18613#L576 assume !false; 18611#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18597#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18595#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18593#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 18590#L501 assume !(0 != eval_~tmp~0); 18591#L591 start_simulation_~kernel_st~0 := 2; 19059#L409-1 start_simulation_~kernel_st~0 := 3; 19052#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 19047#L601-4 assume !(0 == ~T1_E~0); 19042#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19037#L611-3 assume !(0 == ~T3_E~0); 19033#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19028#L621-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19027#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19026#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19025#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19024#L641-3 assume !(0 == ~E_3~0); 19023#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19022#L651-3 assume !(0 == ~E_5~0); 19021#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19020#L294-21 assume !(1 == ~m_pc~0); 19019#L294-23 is_master_triggered_~__retres1~0 := 0; 19018#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19017#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 19016#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19015#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19014#L313-21 assume !(1 == ~t1_pc~0); 19012#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 19010#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19008#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19006#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19004#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19002#L332-21 assume !(1 == ~t2_pc~0); 19000#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 18998#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18995#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18993#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18991#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18989#L351-21 assume !(1 == ~t3_pc~0); 18986#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 18984#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18982#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18980#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18978#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18976#L370-21 assume !(1 == ~t4_pc~0); 18974#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 18972#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18969#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 18967#L777-21 assume !(0 != activate_threads_~tmp___3~0); 18965#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18963#L389-21 assume !(1 == ~t5_pc~0); 18960#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 18958#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18956#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18954#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 18952#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 18950#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18948#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18945#L679-3 assume !(1 == ~T3_E~0); 18943#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18941#L689-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18939#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18937#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18935#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18933#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18931#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18929#L719-3 assume !(1 == ~E_5~0); 18927#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18922#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18916#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18914#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 18910#L949 assume !(0 == start_simulation_~tmp~3); 18909#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 18902#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 18897#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 18895#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 18894#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 18892#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 18891#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 18890#L962 assume !(0 != start_simulation_~tmp___0~1); 16590#L930-1 [2019-12-07 18:26:21,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,238 INFO L82 PathProgramCache]: Analyzing trace with hash -335164611, now seen corresponding path program 1 times [2019-12-07 18:26:21,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,239 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740706083] [2019-12-07 18:26:21,239 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,257 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740706083] [2019-12-07 18:26:21,257 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,257 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:21,257 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734722788] [2019-12-07 18:26:21,257 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:21,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,257 INFO L82 PathProgramCache]: Analyzing trace with hash -1296006256, now seen corresponding path program 1 times [2019-12-07 18:26:21,257 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432084605] [2019-12-07 18:26:21,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,278 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432084605] [2019-12-07 18:26:21,278 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,278 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:21,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995074934] [2019-12-07 18:26:21,279 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:21,279 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:21,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:21,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:21,279 INFO L87 Difference]: Start difference. First operand 3108 states and 4488 transitions. cyclomatic complexity: 1388 Second operand 3 states. [2019-12-07 18:26:21,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:21,303 INFO L93 Difference]: Finished difference Result 3108 states and 4462 transitions. [2019-12-07 18:26:21,304 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:21,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3108 states and 4462 transitions. [2019-12-07 18:26:21,315 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2019-12-07 18:26:21,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3108 states to 3108 states and 4462 transitions. [2019-12-07 18:26:21,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3108 [2019-12-07 18:26:21,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3108 [2019-12-07 18:26:21,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3108 states and 4462 transitions. [2019-12-07 18:26:21,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:21,336 INFO L688 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2019-12-07 18:26:21,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3108 states and 4462 transitions. [2019-12-07 18:26:21,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3108 to 3108. [2019-12-07 18:26:21,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3108 states. [2019-12-07 18:26:21,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3108 states to 3108 states and 4462 transitions. [2019-12-07 18:26:21,373 INFO L711 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2019-12-07 18:26:21,373 INFO L591 BuchiCegarLoop]: Abstraction has 3108 states and 4462 transitions. [2019-12-07 18:26:21,373 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 18:26:21,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3108 states and 4462 transitions. [2019-12-07 18:26:21,380 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3012 [2019-12-07 18:26:21,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:21,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:21,380 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,380 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,381 INFO L794 eck$LassoCheckResult]: Stem: 23180#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 23088#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22971#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22928#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 22929#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23014#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23015#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22930#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22931#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22977#L441-1 assume !(0 == ~M_E~0); 22978#L601-1 assume !(0 == ~T1_E~0); 22981#L606-1 assume !(0 == ~T2_E~0); 22874#L611-1 assume !(0 == ~T3_E~0); 22875#L616-1 assume !(0 == ~T4_E~0); 22722#L621-1 assume !(0 == ~T5_E~0); 22723#L626-1 assume !(0 == ~E_M~0); 22822#L631-1 assume !(0 == ~E_1~0); 22823#L636-1 assume !(0 == ~E_2~0); 23046#L641-1 assume !(0 == ~E_3~0); 23047#L646-1 assume !(0 == ~E_4~0); 22967#L651-1 assume !(0 == ~E_5~0); 22968#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23253#L294 assume !(1 == ~m_pc~0); 23276#L294-2 is_master_triggered_~__retres1~0 := 0; 23293#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23150#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23151#L745 assume !(0 != activate_threads_~tmp~1); 23307#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22915#L313 assume !(1 == ~t1_pc~0); 22868#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 22867#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22864#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22738#L753 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22739#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22743#L332 assume !(1 == ~t2_pc~0); 22940#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 22938#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22939#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22961#L761 assume !(0 != activate_threads_~tmp___1~0); 22962#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22963#L351 assume !(1 == ~t3_pc~0); 23094#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 23095#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23116#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23122#L769 assume !(0 != activate_threads_~tmp___2~0); 23123#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23124#L370 assume !(1 == ~t4_pc~0); 23237#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 23232#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23233#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23250#L777 assume !(0 != activate_threads_~tmp___3~0); 23251#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22811#L389 assume !(1 == ~t5_pc~0); 22777#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 22778#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22807#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22830#L785 assume !(0 != activate_threads_~tmp___4~0); 22831#L785-2 assume !(1 == ~M_E~0); 22833#L669-1 assume !(1 == ~T1_E~0); 23044#L674-1 assume !(1 == ~T2_E~0); 23045#L679-1 assume !(1 == ~T3_E~0); 22965#L684-1 assume !(1 == ~T4_E~0); 22966#L689-1 assume !(1 == ~T5_E~0); 23170#L694-1 assume !(1 == ~E_M~0); 22897#L699-1 assume !(1 == ~E_1~0); 22898#L704-1 assume !(1 == ~E_2~0); 22711#L709-1 assume !(1 == ~E_3~0); 22712#L714-1 assume !(1 == ~E_4~0); 22815#L719-1 assume !(1 == ~E_5~0); 22752#L930-1 [2019-12-07 18:26:21,381 INFO L796 eck$LassoCheckResult]: Loop: 22752#L930-1 assume !false; 22903#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 22825#L576 assume !false; 22826#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22956#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22802#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22958#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22888#L501 assume !(0 != eval_~tmp~0); 22889#L591 start_simulation_~kernel_st~0 := 2; 25691#L409-1 start_simulation_~kernel_st~0 := 3; 25690#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25689#L601-4 assume !(0 == ~T1_E~0); 25688#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25687#L611-3 assume !(0 == ~T3_E~0); 25685#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25683#L621-3 assume !(0 == ~T5_E~0); 25681#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25679#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25677#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25675#L641-3 assume !(0 == ~E_3~0); 25673#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25671#L651-3 assume !(0 == ~E_5~0); 25669#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25667#L294-21 assume !(1 == ~m_pc~0); 25665#L294-23 is_master_triggered_~__retres1~0 := 0; 25663#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25661#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25659#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25657#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25656#L313-21 assume !(1 == ~t1_pc~0); 25654#L313-23 is_transmit1_triggered_~__retres1~1 := 0; 25652#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25650#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25648#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25646#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25643#L332-21 assume !(1 == ~t2_pc~0); 25641#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 25638#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25636#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25634#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25632#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25630#L351-21 assume !(1 == ~t3_pc~0); 25627#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 25626#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25625#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25623#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25621#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25619#L370-21 assume !(1 == ~t4_pc~0); 25617#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 25614#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25612#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 25610#L777-21 assume !(0 != activate_threads_~tmp___3~0); 25608#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25606#L389-21 assume !(1 == ~t5_pc~0); 25603#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 25601#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25599#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25597#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25595#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 25593#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25590#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25588#L679-3 assume !(1 == ~T3_E~0); 25586#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25584#L689-3 assume !(1 == ~T5_E~0); 25582#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25580#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25578#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25576#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25574#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25572#L719-3 assume !(1 == ~E_5~0); 25570#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25565#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25558#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23038#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 23039#L949 assume !(0 == start_simulation_~tmp~3); 23050#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23016#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22809#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22927#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 22969#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22970#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 23125#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 22751#L962 assume !(0 != start_simulation_~tmp___0~1); 22752#L930-1 [2019-12-07 18:26:21,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,381 INFO L82 PathProgramCache]: Analyzing trace with hash 1439842751, now seen corresponding path program 1 times [2019-12-07 18:26:21,381 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,381 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119003125] [2019-12-07 18:26:21,381 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,419 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119003125] [2019-12-07 18:26:21,419 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:21,419 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732496955] [2019-12-07 18:26:21,419 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:21,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,420 INFO L82 PathProgramCache]: Analyzing trace with hash -1159714548, now seen corresponding path program 1 times [2019-12-07 18:26:21,420 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,420 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393262104] [2019-12-07 18:26:21,420 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393262104] [2019-12-07 18:26:21,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:21,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467937021] [2019-12-07 18:26:21,443 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:21,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:21,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:26:21,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:26:21,444 INFO L87 Difference]: Start difference. First operand 3108 states and 4462 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2019-12-07 18:26:21,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:21,608 INFO L93 Difference]: Finished difference Result 8447 states and 12061 transitions. [2019-12-07 18:26:21,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:26:21,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8447 states and 12061 transitions. [2019-12-07 18:26:21,634 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8224 [2019-12-07 18:26:21,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8447 states to 8447 states and 12061 transitions. [2019-12-07 18:26:21,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8447 [2019-12-07 18:26:21,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8447 [2019-12-07 18:26:21,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8447 states and 12061 transitions. [2019-12-07 18:26:21,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:21,685 INFO L688 BuchiCegarLoop]: Abstraction has 8447 states and 12061 transitions. [2019-12-07 18:26:21,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8447 states and 12061 transitions. [2019-12-07 18:26:21,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8447 to 3267. [2019-12-07 18:26:21,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3267 states. [2019-12-07 18:26:21,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3267 states to 3267 states and 4621 transitions. [2019-12-07 18:26:21,737 INFO L711 BuchiCegarLoop]: Abstraction has 3267 states and 4621 transitions. [2019-12-07 18:26:21,737 INFO L591 BuchiCegarLoop]: Abstraction has 3267 states and 4621 transitions. [2019-12-07 18:26:21,737 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 18:26:21,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3267 states and 4621 transitions. [2019-12-07 18:26:21,744 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3168 [2019-12-07 18:26:21,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:21,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:21,745 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,745 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,745 INFO L794 eck$LassoCheckResult]: Stem: 34770#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 34675#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 34562#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34518#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 34519#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34608#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34609#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34520#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34521#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34569#L441-1 assume !(0 == ~M_E~0); 34570#L601-1 assume !(0 == ~T1_E~0); 34572#L606-1 assume !(0 == ~T2_E~0); 34444#L611-1 assume !(0 == ~T3_E~0); 34445#L616-1 assume !(0 == ~T4_E~0); 34292#L621-1 assume !(0 == ~T5_E~0); 34293#L626-1 assume !(0 == ~E_M~0); 34390#L631-1 assume !(0 == ~E_1~0); 34391#L636-1 assume !(0 == ~E_2~0); 34634#L641-1 assume !(0 == ~E_3~0); 34635#L646-1 assume !(0 == ~E_4~0); 34558#L651-1 assume !(0 == ~E_5~0); 34559#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34844#L294 assume !(1 == ~m_pc~0); 34869#L294-2 is_master_triggered_~__retres1~0 := 0; 34886#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34738#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34739#L745 assume !(0 != activate_threads_~tmp~1); 34898#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34499#L313 assume !(1 == ~t1_pc~0); 34438#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 34497#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34498#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34307#L753 assume !(0 != activate_threads_~tmp___0~0); 34308#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34312#L332 assume !(1 == ~t2_pc~0); 34530#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 34528#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34529#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34552#L761 assume !(0 != activate_threads_~tmp___1~0); 34553#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34554#L351 assume !(1 == ~t3_pc~0); 34682#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 34683#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34704#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34710#L769 assume !(0 != activate_threads_~tmp___2~0); 34711#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34712#L370 assume !(1 == ~t4_pc~0); 34829#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 34824#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34825#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34841#L777 assume !(0 != activate_threads_~tmp___3~0); 34842#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34380#L389 assume !(1 == ~t5_pc~0); 34346#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 34347#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34378#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34400#L785 assume !(0 != activate_threads_~tmp___4~0); 34401#L785-2 assume !(1 == ~M_E~0); 34402#L669-1 assume !(1 == ~T1_E~0); 34632#L674-1 assume !(1 == ~T2_E~0); 34633#L679-1 assume !(1 == ~T3_E~0); 34556#L684-1 assume !(1 == ~T4_E~0); 34557#L689-1 assume !(1 == ~T5_E~0); 34758#L694-1 assume !(1 == ~E_M~0); 34470#L699-1 assume !(1 == ~E_1~0); 34471#L704-1 assume !(1 == ~E_2~0); 34281#L709-1 assume !(1 == ~E_3~0); 34282#L714-1 assume !(1 == ~E_4~0); 34383#L719-1 assume !(1 == ~E_5~0); 34384#L930-1 [2019-12-07 18:26:21,745 INFO L796 eck$LassoCheckResult]: Loop: 34384#L930-1 assume !false; 35382#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 35380#L576 assume !false; 35378#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35361#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35360#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35359#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 35357#L501 assume !(0 != eval_~tmp~0); 35358#L591 start_simulation_~kernel_st~0 := 2; 35617#L409-1 start_simulation_~kernel_st~0 := 3; 35615#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35613#L601-4 assume !(0 == ~T1_E~0); 35611#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35609#L611-3 assume !(0 == ~T3_E~0); 35607#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35605#L621-3 assume !(0 == ~T5_E~0); 35603#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35599#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35597#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35596#L641-3 assume !(0 == ~E_3~0); 35595#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35594#L651-3 assume !(0 == ~E_5~0); 35593#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35592#L294-21 assume !(1 == ~m_pc~0); 35591#L294-23 is_master_triggered_~__retres1~0 := 0; 35590#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35589#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 35588#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35587#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35586#L313-21 assume 1 == ~t1_pc~0; 35584#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35582#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35580#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35578#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35577#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35576#L332-21 assume !(1 == ~t2_pc~0); 35575#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 35574#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35573#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35572#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35571#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35555#L351-21 assume !(1 == ~t3_pc~0); 35552#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 35550#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35548#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35546#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35544#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35542#L370-21 assume !(1 == ~t4_pc~0); 35540#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 35538#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35535#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35533#L777-21 assume !(0 != activate_threads_~tmp___3~0); 35531#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35529#L389-21 assume !(1 == ~t5_pc~0); 35526#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 35524#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35522#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35520#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35518#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 35516#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35514#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35511#L679-3 assume !(1 == ~T3_E~0); 35509#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35507#L689-3 assume !(1 == ~T5_E~0); 35505#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35503#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35501#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35499#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35497#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35495#L719-3 assume !(1 == ~E_5~0); 35493#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35488#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35482#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35480#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 35476#L949 assume !(0 == start_simulation_~tmp~3); 35475#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35456#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35451#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35449#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 35447#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35445#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 35443#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 35441#L962 assume !(0 != start_simulation_~tmp___0~1); 34384#L930-1 [2019-12-07 18:26:21,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,746 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2019-12-07 18:26:21,746 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480224007] [2019-12-07 18:26:21,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:21,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:21,780 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:21,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,780 INFO L82 PathProgramCache]: Analyzing trace with hash -1262515795, now seen corresponding path program 1 times [2019-12-07 18:26:21,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208535078] [2019-12-07 18:26:21,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:21,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:21,802 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208535078] [2019-12-07 18:26:21,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:21,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:21,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273404558] [2019-12-07 18:26:21,803 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:21,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:21,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:26:21,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:26:21,803 INFO L87 Difference]: Start difference. First operand 3267 states and 4621 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2019-12-07 18:26:21,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:21,883 INFO L93 Difference]: Finished difference Result 5847 states and 8165 transitions. [2019-12-07 18:26:21,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:26:21,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5847 states and 8165 transitions. [2019-12-07 18:26:21,905 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5724 [2019-12-07 18:26:21,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5847 states to 5847 states and 8165 transitions. [2019-12-07 18:26:21,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5847 [2019-12-07 18:26:21,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5847 [2019-12-07 18:26:21,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5847 states and 8165 transitions. [2019-12-07 18:26:21,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:21,933 INFO L688 BuchiCegarLoop]: Abstraction has 5847 states and 8165 transitions. [2019-12-07 18:26:21,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5847 states and 8165 transitions. [2019-12-07 18:26:21,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5847 to 3291. [2019-12-07 18:26:21,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3291 states. [2019-12-07 18:26:21,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3291 states to 3291 states and 4645 transitions. [2019-12-07 18:26:21,985 INFO L711 BuchiCegarLoop]: Abstraction has 3291 states and 4645 transitions. [2019-12-07 18:26:21,985 INFO L591 BuchiCegarLoop]: Abstraction has 3291 states and 4645 transitions. [2019-12-07 18:26:21,986 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 18:26:21,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3291 states and 4645 transitions. [2019-12-07 18:26:21,993 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3192 [2019-12-07 18:26:21,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:21,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:21,994 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,994 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:21,994 INFO L794 eck$LassoCheckResult]: Stem: 43890#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43798#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43678#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43634#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 43635#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43723#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43724#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43638#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43639#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43685#L441-1 assume !(0 == ~M_E~0); 43686#L601-1 assume !(0 == ~T1_E~0); 43688#L606-1 assume !(0 == ~T2_E~0); 43574#L611-1 assume !(0 == ~T3_E~0); 43575#L616-1 assume !(0 == ~T4_E~0); 43422#L621-1 assume !(0 == ~T5_E~0); 43423#L626-1 assume !(0 == ~E_M~0); 43521#L631-1 assume !(0 == ~E_1~0); 43522#L636-1 assume !(0 == ~E_2~0); 43753#L641-1 assume !(0 == ~E_3~0); 43754#L646-1 assume !(0 == ~E_4~0); 43674#L651-1 assume !(0 == ~E_5~0); 43675#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43964#L294 assume !(1 == ~m_pc~0); 43989#L294-2 is_master_triggered_~__retres1~0 := 0; 44007#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43861#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 43862#L745 assume !(0 != activate_threads_~tmp~1); 44017#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43619#L313 assume !(1 == ~t1_pc~0); 43567#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 43618#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43563#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 43438#L753 assume !(0 != activate_threads_~tmp___0~0); 43439#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43442#L332 assume !(1 == ~t2_pc~0); 43646#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 43644#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43645#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43668#L761 assume !(0 != activate_threads_~tmp___1~0); 43669#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43670#L351 assume !(1 == ~t3_pc~0); 43804#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 43805#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43826#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43833#L769 assume !(0 != activate_threads_~tmp___2~0); 43834#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43835#L370 assume !(1 == ~t4_pc~0); 43947#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 43944#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43945#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 43961#L777 assume !(0 != activate_threads_~tmp___3~0); 43962#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43511#L389 assume !(1 == ~t5_pc~0); 43478#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 43479#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43509#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43530#L785 assume !(0 != activate_threads_~tmp___4~0); 43531#L785-2 assume !(1 == ~M_E~0); 43532#L669-1 assume !(1 == ~T1_E~0); 43751#L674-1 assume !(1 == ~T2_E~0); 43752#L679-1 assume !(1 == ~T3_E~0); 43672#L684-1 assume !(1 == ~T4_E~0); 43673#L689-1 assume !(1 == ~T5_E~0); 43881#L694-1 assume !(1 == ~E_M~0); 43595#L699-1 assume !(1 == ~E_1~0); 43596#L704-1 assume !(1 == ~E_2~0); 43411#L709-1 assume !(1 == ~E_3~0); 43412#L714-1 assume !(1 == ~E_4~0); 43514#L719-1 assume !(1 == ~E_5~0); 43515#L930-1 [2019-12-07 18:26:21,994 INFO L796 eck$LassoCheckResult]: Loop: 43515#L930-1 assume !false; 43965#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 43524#L576 assume !false; 43525#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43663#L454 assume !(0 == ~m_st~0); 43744#L458 assume !(0 == ~t1_st~0); 43900#L462 assume !(0 == ~t2_st~0); 43499#L466 assume !(0 == ~t3_st~0); 43500#L470 assume !(0 == ~t4_st~0); 43692#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 43664#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43665#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 45114#L501 assume !(0 != eval_~tmp~0); 44020#L591 start_simulation_~kernel_st~0 := 2; 43640#L409-1 start_simulation_~kernel_st~0 := 3; 43641#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 43959#L601-4 assume !(0 == ~T1_E~0); 43691#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43584#L611-3 assume !(0 == ~T3_E~0); 43585#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43428#L621-3 assume !(0 == ~T5_E~0); 43429#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43494#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43495#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43736#L641-3 assume !(0 == ~E_3~0); 43737#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43660#L651-3 assume !(0 == ~E_5~0); 43661#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43958#L294-21 assume !(1 == ~m_pc~0); 43970#L294-23 is_master_triggered_~__retres1~0 := 0; 43971#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45003#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45002#L745-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45001#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45000#L313-21 assume 1 == ~t1_pc~0; 44998#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 44405#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44406#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44401#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43613#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44145#L332-21 assume !(1 == ~t2_pc~0); 43755#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 43756#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43711#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 43712#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43769#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43770#L351-21 assume 1 == ~t3_pc~0; 43883#L352-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43786#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43787#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 43793#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43794#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43797#L370-21 assume !(1 == ~t4_pc~0); 44018#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 46607#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46606#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 46605#L777-21 assume !(0 != activate_threads_~tmp___3~0); 46604#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46603#L389-21 assume !(1 == ~t5_pc~0); 46601#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 46600#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46599#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 46598#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 46597#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 46596#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46595#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46594#L679-3 assume !(1 == ~T3_E~0); 46593#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46592#L689-3 assume !(1 == ~T5_E~0); 46591#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46590#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46589#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46588#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46587#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46530#L719-3 assume !(1 == ~E_5~0); 46531#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43745#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43503#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43667#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 43743#L949 assume !(0 == start_simulation_~tmp~3); 43759#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43760#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 46567#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 46566#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 46565#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 46564#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 46563#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 46562#L962 assume !(0 != start_simulation_~tmp___0~1); 43515#L930-1 [2019-12-07 18:26:21,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:21,995 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2019-12-07 18:26:21,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:21,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99660387] [2019-12-07 18:26:21,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:21,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,014 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:22,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,014 INFO L82 PathProgramCache]: Analyzing trace with hash 215214055, now seen corresponding path program 1 times [2019-12-07 18:26:22,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710901675] [2019-12-07 18:26:22,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:22,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:22,057 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710901675] [2019-12-07 18:26:22,058 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:22,058 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:26:22,058 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779651715] [2019-12-07 18:26:22,058 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:22,059 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:22,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:26:22,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:26:22,070 INFO L87 Difference]: Start difference. First operand 3291 states and 4645 transitions. cyclomatic complexity: 1362 Second operand 5 states. [2019-12-07 18:26:22,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:22,201 INFO L93 Difference]: Finished difference Result 6491 states and 9104 transitions. [2019-12-07 18:26:22,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:26:22,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6491 states and 9104 transitions. [2019-12-07 18:26:22,219 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6376 [2019-12-07 18:26:22,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6491 states to 6491 states and 9104 transitions. [2019-12-07 18:26:22,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6491 [2019-12-07 18:26:22,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6491 [2019-12-07 18:26:22,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6491 states and 9104 transitions. [2019-12-07 18:26:22,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:22,240 INFO L688 BuchiCegarLoop]: Abstraction has 6491 states and 9104 transitions. [2019-12-07 18:26:22,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6491 states and 9104 transitions. [2019-12-07 18:26:22,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6491 to 3375. [2019-12-07 18:26:22,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3375 states. [2019-12-07 18:26:22,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3375 states to 3375 states and 4704 transitions. [2019-12-07 18:26:22,283 INFO L711 BuchiCegarLoop]: Abstraction has 3375 states and 4704 transitions. [2019-12-07 18:26:22,283 INFO L591 BuchiCegarLoop]: Abstraction has 3375 states and 4704 transitions. [2019-12-07 18:26:22,283 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 18:26:22,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3375 states and 4704 transitions. [2019-12-07 18:26:22,289 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3276 [2019-12-07 18:26:22,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:22,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:22,290 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,290 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,290 INFO L794 eck$LassoCheckResult]: Stem: 53689#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 53597#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 53479#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53435#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 53436#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53526#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53527#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53439#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53440#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53486#L441-1 assume !(0 == ~M_E~0); 53487#L601-1 assume !(0 == ~T1_E~0); 53489#L606-1 assume !(0 == ~T2_E~0); 53372#L611-1 assume !(0 == ~T3_E~0); 53373#L616-1 assume !(0 == ~T4_E~0); 53218#L621-1 assume !(0 == ~T5_E~0); 53219#L626-1 assume !(0 == ~E_M~0); 53319#L631-1 assume !(0 == ~E_1~0); 53320#L636-1 assume !(0 == ~E_2~0); 53555#L641-1 assume !(0 == ~E_3~0); 53556#L646-1 assume !(0 == ~E_4~0); 53475#L651-1 assume !(0 == ~E_5~0); 53476#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53767#L294 assume !(1 == ~m_pc~0); 53796#L294-2 is_master_triggered_~__retres1~0 := 0; 53823#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53660#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 53661#L745 assume !(0 != activate_threads_~tmp~1); 53838#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53415#L313 assume !(1 == ~t1_pc~0); 53365#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 53414#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53362#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 53233#L753 assume !(0 != activate_threads_~tmp___0~0); 53234#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53237#L332 assume !(1 == ~t2_pc~0); 53447#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 53445#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53446#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 53469#L761 assume !(0 != activate_threads_~tmp___1~0); 53470#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53471#L351 assume !(1 == ~t3_pc~0); 53603#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 53604#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53626#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 53632#L769 assume !(0 != activate_threads_~tmp___2~0); 53633#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 53634#L370 assume !(1 == ~t4_pc~0); 53751#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 53749#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 53750#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 53764#L777 assume !(0 != activate_threads_~tmp___3~0); 53765#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53309#L389 assume !(1 == ~t5_pc~0); 53273#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 53274#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53307#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53328#L785 assume !(0 != activate_threads_~tmp___4~0); 53329#L785-2 assume !(1 == ~M_E~0); 53330#L669-1 assume !(1 == ~T1_E~0); 53553#L674-1 assume !(1 == ~T2_E~0); 53554#L679-1 assume !(1 == ~T3_E~0); 53473#L684-1 assume !(1 == ~T4_E~0); 53474#L689-1 assume !(1 == ~T5_E~0); 53680#L694-1 assume !(1 == ~E_M~0); 53393#L699-1 assume !(1 == ~E_1~0); 53394#L704-1 assume !(1 == ~E_2~0); 53206#L709-1 assume !(1 == ~E_3~0); 53207#L714-1 assume !(1 == ~E_4~0); 53314#L719-1 assume !(1 == ~E_5~0); 53315#L930-1 [2019-12-07 18:26:22,291 INFO L796 eck$LassoCheckResult]: Loop: 53315#L930-1 assume !false; 55211#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 55210#L576 assume !false; 55209#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55202#L454 assume !(0 == ~m_st~0); 55203#L458 assume !(0 == ~t1_st~0); 55206#L462 assume !(0 == ~t2_st~0); 55208#L466 assume !(0 == ~t3_st~0); 55204#L470 assume !(0 == ~t4_st~0); 55205#L474 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 55207#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55198#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 55199#L501 assume !(0 != eval_~tmp~0); 56443#L591 start_simulation_~kernel_st~0 := 2; 56442#L409-1 start_simulation_~kernel_st~0 := 3; 56441#L601-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56440#L601-4 assume !(0 == ~T1_E~0); 56439#L606-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56438#L611-3 assume !(0 == ~T3_E~0); 56437#L616-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56436#L621-3 assume !(0 == ~T5_E~0); 56435#L626-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56434#L631-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56433#L636-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56432#L641-3 assume !(0 == ~E_3~0); 56431#L646-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56430#L651-3 assume !(0 == ~E_5~0); 53760#L656-3 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53761#L294-21 assume !(1 == ~m_pc~0); 53772#L294-23 is_master_triggered_~__retres1~0 := 0; 55197#L305-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55196#L306-7 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 55195#L745-21 assume !(0 != activate_threads_~tmp~1); 55194#L745-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55193#L313-21 assume 1 == ~t1_pc~0; 55191#L314-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 55189#L324-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55187#L325-7 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 55185#L753-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55184#L753-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55183#L332-21 assume !(1 == ~t2_pc~0); 55182#L332-23 is_transmit2_triggered_~__retres1~2 := 0; 55181#L343-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55180#L344-7 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 55179#L761-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 55178#L761-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55177#L351-21 assume !(1 == ~t3_pc~0); 55175#L351-23 is_transmit3_triggered_~__retres1~3 := 0; 55174#L362-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55173#L363-7 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 55172#L769-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 55170#L769-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55168#L370-21 assume !(1 == ~t4_pc~0); 55166#L370-23 is_transmit4_triggered_~__retres1~4 := 0; 55164#L381-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55162#L382-7 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 55160#L777-21 assume !(0 != activate_threads_~tmp___3~0); 55158#L777-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55156#L389-21 assume !(1 == ~t5_pc~0); 55153#L389-23 is_transmit5_triggered_~__retres1~5 := 0; 55151#L400-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55149#L401-7 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 55147#L785-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 55145#L785-23 assume 1 == ~M_E~0;~M_E~0 := 2; 55143#L669-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55141#L674-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55139#L679-3 assume !(1 == ~T3_E~0); 55137#L684-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55135#L689-3 assume !(1 == ~T5_E~0); 55133#L694-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55131#L699-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55129#L704-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55127#L709-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55124#L714-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55121#L719-3 assume !(1 == ~E_5~0); 55118#L724-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55114#L454-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55108#L486-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55106#L487-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 55102#L949 assume !(0 == start_simulation_~tmp~3); 55103#L949-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55233#L454-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55227#L486-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55225#L487-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 55223#L904 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 55221#L911 stop_simulation_#res := stop_simulation_~__retres2~0; 55219#L912 start_simulation_#t~ret17 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 55216#L962 assume !(0 != start_simulation_~tmp___0~1); 53315#L930-1 [2019-12-07 18:26:22,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,291 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2019-12-07 18:26:22,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,291 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85873519] [2019-12-07 18:26:22,291 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,305 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:22,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,306 INFO L82 PathProgramCache]: Analyzing trace with hash -1899625596, now seen corresponding path program 1 times [2019-12-07 18:26:22,306 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,306 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752974375] [2019-12-07 18:26:22,306 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:22,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:22,326 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752974375] [2019-12-07 18:26:22,326 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:22,326 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:22,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057901295] [2019-12-07 18:26:22,326 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 18:26:22,326 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:22,327 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:22,327 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:22,327 INFO L87 Difference]: Start difference. First operand 3375 states and 4704 transitions. cyclomatic complexity: 1337 Second operand 3 states. [2019-12-07 18:26:22,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:22,359 INFO L93 Difference]: Finished difference Result 5777 states and 7930 transitions. [2019-12-07 18:26:22,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:22,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5777 states and 7930 transitions. [2019-12-07 18:26:22,374 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5660 [2019-12-07 18:26:22,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5777 states to 5777 states and 7930 transitions. [2019-12-07 18:26:22,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5777 [2019-12-07 18:26:22,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5777 [2019-12-07 18:26:22,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5777 states and 7930 transitions. [2019-12-07 18:26:22,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:22,388 INFO L688 BuchiCegarLoop]: Abstraction has 5777 states and 7930 transitions. [2019-12-07 18:26:22,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5777 states and 7930 transitions. [2019-12-07 18:26:22,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5777 to 5625. [2019-12-07 18:26:22,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5625 states. [2019-12-07 18:26:22,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5625 states to 5625 states and 7730 transitions. [2019-12-07 18:26:22,431 INFO L711 BuchiCegarLoop]: Abstraction has 5625 states and 7730 transitions. [2019-12-07 18:26:22,432 INFO L591 BuchiCegarLoop]: Abstraction has 5625 states and 7730 transitions. [2019-12-07 18:26:22,432 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 18:26:22,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5625 states and 7730 transitions. [2019-12-07 18:26:22,441 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5508 [2019-12-07 18:26:22,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:22,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:22,442 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,442 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,442 INFO L794 eck$LassoCheckResult]: Stem: 62857#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 62765#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 62644#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62600#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 62601#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62693#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62694#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62604#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62605#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62651#L441-1 assume !(0 == ~M_E~0); 62652#L601-1 assume !(0 == ~T1_E~0); 62654#L606-1 assume !(0 == ~T2_E~0); 62528#L611-1 assume !(0 == ~T3_E~0); 62529#L616-1 assume !(0 == ~T4_E~0); 62376#L621-1 assume !(0 == ~T5_E~0); 62377#L626-1 assume !(0 == ~E_M~0); 62476#L631-1 assume !(0 == ~E_1~0); 62477#L636-1 assume !(0 == ~E_2~0); 62724#L641-1 assume !(0 == ~E_3~0); 62725#L646-1 assume !(0 == ~E_4~0); 62640#L651-1 assume !(0 == ~E_5~0); 62641#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62942#L294 assume !(1 == ~m_pc~0); 62977#L294-2 is_master_triggered_~__retres1~0 := 0; 62999#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62830#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62831#L745 assume !(0 != activate_threads_~tmp~1); 63012#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62579#L313 assume !(1 == ~t1_pc~0); 62521#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 62578#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62518#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62391#L753 assume !(0 != activate_threads_~tmp___0~0); 62392#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62395#L332 assume !(1 == ~t2_pc~0); 62612#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 62610#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62611#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62634#L761 assume !(0 != activate_threads_~tmp___1~0); 62635#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62636#L351 assume !(1 == ~t3_pc~0); 62771#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 62772#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62793#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62799#L769 assume !(0 != activate_threads_~tmp___2~0); 62800#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62801#L370 assume !(1 == ~t4_pc~0); 62925#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 62923#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62924#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62939#L777 assume !(0 != activate_threads_~tmp___3~0); 62940#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62466#L389 assume !(1 == ~t5_pc~0); 62432#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 62433#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62464#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 62485#L785 assume !(0 != activate_threads_~tmp___4~0); 62486#L785-2 assume !(1 == ~M_E~0); 62487#L669-1 assume !(1 == ~T1_E~0); 62722#L674-1 assume !(1 == ~T2_E~0); 62723#L679-1 assume !(1 == ~T3_E~0); 62638#L684-1 assume !(1 == ~T4_E~0); 62639#L689-1 assume !(1 == ~T5_E~0); 62847#L694-1 assume !(1 == ~E_M~0); 62551#L699-1 assume !(1 == ~E_1~0); 62552#L704-1 assume !(1 == ~E_2~0); 62364#L709-1 assume !(1 == ~E_3~0); 62365#L714-1 assume !(1 == ~E_4~0); 62471#L719-1 assume !(1 == ~E_5~0); 62472#L930-1 assume !false; 67947#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 67946#L576 [2019-12-07 18:26:22,442 INFO L796 eck$LassoCheckResult]: Loop: 67946#L576 assume !false; 67945#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67944#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67477#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 62714#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 62541#L501 assume 0 != eval_~tmp~0; 62542#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 62711#L509 assume !(0 != eval_~tmp_ndt_1~0); 62712#L506 assume !(0 == ~t1_st~0); 65358#L520 assume !(0 == ~t2_st~0); 65350#L534 assume !(0 == ~t3_st~0); 65341#L548 assume !(0 == ~t4_st~0); 65335#L562 assume !(0 == ~t5_st~0); 67946#L576 [2019-12-07 18:26:22,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,442 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2019-12-07 18:26:22,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,442 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674919555] [2019-12-07 18:26:22,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,459 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:22,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 1 times [2019-12-07 18:26:22,460 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,460 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68897425] [2019-12-07 18:26:22,460 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,466 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:22,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1605223329, now seen corresponding path program 1 times [2019-12-07 18:26:22,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949750425] [2019-12-07 18:26:22,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:22,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:22,487 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949750425] [2019-12-07 18:26:22,487 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:22,487 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:22,488 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784816664] [2019-12-07 18:26:22,541 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:22,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:22,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:22,541 INFO L87 Difference]: Start difference. First operand 5625 states and 7730 transitions. cyclomatic complexity: 2117 Second operand 3 states. [2019-12-07 18:26:22,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:22,591 INFO L93 Difference]: Finished difference Result 10493 states and 14318 transitions. [2019-12-07 18:26:22,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:22,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10493 states and 14318 transitions. [2019-12-07 18:26:22,616 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10264 [2019-12-07 18:26:22,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10493 states to 10493 states and 14318 transitions. [2019-12-07 18:26:22,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10493 [2019-12-07 18:26:22,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10493 [2019-12-07 18:26:22,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10493 states and 14318 transitions. [2019-12-07 18:26:22,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:22,644 INFO L688 BuchiCegarLoop]: Abstraction has 10493 states and 14318 transitions. [2019-12-07 18:26:22,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states and 14318 transitions. [2019-12-07 18:26:22,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10013. [2019-12-07 18:26:22,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10013 states. [2019-12-07 18:26:22,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10013 states to 10013 states and 13694 transitions. [2019-12-07 18:26:22,714 INFO L711 BuchiCegarLoop]: Abstraction has 10013 states and 13694 transitions. [2019-12-07 18:26:22,714 INFO L591 BuchiCegarLoop]: Abstraction has 10013 states and 13694 transitions. [2019-12-07 18:26:22,714 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 18:26:22,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10013 states and 13694 transitions. [2019-12-07 18:26:22,731 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2019-12-07 18:26:22,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:22,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:22,731 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,731 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,732 INFO L794 eck$LassoCheckResult]: Stem: 78986#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 78892#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 78772#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 78727#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 78728#L416-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 78817#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78818#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78729#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78730#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78778#L441-1 assume !(0 == ~M_E~0); 78779#L601-1 assume !(0 == ~T1_E~0); 78782#L606-1 assume !(0 == ~T2_E~0); 78653#L611-1 assume !(0 == ~T3_E~0); 78654#L616-1 assume !(0 == ~T4_E~0); 78501#L621-1 assume !(0 == ~T5_E~0); 78502#L626-1 assume !(0 == ~E_M~0); 78600#L631-1 assume !(0 == ~E_1~0); 78601#L636-1 assume !(0 == ~E_2~0); 78850#L641-1 assume !(0 == ~E_3~0); 78851#L646-1 assume !(0 == ~E_4~0); 78768#L651-1 assume !(0 == ~E_5~0); 78769#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79061#L294 assume !(1 == ~m_pc~0); 79089#L294-2 is_master_triggered_~__retres1~0 := 0; 79109#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78956#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78957#L745 assume !(0 != activate_threads_~tmp~1); 79124#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78706#L313 assume !(1 == ~t1_pc~0); 78647#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 78704#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78705#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78517#L753 assume !(0 != activate_threads_~tmp___0~0); 78518#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78522#L332 assume !(1 == ~t2_pc~0); 78739#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 78737#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78738#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78762#L761 assume !(0 != activate_threads_~tmp___1~0); 78763#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78764#L351 assume !(1 == ~t3_pc~0); 78898#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 78899#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78921#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78928#L769 assume !(0 != activate_threads_~tmp___2~0); 78929#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78930#L370 assume !(1 == ~t4_pc~0); 79043#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 79038#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79039#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 79058#L777 assume !(0 != activate_threads_~tmp___3~0); 79059#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78589#L389 assume !(1 == ~t5_pc~0); 78554#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 78555#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78585#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78608#L785 assume !(0 != activate_threads_~tmp___4~0); 78609#L785-2 assume !(1 == ~M_E~0); 78611#L669-1 assume !(1 == ~T1_E~0); 78848#L674-1 assume !(1 == ~T2_E~0); 78849#L679-1 assume !(1 == ~T3_E~0); 78766#L684-1 assume !(1 == ~T4_E~0); 78767#L689-1 assume !(1 == ~T5_E~0); 78976#L694-1 assume !(1 == ~E_M~0); 78676#L699-1 assume !(1 == ~E_1~0); 78677#L704-1 assume !(1 == ~E_2~0); 78490#L709-1 assume !(1 == ~E_3~0); 78491#L714-1 assume !(1 == ~E_4~0); 78923#L719-1 assume !(1 == ~E_5~0); 79756#L930-1 assume !false; 79752#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 79713#L576 [2019-12-07 18:26:22,732 INFO L796 eck$LassoCheckResult]: Loop: 79713#L576 assume !false; 79714#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 79705#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 79706#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 79698#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 79699#L501 assume 0 != eval_~tmp~0; 79367#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 79368#L509 assume !(0 != eval_~tmp_ndt_1~0); 79745#L506 assume !(0 == ~t1_st~0); 79739#L520 assume !(0 == ~t2_st~0); 79737#L534 assume !(0 == ~t3_st~0); 79726#L548 assume !(0 == ~t4_st~0); 79724#L562 assume !(0 == ~t5_st~0); 79713#L576 [2019-12-07 18:26:22,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,732 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2019-12-07 18:26:22,732 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,732 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512990795] [2019-12-07 18:26:22,732 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:22,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:22,742 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512990795] [2019-12-07 18:26:22,742 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:22,742 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:22,742 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497428158] [2019-12-07 18:26:22,743 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 18:26:22,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,743 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 2 times [2019-12-07 18:26:22,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120935298] [2019-12-07 18:26:22,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,747 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:22,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:22,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:22,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:22,819 INFO L87 Difference]: Start difference. First operand 10013 states and 13694 transitions. cyclomatic complexity: 3693 Second operand 3 states. [2019-12-07 18:26:22,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:22,845 INFO L93 Difference]: Finished difference Result 9941 states and 13593 transitions. [2019-12-07 18:26:22,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:22,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9941 states and 13593 transitions. [2019-12-07 18:26:22,871 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2019-12-07 18:26:22,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9941 states to 9941 states and 13593 transitions. [2019-12-07 18:26:22,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9941 [2019-12-07 18:26:22,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9941 [2019-12-07 18:26:22,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9941 states and 13593 transitions. [2019-12-07 18:26:22,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:22,900 INFO L688 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2019-12-07 18:26:22,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9941 states and 13593 transitions. [2019-12-07 18:26:22,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9941 to 9941. [2019-12-07 18:26:22,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9941 states. [2019-12-07 18:26:22,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9941 states to 9941 states and 13593 transitions. [2019-12-07 18:26:22,971 INFO L711 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2019-12-07 18:26:22,971 INFO L591 BuchiCegarLoop]: Abstraction has 9941 states and 13593 transitions. [2019-12-07 18:26:22,971 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 18:26:22,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9941 states and 13593 transitions. [2019-12-07 18:26:22,988 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9784 [2019-12-07 18:26:22,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:22,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:22,989 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,989 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:22,989 INFO L794 eck$LassoCheckResult]: Stem: 98948#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 98851#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98728#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 98684#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 98685#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98773#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98774#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98686#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98687#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98734#L441-1 assume !(0 == ~M_E~0); 98735#L601-1 assume !(0 == ~T1_E~0); 98738#L606-1 assume !(0 == ~T2_E~0); 98611#L611-1 assume !(0 == ~T3_E~0); 98612#L616-1 assume !(0 == ~T4_E~0); 98461#L621-1 assume !(0 == ~T5_E~0); 98462#L626-1 assume !(0 == ~E_M~0); 98560#L631-1 assume !(0 == ~E_1~0); 98561#L636-1 assume !(0 == ~E_2~0); 98807#L641-1 assume !(0 == ~E_3~0); 98808#L646-1 assume !(0 == ~E_4~0); 98724#L651-1 assume !(0 == ~E_5~0); 98725#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99028#L294 assume !(1 == ~m_pc~0); 99059#L294-2 is_master_triggered_~__retres1~0 := 0; 99075#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98919#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98920#L745 assume !(0 != activate_threads_~tmp~1); 99089#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98666#L313 assume !(1 == ~t1_pc~0); 98605#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 98665#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98601#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98477#L753 assume !(0 != activate_threads_~tmp___0~0); 98478#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98482#L332 assume !(1 == ~t2_pc~0); 98696#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 98694#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98695#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98718#L761 assume !(0 != activate_threads_~tmp___1~0); 98719#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98720#L351 assume !(1 == ~t3_pc~0); 98858#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 98859#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98884#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98891#L769 assume !(0 != activate_threads_~tmp___2~0); 98892#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98893#L370 assume !(1 == ~t4_pc~0); 99011#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 99006#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 99007#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 99025#L777 assume !(0 != activate_threads_~tmp___3~0); 99026#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98549#L389 assume !(1 == ~t5_pc~0); 98515#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 98516#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98545#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98569#L785 assume !(0 != activate_threads_~tmp___4~0); 98570#L785-2 assume !(1 == ~M_E~0); 98571#L669-1 assume !(1 == ~T1_E~0); 98805#L674-1 assume !(1 == ~T2_E~0); 98806#L679-1 assume !(1 == ~T3_E~0); 98722#L684-1 assume !(1 == ~T4_E~0); 98723#L689-1 assume !(1 == ~T5_E~0); 98939#L694-1 assume !(1 == ~E_M~0); 98635#L699-1 assume !(1 == ~E_1~0); 98636#L704-1 assume !(1 == ~E_2~0); 98450#L709-1 assume !(1 == ~E_3~0); 98451#L714-1 assume !(1 == ~E_4~0); 98553#L719-1 assume !(1 == ~E_5~0); 98554#L930-1 assume !false; 101591#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 101585#L576 [2019-12-07 18:26:22,989 INFO L796 eck$LassoCheckResult]: Loop: 101585#L576 assume !false; 101579#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 101574#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 101568#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 101561#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 101553#L501 assume 0 != eval_~tmp~0; 101549#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 101544#L509 assume !(0 != eval_~tmp_ndt_1~0); 101184#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 101182#L523 assume !(0 != eval_~tmp_ndt_2~0); 101181#L520 assume !(0 == ~t2_st~0); 101178#L534 assume !(0 == ~t3_st~0); 101172#L548 assume !(0 == ~t4_st~0); 101170#L562 assume !(0 == ~t5_st~0); 101585#L576 [2019-12-07 18:26:22,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:22,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2019-12-07 18:26:22,990 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:22,990 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607902267] [2019-12-07 18:26:22,990 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:22,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:22,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,004 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,005 INFO L82 PathProgramCache]: Analyzing trace with hash -11527191, now seen corresponding path program 1 times [2019-12-07 18:26:23,005 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,005 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366298100] [2019-12-07 18:26:23,005 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,010 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,010 INFO L82 PathProgramCache]: Analyzing trace with hash 888960747, now seen corresponding path program 1 times [2019-12-07 18:26:23,010 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,010 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781103569] [2019-12-07 18:26:23,010 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:23,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:23,034 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781103569] [2019-12-07 18:26:23,034 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:23,034 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:23,034 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681735640] [2019-12-07 18:26:23,091 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:23,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:23,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:23,091 INFO L87 Difference]: Start difference. First operand 9941 states and 13593 transitions. cyclomatic complexity: 3664 Second operand 3 states. [2019-12-07 18:26:23,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:23,144 INFO L93 Difference]: Finished difference Result 13023 states and 17719 transitions. [2019-12-07 18:26:23,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:23,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13023 states and 17719 transitions. [2019-12-07 18:26:23,179 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12842 [2019-12-07 18:26:23,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13023 states to 13023 states and 17719 transitions. [2019-12-07 18:26:23,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13023 [2019-12-07 18:26:23,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13023 [2019-12-07 18:26:23,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13023 states and 17719 transitions. [2019-12-07 18:26:23,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:23,213 INFO L688 BuchiCegarLoop]: Abstraction has 13023 states and 17719 transitions. [2019-12-07 18:26:23,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13023 states and 17719 transitions. [2019-12-07 18:26:23,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13023 to 12647. [2019-12-07 18:26:23,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12647 states. [2019-12-07 18:26:23,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12647 states to 12647 states and 17231 transitions. [2019-12-07 18:26:23,305 INFO L711 BuchiCegarLoop]: Abstraction has 12647 states and 17231 transitions. [2019-12-07 18:26:23,305 INFO L591 BuchiCegarLoop]: Abstraction has 12647 states and 17231 transitions. [2019-12-07 18:26:23,305 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 18:26:23,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12647 states and 17231 transitions. [2019-12-07 18:26:23,330 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12466 [2019-12-07 18:26:23,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:23,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:23,331 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:23,331 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:23,331 INFO L794 eck$LassoCheckResult]: Stem: 121905#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 121811#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 121695#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 121650#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 121651#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121741#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121742#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121652#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121653#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121701#L441-1 assume !(0 == ~M_E~0); 121702#L601-1 assume !(0 == ~T1_E~0); 121705#L606-1 assume !(0 == ~T2_E~0); 121584#L611-1 assume !(0 == ~T3_E~0); 121585#L616-1 assume !(0 == ~T4_E~0); 121433#L621-1 assume !(0 == ~T5_E~0); 121434#L626-1 assume !(0 == ~E_M~0); 121532#L631-1 assume !(0 == ~E_1~0); 121533#L636-1 assume !(0 == ~E_2~0); 121768#L641-1 assume !(0 == ~E_3~0); 121769#L646-1 assume !(0 == ~E_4~0); 121691#L651-1 assume !(0 == ~E_5~0); 121692#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121993#L294 assume !(1 == ~m_pc~0); 122026#L294-2 is_master_triggered_~__retres1~0 := 0; 122041#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121876#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 121877#L745 assume !(0 != activate_threads_~tmp~1); 122052#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 121633#L313 assume !(1 == ~t1_pc~0); 121578#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 121632#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121573#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 121448#L753 assume !(0 != activate_threads_~tmp___0~0); 121449#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121454#L332 assume !(1 == ~t2_pc~0); 121662#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 121660#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121661#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121685#L761 assume !(0 != activate_threads_~tmp___1~0); 121686#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121687#L351 assume !(1 == ~t3_pc~0); 121817#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 121818#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121840#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121848#L769 assume !(0 != activate_threads_~tmp___2~0); 121849#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121850#L370 assume !(1 == ~t4_pc~0); 121972#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 121967#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121968#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 121990#L777 assume !(0 != activate_threads_~tmp___3~0); 121991#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 121521#L389 assume !(1 == ~t5_pc~0); 121487#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 121488#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 121517#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 121540#L785 assume !(0 != activate_threads_~tmp___4~0); 121541#L785-2 assume !(1 == ~M_E~0); 121543#L669-1 assume !(1 == ~T1_E~0); 121766#L674-1 assume !(1 == ~T2_E~0); 121767#L679-1 assume !(1 == ~T3_E~0); 121689#L684-1 assume !(1 == ~T4_E~0); 121690#L689-1 assume !(1 == ~T5_E~0); 121896#L694-1 assume !(1 == ~E_M~0); 121607#L699-1 assume !(1 == ~E_1~0); 121608#L704-1 assume !(1 == ~E_2~0); 121422#L709-1 assume !(1 == ~E_3~0); 121423#L714-1 assume !(1 == ~E_4~0); 121525#L719-1 assume !(1 == ~E_5~0); 121526#L930-1 assume !false; 124567#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 124565#L576 [2019-12-07 18:26:23,331 INFO L796 eck$LassoCheckResult]: Loop: 124565#L576 assume !false; 124563#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 124553#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 124551#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 124547#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 124215#L501 assume 0 != eval_~tmp~0; 124216#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 126035#L509 assume !(0 != eval_~tmp_ndt_1~0); 125406#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 125400#L523 assume !(0 != eval_~tmp_ndt_2~0); 125384#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 125377#L537 assume !(0 != eval_~tmp_ndt_3~0); 125371#L534 assume !(0 == ~t3_st~0); 125364#L548 assume !(0 == ~t4_st~0); 124571#L562 assume !(0 == ~t5_st~0); 124565#L576 [2019-12-07 18:26:23,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,332 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2019-12-07 18:26:23,332 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,332 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848674326] [2019-12-07 18:26:23,332 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,344 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,344 INFO L82 PathProgramCache]: Analyzing trace with hash -524557124, now seen corresponding path program 1 times [2019-12-07 18:26:23,345 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,345 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330846510] [2019-12-07 18:26:23,345 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,349 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1620765178, now seen corresponding path program 1 times [2019-12-07 18:26:23,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338674121] [2019-12-07 18:26:23,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:23,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:23,370 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338674121] [2019-12-07 18:26:23,370 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:23,370 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:23,370 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327196666] [2019-12-07 18:26:23,435 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:23,436 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:23,436 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:23,436 INFO L87 Difference]: Start difference. First operand 12647 states and 17231 transitions. cyclomatic complexity: 4596 Second operand 3 states. [2019-12-07 18:26:23,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:23,507 INFO L93 Difference]: Finished difference Result 23117 states and 31385 transitions. [2019-12-07 18:26:23,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:23,507 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23117 states and 31385 transitions. [2019-12-07 18:26:23,576 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22832 [2019-12-07 18:26:23,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23117 states to 23117 states and 31385 transitions. [2019-12-07 18:26:23,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23117 [2019-12-07 18:26:23,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23117 [2019-12-07 18:26:23,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23117 states and 31385 transitions. [2019-12-07 18:26:23,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:23,638 INFO L688 BuchiCegarLoop]: Abstraction has 23117 states and 31385 transitions. [2019-12-07 18:26:23,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23117 states and 31385 transitions. [2019-12-07 18:26:23,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23117 to 22325. [2019-12-07 18:26:23,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22325 states. [2019-12-07 18:26:23,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22325 states to 22325 states and 30401 transitions. [2019-12-07 18:26:23,821 INFO L711 BuchiCegarLoop]: Abstraction has 22325 states and 30401 transitions. [2019-12-07 18:26:23,821 INFO L591 BuchiCegarLoop]: Abstraction has 22325 states and 30401 transitions. [2019-12-07 18:26:23,821 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 18:26:23,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22325 states and 30401 transitions. [2019-12-07 18:26:23,861 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22040 [2019-12-07 18:26:23,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:23,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:23,861 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:23,861 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:23,862 INFO L794 eck$LassoCheckResult]: Stem: 157704#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 157603#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 157473#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 157427#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 157428#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157523#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157524#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157429#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157430#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157480#L441-1 assume !(0 == ~M_E~0); 157481#L601-1 assume !(0 == ~T1_E~0); 157485#L606-1 assume !(0 == ~T2_E~0); 157353#L611-1 assume !(0 == ~T3_E~0); 157354#L616-1 assume !(0 == ~T4_E~0); 157205#L621-1 assume !(0 == ~T5_E~0); 157206#L626-1 assume !(0 == ~E_M~0); 157302#L631-1 assume !(0 == ~E_1~0); 157303#L636-1 assume !(0 == ~E_2~0); 157556#L641-1 assume !(0 == ~E_3~0); 157557#L646-1 assume !(0 == ~E_4~0); 157469#L651-1 assume !(0 == ~E_5~0); 157470#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 157799#L294 assume !(1 == ~m_pc~0); 157836#L294-2 is_master_triggered_~__retres1~0 := 0; 157851#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 157671#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 157672#L745 assume !(0 != activate_threads_~tmp~1); 157870#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 157404#L313 assume !(1 == ~t1_pc~0); 157347#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 157403#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 157343#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 157220#L753 assume !(0 != activate_threads_~tmp___0~0); 157221#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 157225#L332 assume !(1 == ~t2_pc~0); 157439#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 157437#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157438#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 157463#L761 assume !(0 != activate_threads_~tmp___1~0); 157464#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157465#L351 assume !(1 == ~t3_pc~0); 157609#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 157610#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 157635#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157643#L769 assume !(0 != activate_threads_~tmp___2~0); 157644#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 157645#L370 assume !(1 == ~t4_pc~0); 157780#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 157775#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 157776#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 157796#L777 assume !(0 != activate_threads_~tmp___3~0); 157797#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157290#L389 assume !(1 == ~t5_pc~0); 157258#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 157259#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157287#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 157310#L785 assume !(0 != activate_threads_~tmp___4~0); 157311#L785-2 assume !(1 == ~M_E~0); 157313#L669-1 assume !(1 == ~T1_E~0); 157554#L674-1 assume !(1 == ~T2_E~0); 157555#L679-1 assume !(1 == ~T3_E~0); 157467#L684-1 assume !(1 == ~T4_E~0); 157468#L689-1 assume !(1 == ~T5_E~0); 157691#L694-1 assume !(1 == ~E_M~0); 157377#L699-1 assume !(1 == ~E_1~0); 157378#L704-1 assume !(1 == ~E_2~0); 157194#L709-1 assume !(1 == ~E_3~0); 157195#L714-1 assume !(1 == ~E_4~0); 157295#L719-1 assume !(1 == ~E_5~0); 157296#L930-1 assume !false; 161201#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 161196#L576 [2019-12-07 18:26:23,862 INFO L796 eck$LassoCheckResult]: Loop: 161196#L576 assume !false; 161194#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161191#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161188#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161186#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 161184#L501 assume 0 != eval_~tmp~0; 161181#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 161177#L509 assume !(0 != eval_~tmp_ndt_1~0); 161174#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 161080#L523 assume !(0 != eval_~tmp_ndt_2~0); 161173#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 162682#L537 assume !(0 != eval_~tmp_ndt_3~0); 161216#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 161214#L551 assume !(0 != eval_~tmp_ndt_4~0); 161211#L548 assume !(0 == ~t4_st~0); 161205#L562 assume !(0 == ~t5_st~0); 161196#L576 [2019-12-07 18:26:23,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,862 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2019-12-07 18:26:23,862 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,862 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979338546] [2019-12-07 18:26:23,862 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,876 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,876 INFO L82 PathProgramCache]: Analyzing trace with hash 913205966, now seen corresponding path program 1 times [2019-12-07 18:26:23,876 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,876 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049420090] [2019-12-07 18:26:23,876 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:23,881 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:23,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:23,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1301279408, now seen corresponding path program 1 times [2019-12-07 18:26:23,882 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:23,882 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860761084] [2019-12-07 18:26:23,882 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:23,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:23,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:23,900 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860761084] [2019-12-07 18:26:23,900 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:23,900 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:26:23,900 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842118080] [2019-12-07 18:26:23,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:23,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:23,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:23,976 INFO L87 Difference]: Start difference. First operand 22325 states and 30401 transitions. cyclomatic complexity: 8088 Second operand 3 states. [2019-12-07 18:26:24,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:24,053 INFO L93 Difference]: Finished difference Result 29707 states and 40327 transitions. [2019-12-07 18:26:24,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:24,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29707 states and 40327 transitions. [2019-12-07 18:26:24,132 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 29366 [2019-12-07 18:26:24,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29707 states to 29707 states and 40327 transitions. [2019-12-07 18:26:24,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29707 [2019-12-07 18:26:24,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29707 [2019-12-07 18:26:24,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29707 states and 40327 transitions. [2019-12-07 18:26:24,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:24,210 INFO L688 BuchiCegarLoop]: Abstraction has 29707 states and 40327 transitions. [2019-12-07 18:26:24,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29707 states and 40327 transitions. [2019-12-07 18:26:24,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29707 to 29227. [2019-12-07 18:26:24,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29227 states. [2019-12-07 18:26:24,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29227 states to 29227 states and 39703 transitions. [2019-12-07 18:26:24,393 INFO L711 BuchiCegarLoop]: Abstraction has 29227 states and 39703 transitions. [2019-12-07 18:26:24,393 INFO L591 BuchiCegarLoop]: Abstraction has 29227 states and 39703 transitions. [2019-12-07 18:26:24,394 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 18:26:24,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29227 states and 39703 transitions. [2019-12-07 18:26:24,454 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 28886 [2019-12-07 18:26:24,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:24,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:24,455 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:24,455 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:24,455 INFO L794 eck$LassoCheckResult]: Stem: 209748#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 209652#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 209518#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 209474#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 209475#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 209571#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 209572#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209478#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209479#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 209527#L441-1 assume !(0 == ~M_E~0); 209528#L601-1 assume !(0 == ~T1_E~0); 209530#L606-1 assume !(0 == ~T2_E~0); 209399#L611-1 assume !(0 == ~T3_E~0); 209400#L616-1 assume !(0 == ~T4_E~0); 209245#L621-1 assume !(0 == ~T5_E~0); 209246#L626-1 assume !(0 == ~E_M~0); 209345#L631-1 assume !(0 == ~E_1~0); 209346#L636-1 assume !(0 == ~E_2~0); 209603#L641-1 assume !(0 == ~E_3~0); 209604#L646-1 assume !(0 == ~E_4~0); 209514#L651-1 assume !(0 == ~E_5~0); 209515#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 209841#L294 assume !(1 == ~m_pc~0); 209874#L294-2 is_master_triggered_~__retres1~0 := 0; 209894#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 209720#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 209721#L745 assume !(0 != activate_threads_~tmp~1); 209911#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 209452#L313 assume !(1 == ~t1_pc~0); 209391#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 209451#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 209388#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 209261#L753 assume !(0 != activate_threads_~tmp___0~0); 209262#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 209265#L332 assume !(1 == ~t2_pc~0); 209486#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 209484#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 209485#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 209508#L761 assume !(0 != activate_threads_~tmp___1~0); 209509#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 209510#L351 assume !(1 == ~t3_pc~0); 209658#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 209659#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 209681#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 209689#L769 assume !(0 != activate_threads_~tmp___2~0); 209690#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 209691#L370 assume !(1 == ~t4_pc~0); 209819#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 209817#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 209818#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 209838#L777 assume !(0 != activate_threads_~tmp___3~0); 209839#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 209335#L389 assume !(1 == ~t5_pc~0); 209302#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 209303#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 209333#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 209355#L785 assume !(0 != activate_threads_~tmp___4~0); 209356#L785-2 assume !(1 == ~M_E~0); 209357#L669-1 assume !(1 == ~T1_E~0); 209601#L674-1 assume !(1 == ~T2_E~0); 209602#L679-1 assume !(1 == ~T3_E~0); 209512#L684-1 assume !(1 == ~T4_E~0); 209513#L689-1 assume !(1 == ~T5_E~0); 209737#L694-1 assume !(1 == ~E_M~0); 209422#L699-1 assume !(1 == ~E_1~0); 209423#L704-1 assume !(1 == ~E_2~0); 209234#L709-1 assume !(1 == ~E_3~0); 209235#L714-1 assume !(1 == ~E_4~0); 209338#L719-1 assume !(1 == ~E_5~0); 209339#L930-1 assume !false; 218614#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 218612#L576 [2019-12-07 18:26:24,455 INFO L796 eck$LassoCheckResult]: Loop: 218612#L576 assume !false; 218609#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 218606#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 218604#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 218602#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 218600#L501 assume 0 != eval_~tmp~0; 218598#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 218596#L509 assume !(0 != eval_~tmp_ndt_1~0); 218594#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 218484#L523 assume !(0 != eval_~tmp_ndt_2~0); 218592#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 219244#L537 assume !(0 != eval_~tmp_ndt_3~0); 218628#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 218625#L551 assume !(0 != eval_~tmp_ndt_4~0); 218623#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 218620#L565 assume !(0 != eval_~tmp_ndt_5~0); 218618#L562 assume !(0 == ~t5_st~0); 218612#L576 [2019-12-07 18:26:24,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:24,455 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2019-12-07 18:26:24,455 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:24,456 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061467292] [2019-12-07 18:26:24,456 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:24,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:24,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:24,470 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:24,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:24,470 INFO L82 PathProgramCache]: Analyzing trace with hash -1755558441, now seen corresponding path program 1 times [2019-12-07 18:26:24,470 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:24,470 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644518498] [2019-12-07 18:26:24,470 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:24,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:24,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:24,475 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:24,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:24,475 INFO L82 PathProgramCache]: Analyzing trace with hash -1685128299, now seen corresponding path program 1 times [2019-12-07 18:26:24,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:24,475 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817432418] [2019-12-07 18:26:24,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:24,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:26:24,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:26:24,558 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817432418] [2019-12-07 18:26:24,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:26:24,558 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:26:24,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18097550] [2019-12-07 18:26:24,640 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:26:24,640 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:26:24,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:26:24,640 INFO L87 Difference]: Start difference. First operand 29227 states and 39703 transitions. cyclomatic complexity: 10488 Second operand 3 states. [2019-12-07 18:26:24,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:26:24,753 INFO L93 Difference]: Finished difference Result 50701 states and 68749 transitions. [2019-12-07 18:26:24,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:26:24,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50701 states and 68749 transitions. [2019-12-07 18:26:24,903 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 50096 [2019-12-07 18:26:25,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50701 states to 50701 states and 68749 transitions. [2019-12-07 18:26:25,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50701 [2019-12-07 18:26:25,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50701 [2019-12-07 18:26:25,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50701 states and 68749 transitions. [2019-12-07 18:26:25,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 18:26:25,042 INFO L688 BuchiCegarLoop]: Abstraction has 50701 states and 68749 transitions. [2019-12-07 18:26:25,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50701 states and 68749 transitions. [2019-12-07 18:26:25,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50701 to 50269. [2019-12-07 18:26:25,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50269 states. [2019-12-07 18:26:25,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50269 states to 50269 states and 68317 transitions. [2019-12-07 18:26:25,376 INFO L711 BuchiCegarLoop]: Abstraction has 50269 states and 68317 transitions. [2019-12-07 18:26:25,376 INFO L591 BuchiCegarLoop]: Abstraction has 50269 states and 68317 transitions. [2019-12-07 18:26:25,376 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 18:26:25,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50269 states and 68317 transitions. [2019-12-07 18:26:25,506 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 49664 [2019-12-07 18:26:25,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 18:26:25,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 18:26:25,507 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:25,507 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:26:25,508 INFO L794 eck$LassoCheckResult]: Stem: 289690#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 289593#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 289461#L893 havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 289413#L409 assume 1 == ~m_i~0;~m_st~0 := 0; 289414#L416-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 289512#L421-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 289513#L426-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 289417#L431-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 289418#L436-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 289469#L441-1 assume !(0 == ~M_E~0); 289470#L601-1 assume !(0 == ~T1_E~0); 289472#L606-1 assume !(0 == ~T2_E~0); 289338#L611-1 assume !(0 == ~T3_E~0); 289339#L616-1 assume !(0 == ~T4_E~0); 289181#L621-1 assume !(0 == ~T5_E~0); 289182#L626-1 assume !(0 == ~E_M~0); 289284#L631-1 assume !(0 == ~E_1~0); 289285#L636-1 assume !(0 == ~E_2~0); 289541#L641-1 assume !(0 == ~E_3~0); 289542#L646-1 assume !(0 == ~E_4~0); 289457#L651-1 assume !(0 == ~E_5~0); 289458#L656-1 havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289782#L294 assume !(1 == ~m_pc~0); 289826#L294-2 is_master_triggered_~__retres1~0 := 0; 289845#L305 is_master_triggered_#res := is_master_triggered_~__retres1~0; 289662#L306 activate_threads_#t~ret9 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 289663#L745 assume !(0 != activate_threads_~tmp~1); 289861#L745-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 289390#L313 assume !(1 == ~t1_pc~0); 289330#L313-2 is_transmit1_triggered_~__retres1~1 := 0; 289389#L324 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 289327#L325 activate_threads_#t~ret10 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 289197#L753 assume !(0 != activate_threads_~tmp___0~0); 289198#L753-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 289201#L332 assume !(1 == ~t2_pc~0); 289425#L332-2 is_transmit2_triggered_~__retres1~2 := 0; 289423#L343 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 289424#L344 activate_threads_#t~ret11 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 289451#L761 assume !(0 != activate_threads_~tmp___1~0); 289452#L761-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 289453#L351 assume !(1 == ~t3_pc~0); 289599#L351-2 is_transmit3_triggered_~__retres1~3 := 0; 289600#L362 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 289622#L363 activate_threads_#t~ret12 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 289631#L769 assume !(0 != activate_threads_~tmp___2~0); 289632#L769-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 289633#L370 assume !(1 == ~t4_pc~0); 289757#L370-2 is_transmit4_triggered_~__retres1~4 := 0; 289755#L381 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 289756#L382 activate_threads_#t~ret13 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 289779#L777 assume !(0 != activate_threads_~tmp___3~0); 289780#L777-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 289273#L389 assume !(1 == ~t5_pc~0); 289239#L389-2 is_transmit5_triggered_~__retres1~5 := 0; 289240#L400 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 289270#L401 activate_threads_#t~ret14 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 289293#L785 assume !(0 != activate_threads_~tmp___4~0); 289294#L785-2 assume !(1 == ~M_E~0); 289295#L669-1 assume !(1 == ~T1_E~0); 289539#L674-1 assume !(1 == ~T2_E~0); 289540#L679-1 assume !(1 == ~T3_E~0); 289455#L684-1 assume !(1 == ~T4_E~0); 289456#L689-1 assume !(1 == ~T5_E~0); 289679#L694-1 assume !(1 == ~E_M~0); 289361#L699-1 assume !(1 == ~E_1~0); 289362#L704-1 assume !(1 == ~E_2~0); 289170#L709-1 assume !(1 == ~E_3~0); 289171#L714-1 assume !(1 == ~E_4~0); 289276#L719-1 assume !(1 == ~E_5~0); 289277#L930-1 assume !false; 308061#L931 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 308053#L576 [2019-12-07 18:26:25,508 INFO L796 eck$LassoCheckResult]: Loop: 308053#L576 assume !false; 308048#L497 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 308042#L454 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 308035#L486 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 308027#L487 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 308019#L501 assume 0 != eval_~tmp~0; 308011#L501-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 307989#L509 assume !(0 != eval_~tmp_ndt_1~0); 307979#L506 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 307904#L523 assume !(0 != eval_~tmp_ndt_2~0); 307972#L520 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 308107#L537 assume !(0 != eval_~tmp_ndt_3~0); 308100#L534 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 306709#L551 assume !(0 != eval_~tmp_ndt_4~0); 308084#L548 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 308075#L565 assume !(0 != eval_~tmp_ndt_5~0); 308069#L562 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 303597#L579 assume !(0 != eval_~tmp_ndt_6~0); 308053#L576 [2019-12-07 18:26:25,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:25,508 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2019-12-07 18:26:25,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:25,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145496487] [2019-12-07 18:26:25,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:25,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,524 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:25,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:25,525 INFO L82 PathProgramCache]: Analyzing trace with hash 1412259251, now seen corresponding path program 1 times [2019-12-07 18:26:25,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:25,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327449374] [2019-12-07 18:26:25,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:25,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,530 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:25,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:26:25,531 INFO L82 PathProgramCache]: Analyzing trace with hash -699373643, now seen corresponding path program 1 times [2019-12-07 18:26:25,531 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:26:25,531 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045837523] [2019-12-07 18:26:25,531 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:26:25,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:26:25,548 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:26:26,124 WARN L192 SmtUtils]: Spent 465.00 ms on a formula simplification. DAG size of input: 198 DAG size of output: 132 [2019-12-07 18:26:26,251 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 06:26:26 BoogieIcfgContainer [2019-12-07 18:26:26,251 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 18:26:26,251 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:26:26,251 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:26:26,251 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:26:26,252 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:26:19" (3/4) ... [2019-12-07 18:26:26,253 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 18:26:26,301 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_4a69f467-1c04-4504-9369-091553d756a7/bin/uautomizer/witness.graphml [2019-12-07 18:26:26,301 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:26:26,302 INFO L168 Benchmark]: Toolchain (without parser) took 7583.74 ms. Allocated memory was 1.0 GB in the beginning and 1.6 GB in the end (delta: 524.3 MB). Free memory was 947.8 MB in the beginning and 1.2 GB in the end (delta: -249.9 MB). Peak memory consumption was 274.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,302 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:26:26,303 INFO L168 Benchmark]: CACSL2BoogieTranslator took 263.77 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 947.8 MB in the beginning and 1.1 GB in the end (delta: -138.6 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,303 INFO L168 Benchmark]: Boogie Procedure Inliner took 46.64 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,303 INFO L168 Benchmark]: Boogie Preprocessor took 42.23 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,303 INFO L168 Benchmark]: RCFGBuilder took 684.61 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 960.7 MB in the end (delta: 115.1 MB). Peak memory consumption was 115.1 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,304 INFO L168 Benchmark]: BuchiAutomizer took 6493.18 ms. Allocated memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: 426.2 MB). Free memory was 960.7 MB in the beginning and 1.2 GB in the end (delta: -241.4 MB). Peak memory consumption was 717.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,304 INFO L168 Benchmark]: Witness Printer took 50.11 ms. Allocated memory is still 1.6 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 4.3 MB). Peak memory consumption was 4.3 MB. Max. memory is 11.5 GB. [2019-12-07 18:26:26,306 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 963.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 263.77 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 98.0 MB). Free memory was 947.8 MB in the beginning and 1.1 GB in the end (delta: -138.6 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 46.64 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 42.23 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 684.61 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 960.7 MB in the end (delta: 115.1 MB). Peak memory consumption was 115.1 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 6493.18 ms. Allocated memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: 426.2 MB). Free memory was 960.7 MB in the beginning and 1.2 GB in the end (delta: -241.4 MB). Peak memory consumption was 717.7 MB. Max. memory is 11.5 GB. * Witness Printer took 50.11 ms. Allocated memory is still 1.6 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 4.3 MB). Peak memory consumption was 4.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 50269 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.4s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.4s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 21 MinimizatonAttempts, 13616 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.0s. Biggest automaton had 50269 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17284 SDtfs, 18776 SDslu, 14402 SDs, 0 SdLazy, 479 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 496]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, token=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34059600=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@685474c0=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51711a0e=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d66f568=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e2192d6=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21ab5a03=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@349363fa=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@467f9a51=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3dffb4af=0, local=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12dc89bd=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c361f4d=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1aaf3b1d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12f78a4c=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@76d3758=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@69d51072=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 496]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int t5_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int t5_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int T5_E = 2; [L38] int E_M = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L51] int token ; [L53] int local ; [L975] int __retres1 ; [L886] m_i = 1 [L887] t1_i = 1 [L888] t2_i = 1 [L889] t3_i = 1 [L890] t4_i = 1 [L891] t5_i = 1 [L916] int kernel_st ; [L917] int tmp ; [L918] int tmp___0 ; [L922] kernel_st = 0 [L416] COND TRUE m_i == 1 [L417] m_st = 0 [L421] COND TRUE t1_i == 1 [L422] t1_st = 0 [L426] COND TRUE t2_i == 1 [L427] t2_st = 0 [L431] COND TRUE t3_i == 1 [L432] t3_st = 0 [L436] COND TRUE t4_i == 1 [L437] t4_st = 0 [L441] COND TRUE t5_i == 1 [L442] t5_st = 0 [L601] COND FALSE !(M_E == 0) [L606] COND FALSE !(T1_E == 0) [L611] COND FALSE !(T2_E == 0) [L616] COND FALSE !(T3_E == 0) [L621] COND FALSE !(T4_E == 0) [L626] COND FALSE !(T5_E == 0) [L631] COND FALSE !(E_M == 0) [L636] COND FALSE !(E_1 == 0) [L641] COND FALSE !(E_2 == 0) [L646] COND FALSE !(E_3 == 0) [L651] COND FALSE !(E_4 == 0) [L656] COND FALSE !(E_5 == 0) [L734] int tmp ; [L735] int tmp___0 ; [L736] int tmp___1 ; [L737] int tmp___2 ; [L738] int tmp___3 ; [L739] int tmp___4 ; [L291] int __retres1 ; [L294] COND FALSE !(m_pc == 1) [L304] __retres1 = 0 [L306] return (__retres1); [L743] tmp = is_master_triggered() [L745] COND FALSE !(\read(tmp)) [L310] int __retres1 ; [L313] COND FALSE !(t1_pc == 1) [L323] __retres1 = 0 [L325] return (__retres1); [L751] tmp___0 = is_transmit1_triggered() [L753] COND FALSE !(\read(tmp___0)) [L329] int __retres1 ; [L332] COND FALSE !(t2_pc == 1) [L342] __retres1 = 0 [L344] return (__retres1); [L759] tmp___1 = is_transmit2_triggered() [L761] COND FALSE !(\read(tmp___1)) [L348] int __retres1 ; [L351] COND FALSE !(t3_pc == 1) [L361] __retres1 = 0 [L363] return (__retres1); [L767] tmp___2 = is_transmit3_triggered() [L769] COND FALSE !(\read(tmp___2)) [L367] int __retres1 ; [L370] COND FALSE !(t4_pc == 1) [L380] __retres1 = 0 [L382] return (__retres1); [L775] tmp___3 = is_transmit4_triggered() [L777] COND FALSE !(\read(tmp___3)) [L386] int __retres1 ; [L389] COND FALSE !(t5_pc == 1) [L399] __retres1 = 0 [L401] return (__retres1); [L783] tmp___4 = is_transmit5_triggered() [L785] COND FALSE !(\read(tmp___4)) [L669] COND FALSE !(M_E == 1) [L674] COND FALSE !(T1_E == 1) [L679] COND FALSE !(T2_E == 1) [L684] COND FALSE !(T3_E == 1) [L689] COND FALSE !(T4_E == 1) [L694] COND FALSE !(T5_E == 1) [L699] COND FALSE !(E_M == 1) [L704] COND FALSE !(E_1 == 1) [L709] COND FALSE !(E_2 == 1) [L714] COND FALSE !(E_3 == 1) [L719] COND FALSE !(E_4 == 1) [L724] COND FALSE !(E_5 == 1) [L930] COND TRUE 1 [L933] kernel_st = 1 [L492] int tmp ; Loop: [L496] COND TRUE 1 [L451] int __retres1 ; [L454] COND TRUE m_st == 0 [L455] __retres1 = 1 [L487] return (__retres1); [L499] tmp = exists_runnable_thread() [L501] COND TRUE \read(tmp) [L506] COND TRUE m_st == 0 [L507] int tmp_ndt_1; [L508] tmp_ndt_1 = __VERIFIER_nondet_int() [L509] COND FALSE !(\read(tmp_ndt_1)) [L520] COND TRUE t1_st == 0 [L521] int tmp_ndt_2; [L522] tmp_ndt_2 = __VERIFIER_nondet_int() [L523] COND FALSE !(\read(tmp_ndt_2)) [L534] COND TRUE t2_st == 0 [L535] int tmp_ndt_3; [L536] tmp_ndt_3 = __VERIFIER_nondet_int() [L537] COND FALSE !(\read(tmp_ndt_3)) [L548] COND TRUE t3_st == 0 [L549] int tmp_ndt_4; [L550] tmp_ndt_4 = __VERIFIER_nondet_int() [L551] COND FALSE !(\read(tmp_ndt_4)) [L562] COND TRUE t4_st == 0 [L563] int tmp_ndt_5; [L564] tmp_ndt_5 = __VERIFIER_nondet_int() [L565] COND FALSE !(\read(tmp_ndt_5)) [L576] COND TRUE t5_st == 0 [L577] int tmp_ndt_6; [L578] tmp_ndt_6 = __VERIFIER_nondet_int() [L579] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...