./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bfc241aa60000364b71cc8fe0c41aa369b7207cc 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 13:00:24,677 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 13:00:24,678 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 13:00:24,687 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 13:00:24,687 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 13:00:24,688 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 13:00:24,689 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 13:00:24,690 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 13:00:24,692 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 13:00:24,693 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 13:00:24,694 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 13:00:24,695 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 13:00:24,695 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 13:00:24,696 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 13:00:24,697 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 13:00:24,698 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 13:00:24,698 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 13:00:24,699 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 13:00:24,701 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 13:00:24,703 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 13:00:24,704 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 13:00:24,705 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 13:00:24,706 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 13:00:24,707 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 13:00:24,709 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 13:00:24,709 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 13:00:24,709 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 13:00:24,710 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 13:00:24,710 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 13:00:24,711 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 13:00:24,711 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 13:00:24,712 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 13:00:24,712 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 13:00:24,713 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 13:00:24,713 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 13:00:24,714 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 13:00:24,714 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 13:00:24,714 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 13:00:24,714 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 13:00:24,715 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 13:00:24,716 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 13:00:24,716 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-12-07 13:00:24,730 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 13:00:24,730 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 13:00:24,731 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 13:00:24,731 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 13:00:24,731 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 13:00:24,731 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-12-07 13:00:24,731 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-12-07 13:00:24,731 INFO L138 SettingsManager]: * Use old map elimination=false [2019-12-07 13:00:24,732 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-12-07 13:00:24,732 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-12-07 13:00:24,732 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-12-07 13:00:24,732 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 13:00:24,732 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 13:00:24,732 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-12-07 13:00:24,733 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-12-07 13:00:24,734 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-12-07 13:00:24,734 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 13:00:24,734 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 13:00:24,735 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-12-07 13:00:24,735 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-12-07 13:00:24,735 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bfc241aa60000364b71cc8fe0c41aa369b7207cc [2019-12-07 13:00:24,842 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 13:00:24,852 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 13:00:24,855 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 13:00:24,856 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 13:00:24,856 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 13:00:24,857 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2019-12-07 13:00:24,904 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/data/94c9ff137/777c44ace16947fab0d4cb61fcd2d235/FLAG515864808 [2019-12-07 13:00:25,257 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 13:00:25,257 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2019-12-07 13:00:25,266 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/data/94c9ff137/777c44ace16947fab0d4cb61fcd2d235/FLAG515864808 [2019-12-07 13:00:25,274 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/data/94c9ff137/777c44ace16947fab0d4cb61fcd2d235 [2019-12-07 13:00:25,276 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 13:00:25,277 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 13:00:25,278 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 13:00:25,278 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 13:00:25,280 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 13:00:25,280 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,282 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38a937d5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25, skipping insertion in model container [2019-12-07 13:00:25,282 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,289 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 13:00:25,321 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 13:00:25,513 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:00:25,517 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 13:00:25,560 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:00:25,576 INFO L208 MainTranslator]: Completed translation [2019-12-07 13:00:25,577 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25 WrapperNode [2019-12-07 13:00:25,577 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 13:00:25,577 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 13:00:25,577 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 13:00:25,577 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 13:00:25,583 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,590 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,632 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 13:00:25,633 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 13:00:25,633 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 13:00:25,633 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 13:00:25,639 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,639 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,644 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,645 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,663 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,679 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,682 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... [2019-12-07 13:00:25,690 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 13:00:25,691 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 13:00:25,691 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 13:00:25,691 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 13:00:25,691 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:25,741 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 13:00:25,741 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 13:00:26,723 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 13:00:26,723 INFO L287 CfgBuilder]: Removed 327 assume(true) statements. [2019-12-07 13:00:26,725 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:00:26 BoogieIcfgContainer [2019-12-07 13:00:26,725 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 13:00:26,726 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-12-07 13:00:26,726 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-12-07 13:00:26,728 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-12-07 13:00:26,728 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 13:00:26,729 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 01:00:25" (1/3) ... [2019-12-07 13:00:26,729 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@76565563 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:00:26, skipping insertion in model container [2019-12-07 13:00:26,729 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 13:00:26,729 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:00:25" (2/3) ... [2019-12-07 13:00:26,730 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@76565563 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 01:00:26, skipping insertion in model container [2019-12-07 13:00:26,730 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-12-07 13:00:26,730 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:00:26" (3/3) ... [2019-12-07 13:00:26,731 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2019-12-07 13:00:26,760 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-12-07 13:00:26,760 INFO L357 BuchiCegarLoop]: Hoare is false [2019-12-07 13:00:26,760 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-12-07 13:00:26,761 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 13:00:26,761 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 13:00:26,761 INFO L361 BuchiCegarLoop]: Difference is false [2019-12-07 13:00:26,761 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 13:00:26,761 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-12-07 13:00:26,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states. [2019-12-07 13:00:26,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 864 [2019-12-07 13:00:26,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:26,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:26,844 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:26,844 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:26,845 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-12-07 13:00:26,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states. [2019-12-07 13:00:26,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 864 [2019-12-07 13:00:26,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:26,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:26,860 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:26,860 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:26,867 INFO L794 eck$LassoCheckResult]: Stem: 330#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 267#L-1true havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 720#L1268true havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 444#L592true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L599-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 770#L604-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 550#L609-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 445#L614-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 232#L619-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 981#L624-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 630#L629-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 413#L634-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 160#L639-1true assume 0 == ~M_E~0;~M_E~0 := 1; 448#L856-1true assume !(0 == ~T1_E~0); 238#L861-1true assume !(0 == ~T2_E~0); 865#L866-1true assume !(0 == ~T3_E~0); 649#L871-1true assume !(0 == ~T4_E~0); 430#L876-1true assume !(0 == ~T5_E~0); 316#L881-1true assume !(0 == ~T6_E~0); 81#L886-1true assume !(0 == ~T7_E~0); 860#L891-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 510#L896-1true assume !(0 == ~E_M~0); 287#L901-1true assume !(0 == ~E_1~0); 58#L906-1true assume !(0 == ~E_2~0); 953#L911-1true assume !(0 == ~E_3~0); 714#L916-1true assume !(0 == ~E_4~0); 376#L921-1true assume !(0 == ~E_5~0); 124#L926-1true assume !(0 == ~E_6~0); 925#L931-1true assume 0 == ~E_7~0;~E_7~0 := 1; 806#L936-1true assume !(0 == ~E_8~0); 592#L941-1true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104#L420true assume !(1 == ~m_pc~0); 107#L420-2true is_master_triggered_~__retres1~0 := 0; 636#L431true is_master_triggered_#res := is_master_triggered_~__retres1~0; 706#L432true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 934#L1063true assume !(0 != activate_threads_~tmp~1); 936#L1063-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 279#L439true assume 1 == ~t1_pc~0; 343#L440true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 755#L450true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 829#L451true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 690#L1071true assume !(0 != activate_threads_~tmp___0~0); 679#L1071-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 418#L458true assume !(1 == ~t2_pc~0); 403#L458-2true is_transmit2_triggered_~__retres1~2 := 0; 912#L469true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 976#L470true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 323#L1079true assume !(0 != activate_threads_~tmp___1~0); 325#L1079-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 537#L477true assume 1 == ~t3_pc~0; 609#L478true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 40#L488true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 95#L489true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 967#L1087true assume !(0 != activate_threads_~tmp___2~0); 957#L1087-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 676#L496true assume !(1 == ~t4_pc~0); 663#L496-2true is_transmit4_triggered_~__retres1~4 := 0; 166#L507true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 115#L508true activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 600#L1095true assume !(0 != activate_threads_~tmp___3~0); 601#L1095-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 939#L515true assume 1 == ~t5_pc~0; 752#L516true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 434#L526true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 286#L527true activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 261#L1103true assume !(0 != activate_threads_~tmp___4~0); 246#L1103-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 74#L534true assume 1 == ~t6_pc~0; 907#L535true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 578#L545true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 415#L546true activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 735#L1111true assume !(0 != activate_threads_~tmp___5~0); 738#L1111-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 215#L553true assume !(1 == ~t7_pc~0); 219#L553-2true is_transmit7_triggered_~__retres1~7 := 0; 702#L564true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 551#L565true activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 399#L1119true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 386#L1119-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 358#L572true assume 1 == ~t8_pc~0; 162#L573true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 844#L583true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 673#L584true activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23#L1127true assume !(0 != activate_threads_~tmp___7~0); 24#L1127-2true assume !(1 == ~M_E~0); 862#L954-1true assume !(1 == ~T1_E~0); 645#L959-1true assume !(1 == ~T2_E~0); 428#L964-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 310#L969-1true assume !(1 == ~T4_E~0); 79#L974-1true assume !(1 == ~T5_E~0); 856#L979-1true assume !(1 == ~T6_E~0); 505#L984-1true assume !(1 == ~T7_E~0); 290#L989-1true assume !(1 == ~T8_E~0); 178#L994-1true assume !(1 == ~E_M~0); 959#L999-1true assume !(1 == ~E_1~0); 719#L1004-1true assume 1 == ~E_2~0;~E_2~0 := 2; 390#L1009-1true assume !(1 == ~E_3~0); 129#L1014-1true assume !(1 == ~E_4~0); 938#L1019-1true assume !(1 == ~E_5~0); 813#L1024-1true assume !(1 == ~E_6~0); 588#L1029-1true assume !(1 == ~E_7~0); 367#L1034-1true assume !(1 == ~E_8~0); 64#L1305-1true [2019-12-07 13:00:26,869 INFO L796 eck$LassoCheckResult]: Loop: 64#L1305-1true assume !false; 900#L1306true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 596#L831true assume !true; 772#L846true start_simulation_~kernel_st~0 := 2; 446#L592-1true start_simulation_~kernel_st~0 := 3; 449#L856-2true assume 0 == ~M_E~0;~M_E~0 := 1; 439#L856-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 242#L861-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 867#L866-3true assume !(0 == ~T3_E~0); 639#L871-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 420#L876-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 302#L881-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 76#L886-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 851#L891-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 499#L896-3true assume 0 == ~E_M~0;~E_M~0 := 1; 288#L901-3true assume 0 == ~E_1~0;~E_1~0 := 1; 60#L906-3true assume !(0 == ~E_2~0); 955#L911-3true assume 0 == ~E_3~0;~E_3~0 := 1; 715#L916-3true assume 0 == ~E_4~0;~E_4~0 := 1; 379#L921-3true assume 0 == ~E_5~0;~E_5~0 := 1; 125#L926-3true assume 0 == ~E_6~0;~E_6~0 := 1; 930#L931-3true assume 0 == ~E_7~0;~E_7~0 := 1; 807#L936-3true assume 0 == ~E_8~0;~E_8~0 := 1; 594#L941-3true havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 221#L420-30true assume 1 == ~m_pc~0; 192#L421-10true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 730#L431-10true is_master_triggered_#res := is_master_triggered_~__retres1~0; 688#L432-10true activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 868#L1063-30true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 869#L1063-32true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 341#L439-30true assume !(1 == ~t1_pc~0); 345#L439-32true is_transmit1_triggered_~__retres1~1 := 0; 734#L450-10true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 809#L451-10true activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 516#L1071-30true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 518#L1071-32true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 476#L458-30true assume !(1 == ~t2_pc~0); 480#L458-32true is_transmit2_triggered_~__retres1~2 := 0; 880#L469-10true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 963#L470-10true activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 126#L1079-30true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 127#L1079-32true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 496#L477-30true assume !(1 == ~t3_pc~0); 611#L477-32true is_transmit3_triggered_~__retres1~3 := 0; 20#L488-10true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93#L489-10true activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 791#L1087-30true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 793#L1087-32true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 632#L496-30true assume 1 == ~t4_pc~0; 726#L497-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 140#L507-10true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 256#L508-10true activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 431#L1095-30true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 432#L1095-32true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 771#L515-30true assume !(1 == ~t5_pc~0); 754#L515-32true is_transmit5_triggered_~__retres1~5 := 0; 292#L526-10true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 275#L527-10true activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 190#L1103-30true assume !(0 != activate_threads_~tmp___4~0); 194#L1103-32true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 905#L534-30true assume 1 == ~t6_pc~0; 875#L535-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 560#L545-10true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 394#L546-10true activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 808#L1111-30true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 811#L1111-32true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 55#L553-30true assume 1 == ~t7_pc~0; 35#L554-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 701#L564-10true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 529#L565-10true activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 458#L1119-30true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 461#L1119-32true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 161#L572-30true assume !(1 == ~t8_pc~0); 165#L572-32true is_transmit8_triggered_~__retres1~8 := 0; 818#L583-10true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 657#L584-10true activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 82#L1127-30true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 84#L1127-32true assume 1 == ~M_E~0;~M_E~0 := 2; 864#L954-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 648#L959-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 429#L964-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 315#L969-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 80#L974-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 859#L979-3true assume !(1 == ~T6_E~0); 509#L984-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 291#L989-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 182#L994-3true assume 1 == ~E_M~0;~E_M~0 := 2; 952#L999-3true assume 1 == ~E_1~0;~E_1~0 := 2; 713#L1004-3true assume 1 == ~E_2~0;~E_2~0 := 2; 375#L1009-3true assume 1 == ~E_3~0;~E_3~0 := 2; 123#L1014-3true assume 1 == ~E_4~0;~E_4~0 := 2; 924#L1019-3true assume !(1 == ~E_5~0); 805#L1024-3true assume 1 == ~E_6~0;~E_6~0 := 2; 591#L1029-3true assume 1 == ~E_7~0;~E_7~0 := 2; 370#L1034-3true assume 1 == ~E_8~0;~E_8~0 := 2; 16#L1039-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 711#L652-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 587#L699-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 423#L700-1true start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 208#L1324true assume !(0 == start_simulation_~tmp~3); 210#L1324-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 712#L652-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 576#L699-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 425#L700-2true stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 112#L1279true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 799#L1286true stop_simulation_#res := stop_simulation_~__retres2~0; 744#L1287true start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 603#L1337true assume !(0 != start_simulation_~tmp___0~1); 64#L1305-1true [2019-12-07 13:00:26,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:26,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1715933315, now seen corresponding path program 1 times [2019-12-07 13:00:26,880 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:26,881 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928656226] [2019-12-07 13:00:26,881 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:26,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,042 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928656226] [2019-12-07 13:00:27,043 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,043 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,044 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243399781] [2019-12-07 13:00:27,048 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,049 INFO L82 PathProgramCache]: Analyzing trace with hash 1775587483, now seen corresponding path program 1 times [2019-12-07 13:00:27,049 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31983203] [2019-12-07 13:00:27,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,076 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31983203] [2019-12-07 13:00:27,076 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,076 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:27,076 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625291132] [2019-12-07 13:00:27,078 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,078 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,088 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,089 INFO L87 Difference]: Start difference. First operand 979 states. Second operand 3 states. [2019-12-07 13:00:27,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,127 INFO L93 Difference]: Finished difference Result 979 states and 1471 transitions. [2019-12-07 13:00:27,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 979 states and 1471 transitions. [2019-12-07 13:00:27,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 979 states to 973 states and 1465 transitions. [2019-12-07 13:00:27,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1465 transitions. [2019-12-07 13:00:27,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,152 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2019-12-07 13:00:27,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1465 transitions. [2019-12-07 13:00:27,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1465 transitions. [2019-12-07 13:00:27,199 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2019-12-07 13:00:27,199 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1465 transitions. [2019-12-07 13:00:27,199 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-12-07 13:00:27,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1465 transitions. [2019-12-07 13:00:27,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,205 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,205 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,205 INFO L794 eck$LassoCheckResult]: Stem: 2455#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2383#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2384#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2592#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1971#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1972#L604-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2690#L609-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2593#L614-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2347#L619-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2348#L624-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2753#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2555#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2248#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 2249#L856-1 assume !(0 == ~T1_E~0); 2352#L861-1 assume !(0 == ~T2_E~0); 2353#L866-1 assume !(0 == ~T3_E~0); 2777#L871-1 assume !(0 == ~T4_E~0); 2580#L876-1 assume !(0 == ~T5_E~0); 2441#L881-1 assume !(0 == ~T6_E~0); 2121#L886-1 assume !(0 == ~T7_E~0); 2122#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2651#L896-1 assume !(0 == ~E_M~0); 2411#L901-1 assume !(0 == ~E_1~0); 2078#L906-1 assume !(0 == ~E_2~0); 2079#L911-1 assume !(0 == ~E_3~0); 2824#L916-1 assume !(0 == ~E_4~0); 2495#L921-1 assume !(0 == ~E_5~0); 2184#L926-1 assume !(0 == ~E_6~0); 2185#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 2880#L936-1 assume !(0 == ~E_8~0); 2725#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2148#L420 assume !(1 == ~m_pc~0); 2149#L420-2 is_master_triggered_~__retres1~0 := 0; 2155#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2762#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2821#L1063 assume !(0 != activate_threads_~tmp~1); 2932#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2400#L439 assume 1 == ~t1_pc~0; 2401#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2405#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2857#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2814#L1071 assume !(0 != activate_threads_~tmp___0~0); 2800#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2563#L458 assume !(1 == ~t2_pc~0); 2539#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 2540#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2928#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2450#L1079 assume !(0 != activate_threads_~tmp___1~0); 2451#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2452#L477 assume 1 == ~t3_pc~0; 2677#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2042#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2043#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2139#L1087 assume !(0 != activate_threads_~tmp___2~0); 2938#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2797#L496 assume !(1 == ~t4_pc~0); 2759#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 2259#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2169#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2170#L1095 assume !(0 != activate_threads_~tmp___3~0); 2732#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2733#L515 assume 1 == ~t5_pc~0; 2853#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2583#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2410#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2373#L1103 assume !(0 != activate_threads_~tmp___4~0); 2361#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2106#L534 assume 1 == ~t6_pc~0; 2107#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2097#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2557#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2558#L1111 assume !(0 != activate_threads_~tmp___5~0); 2834#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2332#L553 assume !(1 == ~t7_pc~0); 2076#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 2075#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2691#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2533#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2512#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2481#L572 assume 1 == ~t8_pc~0; 2251#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2252#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2794#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2003#L1127 assume !(0 != activate_threads_~tmp___7~0); 2004#L1127-2 assume !(1 == ~M_E~0); 2005#L954-1 assume !(1 == ~T1_E~0); 2774#L959-1 assume !(1 == ~T2_E~0); 2578#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2435#L969-1 assume !(1 == ~T4_E~0); 2117#L974-1 assume !(1 == ~T5_E~0); 2118#L979-1 assume !(1 == ~T6_E~0); 2648#L984-1 assume !(1 == ~T7_E~0); 2415#L989-1 assume !(1 == ~T8_E~0); 2275#L994-1 assume !(1 == ~E_M~0); 2276#L999-1 assume !(1 == ~E_1~0); 2827#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2518#L1009-1 assume !(1 == ~E_3~0); 2192#L1014-1 assume !(1 == ~E_4~0); 2193#L1019-1 assume !(1 == ~E_5~0); 2883#L1024-1 assume !(1 == ~E_6~0); 2721#L1029-1 assume !(1 == ~E_7~0); 2486#L1034-1 assume !(1 == ~E_8~0); 2085#L1305-1 [2019-12-07 13:00:27,206 INFO L796 eck$LassoCheckResult]: Loop: 2085#L1305-1 assume !false; 2086#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2354#L831 assume !false; 2113#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2114#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2066#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2570#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2571#L714 assume !(0 != eval_~tmp~0); 2870#L846 start_simulation_~kernel_st~0 := 2; 2594#L592-1 start_simulation_~kernel_st~0 := 3; 2595#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2588#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2357#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2358#L866-3 assume !(0 == ~T3_E~0); 2767#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2567#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2427#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2111#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2112#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2642#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2412#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2080#L906-3 assume !(0 == ~E_2~0); 2081#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2825#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2499#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2186#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2187#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2881#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2727#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2338#L420-30 assume 1 == ~m_pc~0; 2297#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2299#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2810#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2811#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2894#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2474#L439-30 assume 1 == ~t1_pc~0; 2443#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2444#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2833#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2656#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2657#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2624#L458-30 assume 1 == ~t2_pc~0; 2611#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2612#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2906#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2188#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2189#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2190#L477-30 assume 1 == ~t3_pc~0; 2637#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1997#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1998#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2137#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2873#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2755#L496-30 assume 1 == ~t4_pc~0; 2756#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2214#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2215#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2368#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2581#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2582#L515-30 assume 1 == ~t5_pc~0; 2851#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2417#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2396#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2293#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 2294#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2301#L534-30 assume 1 == ~t6_pc~0; 2900#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2702#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2524#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2525#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2882#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2073#L553-30 assume !(1 == ~t7_pc~0); 2032#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 2033#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2670#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2609#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2610#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2250#L572-30 assume 1 == ~t8_pc~0; 2202#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2203#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2782#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2123#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2124#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 2126#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2776#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2579#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2440#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2119#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2120#L979-3 assume !(1 == ~T6_E~0); 2650#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2416#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2278#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2279#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2823#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2494#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2182#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2183#L1019-3 assume !(1 == ~E_5~0); 2879#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2724#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2488#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1990#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1991#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2068#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2572#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2320#L1324 assume !(0 == start_simulation_~tmp~3); 2322#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2323#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2071#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2574#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2165#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2166#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 2843#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2734#L1337 assume !(0 != start_simulation_~tmp___0~1); 2085#L1305-1 [2019-12-07 13:00:27,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,206 INFO L82 PathProgramCache]: Analyzing trace with hash 684892417, now seen corresponding path program 1 times [2019-12-07 13:00:27,206 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,206 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962951726] [2019-12-07 13:00:27,206 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,245 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962951726] [2019-12-07 13:00:27,245 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,245 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,245 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228189742] [2019-12-07 13:00:27,245 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,246 INFO L82 PathProgramCache]: Analyzing trace with hash 417907483, now seen corresponding path program 1 times [2019-12-07 13:00:27,246 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,246 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975987418] [2019-12-07 13:00:27,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,309 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975987418] [2019-12-07 13:00:27,309 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,309 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,309 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859847717] [2019-12-07 13:00:27,310 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,310 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,311 INFO L87 Difference]: Start difference. First operand 973 states and 1465 transitions. cyclomatic complexity: 493 Second operand 3 states. [2019-12-07 13:00:27,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,325 INFO L93 Difference]: Finished difference Result 973 states and 1464 transitions. [2019-12-07 13:00:27,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1464 transitions. [2019-12-07 13:00:27,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1464 transitions. [2019-12-07 13:00:27,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1464 transitions. [2019-12-07 13:00:27,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,338 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2019-12-07 13:00:27,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1464 transitions. [2019-12-07 13:00:27,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1464 transitions. [2019-12-07 13:00:27,350 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2019-12-07 13:00:27,351 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1464 transitions. [2019-12-07 13:00:27,351 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-12-07 13:00:27,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1464 transitions. [2019-12-07 13:00:27,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,356 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,356 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,356 INFO L794 eck$LassoCheckResult]: Stem: 4408#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4336#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4337#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4545#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 3924#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3925#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4643#L609-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4546#L614-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4300#L619-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4301#L624-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4706#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4508#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4201#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 4202#L856-1 assume !(0 == ~T1_E~0); 4305#L861-1 assume !(0 == ~T2_E~0); 4306#L866-1 assume !(0 == ~T3_E~0); 4730#L871-1 assume !(0 == ~T4_E~0); 4533#L876-1 assume !(0 == ~T5_E~0); 4394#L881-1 assume !(0 == ~T6_E~0); 4074#L886-1 assume !(0 == ~T7_E~0); 4075#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4604#L896-1 assume !(0 == ~E_M~0); 4364#L901-1 assume !(0 == ~E_1~0); 4031#L906-1 assume !(0 == ~E_2~0); 4032#L911-1 assume !(0 == ~E_3~0); 4777#L916-1 assume !(0 == ~E_4~0); 4448#L921-1 assume !(0 == ~E_5~0); 4137#L926-1 assume !(0 == ~E_6~0); 4138#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4833#L936-1 assume !(0 == ~E_8~0); 4678#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4101#L420 assume !(1 == ~m_pc~0); 4102#L420-2 is_master_triggered_~__retres1~0 := 0; 4108#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4715#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4774#L1063 assume !(0 != activate_threads_~tmp~1); 4885#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4353#L439 assume 1 == ~t1_pc~0; 4354#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4358#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4810#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4767#L1071 assume !(0 != activate_threads_~tmp___0~0); 4753#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4516#L458 assume !(1 == ~t2_pc~0); 4492#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 4493#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4881#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4403#L1079 assume !(0 != activate_threads_~tmp___1~0); 4404#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4405#L477 assume 1 == ~t3_pc~0; 4630#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3995#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3996#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4092#L1087 assume !(0 != activate_threads_~tmp___2~0); 4891#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4750#L496 assume !(1 == ~t4_pc~0); 4712#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 4212#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4122#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4123#L1095 assume !(0 != activate_threads_~tmp___3~0); 4685#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4686#L515 assume 1 == ~t5_pc~0; 4806#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4536#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4363#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4326#L1103 assume !(0 != activate_threads_~tmp___4~0); 4314#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4059#L534 assume 1 == ~t6_pc~0; 4060#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4050#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4510#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4511#L1111 assume !(0 != activate_threads_~tmp___5~0); 4787#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4285#L553 assume !(1 == ~t7_pc~0); 4029#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 4028#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4644#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4486#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4465#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4434#L572 assume 1 == ~t8_pc~0; 4204#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4205#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4747#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3956#L1127 assume !(0 != activate_threads_~tmp___7~0); 3957#L1127-2 assume !(1 == ~M_E~0); 3958#L954-1 assume !(1 == ~T1_E~0); 4727#L959-1 assume !(1 == ~T2_E~0); 4531#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4388#L969-1 assume !(1 == ~T4_E~0); 4070#L974-1 assume !(1 == ~T5_E~0); 4071#L979-1 assume !(1 == ~T6_E~0); 4601#L984-1 assume !(1 == ~T7_E~0); 4368#L989-1 assume !(1 == ~T8_E~0); 4228#L994-1 assume !(1 == ~E_M~0); 4229#L999-1 assume !(1 == ~E_1~0); 4780#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4471#L1009-1 assume !(1 == ~E_3~0); 4145#L1014-1 assume !(1 == ~E_4~0); 4146#L1019-1 assume !(1 == ~E_5~0); 4836#L1024-1 assume !(1 == ~E_6~0); 4674#L1029-1 assume !(1 == ~E_7~0); 4439#L1034-1 assume !(1 == ~E_8~0); 4038#L1305-1 [2019-12-07 13:00:27,357 INFO L796 eck$LassoCheckResult]: Loop: 4038#L1305-1 assume !false; 4039#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4307#L831 assume !false; 4066#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4067#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4019#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4523#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4524#L714 assume !(0 != eval_~tmp~0); 4823#L846 start_simulation_~kernel_st~0 := 2; 4547#L592-1 start_simulation_~kernel_st~0 := 3; 4548#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4541#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4310#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4311#L866-3 assume !(0 == ~T3_E~0); 4720#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4520#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4380#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4064#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4065#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4595#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4365#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4033#L906-3 assume !(0 == ~E_2~0); 4034#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4778#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4452#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4139#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4140#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4834#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4680#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4291#L420-30 assume 1 == ~m_pc~0; 4250#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4252#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4763#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4764#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4847#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4427#L439-30 assume 1 == ~t1_pc~0; 4396#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4397#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4786#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4609#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4610#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4577#L458-30 assume 1 == ~t2_pc~0; 4564#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4565#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4859#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4141#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4142#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4143#L477-30 assume 1 == ~t3_pc~0; 4590#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3950#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3951#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4090#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4826#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4708#L496-30 assume 1 == ~t4_pc~0; 4709#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4167#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4168#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4321#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4534#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4535#L515-30 assume 1 == ~t5_pc~0; 4804#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4370#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4349#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4246#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 4247#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4254#L534-30 assume 1 == ~t6_pc~0; 4853#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4655#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4477#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4478#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4835#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4026#L553-30 assume 1 == ~t7_pc~0; 3984#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3986#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4623#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4562#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4563#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4203#L572-30 assume 1 == ~t8_pc~0; 4155#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4156#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4735#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4076#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4077#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 4079#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4729#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4532#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4393#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4072#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4073#L979-3 assume !(1 == ~T6_E~0); 4603#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4369#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4231#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4232#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4776#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4447#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4135#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4136#L1019-3 assume !(1 == ~E_5~0); 4832#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4677#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4441#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3943#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3944#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4021#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4525#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4273#L1324 assume !(0 == start_simulation_~tmp~3); 4275#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4276#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4024#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4527#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4118#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4119#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 4796#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4687#L1337 assume !(0 != start_simulation_~tmp___0~1); 4038#L1305-1 [2019-12-07 13:00:27,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,357 INFO L82 PathProgramCache]: Analyzing trace with hash -916178689, now seen corresponding path program 1 times [2019-12-07 13:00:27,357 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,358 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786539712] [2019-12-07 13:00:27,358 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,395 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786539712] [2019-12-07 13:00:27,395 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,395 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,395 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231468779] [2019-12-07 13:00:27,396 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,396 INFO L82 PathProgramCache]: Analyzing trace with hash -1721545412, now seen corresponding path program 1 times [2019-12-07 13:00:27,396 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,396 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461984912] [2019-12-07 13:00:27,397 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,447 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461984912] [2019-12-07 13:00:27,447 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,447 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867420146] [2019-12-07 13:00:27,448 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,448 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,448 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,448 INFO L87 Difference]: Start difference. First operand 973 states and 1464 transitions. cyclomatic complexity: 492 Second operand 3 states. [2019-12-07 13:00:27,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,460 INFO L93 Difference]: Finished difference Result 973 states and 1463 transitions. [2019-12-07 13:00:27,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1463 transitions. [2019-12-07 13:00:27,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1463 transitions. [2019-12-07 13:00:27,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1463 transitions. [2019-12-07 13:00:27,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,472 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2019-12-07 13:00:27,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1463 transitions. [2019-12-07 13:00:27,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1463 transitions. [2019-12-07 13:00:27,484 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2019-12-07 13:00:27,484 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1463 transitions. [2019-12-07 13:00:27,484 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-12-07 13:00:27,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1463 transitions. [2019-12-07 13:00:27,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,489 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,489 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,489 INFO L794 eck$LassoCheckResult]: Stem: 6361#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6289#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6290#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6498#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 5877#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5878#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6596#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6499#L614-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6253#L619-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6254#L624-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6659#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6461#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6154#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6155#L856-1 assume !(0 == ~T1_E~0); 6258#L861-1 assume !(0 == ~T2_E~0); 6259#L866-1 assume !(0 == ~T3_E~0); 6683#L871-1 assume !(0 == ~T4_E~0); 6486#L876-1 assume !(0 == ~T5_E~0); 6347#L881-1 assume !(0 == ~T6_E~0); 6027#L886-1 assume !(0 == ~T7_E~0); 6028#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6557#L896-1 assume !(0 == ~E_M~0); 6317#L901-1 assume !(0 == ~E_1~0); 5984#L906-1 assume !(0 == ~E_2~0); 5985#L911-1 assume !(0 == ~E_3~0); 6730#L916-1 assume !(0 == ~E_4~0); 6401#L921-1 assume !(0 == ~E_5~0); 6090#L926-1 assume !(0 == ~E_6~0); 6091#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6786#L936-1 assume !(0 == ~E_8~0); 6631#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6054#L420 assume !(1 == ~m_pc~0); 6055#L420-2 is_master_triggered_~__retres1~0 := 0; 6061#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6668#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6727#L1063 assume !(0 != activate_threads_~tmp~1); 6838#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6306#L439 assume 1 == ~t1_pc~0; 6307#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6311#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6763#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6720#L1071 assume !(0 != activate_threads_~tmp___0~0); 6706#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6469#L458 assume !(1 == ~t2_pc~0); 6445#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 6446#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6834#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6356#L1079 assume !(0 != activate_threads_~tmp___1~0); 6357#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6358#L477 assume 1 == ~t3_pc~0; 6583#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5948#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5949#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6045#L1087 assume !(0 != activate_threads_~tmp___2~0); 6844#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6703#L496 assume !(1 == ~t4_pc~0); 6665#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 6165#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6075#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6076#L1095 assume !(0 != activate_threads_~tmp___3~0); 6638#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6639#L515 assume 1 == ~t5_pc~0; 6759#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6489#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6316#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6279#L1103 assume !(0 != activate_threads_~tmp___4~0); 6267#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6012#L534 assume 1 == ~t6_pc~0; 6013#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6003#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6463#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6464#L1111 assume !(0 != activate_threads_~tmp___5~0); 6740#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6238#L553 assume !(1 == ~t7_pc~0); 5982#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 5981#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6597#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6439#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6418#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6387#L572 assume 1 == ~t8_pc~0; 6157#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6158#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6700#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5909#L1127 assume !(0 != activate_threads_~tmp___7~0); 5910#L1127-2 assume !(1 == ~M_E~0); 5911#L954-1 assume !(1 == ~T1_E~0); 6680#L959-1 assume !(1 == ~T2_E~0); 6484#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6341#L969-1 assume !(1 == ~T4_E~0); 6023#L974-1 assume !(1 == ~T5_E~0); 6024#L979-1 assume !(1 == ~T6_E~0); 6554#L984-1 assume !(1 == ~T7_E~0); 6321#L989-1 assume !(1 == ~T8_E~0); 6181#L994-1 assume !(1 == ~E_M~0); 6182#L999-1 assume !(1 == ~E_1~0); 6733#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6424#L1009-1 assume !(1 == ~E_3~0); 6098#L1014-1 assume !(1 == ~E_4~0); 6099#L1019-1 assume !(1 == ~E_5~0); 6789#L1024-1 assume !(1 == ~E_6~0); 6627#L1029-1 assume !(1 == ~E_7~0); 6392#L1034-1 assume !(1 == ~E_8~0); 5991#L1305-1 [2019-12-07 13:00:27,490 INFO L796 eck$LassoCheckResult]: Loop: 5991#L1305-1 assume !false; 5992#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 6260#L831 assume !false; 6019#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6020#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5972#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6476#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6477#L714 assume !(0 != eval_~tmp~0); 6776#L846 start_simulation_~kernel_st~0 := 2; 6500#L592-1 start_simulation_~kernel_st~0 := 3; 6501#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6494#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6263#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6264#L866-3 assume !(0 == ~T3_E~0); 6673#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6473#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6333#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6017#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6018#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6548#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6318#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5986#L906-3 assume !(0 == ~E_2~0); 5987#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6731#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6405#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6092#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6093#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6787#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6633#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6244#L420-30 assume 1 == ~m_pc~0; 6203#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6205#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6716#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6717#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6800#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6380#L439-30 assume 1 == ~t1_pc~0; 6349#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6350#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6739#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6562#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6563#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6530#L458-30 assume 1 == ~t2_pc~0; 6517#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6518#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6812#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6094#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6095#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6096#L477-30 assume !(1 == ~t3_pc~0); 6544#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 5903#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5904#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6043#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6779#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6661#L496-30 assume 1 == ~t4_pc~0; 6662#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6120#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6121#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6274#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6487#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6488#L515-30 assume 1 == ~t5_pc~0; 6757#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6323#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6302#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6199#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 6200#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6207#L534-30 assume 1 == ~t6_pc~0; 6806#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6608#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6430#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6431#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6788#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5979#L553-30 assume 1 == ~t7_pc~0; 5937#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5939#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6576#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6515#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6516#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6156#L572-30 assume 1 == ~t8_pc~0; 6108#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6109#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6688#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6029#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6030#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 6032#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6682#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6485#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6346#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6025#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6026#L979-3 assume !(1 == ~T6_E~0); 6556#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6322#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6184#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6185#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6729#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6400#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6088#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6089#L1019-3 assume !(1 == ~E_5~0); 6785#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6630#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6394#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5896#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5897#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5974#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6478#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 6226#L1324 assume !(0 == start_simulation_~tmp~3); 6228#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6229#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5977#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6480#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 6071#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6072#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 6749#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6640#L1337 assume !(0 != start_simulation_~tmp___0~1); 5991#L1305-1 [2019-12-07 13:00:27,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,490 INFO L82 PathProgramCache]: Analyzing trace with hash 140552513, now seen corresponding path program 1 times [2019-12-07 13:00:27,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402757978] [2019-12-07 13:00:27,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402757978] [2019-12-07 13:00:27,513 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,513 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,513 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [441291570] [2019-12-07 13:00:27,513 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,513 INFO L82 PathProgramCache]: Analyzing trace with hash 1395447323, now seen corresponding path program 1 times [2019-12-07 13:00:27,513 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,514 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215663807] [2019-12-07 13:00:27,514 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,556 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215663807] [2019-12-07 13:00:27,556 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,556 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,557 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154402818] [2019-12-07 13:00:27,557 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,557 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,557 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,557 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,558 INFO L87 Difference]: Start difference. First operand 973 states and 1463 transitions. cyclomatic complexity: 491 Second operand 3 states. [2019-12-07 13:00:27,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,572 INFO L93 Difference]: Finished difference Result 973 states and 1462 transitions. [2019-12-07 13:00:27,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,572 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1462 transitions. [2019-12-07 13:00:27,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1462 transitions. [2019-12-07 13:00:27,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1462 transitions. [2019-12-07 13:00:27,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,588 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2019-12-07 13:00:27,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1462 transitions. [2019-12-07 13:00:27,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1462 transitions. [2019-12-07 13:00:27,605 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2019-12-07 13:00:27,605 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1462 transitions. [2019-12-07 13:00:27,606 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-12-07 13:00:27,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1462 transitions. [2019-12-07 13:00:27,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,612 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,612 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,613 INFO L794 eck$LassoCheckResult]: Stem: 8314#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8242#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8243#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8451#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 7830#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7831#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8549#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8452#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8206#L619-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8207#L624-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8612#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8414#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8107#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 8108#L856-1 assume !(0 == ~T1_E~0); 8211#L861-1 assume !(0 == ~T2_E~0); 8212#L866-1 assume !(0 == ~T3_E~0); 8636#L871-1 assume !(0 == ~T4_E~0); 8439#L876-1 assume !(0 == ~T5_E~0); 8300#L881-1 assume !(0 == ~T6_E~0); 7980#L886-1 assume !(0 == ~T7_E~0); 7981#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8510#L896-1 assume !(0 == ~E_M~0); 8270#L901-1 assume !(0 == ~E_1~0); 7937#L906-1 assume !(0 == ~E_2~0); 7938#L911-1 assume !(0 == ~E_3~0); 8683#L916-1 assume !(0 == ~E_4~0); 8354#L921-1 assume !(0 == ~E_5~0); 8043#L926-1 assume !(0 == ~E_6~0); 8044#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 8739#L936-1 assume !(0 == ~E_8~0); 8584#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8007#L420 assume !(1 == ~m_pc~0); 8008#L420-2 is_master_triggered_~__retres1~0 := 0; 8014#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8621#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8680#L1063 assume !(0 != activate_threads_~tmp~1); 8791#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8259#L439 assume 1 == ~t1_pc~0; 8260#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8264#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8716#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8673#L1071 assume !(0 != activate_threads_~tmp___0~0); 8659#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8422#L458 assume !(1 == ~t2_pc~0); 8398#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 8399#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8787#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8309#L1079 assume !(0 != activate_threads_~tmp___1~0); 8310#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8311#L477 assume 1 == ~t3_pc~0; 8536#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7901#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7902#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7998#L1087 assume !(0 != activate_threads_~tmp___2~0); 8797#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8656#L496 assume !(1 == ~t4_pc~0); 8618#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 8118#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8028#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8029#L1095 assume !(0 != activate_threads_~tmp___3~0); 8591#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8592#L515 assume 1 == ~t5_pc~0; 8712#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8442#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8269#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8232#L1103 assume !(0 != activate_threads_~tmp___4~0); 8220#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7965#L534 assume 1 == ~t6_pc~0; 7966#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7956#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8416#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8417#L1111 assume !(0 != activate_threads_~tmp___5~0); 8693#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8191#L553 assume !(1 == ~t7_pc~0); 7935#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 7934#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8550#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8392#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8371#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8340#L572 assume 1 == ~t8_pc~0; 8110#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8111#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8653#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7862#L1127 assume !(0 != activate_threads_~tmp___7~0); 7863#L1127-2 assume !(1 == ~M_E~0); 7864#L954-1 assume !(1 == ~T1_E~0); 8633#L959-1 assume !(1 == ~T2_E~0); 8437#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8294#L969-1 assume !(1 == ~T4_E~0); 7976#L974-1 assume !(1 == ~T5_E~0); 7977#L979-1 assume !(1 == ~T6_E~0); 8507#L984-1 assume !(1 == ~T7_E~0); 8274#L989-1 assume !(1 == ~T8_E~0); 8134#L994-1 assume !(1 == ~E_M~0); 8135#L999-1 assume !(1 == ~E_1~0); 8686#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8377#L1009-1 assume !(1 == ~E_3~0); 8051#L1014-1 assume !(1 == ~E_4~0); 8052#L1019-1 assume !(1 == ~E_5~0); 8742#L1024-1 assume !(1 == ~E_6~0); 8580#L1029-1 assume !(1 == ~E_7~0); 8345#L1034-1 assume !(1 == ~E_8~0); 7944#L1305-1 [2019-12-07 13:00:27,613 INFO L796 eck$LassoCheckResult]: Loop: 7944#L1305-1 assume !false; 7945#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8213#L831 assume !false; 7972#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7973#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7925#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8429#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8430#L714 assume !(0 != eval_~tmp~0); 8729#L846 start_simulation_~kernel_st~0 := 2; 8453#L592-1 start_simulation_~kernel_st~0 := 3; 8454#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8447#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8216#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8217#L866-3 assume !(0 == ~T3_E~0); 8626#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8426#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8286#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7970#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7971#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8501#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8271#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7939#L906-3 assume !(0 == ~E_2~0); 7940#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8684#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8358#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8045#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8046#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8740#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8586#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8197#L420-30 assume 1 == ~m_pc~0; 8156#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8158#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8669#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8670#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8753#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8333#L439-30 assume !(1 == ~t1_pc~0); 8304#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 8303#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8692#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8515#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8516#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8483#L458-30 assume 1 == ~t2_pc~0; 8470#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8471#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8765#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8047#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8048#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8049#L477-30 assume 1 == ~t3_pc~0; 8496#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7856#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7857#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7996#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8732#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8614#L496-30 assume 1 == ~t4_pc~0; 8615#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8073#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8074#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8227#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8440#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8441#L515-30 assume 1 == ~t5_pc~0; 8710#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8276#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8255#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8152#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 8153#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8160#L534-30 assume 1 == ~t6_pc~0; 8759#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8561#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8383#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8384#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8741#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7932#L553-30 assume 1 == ~t7_pc~0; 7890#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7892#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8529#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8468#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8469#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8109#L572-30 assume 1 == ~t8_pc~0; 8061#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8062#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8641#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7982#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 7983#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 7985#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8635#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8438#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8299#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7978#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7979#L979-3 assume !(1 == ~T6_E~0); 8509#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8275#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8137#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8138#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8682#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8353#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8041#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8042#L1019-3 assume !(1 == ~E_5~0); 8738#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8583#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8347#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7849#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7850#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7927#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8431#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 8179#L1324 assume !(0 == start_simulation_~tmp~3); 8181#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8182#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7930#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8433#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 8024#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 8025#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 8702#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 8593#L1337 assume !(0 != start_simulation_~tmp___0~1); 7944#L1305-1 [2019-12-07 13:00:27,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,613 INFO L82 PathProgramCache]: Analyzing trace with hash -1210832705, now seen corresponding path program 1 times [2019-12-07 13:00:27,614 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,614 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651500780] [2019-12-07 13:00:27,614 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,637 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651500780] [2019-12-07 13:00:27,637 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,637 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047907278] [2019-12-07 13:00:27,638 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1296269211, now seen corresponding path program 1 times [2019-12-07 13:00:27,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065739591] [2019-12-07 13:00:27,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,678 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065739591] [2019-12-07 13:00:27,679 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,679 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,679 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823959325] [2019-12-07 13:00:27,679 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,680 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,680 INFO L87 Difference]: Start difference. First operand 973 states and 1462 transitions. cyclomatic complexity: 490 Second operand 3 states. [2019-12-07 13:00:27,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,693 INFO L93 Difference]: Finished difference Result 973 states and 1461 transitions. [2019-12-07 13:00:27,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1461 transitions. [2019-12-07 13:00:27,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1461 transitions. [2019-12-07 13:00:27,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1461 transitions. [2019-12-07 13:00:27,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,706 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2019-12-07 13:00:27,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1461 transitions. [2019-12-07 13:00:27,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1461 transitions. [2019-12-07 13:00:27,730 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2019-12-07 13:00:27,731 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1461 transitions. [2019-12-07 13:00:27,731 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-12-07 13:00:27,731 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1461 transitions. [2019-12-07 13:00:27,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,737 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,737 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,737 INFO L794 eck$LassoCheckResult]: Stem: 10267#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10195#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10196#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10404#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 9783#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9784#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10502#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10405#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10159#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10160#L624-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10565#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10367#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10060#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 10061#L856-1 assume !(0 == ~T1_E~0); 10164#L861-1 assume !(0 == ~T2_E~0); 10165#L866-1 assume !(0 == ~T3_E~0); 10589#L871-1 assume !(0 == ~T4_E~0); 10392#L876-1 assume !(0 == ~T5_E~0); 10253#L881-1 assume !(0 == ~T6_E~0); 9933#L886-1 assume !(0 == ~T7_E~0); 9934#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10463#L896-1 assume !(0 == ~E_M~0); 10223#L901-1 assume !(0 == ~E_1~0); 9890#L906-1 assume !(0 == ~E_2~0); 9891#L911-1 assume !(0 == ~E_3~0); 10636#L916-1 assume !(0 == ~E_4~0); 10307#L921-1 assume !(0 == ~E_5~0); 9996#L926-1 assume !(0 == ~E_6~0); 9997#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10692#L936-1 assume !(0 == ~E_8~0); 10537#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9960#L420 assume !(1 == ~m_pc~0); 9961#L420-2 is_master_triggered_~__retres1~0 := 0; 9967#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10574#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10633#L1063 assume !(0 != activate_threads_~tmp~1); 10744#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10212#L439 assume 1 == ~t1_pc~0; 10213#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10217#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10669#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10626#L1071 assume !(0 != activate_threads_~tmp___0~0); 10612#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10375#L458 assume !(1 == ~t2_pc~0); 10351#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 10352#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10740#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10262#L1079 assume !(0 != activate_threads_~tmp___1~0); 10263#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10264#L477 assume 1 == ~t3_pc~0; 10489#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9854#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9855#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9951#L1087 assume !(0 != activate_threads_~tmp___2~0); 10750#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10609#L496 assume !(1 == ~t4_pc~0); 10571#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 10071#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9981#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9982#L1095 assume !(0 != activate_threads_~tmp___3~0); 10544#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10545#L515 assume 1 == ~t5_pc~0; 10665#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10395#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10222#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10185#L1103 assume !(0 != activate_threads_~tmp___4~0); 10173#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9918#L534 assume 1 == ~t6_pc~0; 9919#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9909#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10369#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10370#L1111 assume !(0 != activate_threads_~tmp___5~0); 10646#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10144#L553 assume !(1 == ~t7_pc~0); 9888#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 9887#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10503#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10345#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10324#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10293#L572 assume 1 == ~t8_pc~0; 10063#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 10064#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10606#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9815#L1127 assume !(0 != activate_threads_~tmp___7~0); 9816#L1127-2 assume !(1 == ~M_E~0); 9817#L954-1 assume !(1 == ~T1_E~0); 10586#L959-1 assume !(1 == ~T2_E~0); 10390#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10247#L969-1 assume !(1 == ~T4_E~0); 9929#L974-1 assume !(1 == ~T5_E~0); 9930#L979-1 assume !(1 == ~T6_E~0); 10460#L984-1 assume !(1 == ~T7_E~0); 10227#L989-1 assume !(1 == ~T8_E~0); 10087#L994-1 assume !(1 == ~E_M~0); 10088#L999-1 assume !(1 == ~E_1~0); 10639#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10330#L1009-1 assume !(1 == ~E_3~0); 10004#L1014-1 assume !(1 == ~E_4~0); 10005#L1019-1 assume !(1 == ~E_5~0); 10695#L1024-1 assume !(1 == ~E_6~0); 10533#L1029-1 assume !(1 == ~E_7~0); 10298#L1034-1 assume !(1 == ~E_8~0); 9897#L1305-1 [2019-12-07 13:00:27,737 INFO L796 eck$LassoCheckResult]: Loop: 9897#L1305-1 assume !false; 9898#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 10166#L831 assume !false; 9925#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9926#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9878#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10382#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 10383#L714 assume !(0 != eval_~tmp~0); 10682#L846 start_simulation_~kernel_st~0 := 2; 10406#L592-1 start_simulation_~kernel_st~0 := 3; 10407#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10400#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10169#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10170#L866-3 assume !(0 == ~T3_E~0); 10579#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10379#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10239#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9923#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9924#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10454#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10224#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9892#L906-3 assume !(0 == ~E_2~0); 9893#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10637#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10311#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9998#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9999#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10693#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10539#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10150#L420-30 assume 1 == ~m_pc~0; 10109#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10111#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10622#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10623#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10706#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10286#L439-30 assume !(1 == ~t1_pc~0); 10257#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 10256#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10645#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10468#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10469#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10436#L458-30 assume 1 == ~t2_pc~0; 10423#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10424#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10718#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10000#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10001#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10002#L477-30 assume 1 == ~t3_pc~0; 10449#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9809#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9810#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9949#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10685#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10567#L496-30 assume 1 == ~t4_pc~0; 10568#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10026#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10027#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10180#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10393#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10394#L515-30 assume 1 == ~t5_pc~0; 10663#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10229#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10208#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10105#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 10106#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10113#L534-30 assume 1 == ~t6_pc~0; 10712#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10514#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10336#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10337#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10694#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9885#L553-30 assume 1 == ~t7_pc~0; 9843#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9845#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10482#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10421#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10422#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10062#L572-30 assume !(1 == ~t8_pc~0); 10016#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 10015#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10594#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9935#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9936#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 9938#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10588#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10391#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10252#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9931#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9932#L979-3 assume !(1 == ~T6_E~0); 10462#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10228#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10090#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10091#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10635#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10306#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9994#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9995#L1019-3 assume !(1 == ~E_5~0); 10691#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10536#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10300#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9802#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9803#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9880#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10384#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 10132#L1324 assume !(0 == start_simulation_~tmp~3); 10134#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10135#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9883#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10386#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 9977#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9978#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 10655#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 10546#L1337 assume !(0 != start_simulation_~tmp___0~1); 9897#L1305-1 [2019-12-07 13:00:27,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,738 INFO L82 PathProgramCache]: Analyzing trace with hash 408142209, now seen corresponding path program 1 times [2019-12-07 13:00:27,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130240193] [2019-12-07 13:00:27,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,760 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130240193] [2019-12-07 13:00:27,760 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,760 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,760 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244348521] [2019-12-07 13:00:27,761 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,761 INFO L82 PathProgramCache]: Analyzing trace with hash -468547398, now seen corresponding path program 1 times [2019-12-07 13:00:27,761 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,761 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920342858] [2019-12-07 13:00:27,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,797 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920342858] [2019-12-07 13:00:27,797 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,797 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,797 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885004349] [2019-12-07 13:00:27,797 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,798 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,798 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,798 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,798 INFO L87 Difference]: Start difference. First operand 973 states and 1461 transitions. cyclomatic complexity: 489 Second operand 3 states. [2019-12-07 13:00:27,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,808 INFO L93 Difference]: Finished difference Result 973 states and 1460 transitions. [2019-12-07 13:00:27,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1460 transitions. [2019-12-07 13:00:27,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1460 transitions. [2019-12-07 13:00:27,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1460 transitions. [2019-12-07 13:00:27,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,824 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2019-12-07 13:00:27,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1460 transitions. [2019-12-07 13:00:27,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1460 transitions. [2019-12-07 13:00:27,841 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2019-12-07 13:00:27,842 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1460 transitions. [2019-12-07 13:00:27,842 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-12-07 13:00:27,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1460 transitions. [2019-12-07 13:00:27,846 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,848 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,848 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,848 INFO L794 eck$LassoCheckResult]: Stem: 12220#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12148#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12149#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12357#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 11736#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11737#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12455#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12358#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12112#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12113#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12518#L629-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12320#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12013#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 12014#L856-1 assume !(0 == ~T1_E~0); 12117#L861-1 assume !(0 == ~T2_E~0); 12118#L866-1 assume !(0 == ~T3_E~0); 12542#L871-1 assume !(0 == ~T4_E~0); 12345#L876-1 assume !(0 == ~T5_E~0); 12206#L881-1 assume !(0 == ~T6_E~0); 11886#L886-1 assume !(0 == ~T7_E~0); 11887#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12416#L896-1 assume !(0 == ~E_M~0); 12176#L901-1 assume !(0 == ~E_1~0); 11843#L906-1 assume !(0 == ~E_2~0); 11844#L911-1 assume !(0 == ~E_3~0); 12589#L916-1 assume !(0 == ~E_4~0); 12260#L921-1 assume !(0 == ~E_5~0); 11949#L926-1 assume !(0 == ~E_6~0); 11950#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12645#L936-1 assume !(0 == ~E_8~0); 12490#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11913#L420 assume !(1 == ~m_pc~0); 11914#L420-2 is_master_triggered_~__retres1~0 := 0; 11920#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12527#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12586#L1063 assume !(0 != activate_threads_~tmp~1); 12697#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12165#L439 assume 1 == ~t1_pc~0; 12166#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12170#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12622#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12579#L1071 assume !(0 != activate_threads_~tmp___0~0); 12565#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12328#L458 assume !(1 == ~t2_pc~0); 12304#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 12305#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12693#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12215#L1079 assume !(0 != activate_threads_~tmp___1~0); 12216#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12217#L477 assume 1 == ~t3_pc~0; 12442#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11807#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11808#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11904#L1087 assume !(0 != activate_threads_~tmp___2~0); 12703#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12562#L496 assume !(1 == ~t4_pc~0); 12524#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 12024#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11934#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11935#L1095 assume !(0 != activate_threads_~tmp___3~0); 12497#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12498#L515 assume 1 == ~t5_pc~0; 12618#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12348#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12175#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12138#L1103 assume !(0 != activate_threads_~tmp___4~0); 12126#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11871#L534 assume 1 == ~t6_pc~0; 11872#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11862#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12322#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12323#L1111 assume !(0 != activate_threads_~tmp___5~0); 12599#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12097#L553 assume !(1 == ~t7_pc~0); 11841#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 11840#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12456#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12298#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12277#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12246#L572 assume 1 == ~t8_pc~0; 12016#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12017#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12559#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11768#L1127 assume !(0 != activate_threads_~tmp___7~0); 11769#L1127-2 assume !(1 == ~M_E~0); 11770#L954-1 assume !(1 == ~T1_E~0); 12539#L959-1 assume !(1 == ~T2_E~0); 12343#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12200#L969-1 assume !(1 == ~T4_E~0); 11882#L974-1 assume !(1 == ~T5_E~0); 11883#L979-1 assume !(1 == ~T6_E~0); 12413#L984-1 assume !(1 == ~T7_E~0); 12180#L989-1 assume !(1 == ~T8_E~0); 12040#L994-1 assume !(1 == ~E_M~0); 12041#L999-1 assume !(1 == ~E_1~0); 12592#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12283#L1009-1 assume !(1 == ~E_3~0); 11957#L1014-1 assume !(1 == ~E_4~0); 11958#L1019-1 assume !(1 == ~E_5~0); 12648#L1024-1 assume !(1 == ~E_6~0); 12486#L1029-1 assume !(1 == ~E_7~0); 12251#L1034-1 assume !(1 == ~E_8~0); 11850#L1305-1 [2019-12-07 13:00:27,848 INFO L796 eck$LassoCheckResult]: Loop: 11850#L1305-1 assume !false; 11851#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 12119#L831 assume !false; 11878#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11879#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11831#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12335#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12336#L714 assume !(0 != eval_~tmp~0); 12635#L846 start_simulation_~kernel_st~0 := 2; 12359#L592-1 start_simulation_~kernel_st~0 := 3; 12360#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12353#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12122#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12123#L866-3 assume !(0 == ~T3_E~0); 12532#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12332#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12192#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11876#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11877#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12407#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12177#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11845#L906-3 assume !(0 == ~E_2~0); 11846#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12590#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12264#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11951#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11952#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12646#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12492#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12103#L420-30 assume 1 == ~m_pc~0; 12062#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12064#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12575#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12576#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12659#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12239#L439-30 assume 1 == ~t1_pc~0; 12208#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12209#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12598#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12421#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12422#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12389#L458-30 assume 1 == ~t2_pc~0; 12376#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12377#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12671#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11953#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11954#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11955#L477-30 assume 1 == ~t3_pc~0; 12402#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11762#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11763#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11902#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12638#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12520#L496-30 assume 1 == ~t4_pc~0; 12521#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11979#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11980#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12133#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12346#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12347#L515-30 assume 1 == ~t5_pc~0; 12616#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12182#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12161#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12058#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 12059#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12066#L534-30 assume 1 == ~t6_pc~0; 12665#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12467#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12289#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12290#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12647#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11838#L553-30 assume 1 == ~t7_pc~0; 11796#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11798#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12435#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12374#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12375#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12015#L572-30 assume !(1 == ~t8_pc~0); 11969#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 11968#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12547#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11888#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 11889#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 11891#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12344#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12205#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11884#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11885#L979-3 assume !(1 == ~T6_E~0); 12415#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12181#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12043#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12044#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12588#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12259#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11947#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11948#L1019-3 assume !(1 == ~E_5~0); 12644#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12489#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12253#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11755#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11756#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11833#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12337#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 12085#L1324 assume !(0 == start_simulation_~tmp~3); 12087#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12088#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11836#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12339#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 11930#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 11931#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 12608#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 12499#L1337 assume !(0 != start_simulation_~tmp___0~1); 11850#L1305-1 [2019-12-07 13:00:27,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1291651199, now seen corresponding path program 1 times [2019-12-07 13:00:27,849 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395275224] [2019-12-07 13:00:27,849 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,870 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395275224] [2019-12-07 13:00:27,870 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,870 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020420811] [2019-12-07 13:00:27,871 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,871 INFO L82 PathProgramCache]: Analyzing trace with hash 808605275, now seen corresponding path program 1 times [2019-12-07 13:00:27,871 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,871 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950504877] [2019-12-07 13:00:27,872 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,907 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950504877] [2019-12-07 13:00:27,907 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,907 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,908 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891207051] [2019-12-07 13:00:27,908 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,908 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,908 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,908 INFO L87 Difference]: Start difference. First operand 973 states and 1460 transitions. cyclomatic complexity: 488 Second operand 3 states. [2019-12-07 13:00:27,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,916 INFO L93 Difference]: Finished difference Result 973 states and 1459 transitions. [2019-12-07 13:00:27,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1459 transitions. [2019-12-07 13:00:27,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1459 transitions. [2019-12-07 13:00:27,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:27,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:27,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1459 transitions. [2019-12-07 13:00:27,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:27,927 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2019-12-07 13:00:27,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1459 transitions. [2019-12-07 13:00:27,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:27,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:27,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1459 transitions. [2019-12-07 13:00:27,938 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2019-12-07 13:00:27,938 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1459 transitions. [2019-12-07 13:00:27,938 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-12-07 13:00:27,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1459 transitions. [2019-12-07 13:00:27,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:27,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:27,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:27,942 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,942 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:27,942 INFO L794 eck$LassoCheckResult]: Stem: 14173#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14101#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14102#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14310#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 13689#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13690#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14408#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14311#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14065#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14066#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14471#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14273#L634-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13966#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 13967#L856-1 assume !(0 == ~T1_E~0); 14070#L861-1 assume !(0 == ~T2_E~0); 14071#L866-1 assume !(0 == ~T3_E~0); 14495#L871-1 assume !(0 == ~T4_E~0); 14298#L876-1 assume !(0 == ~T5_E~0); 14159#L881-1 assume !(0 == ~T6_E~0); 13839#L886-1 assume !(0 == ~T7_E~0); 13840#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14369#L896-1 assume !(0 == ~E_M~0); 14129#L901-1 assume !(0 == ~E_1~0); 13796#L906-1 assume !(0 == ~E_2~0); 13797#L911-1 assume !(0 == ~E_3~0); 14542#L916-1 assume !(0 == ~E_4~0); 14213#L921-1 assume !(0 == ~E_5~0); 13902#L926-1 assume !(0 == ~E_6~0); 13903#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 14598#L936-1 assume !(0 == ~E_8~0); 14443#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13866#L420 assume !(1 == ~m_pc~0); 13867#L420-2 is_master_triggered_~__retres1~0 := 0; 13873#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14480#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14539#L1063 assume !(0 != activate_threads_~tmp~1); 14650#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14118#L439 assume 1 == ~t1_pc~0; 14119#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14123#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14575#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14532#L1071 assume !(0 != activate_threads_~tmp___0~0); 14518#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14281#L458 assume !(1 == ~t2_pc~0); 14257#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 14258#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14646#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14168#L1079 assume !(0 != activate_threads_~tmp___1~0); 14169#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14170#L477 assume 1 == ~t3_pc~0; 14395#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13760#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13761#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13857#L1087 assume !(0 != activate_threads_~tmp___2~0); 14656#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14515#L496 assume !(1 == ~t4_pc~0); 14477#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 13977#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13887#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13888#L1095 assume !(0 != activate_threads_~tmp___3~0); 14450#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14451#L515 assume 1 == ~t5_pc~0; 14571#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14301#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14128#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14091#L1103 assume !(0 != activate_threads_~tmp___4~0); 14079#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13824#L534 assume 1 == ~t6_pc~0; 13825#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13815#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14275#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14276#L1111 assume !(0 != activate_threads_~tmp___5~0); 14552#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14050#L553 assume !(1 == ~t7_pc~0); 13794#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 13793#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14409#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14251#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14230#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14199#L572 assume 1 == ~t8_pc~0; 13969#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13970#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14512#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13721#L1127 assume !(0 != activate_threads_~tmp___7~0); 13722#L1127-2 assume !(1 == ~M_E~0); 13723#L954-1 assume !(1 == ~T1_E~0); 14492#L959-1 assume !(1 == ~T2_E~0); 14296#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14153#L969-1 assume !(1 == ~T4_E~0); 13835#L974-1 assume !(1 == ~T5_E~0); 13836#L979-1 assume !(1 == ~T6_E~0); 14366#L984-1 assume !(1 == ~T7_E~0); 14133#L989-1 assume !(1 == ~T8_E~0); 13993#L994-1 assume !(1 == ~E_M~0); 13994#L999-1 assume !(1 == ~E_1~0); 14545#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14236#L1009-1 assume !(1 == ~E_3~0); 13910#L1014-1 assume !(1 == ~E_4~0); 13911#L1019-1 assume !(1 == ~E_5~0); 14601#L1024-1 assume !(1 == ~E_6~0); 14439#L1029-1 assume !(1 == ~E_7~0); 14204#L1034-1 assume !(1 == ~E_8~0); 13803#L1305-1 [2019-12-07 13:00:27,943 INFO L796 eck$LassoCheckResult]: Loop: 13803#L1305-1 assume !false; 13804#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 14072#L831 assume !false; 13831#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13832#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13784#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14288#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 14289#L714 assume !(0 != eval_~tmp~0); 14588#L846 start_simulation_~kernel_st~0 := 2; 14312#L592-1 start_simulation_~kernel_st~0 := 3; 14313#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14306#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14075#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14076#L866-3 assume !(0 == ~T3_E~0); 14485#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14285#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14145#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13829#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13830#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14360#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14130#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13798#L906-3 assume !(0 == ~E_2~0); 13799#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14543#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14217#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13904#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13905#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14599#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14445#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14056#L420-30 assume !(1 == ~m_pc~0); 14016#L420-32 is_master_triggered_~__retres1~0 := 0; 14017#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14528#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14529#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14612#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14192#L439-30 assume 1 == ~t1_pc~0; 14161#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14162#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14551#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14374#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14375#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14342#L458-30 assume 1 == ~t2_pc~0; 14329#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14330#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14624#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13906#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13907#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13908#L477-30 assume 1 == ~t3_pc~0; 14355#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13715#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13716#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13855#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14591#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14473#L496-30 assume 1 == ~t4_pc~0; 14474#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13932#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13933#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14086#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14299#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14300#L515-30 assume 1 == ~t5_pc~0; 14569#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14135#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14114#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14011#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 14012#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14019#L534-30 assume 1 == ~t6_pc~0; 14618#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14420#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14242#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14243#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14600#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13791#L553-30 assume 1 == ~t7_pc~0; 13749#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13751#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14388#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14327#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14328#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13968#L572-30 assume 1 == ~t8_pc~0; 13920#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13921#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14500#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13841#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13842#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 13844#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14494#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14297#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14158#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13837#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13838#L979-3 assume !(1 == ~T6_E~0); 14368#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14134#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13996#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13997#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14541#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14212#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13900#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13901#L1019-3 assume !(1 == ~E_5~0); 14597#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14442#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14206#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13708#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13709#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13786#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14290#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 14038#L1324 assume !(0 == start_simulation_~tmp~3); 14040#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14041#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13789#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14292#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 13883#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 13884#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 14561#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 14452#L1337 assume !(0 != start_simulation_~tmp___0~1); 13803#L1305-1 [2019-12-07 13:00:27,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,943 INFO L82 PathProgramCache]: Analyzing trace with hash 1320151489, now seen corresponding path program 1 times [2019-12-07 13:00:27,943 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,943 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919145163] [2019-12-07 13:00:27,943 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919145163] [2019-12-07 13:00:27,958 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,958 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,958 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165538378] [2019-12-07 13:00:27,959 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:27,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:27,959 INFO L82 PathProgramCache]: Analyzing trace with hash 2118515803, now seen corresponding path program 1 times [2019-12-07 13:00:27,959 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:27,959 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723908450] [2019-12-07 13:00:27,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:27,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:27,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:27,984 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723908450] [2019-12-07 13:00:27,984 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:27,984 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:27,985 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385339311] [2019-12-07 13:00:27,985 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:27,985 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:27,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:27,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:27,985 INFO L87 Difference]: Start difference. First operand 973 states and 1459 transitions. cyclomatic complexity: 487 Second operand 3 states. [2019-12-07 13:00:27,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:27,993 INFO L93 Difference]: Finished difference Result 973 states and 1458 transitions. [2019-12-07 13:00:27,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:27,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1458 transitions. [2019-12-07 13:00:27,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:28,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1458 transitions. [2019-12-07 13:00:28,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2019-12-07 13:00:28,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2019-12-07 13:00:28,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1458 transitions. [2019-12-07 13:00:28,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,003 INFO L688 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2019-12-07 13:00:28,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1458 transitions. [2019-12-07 13:00:28,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 973. [2019-12-07 13:00:28,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 973 states. [2019-12-07 13:00:28,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1458 transitions. [2019-12-07 13:00:28,014 INFO L711 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2019-12-07 13:00:28,014 INFO L591 BuchiCegarLoop]: Abstraction has 973 states and 1458 transitions. [2019-12-07 13:00:28,015 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-12-07 13:00:28,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973 states and 1458 transitions. [2019-12-07 13:00:28,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 862 [2019-12-07 13:00:28,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,018 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,018 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,019 INFO L794 eck$LassoCheckResult]: Stem: 16126#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16054#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16055#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16263#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 15642#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15643#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16361#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16264#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16018#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16019#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16424#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16226#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15919#L639-1 assume 0 == ~M_E~0;~M_E~0 := 1; 15920#L856-1 assume !(0 == ~T1_E~0); 16023#L861-1 assume !(0 == ~T2_E~0); 16024#L866-1 assume !(0 == ~T3_E~0); 16448#L871-1 assume !(0 == ~T4_E~0); 16251#L876-1 assume !(0 == ~T5_E~0); 16112#L881-1 assume !(0 == ~T6_E~0); 15792#L886-1 assume !(0 == ~T7_E~0); 15793#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16322#L896-1 assume !(0 == ~E_M~0); 16082#L901-1 assume !(0 == ~E_1~0); 15749#L906-1 assume !(0 == ~E_2~0); 15750#L911-1 assume !(0 == ~E_3~0); 16495#L916-1 assume !(0 == ~E_4~0); 16166#L921-1 assume !(0 == ~E_5~0); 15855#L926-1 assume !(0 == ~E_6~0); 15856#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 16551#L936-1 assume !(0 == ~E_8~0); 16396#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15819#L420 assume !(1 == ~m_pc~0); 15820#L420-2 is_master_triggered_~__retres1~0 := 0; 15826#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16433#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16492#L1063 assume !(0 != activate_threads_~tmp~1); 16603#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16071#L439 assume 1 == ~t1_pc~0; 16072#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16076#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16528#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16485#L1071 assume !(0 != activate_threads_~tmp___0~0); 16471#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16234#L458 assume !(1 == ~t2_pc~0); 16210#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 16211#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16599#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16121#L1079 assume !(0 != activate_threads_~tmp___1~0); 16122#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16123#L477 assume 1 == ~t3_pc~0; 16348#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15713#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15714#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15810#L1087 assume !(0 != activate_threads_~tmp___2~0); 16609#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16468#L496 assume !(1 == ~t4_pc~0); 16430#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 15930#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15840#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15841#L1095 assume !(0 != activate_threads_~tmp___3~0); 16403#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16404#L515 assume 1 == ~t5_pc~0; 16524#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16254#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16081#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16044#L1103 assume !(0 != activate_threads_~tmp___4~0); 16032#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15777#L534 assume 1 == ~t6_pc~0; 15778#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15768#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16228#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16229#L1111 assume !(0 != activate_threads_~tmp___5~0); 16505#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16003#L553 assume !(1 == ~t7_pc~0); 15747#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 15746#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16362#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16204#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16183#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16152#L572 assume 1 == ~t8_pc~0; 15922#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15923#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16465#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15674#L1127 assume !(0 != activate_threads_~tmp___7~0); 15675#L1127-2 assume !(1 == ~M_E~0); 15676#L954-1 assume !(1 == ~T1_E~0); 16445#L959-1 assume !(1 == ~T2_E~0); 16249#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16106#L969-1 assume !(1 == ~T4_E~0); 15788#L974-1 assume !(1 == ~T5_E~0); 15789#L979-1 assume !(1 == ~T6_E~0); 16319#L984-1 assume !(1 == ~T7_E~0); 16086#L989-1 assume !(1 == ~T8_E~0); 15946#L994-1 assume !(1 == ~E_M~0); 15947#L999-1 assume !(1 == ~E_1~0); 16498#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16189#L1009-1 assume !(1 == ~E_3~0); 15863#L1014-1 assume !(1 == ~E_4~0); 15864#L1019-1 assume !(1 == ~E_5~0); 16554#L1024-1 assume !(1 == ~E_6~0); 16392#L1029-1 assume !(1 == ~E_7~0); 16157#L1034-1 assume !(1 == ~E_8~0); 15756#L1305-1 [2019-12-07 13:00:28,019 INFO L796 eck$LassoCheckResult]: Loop: 15756#L1305-1 assume !false; 15757#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 16025#L831 assume !false; 15784#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15785#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15737#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16241#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 16242#L714 assume !(0 != eval_~tmp~0); 16541#L846 start_simulation_~kernel_st~0 := 2; 16265#L592-1 start_simulation_~kernel_st~0 := 3; 16266#L856-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16259#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16028#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16029#L866-3 assume !(0 == ~T3_E~0); 16438#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16238#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16098#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15782#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15783#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16313#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16083#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15751#L906-3 assume !(0 == ~E_2~0); 15752#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16496#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16170#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15857#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15858#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16552#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16398#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16009#L420-30 assume 1 == ~m_pc~0; 15968#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 15970#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16481#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16482#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16565#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16145#L439-30 assume 1 == ~t1_pc~0; 16114#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 16115#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16504#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16327#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16328#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16295#L458-30 assume 1 == ~t2_pc~0; 16282#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16283#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16577#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15859#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15860#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15861#L477-30 assume 1 == ~t3_pc~0; 16308#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15668#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15669#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15808#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16544#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16426#L496-30 assume 1 == ~t4_pc~0; 16427#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15885#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15886#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16039#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16252#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16253#L515-30 assume 1 == ~t5_pc~0; 16522#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16088#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16067#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15964#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 15965#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15972#L534-30 assume 1 == ~t6_pc~0; 16571#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16373#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16195#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16196#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 16553#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15744#L553-30 assume 1 == ~t7_pc~0; 15702#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15704#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16341#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16280#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16281#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15921#L572-30 assume 1 == ~t8_pc~0; 15873#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15874#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16453#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15794#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15795#L1127-32 assume 1 == ~M_E~0;~M_E~0 := 2; 15797#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16447#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16250#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16111#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15790#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15791#L979-3 assume !(1 == ~T6_E~0); 16321#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16087#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15949#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15950#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16494#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16165#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15853#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15854#L1019-3 assume !(1 == ~E_5~0); 16550#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16395#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16159#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15661#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15662#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15739#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16243#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 15991#L1324 assume !(0 == start_simulation_~tmp~3); 15993#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15994#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15742#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 16245#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 15836#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 15837#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 16514#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 16405#L1337 assume !(0 != start_simulation_~tmp___0~1); 15756#L1305-1 [2019-12-07 13:00:28,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,019 INFO L82 PathProgramCache]: Analyzing trace with hash -1034233793, now seen corresponding path program 1 times [2019-12-07 13:00:28,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021148356] [2019-12-07 13:00:28,020 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021148356] [2019-12-07 13:00:28,039 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,039 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,039 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527402117] [2019-12-07 13:00:28,040 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,040 INFO L82 PathProgramCache]: Analyzing trace with hash -1721545412, now seen corresponding path program 2 times [2019-12-07 13:00:28,040 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,040 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613908089] [2019-12-07 13:00:28,040 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,065 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613908089] [2019-12-07 13:00:28,065 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,065 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,065 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762363469] [2019-12-07 13:00:28,066 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,066 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,066 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,066 INFO L87 Difference]: Start difference. First operand 973 states and 1458 transitions. cyclomatic complexity: 486 Second operand 3 states. [2019-12-07 13:00:28,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:28,102 INFO L93 Difference]: Finished difference Result 1771 states and 2645 transitions. [2019-12-07 13:00:28,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:28,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2645 transitions. [2019-12-07 13:00:28,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2645 transitions. [2019-12-07 13:00:28,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2019-12-07 13:00:28,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2019-12-07 13:00:28,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2645 transitions. [2019-12-07 13:00:28,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,128 INFO L688 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2019-12-07 13:00:28,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2645 transitions. [2019-12-07 13:00:28,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2019-12-07 13:00:28,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1771 states. [2019-12-07 13:00:28,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2645 transitions. [2019-12-07 13:00:28,161 INFO L711 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2019-12-07 13:00:28,161 INFO L591 BuchiCegarLoop]: Abstraction has 1771 states and 2645 transitions. [2019-12-07 13:00:28,161 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-12-07 13:00:28,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2645 transitions. [2019-12-07 13:00:28,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,168 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,168 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,168 INFO L794 eck$LassoCheckResult]: Stem: 18883#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 18811#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18812#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19023#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 18393#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18394#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19127#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19024#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18774#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18775#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19202#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18985#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18672#L639-1 assume !(0 == ~M_E~0); 18673#L856-1 assume !(0 == ~T1_E~0); 18779#L861-1 assume !(0 == ~T2_E~0); 18780#L866-1 assume !(0 == ~T3_E~0); 19228#L871-1 assume !(0 == ~T4_E~0); 19011#L876-1 assume !(0 == ~T5_E~0); 18869#L881-1 assume !(0 == ~T6_E~0); 18544#L886-1 assume !(0 == ~T7_E~0); 18545#L891-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19087#L896-1 assume !(0 == ~E_M~0); 18839#L901-1 assume !(0 == ~E_1~0); 18500#L906-1 assume !(0 == ~E_2~0); 18501#L911-1 assume !(0 == ~E_3~0); 19281#L916-1 assume !(0 == ~E_4~0); 18925#L921-1 assume !(0 == ~E_5~0); 18607#L926-1 assume !(0 == ~E_6~0); 18608#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 19354#L936-1 assume !(0 == ~E_8~0); 19168#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18571#L420 assume !(1 == ~m_pc~0); 18572#L420-2 is_master_triggered_~__retres1~0 := 0; 18578#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19211#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19276#L1063 assume !(0 != activate_threads_~tmp~1); 19411#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18828#L439 assume 1 == ~t1_pc~0; 18829#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18833#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19321#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19266#L1071 assume !(0 != activate_threads_~tmp___0~0); 19252#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18993#L458 assume !(1 == ~t2_pc~0); 18969#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 18970#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19407#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18878#L1079 assume !(0 != activate_threads_~tmp___1~0); 18879#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18880#L477 assume 1 == ~t3_pc~0; 19113#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18464#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18465#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18562#L1087 assume !(0 != activate_threads_~tmp___2~0); 19417#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19249#L496 assume !(1 == ~t4_pc~0); 19208#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 18685#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18592#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 18593#L1095 assume !(0 != activate_threads_~tmp___3~0); 19176#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19177#L515 assume 1 == ~t5_pc~0; 19317#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19014#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18838#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18801#L1103 assume !(0 != activate_threads_~tmp___4~0); 18788#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18528#L534 assume 1 == ~t6_pc~0; 18529#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 18519#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18987#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18988#L1111 assume !(0 != activate_threads_~tmp___5~0); 19296#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18759#L553 assume !(1 == ~t7_pc~0); 18498#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 18497#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19128#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18963#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18942#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18910#L572 assume 1 == ~t8_pc~0; 18677#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18678#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19246#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18425#L1127 assume !(0 != activate_threads_~tmp___7~0); 18426#L1127-2 assume !(1 == ~M_E~0); 18427#L954-1 assume !(1 == ~T1_E~0); 19225#L959-1 assume !(1 == ~T2_E~0); 19009#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18863#L969-1 assume !(1 == ~T4_E~0); 18540#L974-1 assume !(1 == ~T5_E~0); 18541#L979-1 assume !(1 == ~T6_E~0); 19084#L984-1 assume !(1 == ~T7_E~0); 18843#L989-1 assume !(1 == ~T8_E~0); 18702#L994-1 assume !(1 == ~E_M~0); 18703#L999-1 assume !(1 == ~E_1~0); 19286#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 18948#L1009-1 assume !(1 == ~E_3~0); 18615#L1014-1 assume !(1 == ~E_4~0); 18616#L1019-1 assume !(1 == ~E_5~0); 19357#L1024-1 assume !(1 == ~E_6~0); 19164#L1029-1 assume !(1 == ~E_7~0); 18915#L1034-1 assume !(1 == ~E_8~0); 18916#L1305-1 [2019-12-07 13:00:28,168 INFO L796 eck$LassoCheckResult]: Loop: 18916#L1305-1 assume !false; 19430#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 19172#L831 assume !false; 18535#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18536#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 19163#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19000#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 19001#L714 assume !(0 != eval_~tmp~0); 19336#L846 start_simulation_~kernel_st~0 := 2; 19337#L592-1 start_simulation_~kernel_st~0 := 3; 19028#L856-2 assume !(0 == ~M_E~0); 19019#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18784#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18785#L866-3 assume !(0 == ~T3_E~0); 19216#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18997#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18855#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18533#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18534#L891-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19077#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18840#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18502#L906-3 assume !(0 == ~E_2~0); 18503#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19282#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19283#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20028#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20027#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20026#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20025#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20024#L420-30 assume !(1 == ~m_pc~0); 20022#L420-32 is_master_triggered_~__retres1~0 := 0; 20021#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20020#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20019#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20018#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20017#L439-30 assume !(1 == ~t1_pc~0); 20016#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 20014#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20013#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20012#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20011#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20010#L458-30 assume !(1 == ~t2_pc~0); 20008#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 20007#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20006#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20005#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20004#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20003#L477-30 assume 1 == ~t3_pc~0; 20001#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20000#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19999#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19998#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19997#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19996#L496-30 assume !(1 == ~t4_pc~0); 19994#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 19993#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19992#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19991#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 19990#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19989#L515-30 assume 1 == ~t5_pc~0; 19987#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19986#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19985#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19984#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 19983#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19982#L534-30 assume 1 == ~t6_pc~0; 19980#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19979#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19978#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 19977#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19976#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19975#L553-30 assume !(1 == ~t7_pc~0); 19973#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 19972#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19971#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 19970#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19969#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19968#L572-30 assume 1 == ~t8_pc~0; 18626#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18627#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19234#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18546#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18547#L1127-32 assume !(1 == ~M_E~0); 18549#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19227#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19010#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18868#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18542#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18543#L979-3 assume !(1 == ~T6_E~0); 19086#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18844#L989-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18705#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18706#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19280#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18924#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18605#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18606#L1019-3 assume !(1 == ~E_5~0); 19353#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19167#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18918#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18412#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18413#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18490#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19002#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 18747#L1324 assume !(0 == start_simulation_~tmp~3); 18749#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18750#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 19157#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19004#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 19005#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19448#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 19305#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 19306#L1337 assume !(0 != start_simulation_~tmp___0~1); 18916#L1305-1 [2019-12-07 13:00:28,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,169 INFO L82 PathProgramCache]: Analyzing trace with hash 842829437, now seen corresponding path program 1 times [2019-12-07 13:00:28,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882053530] [2019-12-07 13:00:28,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,191 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882053530] [2019-12-07 13:00:28,191 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,191 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,191 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413653850] [2019-12-07 13:00:28,192 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,192 INFO L82 PathProgramCache]: Analyzing trace with hash -742877861, now seen corresponding path program 1 times [2019-12-07 13:00:28,192 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,192 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172469787] [2019-12-07 13:00:28,192 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,218 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172469787] [2019-12-07 13:00:28,218 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,219 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,219 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323194388] [2019-12-07 13:00:28,219 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,219 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,219 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,219 INFO L87 Difference]: Start difference. First operand 1771 states and 2645 transitions. cyclomatic complexity: 875 Second operand 3 states. [2019-12-07 13:00:28,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:28,244 INFO L93 Difference]: Finished difference Result 1771 states and 2637 transitions. [2019-12-07 13:00:28,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:28,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2637 transitions. [2019-12-07 13:00:28,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2637 transitions. [2019-12-07 13:00:28,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2019-12-07 13:00:28,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2019-12-07 13:00:28,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2637 transitions. [2019-12-07 13:00:28,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,263 INFO L688 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2019-12-07 13:00:28,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2637 transitions. [2019-12-07 13:00:28,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2019-12-07 13:00:28,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1771 states. [2019-12-07 13:00:28,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2637 transitions. [2019-12-07 13:00:28,288 INFO L711 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2019-12-07 13:00:28,288 INFO L591 BuchiCegarLoop]: Abstraction has 1771 states and 2637 transitions. [2019-12-07 13:00:28,288 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-12-07 13:00:28,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2637 transitions. [2019-12-07 13:00:28,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,292 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,292 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,293 INFO L794 eck$LassoCheckResult]: Stem: 22435#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 22360#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 22361#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22572#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 21942#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21943#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22679#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22573#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22320#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22321#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22747#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22534#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22222#L639-1 assume !(0 == ~M_E~0); 22223#L856-1 assume !(0 == ~T1_E~0); 22325#L861-1 assume !(0 == ~T2_E~0); 22326#L866-1 assume !(0 == ~T3_E~0); 22772#L871-1 assume !(0 == ~T4_E~0); 22559#L876-1 assume !(0 == ~T5_E~0); 22417#L881-1 assume !(0 == ~T6_E~0); 22093#L886-1 assume !(0 == ~T7_E~0); 22094#L891-1 assume !(0 == ~T8_E~0); 22637#L896-1 assume !(0 == ~E_M~0); 22385#L901-1 assume !(0 == ~E_1~0); 22049#L906-1 assume !(0 == ~E_2~0); 22050#L911-1 assume !(0 == ~E_3~0); 22828#L916-1 assume !(0 == ~E_4~0); 22476#L921-1 assume !(0 == ~E_5~0); 22157#L926-1 assume !(0 == ~E_6~0); 22158#L931-1 assume 0 == ~E_7~0;~E_7~0 := 1; 22896#L936-1 assume !(0 == ~E_8~0); 22718#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22121#L420 assume !(1 == ~m_pc~0); 22122#L420-2 is_master_triggered_~__retres1~0 := 0; 22128#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22760#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22822#L1063 assume !(0 != activate_threads_~tmp~1); 22951#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22374#L439 assume 1 == ~t1_pc~0; 22375#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22379#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22866#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22814#L1071 assume !(0 != activate_threads_~tmp___0~0); 22800#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22542#L458 assume !(1 == ~t2_pc~0); 22518#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 22519#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22947#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22426#L1079 assume !(0 != activate_threads_~tmp___1~0); 22427#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22428#L477 assume 1 == ~t3_pc~0; 22665#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22017#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22018#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22112#L1087 assume !(0 != activate_threads_~tmp___2~0); 22957#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22797#L496 assume !(1 == ~t4_pc~0); 22753#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 22237#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22142#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22143#L1095 assume !(0 != activate_threads_~tmp___3~0); 22724#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22725#L515 assume 1 == ~t5_pc~0; 22860#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22562#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22384#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22347#L1103 assume !(0 != activate_threads_~tmp___4~0); 22335#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22077#L534 assume 1 == ~t6_pc~0; 22078#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22068#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22536#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22537#L1111 assume !(0 != activate_threads_~tmp___5~0); 22839#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22306#L553 assume !(1 == ~t7_pc~0); 22047#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 22046#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22681#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22511#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22490#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22459#L572 assume 1 == ~t8_pc~0; 22226#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 22227#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 22794#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21974#L1127 assume !(0 != activate_threads_~tmp___7~0); 21975#L1127-2 assume !(1 == ~M_E~0); 21976#L954-1 assume !(1 == ~T1_E~0); 22770#L959-1 assume !(1 == ~T2_E~0); 22557#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22411#L969-1 assume !(1 == ~T4_E~0); 22089#L974-1 assume !(1 == ~T5_E~0); 22090#L979-1 assume !(1 == ~T6_E~0); 22633#L984-1 assume !(1 == ~T7_E~0); 22389#L989-1 assume !(1 == ~T8_E~0); 22249#L994-1 assume !(1 == ~E_M~0); 22250#L999-1 assume !(1 == ~E_1~0); 22832#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22496#L1009-1 assume !(1 == ~E_3~0); 22167#L1014-1 assume !(1 == ~E_4~0); 22168#L1019-1 assume !(1 == ~E_5~0); 22899#L1024-1 assume !(1 == ~E_6~0); 22713#L1029-1 assume !(1 == ~E_7~0); 22463#L1034-1 assume !(1 == ~E_8~0); 22464#L1305-1 [2019-12-07 13:00:28,293 INFO L796 eck$LassoCheckResult]: Loop: 22464#L1305-1 assume !false; 22973#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 22972#L831 assume !false; 22971#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22970#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22711#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22549#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22550#L714 assume !(0 != eval_~tmp~0); 22877#L846 start_simulation_~kernel_st~0 := 2; 22878#L592-1 start_simulation_~kernel_st~0 := 3; 22577#L856-2 assume !(0 == ~M_E~0); 22568#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22330#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22331#L866-3 assume !(0 == ~T3_E~0); 22761#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22546#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22403#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22082#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22083#L891-3 assume !(0 == ~T8_E~0); 22626#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22386#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22051#L906-3 assume !(0 == ~E_2~0); 22052#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22829#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22478#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22159#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22160#L931-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22897#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22719#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22311#L420-30 assume 1 == ~m_pc~0; 22270#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 22272#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22810#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22811#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22913#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22450#L439-30 assume 1 == ~t1_pc~0; 22419#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22420#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22838#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22642#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22643#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22607#L458-30 assume 1 == ~t2_pc~0; 22594#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22595#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22925#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22161#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22162#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22163#L477-30 assume 1 == ~t3_pc~0; 22621#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 21968#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21969#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22110#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22888#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22749#L496-30 assume 1 == ~t4_pc~0; 22750#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22187#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22188#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22342#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22560#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22561#L515-30 assume 1 == ~t5_pc~0; 22858#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22391#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22370#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22263#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 22264#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22274#L534-30 assume 1 == ~t6_pc~0; 22919#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22691#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22502#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22503#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22898#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22044#L553-30 assume 1 == ~t7_pc~0; 22002#L554-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 22004#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22657#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 22592#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22593#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 22221#L572-30 assume !(1 == ~t8_pc~0); 22177#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 22176#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 22777#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 22778#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 22098#L1127-32 assume !(1 == ~M_E~0); 22099#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22771#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22558#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22416#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22091#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22092#L979-3 assume !(1 == ~T6_E~0); 22635#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22636#L989-3 assume !(1 == ~T8_E~0); 23439#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23438#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23437#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23436#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23435#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23434#L1019-3 assume !(1 == ~E_5~0); 23433#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23432#L1029-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23431#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23429#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 23421#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 23412#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 23410#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 23023#L1324 assume !(0 == start_simulation_~tmp~3); 23018#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22826#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 22042#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22553#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 22138#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 22139#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 22848#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 22849#L1337 assume !(0 != start_simulation_~tmp___0~1); 22464#L1305-1 [2019-12-07 13:00:28,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,293 INFO L82 PathProgramCache]: Analyzing trace with hash -1885379909, now seen corresponding path program 1 times [2019-12-07 13:00:28,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812008340] [2019-12-07 13:00:28,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,324 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812008340] [2019-12-07 13:00:28,325 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,325 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,325 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935883140] [2019-12-07 13:00:28,325 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,325 INFO L82 PathProgramCache]: Analyzing trace with hash -977242013, now seen corresponding path program 1 times [2019-12-07 13:00:28,325 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120278554] [2019-12-07 13:00:28,326 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,351 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120278554] [2019-12-07 13:00:28,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,352 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,352 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103574206] [2019-12-07 13:00:28,352 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,352 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,352 INFO L87 Difference]: Start difference. First operand 1771 states and 2637 transitions. cyclomatic complexity: 867 Second operand 3 states. [2019-12-07 13:00:28,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:28,395 INFO L93 Difference]: Finished difference Result 1771 states and 2609 transitions. [2019-12-07 13:00:28,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:28,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1771 states and 2609 transitions. [2019-12-07 13:00:28,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1771 states to 1771 states and 2609 transitions. [2019-12-07 13:00:28,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1771 [2019-12-07 13:00:28,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1771 [2019-12-07 13:00:28,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1771 states and 2609 transitions. [2019-12-07 13:00:28,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,412 INFO L688 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2019-12-07 13:00:28,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1771 states and 2609 transitions. [2019-12-07 13:00:28,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1771 to 1771. [2019-12-07 13:00:28,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1771 states. [2019-12-07 13:00:28,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2609 transitions. [2019-12-07 13:00:28,435 INFO L711 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2019-12-07 13:00:28,435 INFO L591 BuchiCegarLoop]: Abstraction has 1771 states and 2609 transitions. [2019-12-07 13:00:28,435 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-12-07 13:00:28,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1771 states and 2609 transitions. [2019-12-07 13:00:28,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1660 [2019-12-07 13:00:28,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,440 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,440 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,440 INFO L794 eck$LassoCheckResult]: Stem: 25986#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 25911#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25912#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26123#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 25491#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25492#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26227#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26124#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25871#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25872#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26300#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26086#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25764#L639-1 assume !(0 == ~M_E~0); 25765#L856-1 assume !(0 == ~T1_E~0); 25877#L861-1 assume !(0 == ~T2_E~0); 25878#L866-1 assume !(0 == ~T3_E~0); 26325#L871-1 assume !(0 == ~T4_E~0); 26111#L876-1 assume !(0 == ~T5_E~0); 25968#L881-1 assume !(0 == ~T6_E~0); 25636#L886-1 assume !(0 == ~T7_E~0); 25637#L891-1 assume !(0 == ~T8_E~0); 26185#L896-1 assume !(0 == ~E_M~0); 25937#L901-1 assume !(0 == ~E_1~0); 25590#L906-1 assume !(0 == ~E_2~0); 25591#L911-1 assume !(0 == ~E_3~0); 26377#L916-1 assume !(0 == ~E_4~0); 26027#L921-1 assume !(0 == ~E_5~0); 25699#L926-1 assume !(0 == ~E_6~0); 25700#L931-1 assume !(0 == ~E_7~0); 26447#L936-1 assume !(0 == ~E_8~0); 26270#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25663#L420 assume !(1 == ~m_pc~0); 25664#L420-2 is_master_triggered_~__retres1~0 := 0; 25670#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26313#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26373#L1063 assume !(0 != activate_threads_~tmp~1); 26505#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25925#L439 assume 1 == ~t1_pc~0; 25926#L440 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 25931#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26415#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26362#L1071 assume !(0 != activate_threads_~tmp___0~0); 26348#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26094#L458 assume !(1 == ~t2_pc~0); 26070#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 26071#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26501#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25977#L1079 assume !(0 != activate_threads_~tmp___1~0); 25978#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25979#L477 assume 1 == ~t3_pc~0; 26214#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 25560#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25561#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25654#L1087 assume !(0 != activate_threads_~tmp___2~0); 26513#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26345#L496 assume !(1 == ~t4_pc~0); 26306#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 25779#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25684#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25685#L1095 assume !(0 != activate_threads_~tmp___3~0); 26276#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26277#L515 assume 1 == ~t5_pc~0; 26408#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26114#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25936#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 25898#L1103 assume !(0 != activate_threads_~tmp___4~0); 25887#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25620#L534 assume 1 == ~t6_pc~0; 25621#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 25610#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26088#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 26089#L1111 assume !(0 != activate_threads_~tmp___5~0); 26387#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25855#L553 assume !(1 == ~t7_pc~0); 25588#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 25860#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26229#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 26064#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 26043#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 26010#L572 assume 1 == ~t8_pc~0; 25768#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 25769#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 26342#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25523#L1127 assume !(0 != activate_threads_~tmp___7~0); 25524#L1127-2 assume !(1 == ~M_E~0); 25525#L954-1 assume !(1 == ~T1_E~0); 26323#L959-1 assume !(1 == ~T2_E~0); 26109#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25962#L969-1 assume !(1 == ~T4_E~0); 25632#L974-1 assume !(1 == ~T5_E~0); 25633#L979-1 assume !(1 == ~T6_E~0); 26182#L984-1 assume !(1 == ~T7_E~0); 25941#L989-1 assume !(1 == ~T8_E~0); 25792#L994-1 assume !(1 == ~E_M~0); 25793#L999-1 assume !(1 == ~E_1~0); 26380#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26049#L1009-1 assume !(1 == ~E_3~0); 25709#L1014-1 assume !(1 == ~E_4~0); 25710#L1019-1 assume !(1 == ~E_5~0); 26450#L1024-1 assume !(1 == ~E_6~0); 26265#L1029-1 assume !(1 == ~E_7~0); 26014#L1034-1 assume !(1 == ~E_8~0); 26015#L1305-1 [2019-12-07 13:00:28,440 INFO L796 eck$LassoCheckResult]: Loop: 26015#L1305-1 assume !false; 26529#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 26528#L831 assume !false; 26527#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26526#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26263#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26101#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 26102#L714 assume !(0 != eval_~tmp~0); 26427#L846 start_simulation_~kernel_st~0 := 2; 26428#L592-1 start_simulation_~kernel_st~0 := 3; 26128#L856-2 assume !(0 == ~M_E~0); 26119#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25882#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25883#L866-3 assume !(0 == ~T3_E~0); 26314#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26098#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25953#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25625#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25626#L891-3 assume !(0 == ~T8_E~0); 26176#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25938#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25592#L906-3 assume !(0 == ~E_2~0); 25593#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26378#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26029#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26030#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27146#L931-3 assume !(0 == ~E_7~0); 27145#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27144#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27143#L420-30 assume !(1 == ~m_pc~0); 27141#L420-32 is_master_triggered_~__retres1~0 := 0; 27140#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27139#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 27138#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27137#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27136#L439-30 assume 1 == ~t1_pc~0; 27134#L440-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27133#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27132#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27131#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27130#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27129#L458-30 assume !(1 == ~t2_pc~0); 27127#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 27126#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27125#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 27124#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27123#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27122#L477-30 assume 1 == ~t3_pc~0; 27120#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 27119#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27118#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27117#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27116#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27115#L496-30 assume !(1 == ~t4_pc~0); 27113#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 27112#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27111#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27110#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27109#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27108#L515-30 assume 1 == ~t5_pc~0; 27106#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 27105#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27104#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27103#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 25823#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 25824#L534-30 assume 1 == ~t6_pc~0; 26470#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 26239#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26055#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 26056#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 26449#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 25586#L553-30 assume !(1 == ~t7_pc~0); 25549#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 25556#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26207#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 26141#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 26142#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25763#L572-30 assume 1 == ~t8_pc~0; 25717#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 25718#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 26330#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25638#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25639#L1127-32 assume !(1 == ~M_E~0); 25641#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26324#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26110#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25967#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25634#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25635#L979-3 assume !(1 == ~T6_E~0); 26184#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25942#L989-3 assume !(1 == ~T8_E~0); 25795#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25796#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26376#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26023#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25697#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25698#L1019-3 assume !(1 == ~E_5~0); 26446#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26266#L1029-3 assume !(1 == ~E_7~0); 26267#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26903#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26893#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 26884#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26881#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 26879#L1324 assume !(0 == start_simulation_~tmp~3); 26876#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 26375#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 25584#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 26105#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 25680#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 25681#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 26396#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 26397#L1337 assume !(0 != start_simulation_~tmp___0~1); 26015#L1305-1 [2019-12-07 13:00:28,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,441 INFO L82 PathProgramCache]: Analyzing trace with hash -998157063, now seen corresponding path program 1 times [2019-12-07 13:00:28,441 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,441 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539911113] [2019-12-07 13:00:28,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,461 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539911113] [2019-12-07 13:00:28,461 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,461 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,461 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866617805] [2019-12-07 13:00:28,461 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,462 INFO L82 PathProgramCache]: Analyzing trace with hash -1785918204, now seen corresponding path program 1 times [2019-12-07 13:00:28,462 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,462 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765191139] [2019-12-07 13:00:28,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,487 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765191139] [2019-12-07 13:00:28,487 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,487 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,487 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326900938] [2019-12-07 13:00:28,487 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,487 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,488 INFO L87 Difference]: Start difference. First operand 1771 states and 2609 transitions. cyclomatic complexity: 839 Second operand 3 states. [2019-12-07 13:00:28,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:28,545 INFO L93 Difference]: Finished difference Result 3283 states and 4808 transitions. [2019-12-07 13:00:28,545 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:28,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3283 states and 4808 transitions. [2019-12-07 13:00:28,555 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3169 [2019-12-07 13:00:28,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3283 states to 3283 states and 4808 transitions. [2019-12-07 13:00:28,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3283 [2019-12-07 13:00:28,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3283 [2019-12-07 13:00:28,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3283 states and 4808 transitions. [2019-12-07 13:00:28,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,575 INFO L688 BuchiCegarLoop]: Abstraction has 3283 states and 4808 transitions. [2019-12-07 13:00:28,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3283 states and 4808 transitions. [2019-12-07 13:00:28,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3283 to 3279. [2019-12-07 13:00:28,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3279 states. [2019-12-07 13:00:28,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3279 states to 3279 states and 4804 transitions. [2019-12-07 13:00:28,615 INFO L711 BuchiCegarLoop]: Abstraction has 3279 states and 4804 transitions. [2019-12-07 13:00:28,615 INFO L591 BuchiCegarLoop]: Abstraction has 3279 states and 4804 transitions. [2019-12-07 13:00:28,615 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-12-07 13:00:28,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3279 states and 4804 transitions. [2019-12-07 13:00:28,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3165 [2019-12-07 13:00:28,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,623 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,623 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,624 INFO L794 eck$LassoCheckResult]: Stem: 31060#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 30981#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 30982#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 31218#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 30552#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30553#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31332#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31219#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30944#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30945#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31412#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31177#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30829#L639-1 assume !(0 == ~M_E~0); 30830#L856-1 assume !(0 == ~T1_E~0); 30949#L861-1 assume !(0 == ~T2_E~0); 30950#L866-1 assume !(0 == ~T3_E~0); 31437#L871-1 assume !(0 == ~T4_E~0); 31203#L876-1 assume !(0 == ~T5_E~0); 31042#L881-1 assume !(0 == ~T6_E~0); 30697#L886-1 assume !(0 == ~T7_E~0); 30698#L891-1 assume !(0 == ~T8_E~0); 31290#L896-1 assume !(0 == ~E_M~0); 31009#L901-1 assume !(0 == ~E_1~0); 30652#L906-1 assume !(0 == ~E_2~0); 30653#L911-1 assume !(0 == ~E_3~0); 31492#L916-1 assume !(0 == ~E_4~0); 31115#L921-1 assume !(0 == ~E_5~0); 30762#L926-1 assume !(0 == ~E_6~0); 30763#L931-1 assume !(0 == ~E_7~0); 31570#L936-1 assume !(0 == ~E_8~0); 31376#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30726#L420 assume !(1 == ~m_pc~0); 30727#L420-2 is_master_triggered_~__retres1~0 := 0; 30733#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31421#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 31488#L1063 assume !(0 != activate_threads_~tmp~1); 31645#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30998#L439 assume !(1 == ~t1_pc~0); 30999#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 31002#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31528#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 31479#L1071 assume !(0 != activate_threads_~tmp___0~0); 31462#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31185#L458 assume !(1 == ~t2_pc~0); 31161#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 31162#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31637#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31051#L1079 assume !(0 != activate_threads_~tmp___1~0); 31052#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31053#L477 assume 1 == ~t3_pc~0; 31319#L478 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30618#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30619#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30717#L1087 assume !(0 != activate_threads_~tmp___2~0); 31652#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31459#L496 assume !(1 == ~t4_pc~0); 31418#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 30840#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30747#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30748#L1095 assume !(0 != activate_threads_~tmp___3~0); 31385#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31386#L515 assume 1 == ~t5_pc~0; 31524#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 31208#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31008#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30972#L1103 assume !(0 != activate_threads_~tmp___4~0); 30959#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30681#L534 assume 1 == ~t6_pc~0; 30682#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 30672#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31179#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 31180#L1111 assume !(0 != activate_threads_~tmp___5~0); 31505#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30925#L553 assume !(1 == ~t7_pc~0); 30650#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 30933#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31333#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 31154#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 31132#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 31092#L572 assume 1 == ~t8_pc~0; 30832#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 30833#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31456#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 30584#L1127 assume !(0 != activate_threads_~tmp___7~0); 30585#L1127-2 assume !(1 == ~M_E~0); 30586#L954-1 assume !(1 == ~T1_E~0); 31434#L959-1 assume !(1 == ~T2_E~0); 31201#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31036#L969-1 assume !(1 == ~T4_E~0); 30693#L974-1 assume !(1 == ~T5_E~0); 30694#L979-1 assume !(1 == ~T6_E~0); 31285#L984-1 assume !(1 == ~T7_E~0); 31013#L989-1 assume !(1 == ~T8_E~0); 30859#L994-1 assume !(1 == ~E_M~0); 30860#L999-1 assume !(1 == ~E_1~0); 31496#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31138#L1009-1 assume !(1 == ~E_3~0); 30770#L1014-1 assume !(1 == ~E_4~0); 30771#L1019-1 assume !(1 == ~E_5~0); 31576#L1024-1 assume !(1 == ~E_6~0); 31371#L1029-1 assume !(1 == ~E_7~0); 31100#L1034-1 assume !(1 == ~E_8~0); 31101#L1305-1 [2019-12-07 13:00:28,624 INFO L796 eck$LassoCheckResult]: Loop: 31101#L1305-1 assume !false; 32057#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 31380#L831 assume !false; 30688#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 30689#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 30640#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 31192#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 31193#L714 assume !(0 != eval_~tmp~0); 31545#L846 start_simulation_~kernel_st~0 := 2; 31220#L592-1 start_simulation_~kernel_st~0 := 3; 31221#L856-2 assume !(0 == ~M_E~0); 31214#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30955#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30956#L866-3 assume !(0 == ~T3_E~0); 31427#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31189#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31028#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30686#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30687#L891-3 assume !(0 == ~T8_E~0); 31277#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31010#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30654#L906-3 assume !(0 == ~E_2~0); 30655#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31493#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31119#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30764#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30765#L931-3 assume !(0 == ~E_7~0); 31571#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31378#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30934#L420-30 assume 1 == ~m_pc~0; 30884#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 30886#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31475#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 31476#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 31596#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31079#L439-30 assume !(1 == ~t1_pc~0); 31080#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 31082#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31504#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 31295#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 31296#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31258#L458-30 assume 1 == ~t2_pc~0; 31242#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 31243#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31611#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30766#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30767#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30768#L477-30 assume 1 == ~t3_pc~0; 31272#L478-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30578#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30579#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30715#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31558#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31414#L496-30 assume 1 == ~t4_pc~0; 31415#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 30793#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30794#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30966#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31204#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31205#L515-30 assume 1 == ~t5_pc~0; 31522#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 31016#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30994#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30880#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 30881#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30889#L534-30 assume 1 == ~t6_pc~0; 31604#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 31344#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31144#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 31145#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 31572#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30648#L553-30 assume !(1 == ~t7_pc~0); 30610#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 30617#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31309#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 31240#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 31241#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 30831#L572-30 assume 1 == ~t8_pc~0; 30781#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 30782#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31443#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 30699#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 30700#L1127-32 assume !(1 == ~M_E~0); 30703#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31436#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31202#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31041#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30695#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30696#L979-3 assume !(1 == ~T6_E~0); 31288#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31289#L989-3 assume !(1 == ~T8_E~0); 32232#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32231#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32230#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32229#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32228#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32227#L1019-3 assume !(1 == ~E_5~0); 32226#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32225#L1029-3 assume !(1 == ~E_7~0); 32223#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32221#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 32213#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32204#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 32202#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 30912#L1324 assume !(0 == start_simulation_~tmp~3); 30914#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 32081#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 32071#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 32069#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 32066#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 32064#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 32062#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 32060#L1337 assume !(0 != start_simulation_~tmp___0~1); 31101#L1305-1 [2019-12-07 13:00:28,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,624 INFO L82 PathProgramCache]: Analyzing trace with hash -620514246, now seen corresponding path program 1 times [2019-12-07 13:00:28,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549742994] [2019-12-07 13:00:28,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549742994] [2019-12-07 13:00:28,645 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,645 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,645 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187579603] [2019-12-07 13:00:28,646 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,646 INFO L82 PathProgramCache]: Analyzing trace with hash -216265082, now seen corresponding path program 1 times [2019-12-07 13:00:28,646 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,646 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664912682] [2019-12-07 13:00:28,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664912682] [2019-12-07 13:00:28,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,674 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,674 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817498179] [2019-12-07 13:00:28,675 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,675 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,675 INFO L87 Difference]: Start difference. First operand 3279 states and 4804 transitions. cyclomatic complexity: 1527 Second operand 3 states. [2019-12-07 13:00:28,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:28,741 INFO L93 Difference]: Finished difference Result 6157 states and 8974 transitions. [2019-12-07 13:00:28,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:28,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6157 states and 8974 transitions. [2019-12-07 13:00:28,759 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6032 [2019-12-07 13:00:28,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6157 states to 6157 states and 8974 transitions. [2019-12-07 13:00:28,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6157 [2019-12-07 13:00:28,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6157 [2019-12-07 13:00:28,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6157 states and 8974 transitions. [2019-12-07 13:00:28,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:28,796 INFO L688 BuchiCegarLoop]: Abstraction has 6157 states and 8974 transitions. [2019-12-07 13:00:28,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6157 states and 8974 transitions. [2019-12-07 13:00:28,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6157 to 6149. [2019-12-07 13:00:28,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6149 states. [2019-12-07 13:00:28,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6149 states to 6149 states and 8966 transitions. [2019-12-07 13:00:28,873 INFO L711 BuchiCegarLoop]: Abstraction has 6149 states and 8966 transitions. [2019-12-07 13:00:28,873 INFO L591 BuchiCegarLoop]: Abstraction has 6149 states and 8966 transitions. [2019-12-07 13:00:28,873 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-12-07 13:00:28,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6149 states and 8966 transitions. [2019-12-07 13:00:28,886 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6024 [2019-12-07 13:00:28,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:28,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:28,887 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,888 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:28,888 INFO L794 eck$LassoCheckResult]: Stem: 40498#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 40420#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 40421#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40660#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 39995#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39996#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40769#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40661#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40384#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40385#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40865#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40622#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40272#L639-1 assume !(0 == ~M_E~0); 40273#L856-1 assume !(0 == ~T1_E~0); 40389#L861-1 assume !(0 == ~T2_E~0); 40390#L866-1 assume !(0 == ~T3_E~0); 40891#L871-1 assume !(0 == ~T4_E~0); 40647#L876-1 assume !(0 == ~T5_E~0); 40482#L881-1 assume !(0 == ~T6_E~0); 40141#L886-1 assume !(0 == ~T7_E~0); 40142#L891-1 assume !(0 == ~T8_E~0); 40727#L896-1 assume !(0 == ~E_M~0); 40448#L901-1 assume !(0 == ~E_1~0); 40096#L906-1 assume !(0 == ~E_2~0); 40097#L911-1 assume !(0 == ~E_3~0); 40947#L916-1 assume !(0 == ~E_4~0); 40559#L921-1 assume !(0 == ~E_5~0); 40206#L926-1 assume !(0 == ~E_6~0); 40207#L931-1 assume !(0 == ~E_7~0); 41023#L936-1 assume !(0 == ~E_8~0); 40811#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40170#L420 assume !(1 == ~m_pc~0); 40171#L420-2 is_master_triggered_~__retres1~0 := 0; 40177#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40875#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40942#L1063 assume !(0 != activate_threads_~tmp~1); 41100#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40438#L439 assume !(1 == ~t1_pc~0); 40439#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 40442#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40986#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40931#L1071 assume !(0 != activate_threads_~tmp___0~0); 40915#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40630#L458 assume !(1 == ~t2_pc~0); 40604#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 40605#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41089#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40491#L1079 assume !(0 != activate_threads_~tmp___1~0); 40492#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40493#L477 assume !(1 == ~t3_pc~0); 40757#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 40063#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40064#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40160#L1087 assume !(0 != activate_threads_~tmp___2~0); 41107#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40912#L496 assume !(1 == ~t4_pc~0); 40871#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 40283#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40191#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 40192#L1095 assume !(0 != activate_threads_~tmp___3~0); 40822#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40823#L515 assume 1 == ~t5_pc~0; 40982#L516 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 40651#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40447#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 40412#L1103 assume !(0 != activate_threads_~tmp___4~0); 40398#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40125#L534 assume 1 == ~t6_pc~0; 40126#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 40116#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40624#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 40625#L1111 assume !(0 != activate_threads_~tmp___5~0); 40961#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40365#L553 assume !(1 == ~t7_pc~0); 40094#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 40373#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40770#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 40598#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40576#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40537#L572 assume 1 == ~t8_pc~0; 40275#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 40276#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40909#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 40029#L1127 assume !(0 != activate_threads_~tmp___7~0); 40030#L1127-2 assume !(1 == ~M_E~0); 40031#L954-1 assume !(1 == ~T1_E~0); 40888#L959-1 assume !(1 == ~T2_E~0); 40645#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40476#L969-1 assume !(1 == ~T4_E~0); 40137#L974-1 assume !(1 == ~T5_E~0); 40138#L979-1 assume !(1 == ~T6_E~0); 40723#L984-1 assume !(1 == ~T7_E~0); 40453#L989-1 assume !(1 == ~T8_E~0); 40301#L994-1 assume !(1 == ~E_M~0); 40302#L999-1 assume !(1 == ~E_1~0); 40950#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 40582#L1009-1 assume !(1 == ~E_3~0); 40214#L1014-1 assume !(1 == ~E_4~0); 40215#L1019-1 assume !(1 == ~E_5~0); 41027#L1024-1 assume !(1 == ~E_6~0); 40806#L1029-1 assume !(1 == ~E_7~0); 40548#L1034-1 assume !(1 == ~E_8~0); 40104#L1305-1 [2019-12-07 13:00:28,888 INFO L796 eck$LassoCheckResult]: Loop: 40104#L1305-1 assume !false; 40105#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 40391#L831 assume !false; 40132#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 40133#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 40084#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 40805#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 41001#L714 assume !(0 != eval_~tmp~0); 41003#L846 start_simulation_~kernel_st~0 := 2; 46089#L592-1 start_simulation_~kernel_st~0 := 3; 46087#L856-2 assume !(0 == ~M_E~0); 46085#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46083#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46081#L866-3 assume !(0 == ~T3_E~0); 46079#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46077#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46075#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46073#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46071#L891-3 assume !(0 == ~T8_E~0); 46069#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46067#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46065#L906-3 assume !(0 == ~E_2~0); 46063#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46061#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46059#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46057#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46055#L931-3 assume !(0 == ~E_7~0); 46053#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46051#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46048#L420-30 assume !(1 == ~m_pc~0); 46045#L420-32 is_master_triggered_~__retres1~0 := 0; 46043#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46041#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 46040#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45877#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40519#L439-30 assume !(1 == ~t1_pc~0); 40520#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 40522#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40960#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40733#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40734#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40697#L458-30 assume 1 == ~t2_pc~0; 40683#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40684#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41065#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40210#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40211#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40212#L477-30 assume !(1 == ~t3_pc~0); 45963#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 40023#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40024#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40158#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 41010#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40867#L496-30 assume 1 == ~t4_pc~0; 40868#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40874#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45945#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 45944#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40649#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40650#L515-30 assume 1 == ~t5_pc~0; 40980#L516-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 40455#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40433#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 40321#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 40322#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40330#L534-30 assume 1 == ~t6_pc~0; 41057#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 40783#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40784#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 45741#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 45740#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45739#L553-30 assume !(1 == ~t7_pc~0); 45737#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 45736#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 45728#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 40681#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40682#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40274#L572-30 assume 1 == ~t8_pc~0; 40224#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 40225#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40897#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 40143#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 40144#L1127-32 assume !(1 == ~M_E~0); 40147#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45913#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45912#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45911#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45910#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45909#L979-3 assume !(1 == ~T6_E~0); 45908#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45907#L989-3 assume !(1 == ~T8_E~0); 45906#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45905#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45904#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45903#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45902#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45901#L1019-3 assume !(1 == ~E_5~0); 45900#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45899#L1029-3 assume !(1 == ~E_7~0); 45898#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45897#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 45895#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 45887#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 45886#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 45885#L1324 assume !(0 == start_simulation_~tmp~3); 44639#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 40945#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 40090#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 40641#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 40187#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 40188#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 40971#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 40825#L1337 assume !(0 != start_simulation_~tmp___0~1); 40104#L1305-1 [2019-12-07 13:00:28,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,888 INFO L82 PathProgramCache]: Analyzing trace with hash -894292741, now seen corresponding path program 1 times [2019-12-07 13:00:28,888 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,888 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785703140] [2019-12-07 13:00:28,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,910 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785703140] [2019-12-07 13:00:28,910 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,910 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:28,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781370184] [2019-12-07 13:00:28,911 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:28,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:28,911 INFO L82 PathProgramCache]: Analyzing trace with hash -1849145724, now seen corresponding path program 1 times [2019-12-07 13:00:28,911 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:28,911 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356383296] [2019-12-07 13:00:28,911 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:28,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:28,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:28,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356383296] [2019-12-07 13:00:28,936 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:28,936 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:28,936 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371952801] [2019-12-07 13:00:28,936 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:28,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:28,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:28,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:28,936 INFO L87 Difference]: Start difference. First operand 6149 states and 8966 transitions. cyclomatic complexity: 2821 Second operand 3 states. [2019-12-07 13:00:29,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:29,025 INFO L93 Difference]: Finished difference Result 11616 states and 16859 transitions. [2019-12-07 13:00:29,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:29,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11616 states and 16859 transitions. [2019-12-07 13:00:29,070 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11460 [2019-12-07 13:00:29,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11616 states to 11616 states and 16859 transitions. [2019-12-07 13:00:29,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11616 [2019-12-07 13:00:29,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11616 [2019-12-07 13:00:29,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11616 states and 16859 transitions. [2019-12-07 13:00:29,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:29,122 INFO L688 BuchiCegarLoop]: Abstraction has 11616 states and 16859 transitions. [2019-12-07 13:00:29,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11616 states and 16859 transitions. [2019-12-07 13:00:29,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11616 to 11600. [2019-12-07 13:00:29,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11600 states. [2019-12-07 13:00:29,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11600 states to 11600 states and 16843 transitions. [2019-12-07 13:00:29,218 INFO L711 BuchiCegarLoop]: Abstraction has 11600 states and 16843 transitions. [2019-12-07 13:00:29,218 INFO L591 BuchiCegarLoop]: Abstraction has 11600 states and 16843 transitions. [2019-12-07 13:00:29,218 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-12-07 13:00:29,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11600 states and 16843 transitions. [2019-12-07 13:00:29,241 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11444 [2019-12-07 13:00:29,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:29,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:29,242 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:29,242 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:29,242 INFO L794 eck$LassoCheckResult]: Stem: 58277#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 58199#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 58200#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58420#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 57767#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57768#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58515#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58421#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58158#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58159#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58615#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58383#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58049#L639-1 assume !(0 == ~M_E~0); 58050#L856-1 assume !(0 == ~T1_E~0); 58165#L861-1 assume !(0 == ~T2_E~0); 58166#L866-1 assume !(0 == ~T3_E~0); 58642#L871-1 assume !(0 == ~T4_E~0); 58408#L876-1 assume !(0 == ~T5_E~0); 58255#L881-1 assume !(0 == ~T6_E~0); 57912#L886-1 assume !(0 == ~T7_E~0); 57913#L891-1 assume !(0 == ~T8_E~0); 58480#L896-1 assume !(0 == ~E_M~0); 58224#L901-1 assume !(0 == ~E_1~0); 57867#L906-1 assume !(0 == ~E_2~0); 57868#L911-1 assume !(0 == ~E_3~0); 58693#L916-1 assume !(0 == ~E_4~0); 58324#L921-1 assume !(0 == ~E_5~0); 57981#L926-1 assume !(0 == ~E_6~0); 57982#L931-1 assume !(0 == ~E_7~0); 58770#L936-1 assume !(0 == ~E_8~0); 58557#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57944#L420 assume !(1 == ~m_pc~0); 57945#L420-2 is_master_triggered_~__retres1~0 := 0; 57951#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58629#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 58690#L1063 assume !(0 != activate_threads_~tmp~1); 58844#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58214#L439 assume !(1 == ~t1_pc~0); 58215#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 58218#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58735#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58681#L1071 assume !(0 != activate_threads_~tmp___0~0); 58667#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58391#L458 assume !(1 == ~t2_pc~0); 58366#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 58367#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58837#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58264#L1079 assume !(0 != activate_threads_~tmp___1~0); 58265#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58266#L477 assume !(1 == ~t3_pc~0); 58504#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 57837#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57838#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57933#L1087 assume !(0 != activate_threads_~tmp___2~0); 58855#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58664#L496 assume !(1 == ~t4_pc~0); 58621#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 58064#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57966#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 57967#L1095 assume !(0 != activate_threads_~tmp___3~0); 58567#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58568#L515 assume !(1 == ~t5_pc~0); 58846#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 58411#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 58223#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58187#L1103 assume !(0 != activate_threads_~tmp___4~0); 58176#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 57896#L534 assume 1 == ~t6_pc~0; 57897#L535 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 57887#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 58385#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 58386#L1111 assume !(0 != activate_threads_~tmp___5~0); 58706#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 58142#L553 assume !(1 == ~t7_pc~0); 57865#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 58147#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 58518#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 58360#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 58338#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 58306#L572 assume 1 == ~t8_pc~0; 58053#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 58054#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 58661#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 57800#L1127 assume !(0 != activate_threads_~tmp___7~0); 57801#L1127-2 assume !(1 == ~M_E~0); 57802#L954-1 assume !(1 == ~T1_E~0); 58640#L959-1 assume !(1 == ~T2_E~0); 58406#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58249#L969-1 assume !(1 == ~T4_E~0); 57908#L974-1 assume !(1 == ~T5_E~0); 57909#L979-1 assume !(1 == ~T6_E~0); 58476#L984-1 assume !(1 == ~T7_E~0); 58228#L989-1 assume !(1 == ~T8_E~0); 58077#L994-1 assume !(1 == ~E_M~0); 58078#L999-1 assume !(1 == ~E_1~0); 58696#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 58345#L1009-1 assume !(1 == ~E_3~0); 57992#L1014-1 assume !(1 == ~E_4~0); 57993#L1019-1 assume !(1 == ~E_5~0); 58773#L1024-1 assume !(1 == ~E_6~0); 58553#L1029-1 assume !(1 == ~E_7~0); 58310#L1034-1 assume !(1 == ~E_8~0); 58311#L1305-1 [2019-12-07 13:00:29,243 INFO L796 eck$LassoCheckResult]: Loop: 58311#L1305-1 assume !false; 65075#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 65073#L831 assume !false; 65071#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 65069#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 65059#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 65056#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 65054#L714 assume !(0 != eval_~tmp~0); 58750#L846 start_simulation_~kernel_st~0 := 2; 58422#L592-1 start_simulation_~kernel_st~0 := 3; 58423#L856-2 assume !(0 == ~M_E~0); 58416#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58171#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58172#L866-3 assume !(0 == ~T3_E~0); 58630#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58395#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58241#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57901#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57902#L891-3 assume !(0 == ~T8_E~0); 58471#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 58225#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57869#L906-3 assume !(0 == ~E_2~0); 57870#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58694#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 58325#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57983#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57984#L931-3 assume !(0 == ~E_7~0); 58771#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58559#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58151#L420-30 assume 1 == ~m_pc~0; 58101#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 58103#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58677#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 58678#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 58791#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58293#L439-30 assume !(1 == ~t1_pc~0); 58294#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 58295#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58705#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58484#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 58485#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58453#L458-30 assume 1 == ~t2_pc~0; 58439#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 58440#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58806#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 57985#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57986#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57987#L477-30 assume !(1 == ~t3_pc~0); 58467#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 57794#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57795#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57930#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 58759#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58617#L496-30 assume 1 == ~t4_pc~0; 58618#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 58011#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58012#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58182#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 58409#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58410#L515-30 assume !(1 == ~t5_pc~0); 58728#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 58230#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 58210#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58093#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 58094#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 58105#L534-30 assume 1 == ~t6_pc~0; 58798#L535-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 58529#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 58351#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 58352#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 58772#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57863#L553-30 assume !(1 == ~t7_pc~0); 57824#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 57831#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 58497#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 58437#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 58438#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 58048#L572-30 assume !(1 == ~t8_pc~0); 58001#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 58000#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 58648#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 57914#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 57915#L1127-32 assume !(1 == ~M_E~0); 57917#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65816#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65815#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65814#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65813#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65812#L979-3 assume !(1 == ~T6_E~0); 65811#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65809#L989-3 assume !(1 == ~T8_E~0); 65806#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65804#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65802#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65800#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65798#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65796#L1019-3 assume !(1 == ~E_5~0); 65794#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65792#L1029-3 assume !(1 == ~E_7~0); 65790#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65788#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 65780#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 65771#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 65769#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 65767#L1324 assume !(0 == start_simulation_~tmp~3); 65764#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 65762#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 65752#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 65750#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 65748#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 65746#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 65743#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 65741#L1337 assume !(0 != start_simulation_~tmp___0~1); 58311#L1305-1 [2019-12-07 13:00:29,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:29,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1379467460, now seen corresponding path program 1 times [2019-12-07 13:00:29,243 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:29,243 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549814559] [2019-12-07 13:00:29,243 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:29,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:29,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:29,266 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549814559] [2019-12-07 13:00:29,266 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:29,266 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:29,267 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554028746] [2019-12-07 13:00:29,267 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:29,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:29,267 INFO L82 PathProgramCache]: Analyzing trace with hash 1238712291, now seen corresponding path program 1 times [2019-12-07 13:00:29,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:29,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642513904] [2019-12-07 13:00:29,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:29,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:29,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:29,291 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642513904] [2019-12-07 13:00:29,291 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:29,292 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:29,292 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1084483213] [2019-12-07 13:00:29,292 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:29,292 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:29,292 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:29,292 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:29,292 INFO L87 Difference]: Start difference. First operand 11600 states and 16843 transitions. cyclomatic complexity: 5251 Second operand 3 states. [2019-12-07 13:00:29,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:29,385 INFO L93 Difference]: Finished difference Result 21963 states and 31740 transitions. [2019-12-07 13:00:29,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:29,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21963 states and 31740 transitions. [2019-12-07 13:00:29,445 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21728 [2019-12-07 13:00:29,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21963 states to 21963 states and 31740 transitions. [2019-12-07 13:00:29,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21963 [2019-12-07 13:00:29,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21963 [2019-12-07 13:00:29,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21963 states and 31740 transitions. [2019-12-07 13:00:29,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:29,506 INFO L688 BuchiCegarLoop]: Abstraction has 21963 states and 31740 transitions. [2019-12-07 13:00:29,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21963 states and 31740 transitions. [2019-12-07 13:00:29,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21963 to 21931. [2019-12-07 13:00:29,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21931 states. [2019-12-07 13:00:29,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21931 states to 21931 states and 31708 transitions. [2019-12-07 13:00:29,673 INFO L711 BuchiCegarLoop]: Abstraction has 21931 states and 31708 transitions. [2019-12-07 13:00:29,673 INFO L591 BuchiCegarLoop]: Abstraction has 21931 states and 31708 transitions. [2019-12-07 13:00:29,673 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-12-07 13:00:29,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21931 states and 31708 transitions. [2019-12-07 13:00:29,717 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21696 [2019-12-07 13:00:29,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:29,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:29,718 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:29,718 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:29,718 INFO L794 eck$LassoCheckResult]: Stem: 91829#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 91754#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 91755#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 91985#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 91337#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91338#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92081#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91986#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91717#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91718#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92176#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 91947#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 91609#L639-1 assume !(0 == ~M_E~0); 91610#L856-1 assume !(0 == ~T1_E~0); 91722#L861-1 assume !(0 == ~T2_E~0); 91723#L866-1 assume !(0 == ~T3_E~0); 92200#L871-1 assume !(0 == ~T4_E~0); 91972#L876-1 assume !(0 == ~T5_E~0); 91813#L881-1 assume !(0 == ~T6_E~0); 91480#L886-1 assume !(0 == ~T7_E~0); 91481#L891-1 assume !(0 == ~T8_E~0); 92042#L896-1 assume !(0 == ~E_M~0); 91782#L901-1 assume !(0 == ~E_1~0); 91436#L906-1 assume !(0 == ~E_2~0); 91437#L911-1 assume !(0 == ~E_3~0); 92251#L916-1 assume !(0 == ~E_4~0); 91885#L921-1 assume !(0 == ~E_5~0); 91544#L926-1 assume !(0 == ~E_6~0); 91545#L931-1 assume !(0 == ~E_7~0); 92321#L936-1 assume !(0 == ~E_8~0); 92119#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91508#L420 assume !(1 == ~m_pc~0); 91509#L420-2 is_master_triggered_~__retres1~0 := 0; 91515#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 92185#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 92248#L1063 assume !(0 != activate_threads_~tmp~1); 92396#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91772#L439 assume !(1 == ~t1_pc~0); 91773#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 91776#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92287#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 92240#L1071 assume !(0 != activate_threads_~tmp___0~0); 92226#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91955#L458 assume !(1 == ~t2_pc~0); 91929#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 91930#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92389#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 91822#L1079 assume !(0 != activate_threads_~tmp___1~0); 91823#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91824#L477 assume !(1 == ~t3_pc~0); 92070#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 91403#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91404#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 91498#L1087 assume !(0 != activate_threads_~tmp___2~0); 92403#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 92223#L496 assume !(1 == ~t4_pc~0); 92182#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 91620#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91529#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91530#L1095 assume !(0 != activate_threads_~tmp___3~0); 92131#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 92132#L515 assume !(1 == ~t5_pc~0); 92397#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 91976#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91781#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 91746#L1103 assume !(0 != activate_threads_~tmp___4~0); 91732#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91465#L534 assume !(1 == ~t6_pc~0); 91455#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 91456#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 91949#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 91950#L1111 assume !(0 != activate_threads_~tmp___5~0); 92264#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 91699#L553 assume !(1 == ~t7_pc~0); 91434#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 91705#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 92082#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 91923#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 91902#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 91862#L572 assume 1 == ~t8_pc~0; 91612#L573 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 91613#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 92220#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 91369#L1127 assume !(0 != activate_threads_~tmp___7~0); 91370#L1127-2 assume !(1 == ~M_E~0); 91371#L954-1 assume !(1 == ~T1_E~0); 92197#L959-1 assume !(1 == ~T2_E~0); 91970#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91807#L969-1 assume !(1 == ~T4_E~0); 91476#L974-1 assume !(1 == ~T5_E~0); 91477#L979-1 assume !(1 == ~T6_E~0); 92040#L984-1 assume !(1 == ~T7_E~0); 91786#L989-1 assume !(1 == ~T8_E~0); 91637#L994-1 assume !(1 == ~E_M~0); 91638#L999-1 assume !(1 == ~E_1~0); 92255#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 91908#L1009-1 assume !(1 == ~E_3~0); 91552#L1014-1 assume !(1 == ~E_4~0); 91553#L1019-1 assume !(1 == ~E_5~0); 92325#L1024-1 assume !(1 == ~E_6~0); 92115#L1029-1 assume !(1 == ~E_7~0); 91872#L1034-1 assume !(1 == ~E_8~0); 91873#L1305-1 [2019-12-07 13:00:29,719 INFO L796 eck$LassoCheckResult]: Loop: 91873#L1305-1 assume !false; 94669#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 94426#L831 assume !false; 94427#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 94421#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 94411#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 94409#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 94405#L714 assume !(0 != eval_~tmp~0); 94407#L846 start_simulation_~kernel_st~0 := 2; 98454#L592-1 start_simulation_~kernel_st~0 := 3; 98452#L856-2 assume !(0 == ~M_E~0); 98450#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98448#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98446#L866-3 assume !(0 == ~T3_E~0); 98444#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98442#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98440#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 98438#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 98436#L891-3 assume !(0 == ~T8_E~0); 98434#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 98432#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 98429#L906-3 assume !(0 == ~E_2~0); 98427#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98425#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98423#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98421#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 98419#L931-3 assume !(0 == ~E_7~0); 98416#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98411#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 95444#L420-30 assume 1 == ~m_pc~0; 95441#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 95438#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 95436#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 95434#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 95432#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 95430#L439-30 assume !(1 == ~t1_pc~0); 95428#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 95426#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 95424#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 95422#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 95420#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 95418#L458-30 assume !(1 == ~t2_pc~0); 95413#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 95411#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 95409#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 95407#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 95405#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 95403#L477-30 assume !(1 == ~t3_pc~0); 95401#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 95399#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 95397#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 95395#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 95393#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 95390#L496-30 assume !(1 == ~t4_pc~0); 95387#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 95385#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 95383#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 95381#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 95379#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 95377#L515-30 assume !(1 == ~t5_pc~0); 95375#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 95373#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 95371#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 95369#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 95367#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 95365#L534-30 assume !(1 == ~t6_pc~0); 95363#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 95361#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 95359#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 95357#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 95354#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 95352#L553-30 assume !(1 == ~t7_pc~0); 95349#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 95347#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 95345#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 95343#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 95341#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 95340#L572-30 assume 1 == ~t8_pc~0; 95337#L573-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 95335#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 95332#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 95330#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 94800#L1127-32 assume !(1 == ~M_E~0); 94796#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94797#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94792#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94793#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94788#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94789#L979-3 assume !(1 == ~T6_E~0); 94782#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94783#L989-3 assume !(1 == ~T8_E~0); 94772#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94773#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94764#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94765#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94756#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94757#L1019-3 assume !(1 == ~E_5~0); 94748#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94749#L1029-3 assume !(1 == ~E_7~0); 94740#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 94741#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 94722#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 94715#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 94706#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 94707#L1324 assume !(0 == start_simulation_~tmp~3); 94697#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 94694#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 94683#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 94680#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 94678#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 94676#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 94673#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 94671#L1337 assume !(0 != start_simulation_~tmp___0~1); 91873#L1305-1 [2019-12-07 13:00:29,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:29,719 INFO L82 PathProgramCache]: Analyzing trace with hash -328018371, now seen corresponding path program 1 times [2019-12-07 13:00:29,719 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:29,720 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395366088] [2019-12-07 13:00:29,720 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:29,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:29,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:29,750 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395366088] [2019-12-07 13:00:29,751 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:29,751 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:29,751 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735519723] [2019-12-07 13:00:29,751 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:29,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:29,785 INFO L82 PathProgramCache]: Analyzing trace with hash 2044463905, now seen corresponding path program 1 times [2019-12-07 13:00:29,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:29,785 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421130501] [2019-12-07 13:00:29,785 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:29,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:29,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:29,809 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421130501] [2019-12-07 13:00:29,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:29,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:29,810 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699748915] [2019-12-07 13:00:29,810 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:29,810 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:29,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:29,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:29,810 INFO L87 Difference]: Start difference. First operand 21931 states and 31708 transitions. cyclomatic complexity: 9793 Second operand 3 states. [2019-12-07 13:00:29,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:29,917 INFO L93 Difference]: Finished difference Result 41530 states and 59817 transitions. [2019-12-07 13:00:29,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:29,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41530 states and 59817 transitions. [2019-12-07 13:00:30,028 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41104 [2019-12-07 13:00:30,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41530 states to 41530 states and 59817 transitions. [2019-12-07 13:00:30,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41530 [2019-12-07 13:00:30,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41530 [2019-12-07 13:00:30,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41530 states and 59817 transitions. [2019-12-07 13:00:30,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:30,141 INFO L688 BuchiCegarLoop]: Abstraction has 41530 states and 59817 transitions. [2019-12-07 13:00:30,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41530 states and 59817 transitions. [2019-12-07 13:00:30,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41530 to 41466. [2019-12-07 13:00:30,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41466 states. [2019-12-07 13:00:30,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41466 states to 41466 states and 59753 transitions. [2019-12-07 13:00:30,399 INFO L711 BuchiCegarLoop]: Abstraction has 41466 states and 59753 transitions. [2019-12-07 13:00:30,399 INFO L591 BuchiCegarLoop]: Abstraction has 41466 states and 59753 transitions. [2019-12-07 13:00:30,399 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-12-07 13:00:30,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41466 states and 59753 transitions. [2019-12-07 13:00:30,525 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41040 [2019-12-07 13:00:30,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:30,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:30,526 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:30,526 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:30,527 INFO L794 eck$LassoCheckResult]: Stem: 155319#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 155229#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 155230#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 155473#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 154805#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154806#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155577#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155474#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155188#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155189#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 155652#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155434#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 155080#L639-1 assume !(0 == ~M_E~0); 155081#L856-1 assume !(0 == ~T1_E~0); 155194#L861-1 assume !(0 == ~T2_E~0); 155195#L866-1 assume !(0 == ~T3_E~0); 155678#L871-1 assume !(0 == ~T4_E~0); 155461#L876-1 assume !(0 == ~T5_E~0); 155289#L881-1 assume !(0 == ~T6_E~0); 154946#L886-1 assume !(0 == ~T7_E~0); 154947#L891-1 assume !(0 == ~T8_E~0); 155536#L896-1 assume !(0 == ~E_M~0); 155254#L901-1 assume !(0 == ~E_1~0); 154904#L906-1 assume !(0 == ~E_2~0); 154905#L911-1 assume !(0 == ~E_3~0); 155729#L916-1 assume !(0 == ~E_4~0); 155375#L921-1 assume !(0 == ~E_5~0); 155012#L926-1 assume !(0 == ~E_6~0); 155013#L931-1 assume !(0 == ~E_7~0); 155803#L936-1 assume !(0 == ~E_8~0); 155617#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154976#L420 assume !(1 == ~m_pc~0); 154977#L420-2 is_master_triggered_~__retres1~0 := 0; 154983#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 155666#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 155725#L1063 assume !(0 != activate_threads_~tmp~1); 155878#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 155243#L439 assume !(1 == ~t1_pc~0); 155244#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 155247#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 155769#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 155717#L1071 assume !(0 != activate_threads_~tmp___0~0); 155703#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 155442#L458 assume !(1 == ~t2_pc~0); 155418#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 155419#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 155869#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 155302#L1079 assume !(0 != activate_threads_~tmp___1~0); 155303#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 155305#L477 assume !(1 == ~t3_pc~0); 155566#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 154874#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 154875#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 154966#L1087 assume !(0 != activate_threads_~tmp___2~0); 155885#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 155700#L496 assume !(1 == ~t4_pc~0); 155658#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 155094#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154997#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 154998#L1095 assume !(0 != activate_threads_~tmp___3~0); 155623#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155624#L515 assume !(1 == ~t5_pc~0); 155880#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 155464#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 155253#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 155217#L1103 assume !(0 != activate_threads_~tmp___4~0); 155206#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 154931#L534 assume !(1 == ~t6_pc~0); 154922#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 154923#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 155436#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 155437#L1111 assume !(0 != activate_threads_~tmp___5~0); 155742#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 155173#L553 assume !(1 == ~t7_pc~0); 154902#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 155178#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 155579#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 155411#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 155390#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 155351#L572 assume !(1 == ~t8_pc~0); 155352#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 155353#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 155697#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 154837#L1127 assume !(0 != activate_threads_~tmp___7~0); 154838#L1127-2 assume !(1 == ~M_E~0); 154839#L954-1 assume !(1 == ~T1_E~0); 155676#L959-1 assume !(1 == ~T2_E~0); 155459#L964-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155282#L969-1 assume !(1 == ~T4_E~0); 154942#L974-1 assume !(1 == ~T5_E~0); 154943#L979-1 assume !(1 == ~T6_E~0); 155533#L984-1 assume !(1 == ~T7_E~0); 155258#L989-1 assume !(1 == ~T8_E~0); 155108#L994-1 assume !(1 == ~E_M~0); 155109#L999-1 assume !(1 == ~E_1~0); 155734#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 155396#L1009-1 assume !(1 == ~E_3~0); 155022#L1014-1 assume !(1 == ~E_4~0); 155023#L1019-1 assume !(1 == ~E_5~0); 155806#L1024-1 assume !(1 == ~E_6~0); 155613#L1029-1 assume !(1 == ~E_7~0); 155361#L1034-1 assume !(1 == ~E_8~0); 155362#L1305-1 [2019-12-07 13:00:30,527 INFO L796 eck$LassoCheckResult]: Loop: 155362#L1305-1 assume !false; 165803#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 165802#L831 assume !false; 165801#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 165497#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 165487#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 165486#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 165484#L714 assume !(0 != eval_~tmp~0); 165485#L846 start_simulation_~kernel_st~0 := 2; 167052#L592-1 start_simulation_~kernel_st~0 := 3; 167049#L856-2 assume !(0 == ~M_E~0); 167047#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 167045#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 167043#L866-3 assume !(0 == ~T3_E~0); 167041#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 167039#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 167037#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 167035#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 167033#L891-3 assume !(0 == ~T8_E~0); 167031#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 167029#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 167027#L906-3 assume !(0 == ~E_2~0); 167024#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 167022#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 167020#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 167018#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 167016#L931-3 assume !(0 == ~E_7~0); 167014#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 167012#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 167010#L420-30 assume 1 == ~m_pc~0; 167008#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 167005#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 167003#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 167001#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 166998#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 166996#L439-30 assume !(1 == ~t1_pc~0); 166994#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 166992#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 166990#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 166988#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 166986#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166984#L458-30 assume 1 == ~t2_pc~0; 166982#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 166979#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 166977#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 166975#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 166973#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166971#L477-30 assume !(1 == ~t3_pc~0); 166969#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 166967#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 166965#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 166962#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 166960#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 166958#L496-30 assume !(1 == ~t4_pc~0); 166955#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 166953#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 166951#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 166949#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 166947#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 166945#L515-30 assume !(1 == ~t5_pc~0); 166943#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 166941#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 166940#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 166939#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 166938#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 166937#L534-30 assume !(1 == ~t6_pc~0); 166936#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 166934#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 166931#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 166929#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 166927#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 166925#L553-30 assume !(1 == ~t7_pc~0); 166922#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 166920#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 166918#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 166916#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 166914#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 166912#L572-30 assume !(1 == ~t8_pc~0); 166910#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 166908#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 166905#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 166903#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 166901#L1127-32 assume !(1 == ~M_E~0); 166897#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 166895#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 166893#L964-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 166890#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 166888#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 166886#L979-3 assume !(1 == ~T6_E~0); 166884#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 166882#L989-3 assume !(1 == ~T8_E~0); 166880#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 166877#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 166875#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 166873#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 166871#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 166869#L1019-3 assume !(1 == ~E_5~0); 166867#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 166865#L1029-3 assume !(1 == ~E_7~0); 166863#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 166861#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 166853#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 166844#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 166842#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 166839#L1324 assume !(0 == start_simulation_~tmp~3); 166835#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 166833#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 166823#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 166781#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 166772#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 166763#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 166754#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 166748#L1337 assume !(0 != start_simulation_~tmp___0~1); 155362#L1305-1 [2019-12-07 13:00:30,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:30,527 INFO L82 PathProgramCache]: Analyzing trace with hash 451962558, now seen corresponding path program 1 times [2019-12-07 13:00:30,527 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:30,527 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099636997] [2019-12-07 13:00:30,527 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:30,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:30,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:30,553 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099636997] [2019-12-07 13:00:30,553 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:30,553 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:30,554 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124981812] [2019-12-07 13:00:30,554 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:30,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:30,554 INFO L82 PathProgramCache]: Analyzing trace with hash 765062817, now seen corresponding path program 1 times [2019-12-07 13:00:30,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:30,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359585374] [2019-12-07 13:00:30,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:30,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:30,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:30,584 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359585374] [2019-12-07 13:00:30,584 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:30,584 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:30,585 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41855474] [2019-12-07 13:00:30,585 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:30,585 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:30,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:30,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:30,585 INFO L87 Difference]: Start difference. First operand 41466 states and 59753 transitions. cyclomatic complexity: 18319 Second operand 3 states. [2019-12-07 13:00:30,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:30,665 INFO L93 Difference]: Finished difference Result 41466 states and 59559 transitions. [2019-12-07 13:00:30,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:30,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41466 states and 59559 transitions. [2019-12-07 13:00:30,768 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41040 [2019-12-07 13:00:30,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41466 states to 41466 states and 59559 transitions. [2019-12-07 13:00:30,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41466 [2019-12-07 13:00:30,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41466 [2019-12-07 13:00:30,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41466 states and 59559 transitions. [2019-12-07 13:00:30,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:30,882 INFO L688 BuchiCegarLoop]: Abstraction has 41466 states and 59559 transitions. [2019-12-07 13:00:30,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41466 states and 59559 transitions. [2019-12-07 13:00:31,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41466 to 41466. [2019-12-07 13:00:31,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41466 states. [2019-12-07 13:00:31,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41466 states to 41466 states and 59559 transitions. [2019-12-07 13:00:31,137 INFO L711 BuchiCegarLoop]: Abstraction has 41466 states and 59559 transitions. [2019-12-07 13:00:31,137 INFO L591 BuchiCegarLoop]: Abstraction has 41466 states and 59559 transitions. [2019-12-07 13:00:31,137 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-12-07 13:00:31,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41466 states and 59559 transitions. [2019-12-07 13:00:31,212 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41040 [2019-12-07 13:00:31,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:31,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:31,214 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:31,214 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:31,214 INFO L794 eck$LassoCheckResult]: Stem: 238248#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 238166#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 238167#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 238399#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 237744#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 237745#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 238503#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238400#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 238125#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 238126#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 238575#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 238362#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238021#L639-1 assume !(0 == ~M_E~0); 238022#L856-1 assume !(0 == ~T1_E~0); 238130#L861-1 assume !(0 == ~T2_E~0); 238131#L866-1 assume !(0 == ~T3_E~0); 238601#L871-1 assume !(0 == ~T4_E~0); 238387#L876-1 assume !(0 == ~T5_E~0); 238224#L881-1 assume !(0 == ~T6_E~0); 237889#L886-1 assume !(0 == ~T7_E~0); 237890#L891-1 assume !(0 == ~T8_E~0); 238463#L896-1 assume !(0 == ~E_M~0); 238191#L901-1 assume !(0 == ~E_1~0); 237845#L906-1 assume !(0 == ~E_2~0); 237846#L911-1 assume !(0 == ~E_3~0); 238651#L916-1 assume !(0 == ~E_4~0); 238304#L921-1 assume !(0 == ~E_5~0); 237954#L926-1 assume !(0 == ~E_6~0); 237955#L931-1 assume !(0 == ~E_7~0); 238722#L936-1 assume !(0 == ~E_8~0); 238542#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 237917#L420 assume !(1 == ~m_pc~0); 237918#L420-2 is_master_triggered_~__retres1~0 := 0; 237924#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 238588#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 238648#L1063 assume !(0 != activate_threads_~tmp~1); 238784#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 238181#L439 assume !(1 == ~t1_pc~0); 238182#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 238185#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 238691#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 238640#L1071 assume !(0 != activate_threads_~tmp___0~0); 238626#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 238370#L458 assume !(1 == ~t2_pc~0); 238345#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 238346#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 238775#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 238234#L1079 assume !(0 != activate_threads_~tmp___1~0); 238235#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 238236#L477 assume !(1 == ~t3_pc~0); 238492#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 237813#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 237814#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 237908#L1087 assume !(0 != activate_threads_~tmp___2~0); 238791#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 238623#L496 assume !(1 == ~t4_pc~0); 238581#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 238034#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237939#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 237940#L1095 assume !(0 != activate_threads_~tmp___3~0); 238548#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 238549#L515 assume !(1 == ~t5_pc~0); 238786#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 238390#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 238190#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 238154#L1103 assume !(0 != activate_threads_~tmp___4~0); 238141#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 237874#L534 assume !(1 == ~t6_pc~0); 237864#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 237865#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 238364#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 238365#L1111 assume !(0 != activate_threads_~tmp___5~0); 238662#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 238110#L553 assume !(1 == ~t7_pc~0); 237841#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 238115#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 238505#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 238339#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 238318#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 238280#L572 assume !(1 == ~t8_pc~0); 238281#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 238283#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 238620#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 237776#L1127 assume !(0 != activate_threads_~tmp___7~0); 237777#L1127-2 assume !(1 == ~M_E~0); 237778#L954-1 assume !(1 == ~T1_E~0); 238599#L959-1 assume !(1 == ~T2_E~0); 238385#L964-1 assume !(1 == ~T3_E~0); 238217#L969-1 assume !(1 == ~T4_E~0); 237885#L974-1 assume !(1 == ~T5_E~0); 237886#L979-1 assume !(1 == ~T6_E~0); 238459#L984-1 assume !(1 == ~T7_E~0); 238195#L989-1 assume !(1 == ~T8_E~0); 238047#L994-1 assume !(1 == ~E_M~0); 238048#L999-1 assume !(1 == ~E_1~0); 238655#L1004-1 assume 1 == ~E_2~0;~E_2~0 := 2; 238324#L1009-1 assume !(1 == ~E_3~0); 237965#L1014-1 assume !(1 == ~E_4~0); 237966#L1019-1 assume !(1 == ~E_5~0); 238725#L1024-1 assume !(1 == ~E_6~0); 238538#L1029-1 assume !(1 == ~E_7~0); 238290#L1034-1 assume !(1 == ~E_8~0); 238291#L1305-1 [2019-12-07 13:00:31,214 INFO L796 eck$LassoCheckResult]: Loop: 238291#L1305-1 assume !false; 243299#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 243293#L831 assume !false; 243288#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 243279#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 243265#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 243260#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 243254#L714 assume !(0 != eval_~tmp~0); 243255#L846 start_simulation_~kernel_st~0 := 2; 244130#L592-1 start_simulation_~kernel_st~0 := 3; 244127#L856-2 assume !(0 == ~M_E~0); 244124#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 244119#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 244115#L866-3 assume !(0 == ~T3_E~0); 244111#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 244107#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244103#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 244099#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 244094#L891-3 assume !(0 == ~T8_E~0); 244090#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 244086#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244082#L906-3 assume !(0 == ~E_2~0); 244078#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 244074#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 244070#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 244066#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 244062#L931-3 assume !(0 == ~E_7~0); 244058#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 244056#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 244055#L420-30 assume 1 == ~m_pc~0; 244043#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 244037#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 244032#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 244027#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 244024#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 244020#L439-30 assume !(1 == ~t1_pc~0); 244015#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 244011#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 244007#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 244003#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 243999#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 243995#L458-30 assume 1 == ~t2_pc~0; 243991#L459-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 243985#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 243980#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 243976#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 243972#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 243967#L477-30 assume !(1 == ~t3_pc~0); 243960#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 243955#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 243949#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 243944#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 243939#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 243934#L496-30 assume !(1 == ~t4_pc~0); 243927#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 243921#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 243916#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 243911#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 243906#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 243901#L515-30 assume !(1 == ~t5_pc~0); 243893#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 243888#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 243881#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 243877#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 243873#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 243867#L534-30 assume !(1 == ~t6_pc~0); 243858#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 243853#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 243848#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 243843#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 243837#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 243832#L553-30 assume !(1 == ~t7_pc~0); 243824#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 243819#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 243814#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 243809#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 243803#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 243797#L572-30 assume !(1 == ~t8_pc~0); 243792#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 243787#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 243782#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 243777#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 243771#L1127-32 assume !(1 == ~M_E~0); 243765#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 243761#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 243757#L964-3 assume !(1 == ~T3_E~0); 243753#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 243749#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 243744#L979-3 assume !(1 == ~T6_E~0); 243739#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 243735#L989-3 assume !(1 == ~T8_E~0); 243731#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 243727#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 243723#L1004-3 assume 1 == ~E_2~0;~E_2~0 := 2; 243718#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 243714#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 243710#L1019-3 assume !(1 == ~E_5~0); 243706#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 243702#L1029-3 assume !(1 == ~E_7~0); 243699#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 243696#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 243691#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 243681#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 243677#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 243671#L1324 assume !(0 == start_simulation_~tmp~3); 243665#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 243640#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 243445#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 243441#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 243350#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 243335#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 243324#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 243316#L1337 assume !(0 != start_simulation_~tmp___0~1); 238291#L1305-1 [2019-12-07 13:00:31,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:31,214 INFO L82 PathProgramCache]: Analyzing trace with hash -827901120, now seen corresponding path program 1 times [2019-12-07 13:00:31,215 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:31,215 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500290185] [2019-12-07 13:00:31,215 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:31,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:31,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:31,241 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500290185] [2019-12-07 13:00:31,241 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:31,241 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:31,242 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890227036] [2019-12-07 13:00:31,242 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:31,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:31,242 INFO L82 PathProgramCache]: Analyzing trace with hash 255589727, now seen corresponding path program 1 times [2019-12-07 13:00:31,242 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:31,243 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064129401] [2019-12-07 13:00:31,243 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:31,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:31,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:31,279 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064129401] [2019-12-07 13:00:31,279 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:31,280 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:31,280 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218444955] [2019-12-07 13:00:31,280 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:31,280 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:31,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:31,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:31,280 INFO L87 Difference]: Start difference. First operand 41466 states and 59559 transitions. cyclomatic complexity: 18125 Second operand 3 states. [2019-12-07 13:00:31,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:31,396 INFO L93 Difference]: Finished difference Result 41466 states and 58884 transitions. [2019-12-07 13:00:31,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:31,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41466 states and 58884 transitions. [2019-12-07 13:00:31,607 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41040 [2019-12-07 13:00:31,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41466 states to 41466 states and 58884 transitions. [2019-12-07 13:00:31,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41466 [2019-12-07 13:00:31,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41466 [2019-12-07 13:00:31,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41466 states and 58884 transitions. [2019-12-07 13:00:31,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:31,690 INFO L688 BuchiCegarLoop]: Abstraction has 41466 states and 58884 transitions. [2019-12-07 13:00:31,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41466 states and 58884 transitions. [2019-12-07 13:00:31,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41466 to 41466. [2019-12-07 13:00:31,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41466 states. [2019-12-07 13:00:31,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41466 states to 41466 states and 58884 transitions. [2019-12-07 13:00:31,928 INFO L711 BuchiCegarLoop]: Abstraction has 41466 states and 58884 transitions. [2019-12-07 13:00:31,928 INFO L591 BuchiCegarLoop]: Abstraction has 41466 states and 58884 transitions. [2019-12-07 13:00:31,928 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-12-07 13:00:31,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41466 states and 58884 transitions. [2019-12-07 13:00:32,009 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41040 [2019-12-07 13:00:32,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:32,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:32,010 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:32,010 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:32,010 INFO L794 eck$LassoCheckResult]: Stem: 321173#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 321097#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 321098#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 321336#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 320683#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 320684#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 321442#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 321337#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 321060#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 321061#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 321513#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 321299#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 320953#L639-1 assume !(0 == ~M_E~0); 320954#L856-1 assume !(0 == ~T1_E~0); 321065#L861-1 assume !(0 == ~T2_E~0); 321066#L866-1 assume !(0 == ~T3_E~0); 321538#L871-1 assume !(0 == ~T4_E~0); 321324#L876-1 assume !(0 == ~T5_E~0); 321156#L881-1 assume !(0 == ~T6_E~0); 320822#L886-1 assume !(0 == ~T7_E~0); 320823#L891-1 assume !(0 == ~T8_E~0); 321403#L896-1 assume !(0 == ~E_M~0); 321125#L901-1 assume !(0 == ~E_1~0); 320782#L906-1 assume !(0 == ~E_2~0); 320783#L911-1 assume !(0 == ~E_3~0); 321590#L916-1 assume !(0 == ~E_4~0); 321237#L921-1 assume !(0 == ~E_5~0); 320886#L926-1 assume !(0 == ~E_6~0); 320887#L931-1 assume !(0 == ~E_7~0); 321654#L936-1 assume !(0 == ~E_8~0); 321478#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 320850#L420 assume !(1 == ~m_pc~0); 320851#L420-2 is_master_triggered_~__retres1~0 := 0; 320857#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 321523#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 321587#L1063 assume !(0 != activate_threads_~tmp~1); 321746#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 321114#L439 assume !(1 == ~t1_pc~0); 321115#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 321119#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 321627#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 321578#L1071 assume !(0 != activate_threads_~tmp___0~0); 321563#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 321307#L458 assume !(1 == ~t2_pc~0); 321282#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 321283#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 321734#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 321165#L1079 assume !(0 != activate_threads_~tmp___1~0); 321166#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 321167#L477 assume !(1 == ~t3_pc~0); 321431#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 320749#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 320750#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 320840#L1087 assume !(0 != activate_threads_~tmp___2~0); 321755#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 321560#L496 assume !(1 == ~t4_pc~0); 321520#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 320961#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 320871#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 320872#L1095 assume !(0 != activate_threads_~tmp___3~0); 321485#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 321486#L515 assume !(1 == ~t5_pc~0); 321748#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 321327#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 321124#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 321089#L1103 assume !(0 != activate_threads_~tmp___4~0); 321074#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 320807#L534 assume !(1 == ~t6_pc~0); 320799#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 320800#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 321301#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 321302#L1111 assume !(0 != activate_threads_~tmp___5~0); 321602#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 321042#L553 assume !(1 == ~t7_pc~0); 320780#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 321050#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 321443#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 321276#L1119 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 321254#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 321212#L572 assume !(1 == ~t8_pc~0); 321213#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 321216#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 321557#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 320715#L1127 assume !(0 != activate_threads_~tmp___7~0); 320716#L1127-2 assume !(1 == ~M_E~0); 320717#L954-1 assume !(1 == ~T1_E~0); 321535#L959-1 assume !(1 == ~T2_E~0); 321322#L964-1 assume !(1 == ~T3_E~0); 321150#L969-1 assume !(1 == ~T4_E~0); 320818#L974-1 assume !(1 == ~T5_E~0); 320819#L979-1 assume !(1 == ~T6_E~0); 321398#L984-1 assume !(1 == ~T7_E~0); 321129#L989-1 assume !(1 == ~T8_E~0); 320979#L994-1 assume !(1 == ~E_M~0); 320980#L999-1 assume !(1 == ~E_1~0); 321594#L1004-1 assume !(1 == ~E_2~0); 321260#L1009-1 assume !(1 == ~E_3~0); 320895#L1014-1 assume !(1 == ~E_4~0); 320896#L1019-1 assume !(1 == ~E_5~0); 321658#L1024-1 assume !(1 == ~E_6~0); 321474#L1029-1 assume !(1 == ~E_7~0); 321222#L1034-1 assume !(1 == ~E_8~0); 321223#L1305-1 [2019-12-07 13:00:32,011 INFO L796 eck$LassoCheckResult]: Loop: 321223#L1305-1 assume !false; 327383#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 327048#L831 assume !false; 327380#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 327378#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 327368#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 327366#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 327363#L714 assume !(0 != eval_~tmp~0); 327364#L846 start_simulation_~kernel_st~0 := 2; 331280#L592-1 start_simulation_~kernel_st~0 := 3; 331277#L856-2 assume !(0 == ~M_E~0); 331275#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 331273#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 331271#L866-3 assume !(0 == ~T3_E~0); 331269#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 331267#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 331265#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 331262#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 331260#L891-3 assume !(0 == ~T8_E~0); 331258#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 331256#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 331255#L906-3 assume !(0 == ~E_2~0); 331216#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 331200#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 331117#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 331114#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 331112#L931-3 assume !(0 == ~E_7~0); 331110#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 331108#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 331106#L420-30 assume 1 == ~m_pc~0; 331103#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 331100#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 331098#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 331096#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 331094#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 331092#L439-30 assume !(1 == ~t1_pc~0); 331090#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 331088#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 331086#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 331084#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 331082#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 331076#L458-30 assume !(1 == ~t2_pc~0); 331074#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 331072#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 331070#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 331068#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 331066#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 331064#L477-30 assume !(1 == ~t3_pc~0); 331062#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 331060#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 331058#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 331056#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 331054#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 331052#L496-30 assume !(1 == ~t4_pc~0); 331049#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 331047#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 331045#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 331041#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 331038#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 331036#L515-30 assume !(1 == ~t5_pc~0); 331034#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 331032#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 331030#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 331028#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 331026#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 331023#L534-30 assume !(1 == ~t6_pc~0); 330997#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 330991#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 330984#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 330979#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 330974#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 330068#L553-30 assume !(1 == ~t7_pc~0); 330065#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 330063#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 330061#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 330059#L1119-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 330057#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 330055#L572-30 assume !(1 == ~t8_pc~0); 330053#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 330051#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 330049#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 330047#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 330044#L1127-32 assume !(1 == ~M_E~0); 330040#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 330038#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 330034#L964-3 assume !(1 == ~T3_E~0); 330030#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 330023#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 330014#L979-3 assume !(1 == ~T6_E~0); 330009#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 330003#L989-3 assume !(1 == ~T8_E~0); 329998#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 329995#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 329993#L1004-3 assume !(1 == ~E_2~0); 329991#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 329989#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 329987#L1019-3 assume !(1 == ~E_5~0); 329981#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 329974#L1029-3 assume !(1 == ~E_7~0); 329967#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 329962#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 329763#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 329754#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 329675#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 329666#L1324 assume !(0 == start_simulation_~tmp~3); 329658#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 327407#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 327397#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 327395#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 327393#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 327391#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 327389#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 327386#L1337 assume !(0 != start_simulation_~tmp___0~1); 321223#L1305-1 [2019-12-07 13:00:32,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:32,011 INFO L82 PathProgramCache]: Analyzing trace with hash 947106242, now seen corresponding path program 1 times [2019-12-07 13:00:32,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:32,011 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283185082] [2019-12-07 13:00:32,011 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:32,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:32,064 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283185082] [2019-12-07 13:00:32,064 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:32,064 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:32,064 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17378027] [2019-12-07 13:00:32,065 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:32,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:32,065 INFO L82 PathProgramCache]: Analyzing trace with hash -1047474244, now seen corresponding path program 1 times [2019-12-07 13:00:32,065 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:32,065 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388122055] [2019-12-07 13:00:32,065 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:32,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:32,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:32,101 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [388122055] [2019-12-07 13:00:32,101 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:32,101 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:32,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68716607] [2019-12-07 13:00:32,102 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:32,102 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:32,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:32,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:32,102 INFO L87 Difference]: Start difference. First operand 41466 states and 58884 transitions. cyclomatic complexity: 17450 Second operand 5 states. [2019-12-07 13:00:32,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:32,375 INFO L93 Difference]: Finished difference Result 60434 states and 85851 transitions. [2019-12-07 13:00:32,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:32,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60434 states and 85851 transitions. [2019-12-07 13:00:32,553 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59752 [2019-12-07 13:00:32,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60434 states to 60434 states and 85851 transitions. [2019-12-07 13:00:32,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60434 [2019-12-07 13:00:32,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60434 [2019-12-07 13:00:32,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60434 states and 85851 transitions. [2019-12-07 13:00:32,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:32,810 INFO L688 BuchiCegarLoop]: Abstraction has 60434 states and 85851 transitions. [2019-12-07 13:00:32,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60434 states and 85851 transitions. [2019-12-07 13:00:33,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60434 to 41562. [2019-12-07 13:00:33,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41562 states. [2019-12-07 13:00:33,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41562 states to 41562 states and 58499 transitions. [2019-12-07 13:00:33,077 INFO L711 BuchiCegarLoop]: Abstraction has 41562 states and 58499 transitions. [2019-12-07 13:00:33,077 INFO L591 BuchiCegarLoop]: Abstraction has 41562 states and 58499 transitions. [2019-12-07 13:00:33,077 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-12-07 13:00:33,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41562 states and 58499 transitions. [2019-12-07 13:00:33,160 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41136 [2019-12-07 13:00:33,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:33,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:33,161 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:33,161 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:33,162 INFO L794 eck$LassoCheckResult]: Stem: 423107#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 423025#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 423026#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 423269#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 422596#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 422597#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 423367#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 423270#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422987#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422988#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 423460#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 423230#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 422879#L639-1 assume !(0 == ~M_E~0); 422880#L856-1 assume !(0 == ~T1_E~0); 422992#L861-1 assume !(0 == ~T2_E~0); 422993#L866-1 assume !(0 == ~T3_E~0); 423487#L871-1 assume !(0 == ~T4_E~0); 423255#L876-1 assume !(0 == ~T5_E~0); 423082#L881-1 assume !(0 == ~T6_E~0); 422744#L886-1 assume !(0 == ~T7_E~0); 422745#L891-1 assume !(0 == ~T8_E~0); 423326#L896-1 assume !(0 == ~E_M~0); 423049#L901-1 assume !(0 == ~E_1~0); 422699#L906-1 assume !(0 == ~E_2~0); 422700#L911-1 assume !(0 == ~E_3~0); 423542#L916-1 assume !(0 == ~E_4~0); 423170#L921-1 assume !(0 == ~E_5~0); 422810#L926-1 assume !(0 == ~E_6~0); 422811#L931-1 assume !(0 == ~E_7~0); 423621#L936-1 assume !(0 == ~E_8~0); 423406#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 422773#L420 assume !(1 == ~m_pc~0); 422774#L420-2 is_master_triggered_~__retres1~0 := 0; 422780#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 423471#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 423539#L1063 assume !(0 != activate_threads_~tmp~1); 423695#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 423039#L439 assume !(1 == ~t1_pc~0); 423040#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 423043#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 423583#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 423527#L1071 assume !(0 != activate_threads_~tmp___0~0); 423513#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 423238#L458 assume !(1 == ~t2_pc~0); 423213#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 423214#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 423689#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 423091#L1079 assume !(0 != activate_threads_~tmp___1~0); 423092#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 423093#L477 assume !(1 == ~t3_pc~0); 423355#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 422666#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 422667#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 422764#L1087 assume !(0 != activate_threads_~tmp___2~0); 423703#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 423510#L496 assume !(1 == ~t4_pc~0); 423466#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 422891#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 422795#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 422796#L1095 assume !(0 != activate_threads_~tmp___3~0); 423416#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 423417#L515 assume !(1 == ~t5_pc~0); 423697#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 423259#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 423048#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 423015#L1103 assume !(0 != activate_threads_~tmp___4~0); 423003#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 422729#L534 assume !(1 == ~t6_pc~0); 422719#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 422720#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 423232#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 423233#L1111 assume !(0 != activate_threads_~tmp___5~0); 423554#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 422972#L553 assume !(1 == ~t7_pc~0); 422697#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 422977#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 423369#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 423207#L1119 assume !(0 != activate_threads_~tmp___6~0); 423184#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 423144#L572 assume !(1 == ~t8_pc~0); 423145#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 423147#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 423506#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 422630#L1127 assume !(0 != activate_threads_~tmp___7~0); 422631#L1127-2 assume !(1 == ~M_E~0); 422632#L954-1 assume !(1 == ~T1_E~0); 423485#L959-1 assume !(1 == ~T2_E~0); 423253#L964-1 assume !(1 == ~T3_E~0); 423076#L969-1 assume !(1 == ~T4_E~0); 422740#L974-1 assume !(1 == ~T5_E~0); 422741#L979-1 assume !(1 == ~T6_E~0); 423324#L984-1 assume !(1 == ~T7_E~0); 423053#L989-1 assume !(1 == ~T8_E~0); 422906#L994-1 assume !(1 == ~E_M~0); 422907#L999-1 assume !(1 == ~E_1~0); 423545#L1004-1 assume !(1 == ~E_2~0); 423190#L1009-1 assume !(1 == ~E_3~0); 422820#L1014-1 assume !(1 == ~E_4~0); 422821#L1019-1 assume !(1 == ~E_5~0); 423624#L1024-1 assume !(1 == ~E_6~0); 423402#L1029-1 assume !(1 == ~E_7~0); 423155#L1034-1 assume !(1 == ~E_8~0); 423156#L1305-1 [2019-12-07 13:00:33,162 INFO L796 eck$LassoCheckResult]: Loop: 423156#L1305-1 assume !false; 433053#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 433044#L831 assume !false; 433036#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 429859#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 429849#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 429847#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 429844#L714 assume !(0 != eval_~tmp~0); 429845#L846 start_simulation_~kernel_st~0 := 2; 430485#L592-1 start_simulation_~kernel_st~0 := 3; 430484#L856-2 assume !(0 == ~M_E~0); 430483#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 430482#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 430481#L866-3 assume !(0 == ~T3_E~0); 430480#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 430479#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 430477#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 430475#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 430473#L891-3 assume !(0 == ~T8_E~0); 430471#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 430469#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 430467#L906-3 assume !(0 == ~E_2~0); 430465#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 430463#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 430461#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 430459#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 430457#L931-3 assume !(0 == ~E_7~0); 430455#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 430453#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 430451#L420-30 assume !(1 == ~m_pc~0); 430448#L420-32 is_master_triggered_~__retres1~0 := 0; 430446#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 430444#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 430442#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 430440#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 430438#L439-30 assume !(1 == ~t1_pc~0); 430436#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 430433#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 430431#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 430429#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 430427#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 430423#L458-30 assume !(1 == ~t2_pc~0); 430420#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 430418#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 430416#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 430414#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 430412#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 430411#L477-30 assume !(1 == ~t3_pc~0); 430408#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 430406#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 430404#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 430402#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 430400#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 430398#L496-30 assume 1 == ~t4_pc~0; 430396#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 430392#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 430390#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 430388#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 430386#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 430384#L515-30 assume !(1 == ~t5_pc~0); 430382#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 430379#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 430377#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 430375#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 430373#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 430371#L534-30 assume !(1 == ~t6_pc~0); 430369#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 430367#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 430365#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 430364#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 430363#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 430362#L553-30 assume !(1 == ~t7_pc~0); 430360#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 430359#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 430358#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 430357#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 430356#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 430355#L572-30 assume !(1 == ~t8_pc~0); 430354#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 430353#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 430352#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 430351#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 430350#L1127-32 assume !(1 == ~M_E~0); 430179#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 430349#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 430348#L964-3 assume !(1 == ~T3_E~0); 430347#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 430346#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 430345#L979-3 assume !(1 == ~T6_E~0); 430344#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 430343#L989-3 assume !(1 == ~T8_E~0); 430342#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 430341#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 430339#L1004-3 assume !(1 == ~E_2~0); 430337#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 430335#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 430333#L1019-3 assume !(1 == ~E_5~0); 430331#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 430329#L1029-3 assume !(1 == ~E_7~0); 430327#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 430325#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 430319#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 430310#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 430308#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 430305#L1324 assume !(0 == start_simulation_~tmp~3); 430306#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 433200#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 433190#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 433188#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 433186#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 433184#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 433182#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 433180#L1337 assume !(0 != start_simulation_~tmp___0~1); 423156#L1305-1 [2019-12-07 13:00:33,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:33,162 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 1 times [2019-12-07 13:00:33,162 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:33,162 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052703327] [2019-12-07 13:00:33,162 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:33,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:33,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:33,216 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:33,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:33,216 INFO L82 PathProgramCache]: Analyzing trace with hash -625255430, now seen corresponding path program 1 times [2019-12-07 13:00:33,216 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:33,216 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742334609] [2019-12-07 13:00:33,216 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:33,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:33,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:33,238 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742334609] [2019-12-07 13:00:33,238 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:33,238 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:33,238 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631734113] [2019-12-07 13:00:33,238 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:33,239 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:33,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:33,239 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:33,239 INFO L87 Difference]: Start difference. First operand 41562 states and 58499 transitions. cyclomatic complexity: 16969 Second operand 3 states. [2019-12-07 13:00:33,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:33,321 INFO L93 Difference]: Finished difference Result 46662 states and 65641 transitions. [2019-12-07 13:00:33,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:33,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46662 states and 65641 transitions. [2019-12-07 13:00:33,438 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46160 [2019-12-07 13:00:33,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46662 states to 46662 states and 65641 transitions. [2019-12-07 13:00:33,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46662 [2019-12-07 13:00:33,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46662 [2019-12-07 13:00:33,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46662 states and 65641 transitions. [2019-12-07 13:00:33,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:33,548 INFO L688 BuchiCegarLoop]: Abstraction has 46662 states and 65641 transitions. [2019-12-07 13:00:33,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46662 states and 65641 transitions. [2019-12-07 13:00:33,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46662 to 46662. [2019-12-07 13:00:33,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46662 states. [2019-12-07 13:00:33,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46662 states to 46662 states and 65641 transitions. [2019-12-07 13:00:33,797 INFO L711 BuchiCegarLoop]: Abstraction has 46662 states and 65641 transitions. [2019-12-07 13:00:33,797 INFO L591 BuchiCegarLoop]: Abstraction has 46662 states and 65641 transitions. [2019-12-07 13:00:33,797 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-12-07 13:00:33,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46662 states and 65641 transitions. [2019-12-07 13:00:33,895 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46160 [2019-12-07 13:00:33,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:33,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:33,897 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:33,897 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:33,897 INFO L794 eck$LassoCheckResult]: Stem: 511348#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 511257#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 511258#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 511514#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 510826#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510827#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 511632#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 511515#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 511220#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 511221#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 511719#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 511474#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 511110#L639-1 assume !(0 == ~M_E~0); 511111#L856-1 assume !(0 == ~T1_E~0); 511225#L861-1 assume !(0 == ~T2_E~0); 511226#L866-1 assume !(0 == ~T3_E~0); 511746#L871-1 assume !(0 == ~T4_E~0); 511500#L876-1 assume !(0 == ~T5_E~0); 511326#L881-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 511327#L886-1 assume !(0 == ~T7_E~0); 511911#L891-1 assume !(0 == ~T8_E~0); 511912#L896-1 assume !(0 == ~E_M~0); 511287#L901-1 assume !(0 == ~E_1~0); 511288#L906-1 assume !(0 == ~E_2~0); 511983#L911-1 assume !(0 == ~E_3~0); 511984#L916-1 assume !(0 == ~E_4~0); 511412#L921-1 assume !(0 == ~E_5~0); 511041#L926-1 assume !(0 == ~E_6~0); 511042#L931-1 assume !(0 == ~E_7~0); 511888#L936-1 assume !(0 == ~E_8~0); 511889#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 511003#L420 assume !(1 == ~m_pc~0); 511004#L420-2 is_master_triggered_~__retres1~0 := 0; 511729#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 511730#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 511969#L1063 assume !(0 != activate_threads_~tmp~1); 511970#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 511275#L439 assume !(1 == ~t1_pc~0); 511276#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 511847#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 511848#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 511790#L1071 assume !(0 != activate_threads_~tmp___0~0); 511791#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 511482#L458 assume !(1 == ~t2_pc~0); 511483#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 511959#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 511960#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 511995#L1079 assume !(0 != activate_threads_~tmp___1~0); 511341#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 511342#L477 assume !(1 == ~t3_pc~0); 511623#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 511624#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 510992#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 510993#L1087 assume !(0 != activate_threads_~tmp___2~0); 511985#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 511986#L496 assume !(1 == ~t4_pc~0); 511726#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 511725#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 511026#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 511027#L1095 assume !(0 != activate_threads_~tmp___3~0); 511687#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 511688#L515 assume !(1 == ~t5_pc~0); 511978#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 511979#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 511285#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 511286#L1103 assume !(0 != activate_threads_~tmp___4~0); 512010#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 510956#L534 assume !(1 == ~t6_pc~0); 510957#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 511662#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 511663#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 511822#L1111 assume !(0 != activate_threads_~tmp___5~0); 511823#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 511202#L553 assume !(1 == ~t7_pc~0); 510923#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 511800#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 511801#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 511451#L1119 assume !(0 != activate_threads_~tmp___6~0); 511430#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 511389#L572 assume !(1 == ~t8_pc~0); 511390#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 511392#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 511766#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 510858#L1127 assume !(0 != activate_threads_~tmp___7~0); 510859#L1127-2 assume !(1 == ~M_E~0); 510860#L954-1 assume !(1 == ~T1_E~0); 511743#L959-1 assume !(1 == ~T2_E~0); 511498#L964-1 assume !(1 == ~T3_E~0); 511317#L969-1 assume !(1 == ~T4_E~0); 510968#L974-1 assume !(1 == ~T5_E~0); 510969#L979-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 511581#L984-1 assume !(1 == ~T7_E~0); 511292#L989-1 assume !(1 == ~T8_E~0); 511138#L994-1 assume !(1 == ~E_M~0); 511139#L999-1 assume !(1 == ~E_1~0); 511813#L1004-1 assume !(1 == ~E_2~0); 511436#L1009-1 assume !(1 == ~E_3~0); 511049#L1014-1 assume !(1 == ~E_4~0); 511050#L1019-1 assume !(1 == ~E_5~0); 511892#L1024-1 assume !(1 == ~E_6~0); 511669#L1029-1 assume !(1 == ~E_7~0); 511399#L1034-1 assume !(1 == ~E_8~0); 511400#L1305-1 [2019-12-07 13:00:33,897 INFO L796 eck$LassoCheckResult]: Loop: 511400#L1305-1 assume !false; 522683#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 522681#L831 assume !false; 522679#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 522677#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 522667#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 522665#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 522662#L714 assume !(0 != eval_~tmp~0); 522660#L846 start_simulation_~kernel_st~0 := 2; 522658#L592-1 start_simulation_~kernel_st~0 := 3; 522657#L856-2 assume !(0 == ~M_E~0); 522656#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 522655#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 522654#L866-3 assume !(0 == ~T3_E~0); 522653#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 522652#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 522651#L881-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 522650#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 522648#L891-3 assume !(0 == ~T8_E~0); 522646#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 522644#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 522642#L906-3 assume !(0 == ~E_2~0); 522640#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 522638#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 522636#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 522634#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 522632#L931-3 assume !(0 == ~E_7~0); 522630#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 522628#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 522626#L420-30 assume 1 == ~m_pc~0; 522624#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 522620#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 522618#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 522616#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 522614#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 522612#L439-30 assume !(1 == ~t1_pc~0); 522610#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 522608#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 522606#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 522604#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 522602#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 522597#L458-30 assume !(1 == ~t2_pc~0); 522595#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 522593#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 522591#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 522589#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 522587#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 522585#L477-30 assume !(1 == ~t3_pc~0); 522583#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 522581#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 522579#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 522577#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 522575#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 522573#L496-30 assume 1 == ~t4_pc~0; 522570#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 522567#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 522565#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 522563#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 522561#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 522559#L515-30 assume !(1 == ~t5_pc~0); 522557#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 522555#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 522553#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 522551#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 522549#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 522547#L534-30 assume !(1 == ~t6_pc~0); 522545#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 522543#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 522541#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 522539#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 522537#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 522534#L553-30 assume !(1 == ~t7_pc~0); 522531#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 522529#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 522527#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 522525#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 522523#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 522521#L572-30 assume !(1 == ~t8_pc~0); 522519#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 522517#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 522515#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 522513#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 522509#L1127-32 assume !(1 == ~M_E~0); 522505#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 522503#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 522501#L964-3 assume !(1 == ~T3_E~0); 522499#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 522497#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 522496#L979-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 522494#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 522493#L989-3 assume !(1 == ~T8_E~0); 522492#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 522491#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 522490#L1004-3 assume !(1 == ~E_2~0); 522489#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 522488#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 522487#L1019-3 assume !(1 == ~E_5~0); 522486#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 522485#L1029-3 assume !(1 == ~E_7~0); 522484#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 522483#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 522476#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 522467#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 522465#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 522462#L1324 assume !(0 == start_simulation_~tmp~3); 522463#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 522851#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 522841#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 522839#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 522838#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 522834#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 522832#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 522831#L1337 assume !(0 != start_simulation_~tmp___0~1); 511400#L1305-1 [2019-12-07 13:00:33,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:33,898 INFO L82 PathProgramCache]: Analyzing trace with hash -1586346936, now seen corresponding path program 1 times [2019-12-07 13:00:33,898 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:33,898 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396945199] [2019-12-07 13:00:33,898 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:33,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:34,038 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396945199] [2019-12-07 13:00:34,038 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:34,038 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:34,038 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066717584] [2019-12-07 13:00:34,038 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:34,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:34,038 INFO L82 PathProgramCache]: Analyzing trace with hash -310897959, now seen corresponding path program 1 times [2019-12-07 13:00:34,038 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:34,039 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514001597] [2019-12-07 13:00:34,039 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:34,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:34,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:34,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514001597] [2019-12-07 13:00:34,060 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:34,060 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:34,060 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118287940] [2019-12-07 13:00:34,061 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:34,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:34,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:34,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:34,061 INFO L87 Difference]: Start difference. First operand 46662 states and 65641 transitions. cyclomatic complexity: 19011 Second operand 3 states. [2019-12-07 13:00:34,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:34,133 INFO L93 Difference]: Finished difference Result 41562 states and 58305 transitions. [2019-12-07 13:00:34,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:34,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41562 states and 58305 transitions. [2019-12-07 13:00:34,236 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41136 [2019-12-07 13:00:34,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41562 states to 41562 states and 58305 transitions. [2019-12-07 13:00:34,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41562 [2019-12-07 13:00:34,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41562 [2019-12-07 13:00:34,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41562 states and 58305 transitions. [2019-12-07 13:00:34,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:34,333 INFO L688 BuchiCegarLoop]: Abstraction has 41562 states and 58305 transitions. [2019-12-07 13:00:34,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41562 states and 58305 transitions. [2019-12-07 13:00:34,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41562 to 41562. [2019-12-07 13:00:34,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41562 states. [2019-12-07 13:00:34,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41562 states to 41562 states and 58305 transitions. [2019-12-07 13:00:34,574 INFO L711 BuchiCegarLoop]: Abstraction has 41562 states and 58305 transitions. [2019-12-07 13:00:34,574 INFO L591 BuchiCegarLoop]: Abstraction has 41562 states and 58305 transitions. [2019-12-07 13:00:34,574 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-12-07 13:00:34,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41562 states and 58305 transitions. [2019-12-07 13:00:34,655 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41136 [2019-12-07 13:00:34,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:34,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:34,656 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:34,656 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:34,657 INFO L794 eck$LassoCheckResult]: Stem: 599547#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 599472#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 599473#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 599691#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 599057#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 599058#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 599796#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 599692#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 599435#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 599436#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 599870#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 599654#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 599332#L639-1 assume !(0 == ~M_E~0); 599333#L856-1 assume !(0 == ~T1_E~0); 599440#L861-1 assume !(0 == ~T2_E~0); 599441#L866-1 assume !(0 == ~T3_E~0); 599895#L871-1 assume !(0 == ~T4_E~0); 599679#L876-1 assume !(0 == ~T5_E~0); 599531#L881-1 assume !(0 == ~T6_E~0); 599198#L886-1 assume !(0 == ~T7_E~0); 599199#L891-1 assume !(0 == ~T8_E~0); 599756#L896-1 assume !(0 == ~E_M~0); 599500#L901-1 assume !(0 == ~E_1~0); 599156#L906-1 assume !(0 == ~E_2~0); 599157#L911-1 assume !(0 == ~E_3~0); 599946#L916-1 assume !(0 == ~E_4~0); 599593#L921-1 assume !(0 == ~E_5~0); 599262#L926-1 assume !(0 == ~E_6~0); 599263#L931-1 assume !(0 == ~E_7~0); 600019#L936-1 assume !(0 == ~E_8~0); 599834#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 599225#L420 assume !(1 == ~m_pc~0); 599226#L420-2 is_master_triggered_~__retres1~0 := 0; 599232#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 599881#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 599942#L1063 assume !(0 != activate_threads_~tmp~1); 600101#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 599489#L439 assume !(1 == ~t1_pc~0); 599490#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 599494#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 599986#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 599933#L1071 assume !(0 != activate_threads_~tmp___0~0); 599919#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 599662#L458 assume !(1 == ~t2_pc~0); 599637#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 599638#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 600094#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 599540#L1079 assume !(0 != activate_threads_~tmp___1~0); 599541#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 599542#L477 assume !(1 == ~t3_pc~0); 599784#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 599125#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 599126#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 599216#L1087 assume !(0 != activate_threads_~tmp___2~0); 600113#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 599916#L496 assume !(1 == ~t4_pc~0); 599876#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 599344#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 599247#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 599248#L1095 assume !(0 != activate_threads_~tmp___3~0); 599840#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 599841#L515 assume !(1 == ~t5_pc~0); 600104#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 599682#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 599499#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 599462#L1103 assume !(0 != activate_threads_~tmp___4~0); 599449#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 599183#L534 assume !(1 == ~t6_pc~0); 599175#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 599176#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 599656#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 599657#L1111 assume !(0 != activate_threads_~tmp___5~0); 599957#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 599419#L553 assume !(1 == ~t7_pc~0); 599154#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 599425#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 599797#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 599631#L1119 assume !(0 != activate_threads_~tmp___6~0); 599610#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 599574#L572 assume !(1 == ~t8_pc~0); 599575#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 599577#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 599913#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 599089#L1127 assume !(0 != activate_threads_~tmp___7~0); 599090#L1127-2 assume !(1 == ~M_E~0); 599091#L954-1 assume !(1 == ~T1_E~0); 599893#L959-1 assume !(1 == ~T2_E~0); 599677#L964-1 assume !(1 == ~T3_E~0); 599524#L969-1 assume !(1 == ~T4_E~0); 599194#L974-1 assume !(1 == ~T5_E~0); 599195#L979-1 assume !(1 == ~T6_E~0); 599753#L984-1 assume !(1 == ~T7_E~0); 599504#L989-1 assume !(1 == ~T8_E~0); 599357#L994-1 assume !(1 == ~E_M~0); 599358#L999-1 assume !(1 == ~E_1~0); 599950#L1004-1 assume !(1 == ~E_2~0); 599616#L1009-1 assume !(1 == ~E_3~0); 599270#L1014-1 assume !(1 == ~E_4~0); 599271#L1019-1 assume !(1 == ~E_5~0); 600022#L1024-1 assume !(1 == ~E_6~0); 599830#L1029-1 assume !(1 == ~E_7~0); 599583#L1034-1 assume !(1 == ~E_8~0); 599584#L1305-1 [2019-12-07 13:00:34,657 INFO L796 eck$LassoCheckResult]: Loop: 599584#L1305-1 assume !false; 608609#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 608607#L831 assume !false; 608605#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 608602#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 608592#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 608590#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 608587#L714 assume !(0 != eval_~tmp~0); 608585#L846 start_simulation_~kernel_st~0 := 2; 608583#L592-1 start_simulation_~kernel_st~0 := 3; 608580#L856-2 assume !(0 == ~M_E~0); 608578#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 608576#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 608574#L866-3 assume !(0 == ~T3_E~0); 608572#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 608569#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 608567#L881-3 assume !(0 == ~T6_E~0); 608565#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 608563#L891-3 assume !(0 == ~T8_E~0); 608561#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 608559#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 608557#L906-3 assume !(0 == ~E_2~0); 608555#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 608553#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 608551#L921-3 assume 0 == ~E_5~0;~E_5~0 := 1; 608549#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 608547#L931-3 assume !(0 == ~E_7~0); 608545#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 608542#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 608540#L420-30 assume !(1 == ~m_pc~0); 608537#L420-32 is_master_triggered_~__retres1~0 := 0; 608535#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 608533#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 608531#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 608529#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 608527#L439-30 assume !(1 == ~t1_pc~0); 608525#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 608523#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 608521#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 608519#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 608517#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 608513#L458-30 assume !(1 == ~t2_pc~0); 608511#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 608509#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 608506#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 608504#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 608502#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 608500#L477-30 assume !(1 == ~t3_pc~0); 608498#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 608496#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 608494#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 608492#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 608490#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 608488#L496-30 assume !(1 == ~t4_pc~0); 608485#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 608480#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 608479#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 608478#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 608477#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 608476#L515-30 assume !(1 == ~t5_pc~0); 608475#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 608474#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 608473#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 608472#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 608471#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 608470#L534-30 assume !(1 == ~t6_pc~0); 608469#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 608468#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 608467#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 608466#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 608465#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 608464#L553-30 assume !(1 == ~t7_pc~0); 608462#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 608461#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 608460#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 608459#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 608458#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 608457#L572-30 assume !(1 == ~t8_pc~0); 608456#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 608455#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 608454#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 608453#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 608451#L1127-32 assume !(1 == ~M_E~0); 608294#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 608448#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 608446#L964-3 assume !(1 == ~T3_E~0); 608444#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 608442#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 608440#L979-3 assume !(1 == ~T6_E~0); 608438#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 608436#L989-3 assume !(1 == ~T8_E~0); 608434#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 608432#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 608430#L1004-3 assume !(1 == ~E_2~0); 608428#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 608426#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 608424#L1019-3 assume !(1 == ~E_5~0); 608422#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 608420#L1029-3 assume !(1 == ~E_7~0); 608418#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 608416#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 608408#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 608399#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 608397#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 608394#L1324 assume !(0 == start_simulation_~tmp~3); 608395#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 609361#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 609352#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 609351#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 609350#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 609349#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 609348#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 609347#L1337 assume !(0 != start_simulation_~tmp___0~1); 599584#L1305-1 [2019-12-07 13:00:34,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:34,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 2 times [2019-12-07 13:00:34,657 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:34,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396575417] [2019-12-07 13:00:34,657 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:34,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:34,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:34,689 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:34,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:34,689 INFO L82 PathProgramCache]: Analyzing trace with hash -930668517, now seen corresponding path program 1 times [2019-12-07 13:00:34,689 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:34,689 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404844629] [2019-12-07 13:00:34,689 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:34,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:34,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:34,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404844629] [2019-12-07 13:00:34,712 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:34,712 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:34,712 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067694187] [2019-12-07 13:00:34,713 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:34,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:34,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:34,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:34,713 INFO L87 Difference]: Start difference. First operand 41562 states and 58305 transitions. cyclomatic complexity: 16775 Second operand 3 states. [2019-12-07 13:00:34,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:34,885 INFO L93 Difference]: Finished difference Result 62262 states and 86918 transitions. [2019-12-07 13:00:34,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:34,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62262 states and 86918 transitions. [2019-12-07 13:00:35,064 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61632 [2019-12-07 13:00:35,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62262 states to 62262 states and 86918 transitions. [2019-12-07 13:00:35,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62262 [2019-12-07 13:00:35,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62262 [2019-12-07 13:00:35,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62262 states and 86918 transitions. [2019-12-07 13:00:35,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:35,239 INFO L688 BuchiCegarLoop]: Abstraction has 62262 states and 86918 transitions. [2019-12-07 13:00:35,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62262 states and 86918 transitions. [2019-12-07 13:00:35,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62262 to 62230. [2019-12-07 13:00:35,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62230 states. [2019-12-07 13:00:35,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62230 states to 62230 states and 86886 transitions. [2019-12-07 13:00:35,742 INFO L711 BuchiCegarLoop]: Abstraction has 62230 states and 86886 transitions. [2019-12-07 13:00:35,742 INFO L591 BuchiCegarLoop]: Abstraction has 62230 states and 86886 transitions. [2019-12-07 13:00:35,742 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-12-07 13:00:35,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62230 states and 86886 transitions. [2019-12-07 13:00:35,875 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61600 [2019-12-07 13:00:35,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:35,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:35,876 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:35,876 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:35,877 INFO L794 eck$LassoCheckResult]: Stem: 703395#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 703312#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 703313#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 703562#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 702887#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 702888#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 703671#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 703563#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 703273#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 703274#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 703757#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 703522#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 703166#L639-1 assume !(0 == ~M_E~0); 703167#L856-1 assume !(0 == ~T1_E~0); 703278#L861-1 assume !(0 == ~T2_E~0); 703279#L866-1 assume !(0 == ~T3_E~0); 703783#L871-1 assume !(0 == ~T4_E~0); 703548#L876-1 assume !(0 == ~T5_E~0); 703370#L881-1 assume !(0 == ~T6_E~0); 703031#L886-1 assume !(0 == ~T7_E~0); 703032#L891-1 assume !(0 == ~T8_E~0); 703628#L896-1 assume !(0 == ~E_M~0); 703337#L901-1 assume !(0 == ~E_1~0); 702986#L906-1 assume !(0 == ~E_2~0); 702987#L911-1 assume !(0 == ~E_3~0); 703842#L916-1 assume !(0 == ~E_4~0); 703460#L921-1 assume 0 == ~E_5~0;~E_5~0 := 1; 703098#L926-1 assume !(0 == ~E_6~0); 703099#L931-1 assume !(0 == ~E_7~0); 703982#L936-1 assume !(0 == ~E_8~0); 703714#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 703715#L420 assume !(1 == ~m_pc~0); 703068#L420-2 is_master_triggered_~__retres1~0 := 0; 703069#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 703837#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 703838#L1063 assume !(0 != activate_threads_~tmp~1); 703989#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 703990#L439 assume !(1 == ~t1_pc~0); 703330#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 703331#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 703930#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 703931#L1071 assume !(0 != activate_threads_~tmp___0~0); 703811#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 703812#L458 assume !(1 == ~t2_pc~0); 703505#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 703506#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 703979#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 704007#L1079 assume !(0 != activate_threads_~tmp___1~0); 703381#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 703382#L477 assume !(1 == ~t3_pc~0); 704040#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 702956#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 702957#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 704039#L1087 assume !(0 != activate_threads_~tmp___2~0); 704038#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 703806#L496 assume !(1 == ~t4_pc~0); 703807#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 703179#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 703083#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 703084#L1095 assume !(0 != activate_threads_~tmp___3~0); 703724#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 703725#L515 assume !(1 == ~t5_pc~0); 703992#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 703994#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 703336#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 703302#L1103 assume !(0 != activate_threads_~tmp___4~0); 703290#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 703291#L534 assume !(1 == ~t6_pc~0); 703006#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 703007#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 703524#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 703525#L1111 assume !(0 != activate_threads_~tmp___5~0); 703858#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 703257#L553 assume !(1 == ~t7_pc~0); 702984#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 703262#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 703673#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 703674#L1119 assume !(0 != activate_threads_~tmp___6~0); 704027#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 704026#L572 assume !(1 == ~t8_pc~0); 704025#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 704024#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 704023#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 704022#L1127 assume !(0 != activate_threads_~tmp___7~0); 704021#L1127-2 assume !(1 == ~M_E~0); 704020#L954-1 assume !(1 == ~T1_E~0); 704019#L959-1 assume !(1 == ~T2_E~0); 704018#L964-1 assume !(1 == ~T3_E~0); 704017#L969-1 assume !(1 == ~T4_E~0); 704016#L974-1 assume !(1 == ~T5_E~0); 704015#L979-1 assume !(1 == ~T6_E~0); 704014#L984-1 assume !(1 == ~T7_E~0); 704013#L989-1 assume !(1 == ~T8_E~0); 704012#L994-1 assume !(1 == ~E_M~0); 704011#L999-1 assume !(1 == ~E_1~0); 704010#L1004-1 assume !(1 == ~E_2~0); 704009#L1009-1 assume !(1 == ~E_3~0); 703108#L1014-1 assume !(1 == ~E_4~0); 703109#L1019-1 assume 1 == ~E_5~0;~E_5~0 := 2; 703925#L1024-1 assume !(1 == ~E_6~0); 703710#L1029-1 assume !(1 == ~E_7~0); 703443#L1034-1 assume !(1 == ~E_8~0); 703444#L1305-1 [2019-12-07 13:00:35,877 INFO L796 eck$LassoCheckResult]: Loop: 703444#L1305-1 assume !false; 741442#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 719563#L831 assume !false; 741439#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 719742#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 719732#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 719730#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 719727#L714 assume !(0 != eval_~tmp~0); 719728#L846 start_simulation_~kernel_st~0 := 2; 723736#L592-1 start_simulation_~kernel_st~0 := 3; 723734#L856-2 assume !(0 == ~M_E~0); 723732#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 723730#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 723728#L866-3 assume !(0 == ~T3_E~0); 723725#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 723723#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 723721#L881-3 assume !(0 == ~T6_E~0); 723719#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 723717#L891-3 assume !(0 == ~T8_E~0); 723715#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 723713#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 723711#L906-3 assume !(0 == ~E_2~0); 723709#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 723707#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 723704#L921-3 assume !(0 == ~E_5~0); 723705#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 723735#L931-3 assume !(0 == ~E_7~0); 723733#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 723731#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 723729#L420-30 assume 1 == ~m_pc~0; 723727#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 723724#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 723722#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 723720#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 723718#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 723716#L439-30 assume !(1 == ~t1_pc~0); 723714#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 723712#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 723710#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 723708#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 723706#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 723701#L458-30 assume !(1 == ~t2_pc~0); 723699#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 723697#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 723695#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 723693#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 723690#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 723688#L477-30 assume !(1 == ~t3_pc~0); 723686#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 723684#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 723682#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 723680#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 723678#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 723676#L496-30 assume 1 == ~t4_pc~0; 723674#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 723671#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 723669#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 723668#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 723665#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 723663#L515-30 assume !(1 == ~t5_pc~0); 723661#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 723659#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 723657#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 723655#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 723653#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 723651#L534-30 assume !(1 == ~t6_pc~0); 723649#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 723647#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 723645#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 723643#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 723641#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 723638#L553-30 assume !(1 == ~t7_pc~0); 723635#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 723633#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 723631#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 723629#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 723627#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 723625#L572-30 assume !(1 == ~t8_pc~0); 723623#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 723621#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 723619#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 723617#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 723615#L1127-32 assume !(1 == ~M_E~0); 723611#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 723609#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 723607#L964-3 assume !(1 == ~T3_E~0); 723605#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 723603#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 723600#L979-3 assume !(1 == ~T6_E~0); 723598#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 723596#L989-3 assume !(1 == ~T8_E~0); 723594#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 723592#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 723590#L1004-3 assume !(1 == ~E_2~0); 723588#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 723586#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 723553#L1019-3 assume !(1 == ~E_5~0); 723550#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 723548#L1029-3 assume !(1 == ~E_7~0); 723546#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 723544#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 723536#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 723527#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 723525#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 723523#L1324 assume !(0 == start_simulation_~tmp~3); 703246#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 703247#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 702980#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 703542#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 703079#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 703080#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 703912#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 741445#L1337 assume !(0 != start_simulation_~tmp___0~1); 703444#L1305-1 [2019-12-07 13:00:35,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:35,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1130035128, now seen corresponding path program 1 times [2019-12-07 13:00:35,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:35,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034631193] [2019-12-07 13:00:35,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:35,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:35,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:35,909 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034631193] [2019-12-07 13:00:35,909 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:35,909 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:00:35,909 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42249918] [2019-12-07 13:00:35,910 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:00:35,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:35,910 INFO L82 PathProgramCache]: Analyzing trace with hash 659988191, now seen corresponding path program 1 times [2019-12-07 13:00:35,910 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:35,910 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267560220] [2019-12-07 13:00:35,910 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:35,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:35,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:35,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267560220] [2019-12-07 13:00:35,964 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:35,964 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 13:00:35,964 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764483351] [2019-12-07 13:00:35,964 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:35,964 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:35,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:35,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:35,965 INFO L87 Difference]: Start difference. First operand 62230 states and 86886 transitions. cyclomatic complexity: 24688 Second operand 3 states. [2019-12-07 13:00:36,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:36,050 INFO L93 Difference]: Finished difference Result 41562 states and 57839 transitions. [2019-12-07 13:00:36,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:36,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41562 states and 57839 transitions. [2019-12-07 13:00:36,152 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41136 [2019-12-07 13:00:36,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41562 states to 41562 states and 57839 transitions. [2019-12-07 13:00:36,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41562 [2019-12-07 13:00:36,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41562 [2019-12-07 13:00:36,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41562 states and 57839 transitions. [2019-12-07 13:00:36,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:36,250 INFO L688 BuchiCegarLoop]: Abstraction has 41562 states and 57839 transitions. [2019-12-07 13:00:36,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41562 states and 57839 transitions. [2019-12-07 13:00:36,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41562 to 41562. [2019-12-07 13:00:36,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41562 states. [2019-12-07 13:00:36,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41562 states to 41562 states and 57839 transitions. [2019-12-07 13:00:36,482 INFO L711 BuchiCegarLoop]: Abstraction has 41562 states and 57839 transitions. [2019-12-07 13:00:36,482 INFO L591 BuchiCegarLoop]: Abstraction has 41562 states and 57839 transitions. [2019-12-07 13:00:36,482 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-12-07 13:00:36,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41562 states and 57839 transitions. [2019-12-07 13:00:36,558 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41136 [2019-12-07 13:00:36,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:36,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:36,559 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:36,559 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:36,559 INFO L794 eck$LassoCheckResult]: Stem: 807200#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 807114#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 807115#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 807352#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 806694#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 806695#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 807449#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 807353#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 807073#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 807074#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 807548#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 807313#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 806968#L639-1 assume !(0 == ~M_E~0); 806969#L856-1 assume !(0 == ~T1_E~0); 807078#L861-1 assume !(0 == ~T2_E~0); 807079#L866-1 assume !(0 == ~T3_E~0); 807573#L871-1 assume !(0 == ~T4_E~0); 807339#L876-1 assume !(0 == ~T5_E~0); 807176#L881-1 assume !(0 == ~T6_E~0); 806836#L886-1 assume !(0 == ~T7_E~0); 806837#L891-1 assume !(0 == ~T8_E~0); 807411#L896-1 assume !(0 == ~E_M~0); 807138#L901-1 assume !(0 == ~E_1~0); 806793#L906-1 assume !(0 == ~E_2~0); 806794#L911-1 assume !(0 == ~E_3~0); 807633#L916-1 assume !(0 == ~E_4~0); 807253#L921-1 assume !(0 == ~E_5~0); 806900#L926-1 assume !(0 == ~E_6~0); 806901#L931-1 assume !(0 == ~E_7~0); 807699#L936-1 assume !(0 == ~E_8~0); 807488#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 806864#L420 assume !(1 == ~m_pc~0); 806865#L420-2 is_master_triggered_~__retres1~0 := 0; 806871#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 807559#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 807628#L1063 assume !(0 != activate_threads_~tmp~1); 807777#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 807128#L439 assume !(1 == ~t1_pc~0); 807129#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 807132#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 807671#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 807616#L1071 assume !(0 != activate_threads_~tmp___0~0); 807602#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 807321#L458 assume !(1 == ~t2_pc~0); 807295#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 807296#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 807770#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 807189#L1079 assume !(0 != activate_threads_~tmp___1~0); 807190#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 807191#L477 assume !(1 == ~t3_pc~0); 807437#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 806762#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 806763#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 806854#L1087 assume !(0 != activate_threads_~tmp___2~0); 807786#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 807599#L496 assume !(1 == ~t4_pc~0); 807554#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 806981#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 806885#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 806886#L1095 assume !(0 != activate_threads_~tmp___3~0); 807500#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 807501#L515 assume !(1 == ~t5_pc~0); 807780#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 807343#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 807137#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 807101#L1103 assume !(0 != activate_threads_~tmp___4~0); 807090#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 806821#L534 assume !(1 == ~t6_pc~0); 806811#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 806812#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 807315#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 807316#L1111 assume !(0 != activate_threads_~tmp___5~0); 807646#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 807057#L553 assume !(1 == ~t7_pc~0); 806791#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 807062#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 807451#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 807289#L1119 assume !(0 != activate_threads_~tmp___6~0); 807267#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 807229#L572 assume !(1 == ~t8_pc~0); 807230#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 807231#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 807596#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 806726#L1127 assume !(0 != activate_threads_~tmp___7~0); 806727#L1127-2 assume !(1 == ~M_E~0); 806728#L954-1 assume !(1 == ~T1_E~0); 807571#L959-1 assume !(1 == ~T2_E~0); 807337#L964-1 assume !(1 == ~T3_E~0); 807169#L969-1 assume !(1 == ~T4_E~0); 806832#L974-1 assume !(1 == ~T5_E~0); 806833#L979-1 assume !(1 == ~T6_E~0); 807407#L984-1 assume !(1 == ~T7_E~0); 807142#L989-1 assume !(1 == ~T8_E~0); 806993#L994-1 assume !(1 == ~E_M~0); 806994#L999-1 assume !(1 == ~E_1~0); 807639#L1004-1 assume !(1 == ~E_2~0); 807273#L1009-1 assume !(1 == ~E_3~0); 806911#L1014-1 assume !(1 == ~E_4~0); 806912#L1019-1 assume !(1 == ~E_5~0); 807702#L1024-1 assume !(1 == ~E_6~0); 807484#L1029-1 assume !(1 == ~E_7~0); 807237#L1034-1 assume !(1 == ~E_8~0); 807238#L1305-1 [2019-12-07 13:00:36,560 INFO L796 eck$LassoCheckResult]: Loop: 807238#L1305-1 assume !false; 812269#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 812267#L831 assume !false; 812265#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 812263#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 812247#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 812236#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 812227#L714 assume !(0 != eval_~tmp~0); 812228#L846 start_simulation_~kernel_st~0 := 2; 812816#L592-1 start_simulation_~kernel_st~0 := 3; 812809#L856-2 assume !(0 == ~M_E~0); 812801#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812795#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 812789#L866-3 assume !(0 == ~T3_E~0); 812783#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 812777#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 812771#L881-3 assume !(0 == ~T6_E~0); 812764#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 812759#L891-3 assume !(0 == ~T8_E~0); 812753#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 812747#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 812741#L906-3 assume !(0 == ~E_2~0); 812733#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 812727#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 812721#L921-3 assume !(0 == ~E_5~0); 812716#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 812711#L931-3 assume !(0 == ~E_7~0); 812707#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 812702#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 812696#L420-30 assume !(1 == ~m_pc~0); 812688#L420-32 is_master_triggered_~__retres1~0 := 0; 812683#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 812678#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 812673#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 812668#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 812661#L439-30 assume !(1 == ~t1_pc~0); 812660#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 812659#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 812658#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 812657#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 812655#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 812640#L458-30 assume !(1 == ~t2_pc~0); 812634#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 812628#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 812621#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 812616#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 812609#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 812602#L477-30 assume !(1 == ~t3_pc~0); 812596#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 812590#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 812584#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 812578#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 812572#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 812567#L496-30 assume !(1 == ~t4_pc~0); 812561#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 812556#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 812442#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 812428#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 812422#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 812416#L515-30 assume !(1 == ~t5_pc~0); 812411#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 812404#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 812398#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 812391#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 812390#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 812389#L534-30 assume !(1 == ~t6_pc~0); 812388#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 812387#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 812386#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 812385#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 812384#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 812383#L553-30 assume !(1 == ~t7_pc~0); 812381#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 812380#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 812378#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 812375#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 812373#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 812371#L572-30 assume !(1 == ~t8_pc~0); 812369#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 812367#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 812365#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 812363#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 812361#L1127-32 assume !(1 == ~M_E~0); 811425#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 812358#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 812356#L964-3 assume !(1 == ~T3_E~0); 812355#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 812354#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 812353#L979-3 assume !(1 == ~T6_E~0); 812352#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 812351#L989-3 assume !(1 == ~T8_E~0); 812349#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 812346#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 812254#L1004-3 assume !(1 == ~E_2~0); 812246#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 812235#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 812226#L1019-3 assume !(1 == ~E_5~0); 812216#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 812204#L1029-3 assume !(1 == ~E_7~0); 812165#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 812156#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 811678#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 811669#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 811667#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 811664#L1324 assume !(0 == start_simulation_~tmp~3); 811665#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 812441#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 812427#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 812421#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 812415#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 812410#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 812403#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 812397#L1337 assume !(0 != start_simulation_~tmp___0~1); 807238#L1305-1 [2019-12-07 13:00:36,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:36,560 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 3 times [2019-12-07 13:00:36,560 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:36,560 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364515565] [2019-12-07 13:00:36,560 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:36,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:36,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:36,581 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:36,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:36,581 INFO L82 PathProgramCache]: Analyzing trace with hash -1701402083, now seen corresponding path program 1 times [2019-12-07 13:00:36,581 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:36,581 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70866414] [2019-12-07 13:00:36,581 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:36,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:36,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:36,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70866414] [2019-12-07 13:00:36,632 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:36,632 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 13:00:36,632 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858487229] [2019-12-07 13:00:36,632 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:36,632 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:36,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 13:00:36,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 13:00:36,633 INFO L87 Difference]: Start difference. First operand 41562 states and 57839 transitions. cyclomatic complexity: 16309 Second operand 11 states. [2019-12-07 13:00:36,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:36,869 INFO L93 Difference]: Finished difference Result 75882 states and 104527 transitions. [2019-12-07 13:00:36,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:00:36,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75882 states and 104527 transitions. [2019-12-07 13:00:37,090 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75136 [2019-12-07 13:00:37,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75882 states to 75882 states and 104527 transitions. [2019-12-07 13:00:37,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75882 [2019-12-07 13:00:37,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75882 [2019-12-07 13:00:37,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75882 states and 104527 transitions. [2019-12-07 13:00:37,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:37,308 INFO L688 BuchiCegarLoop]: Abstraction has 75882 states and 104527 transitions. [2019-12-07 13:00:37,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75882 states and 104527 transitions. [2019-12-07 13:00:37,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75882 to 41754. [2019-12-07 13:00:37,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41754 states. [2019-12-07 13:00:37,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41754 states to 41754 states and 58031 transitions. [2019-12-07 13:00:37,721 INFO L711 BuchiCegarLoop]: Abstraction has 41754 states and 58031 transitions. [2019-12-07 13:00:37,721 INFO L591 BuchiCegarLoop]: Abstraction has 41754 states and 58031 transitions. [2019-12-07 13:00:37,721 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-12-07 13:00:37,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41754 states and 58031 transitions. [2019-12-07 13:00:37,805 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41328 [2019-12-07 13:00:37,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:37,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:37,806 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:37,806 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:37,806 INFO L794 eck$LassoCheckResult]: Stem: 924678#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 924584#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 924585#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 924842#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 924160#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 924161#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 924956#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 924843#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 924547#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 924548#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 925041#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 924803#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 924443#L639-1 assume !(0 == ~M_E~0); 924444#L856-1 assume !(0 == ~T1_E~0); 924552#L861-1 assume !(0 == ~T2_E~0); 924553#L866-1 assume !(0 == ~T3_E~0); 925067#L871-1 assume !(0 == ~T4_E~0); 924830#L876-1 assume !(0 == ~T5_E~0); 924651#L881-1 assume !(0 == ~T6_E~0); 924306#L886-1 assume !(0 == ~T7_E~0); 924307#L891-1 assume !(0 == ~T8_E~0); 924913#L896-1 assume !(0 == ~E_M~0); 924612#L901-1 assume !(0 == ~E_1~0); 924261#L906-1 assume !(0 == ~E_2~0); 924262#L911-1 assume !(0 == ~E_3~0); 925131#L916-1 assume !(0 == ~E_4~0); 924742#L921-1 assume !(0 == ~E_5~0); 924371#L926-1 assume !(0 == ~E_6~0); 924372#L931-1 assume !(0 == ~E_7~0); 925205#L936-1 assume !(0 == ~E_8~0); 924999#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 924334#L420 assume !(1 == ~m_pc~0); 924335#L420-2 is_master_triggered_~__retres1~0 := 0; 924341#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 925050#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 925124#L1063 assume !(0 != activate_threads_~tmp~1); 925296#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 924602#L439 assume !(1 == ~t1_pc~0); 924603#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 924606#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 925166#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 925113#L1071 assume !(0 != activate_threads_~tmp___0~0); 925098#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 924811#L458 assume !(1 == ~t2_pc~0); 924787#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 924788#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 925283#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 924664#L1079 assume !(0 != activate_threads_~tmp___1~0); 924665#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 924667#L477 assume !(1 == ~t3_pc~0); 924944#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 924230#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 924231#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 924325#L1087 assume !(0 != activate_threads_~tmp___2~0); 925309#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 925095#L496 assume !(1 == ~t4_pc~0); 925047#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 924454#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 924355#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 924356#L1095 assume !(0 != activate_threads_~tmp___3~0); 925012#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 925013#L515 assume !(1 == ~t5_pc~0); 925297#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 924833#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 924611#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 924575#L1103 assume !(0 != activate_threads_~tmp___4~0); 924561#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 924291#L534 assume !(1 == ~t6_pc~0); 924283#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 924284#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 924805#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 924806#L1111 assume !(0 != activate_threads_~tmp___5~0); 925144#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 924531#L553 assume !(1 == ~t7_pc~0); 924259#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 924537#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 924957#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 924781#L1119 assume !(0 != activate_threads_~tmp___6~0); 924759#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 924715#L572 assume !(1 == ~t8_pc~0); 924716#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 924719#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 925092#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 924193#L1127 assume !(0 != activate_threads_~tmp___7~0); 924194#L1127-2 assume !(1 == ~M_E~0); 924195#L954-1 assume !(1 == ~T1_E~0); 925063#L959-1 assume !(1 == ~T2_E~0); 924827#L964-1 assume !(1 == ~T3_E~0); 924644#L969-1 assume !(1 == ~T4_E~0); 924302#L974-1 assume !(1 == ~T5_E~0); 924303#L979-1 assume !(1 == ~T6_E~0); 924907#L984-1 assume !(1 == ~T7_E~0); 924616#L989-1 assume !(1 == ~T8_E~0); 924468#L994-1 assume !(1 == ~E_M~0); 924469#L999-1 assume !(1 == ~E_1~0); 925135#L1004-1 assume !(1 == ~E_2~0); 924765#L1009-1 assume !(1 == ~E_3~0); 924380#L1014-1 assume !(1 == ~E_4~0); 924381#L1019-1 assume !(1 == ~E_5~0); 925212#L1024-1 assume !(1 == ~E_6~0); 924995#L1029-1 assume !(1 == ~E_7~0); 924727#L1034-1 assume !(1 == ~E_8~0); 924728#L1305-1 [2019-12-07 13:00:37,807 INFO L796 eck$LassoCheckResult]: Loop: 924728#L1305-1 assume !false; 941837#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 941128#L831 assume !false; 941836#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 941835#L652 assume !(0 == ~m_st~0); 941830#L656 assume !(0 == ~t1_st~0); 941831#L660 assume !(0 == ~t2_st~0); 941834#L664 assume !(0 == ~t3_st~0); 941828#L668 assume !(0 == ~t4_st~0); 941829#L672 assume !(0 == ~t5_st~0); 941833#L676 assume !(0 == ~t6_st~0); 941826#L680 assume !(0 == ~t7_st~0); 941827#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 941832#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 935972#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 935973#L714 assume !(0 != eval_~tmp~0); 942052#L846 start_simulation_~kernel_st~0 := 2; 942050#L592-1 start_simulation_~kernel_st~0 := 3; 942048#L856-2 assume !(0 == ~M_E~0); 942046#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 942044#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 942042#L866-3 assume !(0 == ~T3_E~0); 942040#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 942038#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 942036#L881-3 assume !(0 == ~T6_E~0); 942034#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 942032#L891-3 assume !(0 == ~T8_E~0); 942030#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 942028#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 942026#L906-3 assume !(0 == ~E_2~0); 942024#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 942022#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 942020#L921-3 assume !(0 == ~E_5~0); 942018#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 942016#L931-3 assume !(0 == ~E_7~0); 942014#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 942012#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 942010#L420-30 assume 1 == ~m_pc~0; 942008#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 942004#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 942002#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 942000#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 941998#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 941996#L439-30 assume !(1 == ~t1_pc~0); 941994#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 941992#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 941990#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 941988#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 941986#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 941983#L458-30 assume !(1 == ~t2_pc~0); 941980#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 941978#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 941976#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 941974#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 941972#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 941970#L477-30 assume !(1 == ~t3_pc~0); 941968#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 941966#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 941964#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 941962#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 941960#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 941958#L496-30 assume 1 == ~t4_pc~0; 941956#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 941952#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 941950#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 941948#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 941946#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 941944#L515-30 assume !(1 == ~t5_pc~0); 941942#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 941940#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 941938#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 941936#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 941934#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 941932#L534-30 assume !(1 == ~t6_pc~0); 941930#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 941928#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 941926#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 941924#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 941922#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 941920#L553-30 assume !(1 == ~t7_pc~0); 941916#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 941914#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 941912#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 941910#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 941908#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 941906#L572-30 assume !(1 == ~t8_pc~0); 941904#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 941902#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 941900#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 941898#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 941896#L1127-32 assume !(1 == ~M_E~0); 941893#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 941892#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 941891#L964-3 assume !(1 == ~T3_E~0); 941890#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 941889#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 941888#L979-3 assume !(1 == ~T6_E~0); 941887#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 941886#L989-3 assume !(1 == ~T8_E~0); 941885#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 941884#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 941883#L1004-3 assume !(1 == ~E_2~0); 941882#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 941881#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 941880#L1019-3 assume !(1 == ~E_5~0); 941879#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 941878#L1029-3 assume !(1 == ~E_7~0); 941877#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 941876#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 941874#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 941863#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 941860#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 941856#L1324 assume !(0 == start_simulation_~tmp~3); 941853#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 941852#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 941843#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 941842#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 941841#L1279 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 941840#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 941839#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 941838#L1337 assume !(0 != start_simulation_~tmp___0~1); 924728#L1305-1 [2019-12-07 13:00:37,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:37,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 4 times [2019-12-07 13:00:37,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:37,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832350983] [2019-12-07 13:00:37,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:37,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:37,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:37,829 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:37,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:37,829 INFO L82 PathProgramCache]: Analyzing trace with hash 2079016181, now seen corresponding path program 1 times [2019-12-07 13:00:37,829 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:37,829 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120322090] [2019-12-07 13:00:37,830 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:37,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:37,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:37,872 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120322090] [2019-12-07 13:00:37,872 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:37,872 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:00:37,872 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239678600] [2019-12-07 13:00:37,872 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:37,872 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:37,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 13:00:37,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2019-12-07 13:00:37,873 INFO L87 Difference]: Start difference. First operand 41754 states and 58031 transitions. cyclomatic complexity: 16309 Second operand 8 states. [2019-12-07 13:00:38,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:38,255 INFO L93 Difference]: Finished difference Result 148138 states and 203471 transitions. [2019-12-07 13:00:38,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:00:38,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148138 states and 203471 transitions. [2019-12-07 13:00:38,674 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 146752 [2019-12-07 13:00:38,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148138 states to 148138 states and 203471 transitions. [2019-12-07 13:00:38,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148138 [2019-12-07 13:00:39,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148138 [2019-12-07 13:00:39,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148138 states and 203471 transitions. [2019-12-07 13:00:39,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:39,068 INFO L688 BuchiCegarLoop]: Abstraction has 148138 states and 203471 transitions. [2019-12-07 13:00:39,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148138 states and 203471 transitions. [2019-12-07 13:00:39,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148138 to 41946. [2019-12-07 13:00:39,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41946 states. [2019-12-07 13:00:39,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41946 states to 41946 states and 58223 transitions. [2019-12-07 13:00:39,792 INFO L711 BuchiCegarLoop]: Abstraction has 41946 states and 58223 transitions. [2019-12-07 13:00:39,792 INFO L591 BuchiCegarLoop]: Abstraction has 41946 states and 58223 transitions. [2019-12-07 13:00:39,792 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-12-07 13:00:39,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41946 states and 58223 transitions. [2019-12-07 13:00:39,859 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41520 [2019-12-07 13:00:39,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:39,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:39,860 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:39,861 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:39,861 INFO L794 eck$LassoCheckResult]: Stem: 1114567#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1114492#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1114493#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1114712#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1114072#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1114073#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1114812#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1114713#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1114451#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1114452#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1114906#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1114672#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1114348#L639-1 assume !(0 == ~M_E~0); 1114349#L856-1 assume !(0 == ~T1_E~0); 1114457#L861-1 assume !(0 == ~T2_E~0); 1114458#L866-1 assume !(0 == ~T3_E~0); 1114931#L871-1 assume !(0 == ~T4_E~0); 1114699#L876-1 assume !(0 == ~T5_E~0); 1114548#L881-1 assume !(0 == ~T6_E~0); 1114215#L886-1 assume !(0 == ~T7_E~0); 1114216#L891-1 assume !(0 == ~T8_E~0); 1114774#L896-1 assume !(0 == ~E_M~0); 1114516#L901-1 assume !(0 == ~E_1~0); 1114171#L906-1 assume !(0 == ~E_2~0); 1114172#L911-1 assume !(0 == ~E_3~0); 1114981#L916-1 assume !(0 == ~E_4~0); 1114613#L921-1 assume !(0 == ~E_5~0); 1114281#L926-1 assume !(0 == ~E_6~0); 1114282#L931-1 assume !(0 == ~E_7~0); 1115051#L936-1 assume !(0 == ~E_8~0); 1114852#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1114242#L420 assume !(1 == ~m_pc~0); 1114243#L420-2 is_master_triggered_~__retres1~0 := 0; 1114249#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1114919#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1114977#L1063 assume !(0 != activate_threads_~tmp~1); 1115118#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1114506#L439 assume !(1 == ~t1_pc~0); 1114507#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 1114510#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1115018#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1114969#L1071 assume !(0 != activate_threads_~tmp___0~0); 1114954#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1114680#L458 assume !(1 == ~t2_pc~0); 1114655#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 1114656#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1115111#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1114557#L1079 assume !(0 != activate_threads_~tmp___1~0); 1114558#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1114559#L477 assume !(1 == ~t3_pc~0); 1114801#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 1114141#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1114142#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1114233#L1087 assume !(0 != activate_threads_~tmp___2~0); 1115125#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1114951#L496 assume !(1 == ~t4_pc~0); 1114912#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 1114361#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1114264#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1114265#L1095 assume !(0 != activate_threads_~tmp___3~0); 1114863#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1114864#L515 assume !(1 == ~t5_pc~0); 1115120#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 1114703#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1114515#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1114479#L1103 assume !(0 != activate_threads_~tmp___4~0); 1114467#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1114200#L534 assume !(1 == ~t6_pc~0); 1114190#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 1114191#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1114674#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1114675#L1111 assume !(0 != activate_threads_~tmp___5~0); 1114992#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1114436#L553 assume !(1 == ~t7_pc~0); 1114169#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 1114441#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1114814#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1114649#L1119 assume !(0 != activate_threads_~tmp___6~0); 1114628#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1114593#L572 assume !(1 == ~t8_pc~0); 1114594#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 1114595#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1114948#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1114104#L1127 assume !(0 != activate_threads_~tmp___7~0); 1114105#L1127-2 assume !(1 == ~M_E~0); 1114106#L954-1 assume !(1 == ~T1_E~0); 1114928#L959-1 assume !(1 == ~T2_E~0); 1114697#L964-1 assume !(1 == ~T3_E~0); 1114542#L969-1 assume !(1 == ~T4_E~0); 1114211#L974-1 assume !(1 == ~T5_E~0); 1114212#L979-1 assume !(1 == ~T6_E~0); 1114771#L984-1 assume !(1 == ~T7_E~0); 1114520#L989-1 assume !(1 == ~T8_E~0); 1114374#L994-1 assume !(1 == ~E_M~0); 1114375#L999-1 assume !(1 == ~E_1~0); 1114985#L1004-1 assume !(1 == ~E_2~0); 1114634#L1009-1 assume !(1 == ~E_3~0); 1114291#L1014-1 assume !(1 == ~E_4~0); 1114292#L1019-1 assume !(1 == ~E_5~0); 1115055#L1024-1 assume !(1 == ~E_6~0); 1114847#L1029-1 assume !(1 == ~E_7~0); 1114599#L1034-1 assume !(1 == ~E_8~0); 1114600#L1305-1 [2019-12-07 13:00:39,861 INFO L796 eck$LassoCheckResult]: Loop: 1114600#L1305-1 assume !false; 1124692#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1124690#L831 assume !false; 1124689#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1124688#L652 assume !(0 == ~m_st~0); 1124683#L656 assume !(0 == ~t1_st~0); 1124684#L660 assume !(0 == ~t2_st~0); 1124687#L664 assume !(0 == ~t3_st~0); 1124681#L668 assume !(0 == ~t4_st~0); 1124682#L672 assume !(0 == ~t5_st~0); 1124686#L676 assume !(0 == ~t6_st~0); 1124679#L680 assume !(0 == ~t7_st~0); 1124680#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1124685#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1124673#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1124674#L714 assume !(0 != eval_~tmp~0); 1124912#L846 start_simulation_~kernel_st~0 := 2; 1124910#L592-1 start_simulation_~kernel_st~0 := 3; 1124908#L856-2 assume !(0 == ~M_E~0); 1124906#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1124904#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1124902#L866-3 assume !(0 == ~T3_E~0); 1124900#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1124898#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1124896#L881-3 assume !(0 == ~T6_E~0); 1124894#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1124892#L891-3 assume !(0 == ~T8_E~0); 1124890#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1124888#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1124886#L906-3 assume !(0 == ~E_2~0); 1124884#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1124882#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1124880#L921-3 assume !(0 == ~E_5~0); 1124878#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1124876#L931-3 assume !(0 == ~E_7~0); 1124874#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1124872#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1124870#L420-30 assume !(1 == ~m_pc~0); 1124867#L420-32 is_master_triggered_~__retres1~0 := 0; 1124864#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1124862#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1124860#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1124858#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1124856#L439-30 assume !(1 == ~t1_pc~0); 1124854#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 1124852#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1124850#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1124848#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1124846#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1124843#L458-30 assume !(1 == ~t2_pc~0); 1124840#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 1124838#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1124836#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1124834#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1124832#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1124830#L477-30 assume !(1 == ~t3_pc~0); 1124828#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 1124826#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1124824#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1124822#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1124820#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1124818#L496-30 assume 1 == ~t4_pc~0; 1124816#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1124812#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1124810#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1124808#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1124806#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1124804#L515-30 assume !(1 == ~t5_pc~0); 1124802#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 1124800#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1124798#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1124796#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 1124794#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1124792#L534-30 assume !(1 == ~t6_pc~0); 1124790#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 1124788#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1124786#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1124784#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1124782#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1124780#L553-30 assume !(1 == ~t7_pc~0); 1124776#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 1124774#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1124772#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1124770#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 1124768#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1124766#L572-30 assume !(1 == ~t8_pc~0); 1124764#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 1124762#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1124760#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1124758#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1124756#L1127-32 assume !(1 == ~M_E~0); 1124753#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1124752#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1124751#L964-3 assume !(1 == ~T3_E~0); 1124750#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1124749#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1124748#L979-3 assume !(1 == ~T6_E~0); 1124747#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1124746#L989-3 assume !(1 == ~T8_E~0); 1124745#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1124744#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1124743#L1004-3 assume !(1 == ~E_2~0); 1124742#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1124741#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124740#L1019-3 assume !(1 == ~E_5~0); 1124739#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1124738#L1029-3 assume !(1 == ~E_7~0); 1124737#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1124736#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1124734#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1124723#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1124721#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1124715#L1324 assume !(0 == start_simulation_~tmp~3); 1124713#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1124712#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1124703#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1124701#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1124699#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1124697#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 1124696#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1124695#L1337 assume !(0 != start_simulation_~tmp___0~1); 1114600#L1305-1 [2019-12-07 13:00:39,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:39,861 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 5 times [2019-12-07 13:00:39,861 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:39,862 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436330701] [2019-12-07 13:00:39,862 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:39,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:39,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:39,880 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:39,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:39,880 INFO L82 PathProgramCache]: Analyzing trace with hash 1624050518, now seen corresponding path program 1 times [2019-12-07 13:00:39,881 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:39,881 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647920096] [2019-12-07 13:00:39,881 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:39,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:39,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:39,919 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647920096] [2019-12-07 13:00:39,919 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:39,919 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:39,919 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560487774] [2019-12-07 13:00:39,920 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:39,920 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:39,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:39,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:39,920 INFO L87 Difference]: Start difference. First operand 41946 states and 58223 transitions. cyclomatic complexity: 16309 Second operand 5 states. [2019-12-07 13:00:40,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:40,228 INFO L93 Difference]: Finished difference Result 121159 states and 166888 transitions. [2019-12-07 13:00:40,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:40,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121159 states and 166888 transitions. [2019-12-07 13:00:40,593 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119952 [2019-12-07 13:00:40,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121159 states to 121159 states and 166888 transitions. [2019-12-07 13:00:40,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121159 [2019-12-07 13:00:40,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121159 [2019-12-07 13:00:40,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121159 states and 166888 transitions. [2019-12-07 13:00:40,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:40,930 INFO L688 BuchiCegarLoop]: Abstraction has 121159 states and 166888 transitions. [2019-12-07 13:00:40,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121159 states and 166888 transitions. [2019-12-07 13:00:41,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121159 to 43485. [2019-12-07 13:00:41,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43485 states. [2019-12-07 13:00:41,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43485 states to 43485 states and 59762 transitions. [2019-12-07 13:00:41,374 INFO L711 BuchiCegarLoop]: Abstraction has 43485 states and 59762 transitions. [2019-12-07 13:00:41,374 INFO L591 BuchiCegarLoop]: Abstraction has 43485 states and 59762 transitions. [2019-12-07 13:00:41,374 INFO L424 BuchiCegarLoop]: ======== Iteration 27============ [2019-12-07 13:00:41,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43485 states and 59762 transitions. [2019-12-07 13:00:41,459 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43056 [2019-12-07 13:00:41,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:41,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:41,460 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:41,460 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:41,460 INFO L794 eck$LassoCheckResult]: Stem: 1277727#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1277644#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1277645#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1277887#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1277190#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1277191#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1278000#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1277888#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1277587#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1277588#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1278080#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1277846#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1277468#L639-1 assume !(0 == ~M_E~0); 1277469#L856-1 assume !(0 == ~T1_E~0); 1277596#L861-1 assume !(0 == ~T2_E~0); 1277597#L866-1 assume !(0 == ~T3_E~0); 1278105#L871-1 assume !(0 == ~T4_E~0); 1277872#L876-1 assume !(0 == ~T5_E~0); 1277712#L881-1 assume !(0 == ~T6_E~0); 1277333#L886-1 assume !(0 == ~T7_E~0); 1277334#L891-1 assume !(0 == ~T8_E~0); 1277956#L896-1 assume !(0 == ~E_M~0); 1277672#L901-1 assume !(0 == ~E_1~0); 1277292#L906-1 assume !(0 == ~E_2~0); 1277293#L911-1 assume !(0 == ~E_3~0); 1278165#L916-1 assume !(0 == ~E_4~0); 1277784#L921-1 assume !(0 == ~E_5~0); 1277402#L926-1 assume !(0 == ~E_6~0); 1277403#L931-1 assume !(0 == ~E_7~0); 1278237#L936-1 assume !(0 == ~E_8~0); 1278040#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1277363#L420 assume !(1 == ~m_pc~0); 1277364#L420-2 is_master_triggered_~__retres1~0 := 0; 1277370#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1278089#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1278335#L1063 assume !(0 != activate_threads_~tmp~1); 1278336#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1277662#L439 assume !(1 == ~t1_pc~0); 1277663#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 1277666#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1278201#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1278145#L1071 assume !(0 != activate_threads_~tmp___0~0); 1278131#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1277854#L458 assume !(1 == ~t2_pc~0); 1277828#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 1277829#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1278319#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1277722#L1079 assume !(0 != activate_threads_~tmp___1~0); 1277723#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1277724#L477 assume !(1 == ~t3_pc~0); 1277986#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 1277258#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1277259#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1277352#L1087 assume !(0 != activate_threads_~tmp___2~0); 1278345#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1278128#L496 assume !(1 == ~t4_pc~0); 1278086#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 1277476#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1277385#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1277386#L1095 assume !(0 != activate_threads_~tmp___3~0); 1278050#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1278051#L515 assume !(1 == ~t5_pc~0); 1278338#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 1277876#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1277671#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1277634#L1103 assume !(0 != activate_threads_~tmp___4~0); 1277609#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1277318#L534 assume !(1 == ~t6_pc~0); 1277310#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 1277311#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1277848#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1277849#L1111 assume !(0 != activate_threads_~tmp___5~0); 1278179#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1277562#L553 assume !(1 == ~t7_pc~0); 1277290#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 1277570#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1278001#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1277822#L1119 assume !(0 != activate_threads_~tmp___6~0); 1277801#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1277762#L572 assume !(1 == ~t8_pc~0); 1277763#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 1277766#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1278125#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1277224#L1127 assume !(0 != activate_threads_~tmp___7~0); 1277225#L1127-2 assume !(1 == ~M_E~0); 1277226#L954-1 assume !(1 == ~T1_E~0); 1278101#L959-1 assume !(1 == ~T2_E~0); 1277870#L964-1 assume !(1 == ~T3_E~0); 1277702#L969-1 assume !(1 == ~T4_E~0); 1277329#L974-1 assume !(1 == ~T5_E~0); 1277330#L979-1 assume !(1 == ~T6_E~0); 1277949#L984-1 assume !(1 == ~T7_E~0); 1277676#L989-1 assume !(1 == ~T8_E~0); 1277494#L994-1 assume !(1 == ~E_M~0); 1277495#L999-1 assume !(1 == ~E_1~0); 1278169#L1004-1 assume !(1 == ~E_2~0); 1277807#L1009-1 assume !(1 == ~E_3~0); 1277410#L1014-1 assume !(1 == ~E_4~0); 1277411#L1019-1 assume !(1 == ~E_5~0); 1278240#L1024-1 assume !(1 == ~E_6~0); 1278036#L1029-1 assume !(1 == ~E_7~0); 1277771#L1034-1 assume !(1 == ~E_8~0); 1277772#L1305-1 [2019-12-07 13:00:41,460 INFO L796 eck$LassoCheckResult]: Loop: 1277772#L1305-1 assume !false; 1285536#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1285516#L831 assume !false; 1285515#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1285514#L652 assume !(0 == ~m_st~0); 1285510#L656 assume !(0 == ~t1_st~0); 1285511#L660 assume !(0 == ~t2_st~0); 1285513#L664 assume !(0 == ~t3_st~0); 1285508#L668 assume !(0 == ~t4_st~0); 1285509#L672 assume !(0 == ~t5_st~0); 1285512#L676 assume !(0 == ~t6_st~0); 1285507#L680 assume !(0 == ~t7_st~0); 1285506#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1285504#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1285017#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1285018#L714 assume !(0 != eval_~tmp~0); 1285501#L846 start_simulation_~kernel_st~0 := 2; 1285500#L592-1 start_simulation_~kernel_st~0 := 3; 1285499#L856-2 assume !(0 == ~M_E~0); 1285498#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1285497#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1285496#L866-3 assume !(0 == ~T3_E~0); 1285495#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1285494#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1285493#L881-3 assume !(0 == ~T6_E~0); 1285492#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1285491#L891-3 assume !(0 == ~T8_E~0); 1285490#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1285489#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1285488#L906-3 assume !(0 == ~E_2~0); 1285487#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1285486#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1285485#L921-3 assume !(0 == ~E_5~0); 1285484#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1285483#L931-3 assume !(0 == ~E_7~0); 1285482#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1285481#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1285480#L420-30 assume !(1 == ~m_pc~0); 1285479#L420-32 is_master_triggered_~__retres1~0 := 0; 1285477#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1285475#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1285473#L1063-30 assume !(0 != activate_threads_~tmp~1); 1285471#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1285470#L439-30 assume !(1 == ~t1_pc~0); 1285469#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 1285468#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1285467#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1285466#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1285465#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1285463#L458-30 assume !(1 == ~t2_pc~0); 1285462#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 1285461#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1285460#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1285459#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1285458#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1285457#L477-30 assume !(1 == ~t3_pc~0); 1285456#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 1285455#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1285454#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1285453#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1285452#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1285451#L496-30 assume 1 == ~t4_pc~0; 1285450#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1285448#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1285447#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1285446#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1285445#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1285444#L515-30 assume !(1 == ~t5_pc~0); 1285443#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 1285442#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1285441#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1285440#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 1285439#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1285438#L534-30 assume !(1 == ~t6_pc~0); 1285437#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 1285436#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1285435#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1285434#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1285433#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1285432#L553-30 assume !(1 == ~t7_pc~0); 1285430#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 1285429#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1285428#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1285427#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 1285426#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1285425#L572-30 assume !(1 == ~t8_pc~0); 1285424#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 1285423#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1285422#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1285421#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1285419#L1127-32 assume !(1 == ~M_E~0); 1285232#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1285416#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1285414#L964-3 assume !(1 == ~T3_E~0); 1285412#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1285410#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1285408#L979-3 assume !(1 == ~T6_E~0); 1285406#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1285404#L989-3 assume !(1 == ~T8_E~0); 1285402#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1285400#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1285398#L1004-3 assume !(1 == ~E_2~0); 1285396#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1285394#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1285392#L1019-3 assume !(1 == ~E_5~0); 1285390#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1285388#L1029-3 assume !(1 == ~E_7~0); 1285386#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1285384#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1285371#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1285362#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1285360#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1285357#L1324 assume !(0 == start_simulation_~tmp~3); 1285358#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1285756#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1285745#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1285590#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1285586#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1285581#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 1285580#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1285566#L1337 assume !(0 != start_simulation_~tmp___0~1); 1277772#L1305-1 [2019-12-07 13:00:41,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:41,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 6 times [2019-12-07 13:00:41,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:41,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186082496] [2019-12-07 13:00:41,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:41,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:41,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:41,481 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:41,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:41,481 INFO L82 PathProgramCache]: Analyzing trace with hash 481548052, now seen corresponding path program 1 times [2019-12-07 13:00:41,482 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:41,482 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288411011] [2019-12-07 13:00:41,482 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:41,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:41,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:41,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288411011] [2019-12-07 13:00:41,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:41,505 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:41,505 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948961450] [2019-12-07 13:00:41,506 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:41,506 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:41,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:00:41,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:00:41,506 INFO L87 Difference]: Start difference. First operand 43485 states and 59762 transitions. cyclomatic complexity: 16309 Second operand 3 states. [2019-12-07 13:00:41,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:41,647 INFO L93 Difference]: Finished difference Result 81741 states and 110770 transitions. [2019-12-07 13:00:41,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:00:41,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81741 states and 110770 transitions. [2019-12-07 13:00:41,872 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 80992 [2019-12-07 13:00:42,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81741 states to 81741 states and 110770 transitions. [2019-12-07 13:00:42,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81741 [2019-12-07 13:00:42,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81741 [2019-12-07 13:00:42,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81741 states and 110770 transitions. [2019-12-07 13:00:42,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:42,091 INFO L688 BuchiCegarLoop]: Abstraction has 81741 states and 110770 transitions. [2019-12-07 13:00:42,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81741 states and 110770 transitions. [2019-12-07 13:00:43,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81741 to 78253. [2019-12-07 13:00:43,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78253 states. [2019-12-07 13:00:43,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78253 states to 78253 states and 106290 transitions. [2019-12-07 13:00:43,457 INFO L711 BuchiCegarLoop]: Abstraction has 78253 states and 106290 transitions. [2019-12-07 13:00:43,457 INFO L591 BuchiCegarLoop]: Abstraction has 78253 states and 106290 transitions. [2019-12-07 13:00:43,457 INFO L424 BuchiCegarLoop]: ======== Iteration 28============ [2019-12-07 13:00:43,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78253 states and 106290 transitions. [2019-12-07 13:00:43,619 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77504 [2019-12-07 13:00:43,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:43,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:43,620 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:43,620 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:43,620 INFO L794 eck$LassoCheckResult]: Stem: 1402954#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1402873#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1402874#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1403124#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1402422#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1402423#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1403231#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1403125#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1402826#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1402827#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1403329#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1403083#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1402702#L639-1 assume !(0 == ~M_E~0); 1402703#L856-1 assume !(0 == ~T1_E~0); 1402835#L861-1 assume !(0 == ~T2_E~0); 1402836#L866-1 assume !(0 == ~T3_E~0); 1403355#L871-1 assume !(0 == ~T4_E~0); 1403110#L876-1 assume !(0 == ~T5_E~0); 1402935#L881-1 assume !(0 == ~T6_E~0); 1402571#L886-1 assume !(0 == ~T7_E~0); 1402572#L891-1 assume !(0 == ~T8_E~0); 1403188#L896-1 assume !(0 == ~E_M~0); 1402902#L901-1 assume !(0 == ~E_1~0); 1402526#L906-1 assume !(0 == ~E_2~0); 1402527#L911-1 assume !(0 == ~E_3~0); 1403419#L916-1 assume !(0 == ~E_4~0); 1403019#L921-1 assume !(0 == ~E_5~0); 1402637#L926-1 assume !(0 == ~E_6~0); 1402638#L931-1 assume !(0 == ~E_7~0); 1403499#L936-1 assume !(0 == ~E_8~0); 1403279#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1402599#L420 assume !(1 == ~m_pc~0); 1402600#L420-2 is_master_triggered_~__retres1~0 := 0; 1402606#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1403339#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1403412#L1063 assume !(0 != activate_threads_~tmp~1); 1403594#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1402890#L439 assume !(1 == ~t1_pc~0); 1402891#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 1402894#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1403458#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1403398#L1071 assume !(0 != activate_threads_~tmp___0~0); 1403382#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1403091#L458 assume !(1 == ~t2_pc~0); 1403066#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 1403067#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1403583#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1402944#L1079 assume !(0 != activate_threads_~tmp___1~0); 1402945#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1402946#L477 assume !(1 == ~t3_pc~0); 1403220#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 1402492#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1402493#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1402589#L1087 assume !(0 != activate_threads_~tmp___2~0); 1403605#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1403379#L496 assume !(1 == ~t4_pc~0); 1403336#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 1402711#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1402620#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1402621#L1095 assume !(0 != activate_threads_~tmp___3~0); 1403289#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1403290#L515 assume !(1 == ~t5_pc~0); 1403595#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 1403113#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1402901#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1402865#L1103 assume !(0 != activate_threads_~tmp___4~0); 1402847#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1402556#L534 assume !(1 == ~t6_pc~0); 1402546#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 1402547#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1403085#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1403086#L1111 assume !(0 != activate_threads_~tmp___5~0); 1403435#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1402803#L553 assume !(1 == ~t7_pc~0); 1402524#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 1402809#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1403232#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1403060#L1119 assume !(0 != activate_threads_~tmp___6~0); 1403036#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1402996#L572 assume !(1 == ~t8_pc~0); 1402997#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 1403000#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1403376#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1402458#L1127 assume !(0 != activate_threads_~tmp___7~0); 1402459#L1127-2 assume !(1 == ~M_E~0); 1402460#L954-1 assume !(1 == ~T1_E~0); 1403351#L959-1 assume !(1 == ~T2_E~0); 1403107#L964-1 assume !(1 == ~T3_E~0); 1402929#L969-1 assume !(1 == ~T4_E~0); 1402567#L974-1 assume !(1 == ~T5_E~0); 1402568#L979-1 assume !(1 == ~T6_E~0); 1403185#L984-1 assume !(1 == ~T7_E~0); 1402906#L989-1 assume !(1 == ~T8_E~0); 1402730#L994-1 assume !(1 == ~E_M~0); 1402731#L999-1 assume !(1 == ~E_1~0); 1403423#L1004-1 assume !(1 == ~E_2~0); 1403043#L1009-1 assume !(1 == ~E_3~0); 1402645#L1014-1 assume !(1 == ~E_4~0); 1402646#L1019-1 assume !(1 == ~E_5~0); 1403504#L1024-1 assume !(1 == ~E_6~0); 1403275#L1029-1 assume !(1 == ~E_7~0); 1403005#L1034-1 assume !(1 == ~E_8~0); 1403006#L1305-1 [2019-12-07 13:00:43,621 INFO L796 eck$LassoCheckResult]: Loop: 1403006#L1305-1 assume !false; 1418691#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1418689#L831 assume !false; 1418687#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1418685#L652 assume !(0 == ~m_st~0); 1417503#L656 assume !(0 == ~t1_st~0); 1417502#L660 assume !(0 == ~t2_st~0); 1417501#L664 assume !(0 == ~t3_st~0); 1417500#L668 assume !(0 == ~t4_st~0); 1417496#L672 assume !(0 == ~t5_st~0); 1417494#L676 assume !(0 == ~t6_st~0); 1417492#L680 assume !(0 == ~t7_st~0); 1417489#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1417487#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1417485#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1417482#L714 assume !(0 != eval_~tmp~0); 1417479#L846 start_simulation_~kernel_st~0 := 2; 1417477#L592-1 start_simulation_~kernel_st~0 := 3; 1417475#L856-2 assume !(0 == ~M_E~0); 1417473#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1417471#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1417469#L866-3 assume !(0 == ~T3_E~0); 1417466#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1417464#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1417462#L881-3 assume !(0 == ~T6_E~0); 1417460#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1417458#L891-3 assume !(0 == ~T8_E~0); 1417456#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1417455#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1417454#L906-3 assume !(0 == ~E_2~0); 1417453#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1417452#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1417451#L921-3 assume !(0 == ~E_5~0); 1417450#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1417449#L931-3 assume !(0 == ~E_7~0); 1417448#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1417447#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1417446#L420-30 assume 1 == ~m_pc~0; 1417443#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1417441#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1417440#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1417438#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1417437#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1417436#L439-30 assume !(1 == ~t1_pc~0); 1417435#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 1417434#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1417433#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1417432#L1071-30 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1417431#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1417428#L458-30 assume !(1 == ~t2_pc~0); 1417426#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 1417424#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1417422#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1417420#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1417418#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1417416#L477-30 assume !(1 == ~t3_pc~0); 1417414#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 1417412#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1417410#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1417408#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1417406#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1417404#L496-30 assume !(1 == ~t4_pc~0); 1417401#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 1417399#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1417397#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1417395#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1417393#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1417385#L515-30 assume !(1 == ~t5_pc~0); 1417383#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 1417381#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1417378#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1417377#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 1417375#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1417372#L534-30 assume !(1 == ~t6_pc~0); 1417370#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 1417368#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1417367#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1417366#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1417365#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1417363#L553-30 assume !(1 == ~t7_pc~0); 1417360#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 1417359#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1417358#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1417356#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 1417354#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1417351#L572-30 assume !(1 == ~t8_pc~0); 1417349#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 1417347#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1417344#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1417342#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1417340#L1127-32 assume !(1 == ~M_E~0); 1415917#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1417339#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1417337#L964-3 assume !(1 == ~T3_E~0); 1417335#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1417333#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1417331#L979-3 assume !(1 == ~T6_E~0); 1417329#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1417327#L989-3 assume !(1 == ~T8_E~0); 1417325#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1417323#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1417321#L1004-3 assume !(1 == ~E_2~0); 1417319#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1417317#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1417315#L1019-3 assume !(1 == ~E_5~0); 1417313#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1417311#L1029-3 assume !(1 == ~E_7~0); 1417309#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1417307#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1417304#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1417301#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1417299#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1417296#L1324 assume !(0 == start_simulation_~tmp~3); 1417297#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1418844#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1418842#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1418840#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1418838#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1418836#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 1418835#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1418834#L1337 assume !(0 != start_simulation_~tmp___0~1); 1403006#L1305-1 [2019-12-07 13:00:43,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:43,621 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 7 times [2019-12-07 13:00:43,621 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:43,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793519661] [2019-12-07 13:00:43,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:43,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:43,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:43,642 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:43,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:43,642 INFO L82 PathProgramCache]: Analyzing trace with hash 172472406, now seen corresponding path program 1 times [2019-12-07 13:00:43,643 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:43,643 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689708299] [2019-12-07 13:00:43,643 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:43,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:43,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:43,677 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689708299] [2019-12-07 13:00:43,677 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:43,677 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:43,677 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400273409] [2019-12-07 13:00:43,677 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:43,678 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:43,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:43,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:43,678 INFO L87 Difference]: Start difference. First operand 78253 states and 106290 transitions. cyclomatic complexity: 28069 Second operand 5 states. [2019-12-07 13:00:44,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:44,047 INFO L93 Difference]: Finished difference Result 151693 states and 205041 transitions. [2019-12-07 13:00:44,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:44,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151693 states and 205041 transitions. [2019-12-07 13:00:44,488 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 150432 [2019-12-07 13:00:44,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151693 states to 151693 states and 205041 transitions. [2019-12-07 13:00:44,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151693 [2019-12-07 13:00:44,839 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151693 [2019-12-07 13:00:44,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151693 states and 205041 transitions. [2019-12-07 13:00:44,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:44,893 INFO L688 BuchiCegarLoop]: Abstraction has 151693 states and 205041 transitions. [2019-12-07 13:00:44,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151693 states and 205041 transitions. [2019-12-07 13:00:45,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151693 to 79789. [2019-12-07 13:00:45,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79789 states. [2019-12-07 13:00:45,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79789 states to 79789 states and 107377 transitions. [2019-12-07 13:00:45,550 INFO L711 BuchiCegarLoop]: Abstraction has 79789 states and 107377 transitions. [2019-12-07 13:00:45,550 INFO L591 BuchiCegarLoop]: Abstraction has 79789 states and 107377 transitions. [2019-12-07 13:00:45,550 INFO L424 BuchiCegarLoop]: ======== Iteration 29============ [2019-12-07 13:00:45,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79789 states and 107377 transitions. [2019-12-07 13:00:45,715 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79040 [2019-12-07 13:00:45,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:45,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:45,716 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:45,716 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:45,716 INFO L794 eck$LassoCheckResult]: Stem: 1632897#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1632818#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1632819#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1633059#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1632382#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1632383#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1633162#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1633060#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1632768#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1632769#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1633236#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1633019#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1632652#L639-1 assume !(0 == ~M_E~0); 1632653#L856-1 assume !(0 == ~T1_E~0); 1632774#L861-1 assume !(0 == ~T2_E~0); 1632775#L866-1 assume !(0 == ~T3_E~0); 1633261#L871-1 assume !(0 == ~T4_E~0); 1633046#L876-1 assume !(0 == ~T5_E~0); 1632875#L881-1 assume !(0 == ~T6_E~0); 1632522#L886-1 assume !(0 == ~T7_E~0); 1632523#L891-1 assume !(0 == ~T8_E~0); 1633121#L896-1 assume !(0 == ~E_M~0); 1632844#L901-1 assume !(0 == ~E_1~0); 1632481#L906-1 assume !(0 == ~E_2~0); 1632482#L911-1 assume !(0 == ~E_3~0); 1633314#L916-1 assume !(0 == ~E_4~0); 1632962#L921-1 assume !(0 == ~E_5~0); 1632587#L926-1 assume !(0 == ~E_6~0); 1632588#L931-1 assume !(0 == ~E_7~0); 1633376#L936-1 assume !(0 == ~E_8~0); 1633202#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1632549#L420 assume !(1 == ~m_pc~0); 1632550#L420-2 is_master_triggered_~__retres1~0 := 0; 1632556#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1633247#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1633310#L1063 assume !(0 != activate_threads_~tmp~1); 1633482#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1632834#L439 assume !(1 == ~t1_pc~0); 1632835#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 1632838#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1633349#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1633300#L1071 assume !(0 != activate_threads_~tmp___0~0); 1633286#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1633027#L458 assume !(1 == ~t2_pc~0); 1633003#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 1633004#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1633469#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1632884#L1079 assume !(0 != activate_threads_~tmp___1~0); 1632885#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1632886#L477 assume !(1 == ~t3_pc~0); 1633150#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 1632450#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1632451#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1632540#L1087 assume !(0 != activate_threads_~tmp___2~0); 1633492#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1633283#L496 assume !(1 == ~t4_pc~0); 1633242#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 1632663#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1632570#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1632571#L1095 assume !(0 != activate_threads_~tmp___3~0); 1633208#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1633209#L515 assume !(1 == ~t5_pc~0); 1633485#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 1633050#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1632843#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1632806#L1103 assume !(0 != activate_threads_~tmp___4~0); 1632788#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1632507#L534 assume !(1 == ~t6_pc~0); 1632499#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 1632500#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1633021#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1633022#L1111 assume !(0 != activate_threads_~tmp___5~0); 1633325#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1632747#L553 assume !(1 == ~t7_pc~0); 1632479#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 1632754#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1633164#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1632997#L1119 assume !(0 != activate_threads_~tmp___6~0); 1632976#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1632934#L572 assume !(1 == ~t8_pc~0); 1632935#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 1632937#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1633280#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1632414#L1127 assume !(0 != activate_threads_~tmp___7~0); 1632415#L1127-2 assume !(1 == ~M_E~0); 1632416#L954-1 assume !(1 == ~T1_E~0); 1633259#L959-1 assume !(1 == ~T2_E~0); 1633044#L964-1 assume !(1 == ~T3_E~0); 1632868#L969-1 assume !(1 == ~T4_E~0); 1632518#L974-1 assume !(1 == ~T5_E~0); 1632519#L979-1 assume !(1 == ~T6_E~0); 1633117#L984-1 assume !(1 == ~T7_E~0); 1632848#L989-1 assume !(1 == ~T8_E~0); 1632677#L994-1 assume !(1 == ~E_M~0); 1632678#L999-1 assume !(1 == ~E_1~0); 1633318#L1004-1 assume !(1 == ~E_2~0); 1632982#L1009-1 assume !(1 == ~E_3~0); 1632597#L1014-1 assume !(1 == ~E_4~0); 1632598#L1019-1 assume !(1 == ~E_5~0); 1633381#L1024-1 assume !(1 == ~E_6~0); 1633198#L1029-1 assume !(1 == ~E_7~0); 1632946#L1034-1 assume !(1 == ~E_8~0); 1632947#L1305-1 [2019-12-07 13:00:45,716 INFO L796 eck$LassoCheckResult]: Loop: 1632947#L1305-1 assume !false; 1645632#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1645633#L831 assume !false; 1645122#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1645123#L652 assume !(0 == ~m_st~0); 1644647#L656 assume !(0 == ~t1_st~0); 1644645#L660 assume !(0 == ~t2_st~0); 1644643#L664 assume !(0 == ~t3_st~0); 1644641#L668 assume !(0 == ~t4_st~0); 1644640#L672 assume !(0 == ~t5_st~0); 1644638#L676 assume !(0 == ~t6_st~0); 1644636#L680 assume !(0 == ~t7_st~0); 1644633#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1644631#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1644629#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1644626#L714 assume !(0 != eval_~tmp~0); 1644625#L846 start_simulation_~kernel_st~0 := 2; 1644622#L592-1 start_simulation_~kernel_st~0 := 3; 1644620#L856-2 assume !(0 == ~M_E~0); 1644618#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1644616#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1644614#L866-3 assume !(0 == ~T3_E~0); 1644612#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1644610#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1644608#L881-3 assume !(0 == ~T6_E~0); 1644606#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1644604#L891-3 assume !(0 == ~T8_E~0); 1644602#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1644600#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1644598#L906-3 assume !(0 == ~E_2~0); 1644597#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1644596#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1644595#L921-3 assume !(0 == ~E_5~0); 1644593#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1644591#L931-3 assume !(0 == ~E_7~0); 1644589#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1644588#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1644586#L420-30 assume 1 == ~m_pc~0; 1644583#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1644581#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1644579#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1644577#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1644575#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1644572#L439-30 assume !(1 == ~t1_pc~0); 1644570#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 1644568#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1644566#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1644564#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 1644562#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1644558#L458-30 assume !(1 == ~t2_pc~0); 1644556#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 1644553#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1644551#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1644549#L1079-30 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1644547#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1644545#L477-30 assume !(1 == ~t3_pc~0); 1644542#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 1644540#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1644538#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1644537#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1644524#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1644517#L496-30 assume !(1 == ~t4_pc~0); 1644509#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 1644500#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1644458#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1642325#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1642316#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1642314#L515-30 assume !(1 == ~t5_pc~0); 1642312#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 1642309#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1642307#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1642305#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 1642303#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1642301#L534-30 assume !(1 == ~t6_pc~0); 1642299#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 1642298#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1642296#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1642294#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1642293#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1642291#L553-30 assume !(1 == ~t7_pc~0); 1642288#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 1642286#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1642284#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1642282#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 1642280#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1642277#L572-30 assume !(1 == ~t8_pc~0); 1642275#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 1642273#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1642271#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1642269#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1642267#L1127-32 assume !(1 == ~M_E~0); 1642109#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1642264#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1642262#L964-3 assume !(1 == ~T3_E~0); 1642260#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1642258#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1642256#L979-3 assume !(1 == ~T6_E~0); 1642254#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1642252#L989-3 assume !(1 == ~T8_E~0); 1642250#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1642248#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1642246#L1004-3 assume !(1 == ~E_2~0); 1642244#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1642242#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1642240#L1019-3 assume !(1 == ~E_5~0); 1642238#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1642236#L1029-3 assume !(1 == ~E_7~0); 1642234#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1642232#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1642229#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1642227#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1642224#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1642221#L1324 assume !(0 == start_simulation_~tmp~3); 1642222#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1645805#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1645806#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1645791#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1645792#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1645786#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 1645787#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1645777#L1337 assume !(0 != start_simulation_~tmp___0~1); 1632947#L1305-1 [2019-12-07 13:00:45,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:45,717 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 8 times [2019-12-07 13:00:45,717 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:45,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479836214] [2019-12-07 13:00:45,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:45,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:45,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:45,737 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:45,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:45,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1059695252, now seen corresponding path program 1 times [2019-12-07 13:00:45,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:45,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81039543] [2019-12-07 13:00:45,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:45,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:45,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:45,775 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81039543] [2019-12-07 13:00:45,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:45,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:45,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730189501] [2019-12-07 13:00:45,776 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:45,776 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:45,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:45,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:45,776 INFO L87 Difference]: Start difference. First operand 79789 states and 107377 transitions. cyclomatic complexity: 27620 Second operand 5 states. [2019-12-07 13:00:46,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:46,174 INFO L93 Difference]: Finished difference Result 104589 states and 141264 transitions. [2019-12-07 13:00:46,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:46,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104589 states and 141264 transitions. [2019-12-07 13:00:46,484 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103328 [2019-12-07 13:00:46,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104589 states to 104589 states and 141264 transitions. [2019-12-07 13:00:46,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104589 [2019-12-07 13:00:46,712 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104589 [2019-12-07 13:00:46,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104589 states and 141264 transitions. [2019-12-07 13:00:46,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:46,745 INFO L688 BuchiCegarLoop]: Abstraction has 104589 states and 141264 transitions. [2019-12-07 13:00:46,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104589 states and 141264 transitions. [2019-12-07 13:00:47,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104589 to 79981. [2019-12-07 13:00:47,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79981 states. [2019-12-07 13:00:47,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79981 states to 79981 states and 106672 transitions. [2019-12-07 13:00:47,287 INFO L711 BuchiCegarLoop]: Abstraction has 79981 states and 106672 transitions. [2019-12-07 13:00:47,287 INFO L591 BuchiCegarLoop]: Abstraction has 79981 states and 106672 transitions. [2019-12-07 13:00:47,288 INFO L424 BuchiCegarLoop]: ======== Iteration 30============ [2019-12-07 13:00:47,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79981 states and 106672 transitions. [2019-12-07 13:00:47,454 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79232 [2019-12-07 13:00:47,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:47,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:47,456 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:47,456 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:47,456 INFO L794 eck$LassoCheckResult]: Stem: 1817333#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1817246#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1817247#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1817506#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 1816774#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1816775#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1817639#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1817507#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1817194#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1817195#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1817731#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1817462#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1817061#L639-1 assume !(0 == ~M_E~0); 1817062#L856-1 assume !(0 == ~T1_E~0); 1817204#L861-1 assume !(0 == ~T2_E~0); 1817205#L866-1 assume !(0 == ~T3_E~0); 1817762#L871-1 assume !(0 == ~T4_E~0); 1817490#L876-1 assume !(0 == ~T5_E~0); 1817317#L881-1 assume !(0 == ~T6_E~0); 1816921#L886-1 assume !(0 == ~T7_E~0); 1816922#L891-1 assume !(0 == ~T8_E~0); 1817588#L896-1 assume !(0 == ~E_M~0); 1817278#L901-1 assume !(0 == ~E_1~0); 1816877#L906-1 assume !(0 == ~E_2~0); 1816878#L911-1 assume !(0 == ~E_3~0); 1817834#L916-1 assume !(0 == ~E_4~0); 1817400#L921-1 assume !(0 == ~E_5~0); 1816995#L926-1 assume !(0 == ~E_6~0); 1816996#L931-1 assume !(0 == ~E_7~0); 1817921#L936-1 assume !(0 == ~E_8~0); 1817690#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1816956#L420 assume !(1 == ~m_pc~0); 1816957#L420-2 is_master_triggered_~__retres1~0 := 0; 1816963#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1817741#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1817823#L1063 assume !(0 != activate_threads_~tmp~1); 1818036#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1817266#L439 assume !(1 == ~t1_pc~0); 1817267#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 1817271#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1817872#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1817807#L1071 assume !(0 != activate_threads_~tmp___0~0); 1817793#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1817470#L458 assume !(1 == ~t2_pc~0); 1817446#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 1817447#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1818017#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1817326#L1079 assume !(0 != activate_threads_~tmp___1~0); 1817327#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1817328#L477 assume !(1 == ~t3_pc~0); 1817622#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 1816842#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1816843#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1816945#L1087 assume !(0 != activate_threads_~tmp___2~0); 1818053#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1817790#L496 assume !(1 == ~t4_pc~0); 1817738#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 1817071#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1816978#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1816979#L1095 assume !(0 != activate_threads_~tmp___3~0); 1817699#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1817700#L515 assume !(1 == ~t5_pc~0); 1818040#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 1817495#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1817277#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1817235#L1103 assume !(0 != activate_threads_~tmp___4~0); 1817216#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1816906#L534 assume !(1 == ~t6_pc~0); 1816896#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 1816897#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1817464#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1817465#L1111 assume !(0 != activate_threads_~tmp___5~0); 1817849#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1817167#L553 assume !(1 == ~t7_pc~0); 1816873#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 1817175#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1817640#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1817440#L1119 assume !(0 != activate_threads_~tmp___6~0); 1817417#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1817375#L572 assume !(1 == ~t8_pc~0); 1817376#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 1817378#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1817787#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1816808#L1127 assume !(0 != activate_threads_~tmp___7~0); 1816809#L1127-2 assume !(1 == ~M_E~0); 1816810#L954-1 assume !(1 == ~T1_E~0); 1817756#L959-1 assume !(1 == ~T2_E~0); 1817488#L964-1 assume !(1 == ~T3_E~0); 1817309#L969-1 assume !(1 == ~T4_E~0); 1816917#L974-1 assume !(1 == ~T5_E~0); 1816918#L979-1 assume !(1 == ~T6_E~0); 1817583#L984-1 assume !(1 == ~T7_E~0); 1817282#L989-1 assume !(1 == ~T8_E~0); 1817092#L994-1 assume !(1 == ~E_M~0); 1817093#L999-1 assume !(1 == ~E_1~0); 1817838#L1004-1 assume !(1 == ~E_2~0); 1817424#L1009-1 assume !(1 == ~E_3~0); 1817004#L1014-1 assume !(1 == ~E_4~0); 1817005#L1019-1 assume !(1 == ~E_5~0); 1817928#L1024-1 assume !(1 == ~E_6~0); 1817685#L1029-1 assume !(1 == ~E_7~0); 1817385#L1034-1 assume !(1 == ~E_8~0); 1817386#L1305-1 [2019-12-07 13:00:47,456 INFO L796 eck$LassoCheckResult]: Loop: 1817386#L1305-1 assume !false; 1828603#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1828601#L831 assume !false; 1828600#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1828597#L652 assume !(0 == ~m_st~0); 1826573#L656 assume !(0 == ~t1_st~0); 1826571#L660 assume !(0 == ~t2_st~0); 1826569#L664 assume !(0 == ~t3_st~0); 1826567#L668 assume !(0 == ~t4_st~0); 1826565#L672 assume !(0 == ~t5_st~0); 1826563#L676 assume !(0 == ~t6_st~0); 1826561#L680 assume !(0 == ~t7_st~0); 1826558#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1826556#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1826553#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1826550#L714 assume !(0 != eval_~tmp~0); 1826548#L846 start_simulation_~kernel_st~0 := 2; 1826546#L592-1 start_simulation_~kernel_st~0 := 3; 1826544#L856-2 assume !(0 == ~M_E~0); 1826542#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1826540#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1826538#L866-3 assume !(0 == ~T3_E~0); 1826536#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1826534#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1826532#L881-3 assume !(0 == ~T6_E~0); 1826530#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1826529#L891-3 assume !(0 == ~T8_E~0); 1826527#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1826526#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1826523#L906-3 assume !(0 == ~E_2~0); 1826521#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1826519#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1826517#L921-3 assume !(0 == ~E_5~0); 1826516#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1826514#L931-3 assume !(0 == ~E_7~0); 1826512#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1826510#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1826508#L420-30 assume 1 == ~m_pc~0; 1826505#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1826503#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1826500#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1826497#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1826495#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1826492#L439-30 assume !(1 == ~t1_pc~0); 1826490#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 1826488#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1826486#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1826484#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 1826482#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1826478#L458-30 assume !(1 == ~t2_pc~0); 1826476#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 1826474#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1826472#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1826470#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 1826468#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1826466#L477-30 assume !(1 == ~t3_pc~0); 1826464#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 1826462#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1826460#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1826458#L1087-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1826456#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1826454#L496-30 assume !(1 == ~t4_pc~0); 1826451#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 1826449#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1826447#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1826444#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1826442#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1826440#L515-30 assume !(1 == ~t5_pc~0); 1826437#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 1826435#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1826433#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1826431#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 1826429#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1826427#L534-30 assume !(1 == ~t6_pc~0); 1826425#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 1826423#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1826422#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1826419#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1826417#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1826415#L553-30 assume !(1 == ~t7_pc~0); 1826412#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 1826410#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1826408#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1826406#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 1826403#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1826401#L572-30 assume !(1 == ~t8_pc~0); 1826399#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 1826397#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1826395#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1826393#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1826390#L1127-32 assume !(1 == ~M_E~0); 1825747#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1826387#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1826385#L964-3 assume !(1 == ~T3_E~0); 1826383#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1826381#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1826379#L979-3 assume !(1 == ~T6_E~0); 1826377#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1826375#L989-3 assume !(1 == ~T8_E~0); 1826373#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1826371#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1826369#L1004-3 assume !(1 == ~E_2~0); 1826367#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1826365#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1826363#L1019-3 assume !(1 == ~E_5~0); 1826361#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1826359#L1029-3 assume !(1 == ~E_7~0); 1826356#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1826354#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1826351#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1826349#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1826347#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1826344#L1324 assume !(0 == start_simulation_~tmp~3); 1826345#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1828774#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1828772#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1828770#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1828769#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1828765#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 1828763#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1828762#L1337 assume !(0 != start_simulation_~tmp___0~1); 1817386#L1305-1 [2019-12-07 13:00:47,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:47,456 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 9 times [2019-12-07 13:00:47,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:47,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775338841] [2019-12-07 13:00:47,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:47,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:47,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:47,483 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:47,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:47,483 INFO L82 PathProgramCache]: Analyzing trace with hash 2013635410, now seen corresponding path program 1 times [2019-12-07 13:00:47,483 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:47,483 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416464339] [2019-12-07 13:00:47,483 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:47,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:47,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:47,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416464339] [2019-12-07 13:00:47,523 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:47,523 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:47,523 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305670877] [2019-12-07 13:00:47,523 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:47,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:47,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:47,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:47,523 INFO L87 Difference]: Start difference. First operand 79981 states and 106672 transitions. cyclomatic complexity: 26723 Second operand 5 states. [2019-12-07 13:00:47,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:47,880 INFO L93 Difference]: Finished difference Result 147405 states and 196511 transitions. [2019-12-07 13:00:47,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:47,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147405 states and 196511 transitions. [2019-12-07 13:00:48,305 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 146144 [2019-12-07 13:00:48,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147405 states to 147405 states and 196511 transitions. [2019-12-07 13:00:48,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147405 [2019-12-07 13:00:48,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147405 [2019-12-07 13:00:48,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147405 states and 196511 transitions. [2019-12-07 13:00:48,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:48,709 INFO L688 BuchiCegarLoop]: Abstraction has 147405 states and 196511 transitions. [2019-12-07 13:00:48,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147405 states and 196511 transitions. [2019-12-07 13:00:49,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147405 to 81517. [2019-12-07 13:00:49,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81517 states. [2019-12-07 13:00:49,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81517 states to 81517 states and 107759 transitions. [2019-12-07 13:00:49,352 INFO L711 BuchiCegarLoop]: Abstraction has 81517 states and 107759 transitions. [2019-12-07 13:00:49,352 INFO L591 BuchiCegarLoop]: Abstraction has 81517 states and 107759 transitions. [2019-12-07 13:00:49,352 INFO L424 BuchiCegarLoop]: ======== Iteration 31============ [2019-12-07 13:00:49,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81517 states and 107759 transitions. [2019-12-07 13:00:49,532 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 80768 [2019-12-07 13:00:49,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:49,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:49,533 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:49,533 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:49,534 INFO L794 eck$LassoCheckResult]: Stem: 2044721#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2044629#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2044630#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2044891#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 2044174#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2044175#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2045007#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2044892#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2044577#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2044578#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2045098#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2044853#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2044461#L639-1 assume !(0 == ~M_E~0); 2044462#L856-1 assume !(0 == ~T1_E~0); 2044587#L861-1 assume !(0 == ~T2_E~0); 2044588#L866-1 assume !(0 == ~T3_E~0); 2045123#L871-1 assume !(0 == ~T4_E~0); 2044879#L876-1 assume !(0 == ~T5_E~0); 2044695#L881-1 assume !(0 == ~T6_E~0); 2044318#L886-1 assume !(0 == ~T7_E~0); 2044319#L891-1 assume !(0 == ~T8_E~0); 2044959#L896-1 assume !(0 == ~E_M~0); 2044657#L901-1 assume !(0 == ~E_1~0); 2044273#L906-1 assume !(0 == ~E_2~0); 2044274#L911-1 assume !(0 == ~E_3~0); 2045178#L916-1 assume !(0 == ~E_4~0); 2044791#L921-1 assume !(0 == ~E_5~0); 2044392#L926-1 assume !(0 == ~E_6~0); 2044393#L931-1 assume !(0 == ~E_7~0); 2045249#L936-1 assume !(0 == ~E_8~0); 2045047#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2044353#L420 assume !(1 == ~m_pc~0); 2044354#L420-2 is_master_triggered_~__retres1~0 := 0; 2044360#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2045108#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2045174#L1063 assume !(0 != activate_threads_~tmp~1); 2045329#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2044647#L439 assume !(1 == ~t1_pc~0); 2044648#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 2044651#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2045217#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2045164#L1071 assume !(0 != activate_threads_~tmp___0~0); 2045148#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2044861#L458 assume !(1 == ~t2_pc~0); 2044837#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 2044838#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2045319#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2044709#L1079 assume !(0 != activate_threads_~tmp___1~0); 2044710#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2044712#L477 assume !(1 == ~t3_pc~0); 2044992#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 2044240#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2044241#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2044340#L1087 assume !(0 != activate_threads_~tmp___2~0); 2045340#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2045145#L496 assume !(1 == ~t4_pc~0); 2045104#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 2044471#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2044375#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2044376#L1095 assume !(0 != activate_threads_~tmp___3~0); 2045059#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2045060#L515 assume !(1 == ~t5_pc~0); 2045330#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 2044882#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2044656#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2044620#L1103 assume !(0 != activate_threads_~tmp___4~0); 2044599#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2044303#L534 assume !(1 == ~t6_pc~0); 2044293#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 2044294#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2044855#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2044856#L1111 assume !(0 != activate_threads_~tmp___5~0); 2045193#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2044557#L553 assume !(1 == ~t7_pc~0); 2044271#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 2044563#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2045008#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2044830#L1119 assume !(0 != activate_threads_~tmp___6~0); 2044808#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2044765#L572 assume !(1 == ~t8_pc~0); 2044766#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 2044769#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2045142#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2044206#L1127 assume !(0 != activate_threads_~tmp___7~0); 2044207#L1127-2 assume !(1 == ~M_E~0); 2044208#L954-1 assume !(1 == ~T1_E~0); 2045120#L959-1 assume !(1 == ~T2_E~0); 2044877#L964-1 assume !(1 == ~T3_E~0); 2044685#L969-1 assume !(1 == ~T4_E~0); 2044314#L974-1 assume !(1 == ~T5_E~0); 2044315#L979-1 assume !(1 == ~T6_E~0); 2044956#L984-1 assume !(1 == ~T7_E~0); 2044661#L989-1 assume !(1 == ~T8_E~0); 2044489#L994-1 assume !(1 == ~E_M~0); 2044490#L999-1 assume !(1 == ~E_1~0); 2045182#L1004-1 assume !(1 == ~E_2~0); 2044814#L1009-1 assume !(1 == ~E_3~0); 2044402#L1014-1 assume !(1 == ~E_4~0); 2044403#L1019-1 assume !(1 == ~E_5~0); 2045256#L1024-1 assume !(1 == ~E_6~0); 2045043#L1029-1 assume !(1 == ~E_7~0); 2044778#L1034-1 assume !(1 == ~E_8~0); 2044779#L1305-1 [2019-12-07 13:00:49,534 INFO L796 eck$LassoCheckResult]: Loop: 2044779#L1305-1 assume !false; 2051517#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2051515#L831 assume !false; 2051513#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2051510#L652 assume !(0 == ~m_st~0); 2051511#L656 assume !(0 == ~t1_st~0); 2055243#L660 assume !(0 == ~t2_st~0); 2055237#L664 assume !(0 == ~t3_st~0); 2055232#L668 assume !(0 == ~t4_st~0); 2055227#L672 assume !(0 == ~t5_st~0); 2055222#L676 assume !(0 == ~t6_st~0); 2055217#L680 assume !(0 == ~t7_st~0); 2055210#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2055204#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2055199#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2055194#L714 assume !(0 != eval_~tmp~0); 2055189#L846 start_simulation_~kernel_st~0 := 2; 2055184#L592-1 start_simulation_~kernel_st~0 := 3; 2055178#L856-2 assume !(0 == ~M_E~0); 2055173#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2055168#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2055163#L866-3 assume !(0 == ~T3_E~0); 2055157#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2055152#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2055147#L881-3 assume !(0 == ~T6_E~0); 2055088#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2055087#L891-3 assume !(0 == ~T8_E~0); 2055086#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2055085#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2055084#L906-3 assume !(0 == ~E_2~0); 2055082#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2055080#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2055078#L921-3 assume !(0 == ~E_5~0); 2055077#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2055075#L931-3 assume !(0 == ~E_7~0); 2055073#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2055071#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2055069#L420-30 assume 1 == ~m_pc~0; 2055066#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2055064#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2055061#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2055058#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2055056#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2055054#L439-30 assume !(1 == ~t1_pc~0); 2055052#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 2055050#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2055048#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2055046#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 2055044#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2055040#L458-30 assume !(1 == ~t2_pc~0); 2055038#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 2055036#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2055033#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2055031#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 2055012#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2055006#L477-30 assume !(1 == ~t3_pc~0); 2055000#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 2054993#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2054989#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2054986#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 2054985#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2054984#L496-30 assume 1 == ~t4_pc~0; 2054983#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2054981#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2054980#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2054978#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2054976#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2054974#L515-30 assume !(1 == ~t5_pc~0); 2054973#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 2054971#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2054969#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2054967#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 2054965#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2054963#L534-30 assume !(1 == ~t6_pc~0); 2054961#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 2054960#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2054957#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2054955#L1111-30 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2054953#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2054950#L553-30 assume !(1 == ~t7_pc~0); 2054947#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 2054945#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2054943#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2054931#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 2054924#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2054917#L572-30 assume !(1 == ~t8_pc~0); 2054910#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 2054904#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2054898#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2054892#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2054886#L1127-32 assume !(1 == ~M_E~0); 2052449#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2054876#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2054870#L964-3 assume !(1 == ~T3_E~0); 2054865#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2054860#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2054854#L979-3 assume !(1 == ~T6_E~0); 2054848#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2053653#L989-3 assume !(1 == ~T8_E~0); 2053646#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2053641#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2053635#L1004-3 assume !(1 == ~E_2~0); 2053628#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2052254#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2052251#L1019-3 assume !(1 == ~E_5~0); 2052249#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2052247#L1029-3 assume !(1 == ~E_7~0); 2052245#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2052243#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2052240#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2052238#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2052236#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2052233#L1324 assume !(0 == start_simulation_~tmp~3); 2052230#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2052227#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2052225#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2052222#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2052220#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2052218#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 2052216#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2052214#L1337 assume !(0 != start_simulation_~tmp___0~1); 2044779#L1305-1 [2019-12-07 13:00:49,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:49,534 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 10 times [2019-12-07 13:00:49,534 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:49,534 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424512742] [2019-12-07 13:00:49,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:49,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:49,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:49,553 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:49,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:49,553 INFO L82 PathProgramCache]: Analyzing trace with hash 304424561, now seen corresponding path program 1 times [2019-12-07 13:00:49,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:49,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627097734] [2019-12-07 13:00:49,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:49,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:49,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:49,592 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627097734] [2019-12-07 13:00:49,593 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:49,593 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:49,593 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167494842] [2019-12-07 13:00:49,593 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:49,593 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:49,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:49,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:49,593 INFO L87 Difference]: Start difference. First operand 81517 states and 107759 transitions. cyclomatic complexity: 26274 Second operand 5 states. [2019-12-07 13:00:50,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:50,076 INFO L93 Difference]: Finished difference Result 139677 states and 184846 transitions. [2019-12-07 13:00:50,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:50,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139677 states and 184846 transitions. [2019-12-07 13:00:50,462 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 138416 [2019-12-07 13:00:50,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139677 states to 139677 states and 184846 transitions. [2019-12-07 13:00:50,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139677 [2019-12-07 13:00:50,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139677 [2019-12-07 13:00:50,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139677 states and 184846 transitions. [2019-12-07 13:00:50,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:50,779 INFO L688 BuchiCegarLoop]: Abstraction has 139677 states and 184846 transitions. [2019-12-07 13:00:50,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139677 states and 184846 transitions. [2019-12-07 13:00:51,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139677 to 83053. [2019-12-07 13:00:51,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83053 states. [2019-12-07 13:00:51,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83053 states to 83053 states and 108846 transitions. [2019-12-07 13:00:51,442 INFO L711 BuchiCegarLoop]: Abstraction has 83053 states and 108846 transitions. [2019-12-07 13:00:51,442 INFO L591 BuchiCegarLoop]: Abstraction has 83053 states and 108846 transitions. [2019-12-07 13:00:51,442 INFO L424 BuchiCegarLoop]: ======== Iteration 32============ [2019-12-07 13:00:51,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83053 states and 108846 transitions. [2019-12-07 13:00:51,612 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 82304 [2019-12-07 13:00:51,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:51,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:51,613 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:51,613 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:51,614 INFO L794 eck$LassoCheckResult]: Stem: 2265908#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2265822#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2265823#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2266076#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 2265382#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2265383#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2266182#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2266077#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2265778#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2265779#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2266275#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2266036#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2265660#L639-1 assume !(0 == ~M_E~0); 2265661#L856-1 assume !(0 == ~T1_E~0); 2265786#L861-1 assume !(0 == ~T2_E~0); 2265787#L866-1 assume !(0 == ~T3_E~0); 2266302#L871-1 assume !(0 == ~T4_E~0); 2266063#L876-1 assume !(0 == ~T5_E~0); 2265884#L881-1 assume !(0 == ~T6_E~0); 2265526#L886-1 assume !(0 == ~T7_E~0); 2265527#L891-1 assume !(0 == ~T8_E~0); 2266142#L896-1 assume !(0 == ~E_M~0); 2265852#L901-1 assume !(0 == ~E_1~0); 2265482#L906-1 assume !(0 == ~E_2~0); 2265483#L911-1 assume !(0 == ~E_3~0); 2266356#L916-1 assume !(0 == ~E_4~0); 2265975#L921-1 assume !(0 == ~E_5~0); 2265592#L926-1 assume !(0 == ~E_6~0); 2265593#L931-1 assume !(0 == ~E_7~0); 2266422#L936-1 assume !(0 == ~E_8~0); 2266228#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2265554#L420 assume !(1 == ~m_pc~0); 2265555#L420-2 is_master_triggered_~__retres1~0 := 0; 2265561#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2266284#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2266353#L1063 assume !(0 != activate_threads_~tmp~1); 2266515#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2265842#L439 assume !(1 == ~t1_pc~0); 2265843#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 2265846#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2266391#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2266342#L1071 assume !(0 != activate_threads_~tmp___0~0); 2266328#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2266044#L458 assume !(1 == ~t2_pc~0); 2266020#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 2266021#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2266494#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2265897#L1079 assume !(0 != activate_threads_~tmp___1~0); 2265898#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2265900#L477 assume !(1 == ~t3_pc~0); 2266171#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 2265449#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2265450#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2265544#L1087 assume !(0 != activate_threads_~tmp___2~0); 2266531#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2266325#L496 assume !(1 == ~t4_pc~0); 2266281#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 2265668#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2265575#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2265576#L1095 assume !(0 != activate_threads_~tmp___3~0); 2266238#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2266239#L515 assume !(1 == ~t5_pc~0); 2266519#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 2266066#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2265851#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2265814#L1103 assume !(0 != activate_threads_~tmp___4~0); 2265798#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2265511#L534 assume !(1 == ~t6_pc~0); 2265501#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 2265502#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2266038#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2266039#L1111 assume !(0 != activate_threads_~tmp___5~0); 2266368#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2265756#L553 assume !(1 == ~t7_pc~0); 2265480#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 2265762#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2266183#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2266014#L1119 assume !(0 != activate_threads_~tmp___6~0); 2265992#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2265949#L572 assume !(1 == ~t8_pc~0); 2265950#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 2265953#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2266322#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2265415#L1127 assume !(0 != activate_threads_~tmp___7~0); 2265416#L1127-2 assume !(1 == ~M_E~0); 2265417#L954-1 assume !(1 == ~T1_E~0); 2266297#L959-1 assume !(1 == ~T2_E~0); 2266061#L964-1 assume !(1 == ~T3_E~0); 2265877#L969-1 assume !(1 == ~T4_E~0); 2265522#L974-1 assume !(1 == ~T5_E~0); 2265523#L979-1 assume !(1 == ~T6_E~0); 2266137#L984-1 assume !(1 == ~T7_E~0); 2265856#L989-1 assume !(1 == ~T8_E~0); 2265686#L994-1 assume !(1 == ~E_M~0); 2265687#L999-1 assume !(1 == ~E_1~0); 2266360#L1004-1 assume !(1 == ~E_2~0); 2265998#L1009-1 assume !(1 == ~E_3~0); 2265600#L1014-1 assume !(1 == ~E_4~0); 2265601#L1019-1 assume !(1 == ~E_5~0); 2266427#L1024-1 assume !(1 == ~E_6~0); 2266224#L1029-1 assume !(1 == ~E_7~0); 2265961#L1034-1 assume !(1 == ~E_8~0); 2265962#L1305-1 [2019-12-07 13:00:51,614 INFO L796 eck$LassoCheckResult]: Loop: 2265962#L1305-1 assume !false; 2271937#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2271935#L831 assume !false; 2271931#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2271928#L652 assume !(0 == ~m_st~0); 2271929#L656 assume !(0 == ~t1_st~0); 2273130#L660 assume !(0 == ~t2_st~0); 2273128#L664 assume !(0 == ~t3_st~0); 2273126#L668 assume !(0 == ~t4_st~0); 2273124#L672 assume !(0 == ~t5_st~0); 2273122#L676 assume !(0 == ~t6_st~0); 2273120#L680 assume !(0 == ~t7_st~0); 2273116#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2273114#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2273112#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2273109#L714 assume !(0 != eval_~tmp~0); 2273107#L846 start_simulation_~kernel_st~0 := 2; 2273105#L592-1 start_simulation_~kernel_st~0 := 3; 2273103#L856-2 assume !(0 == ~M_E~0); 2273101#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2273099#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2273097#L866-3 assume !(0 == ~T3_E~0); 2273095#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2273094#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2273091#L881-3 assume !(0 == ~T6_E~0); 2273089#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2273087#L891-3 assume !(0 == ~T8_E~0); 2273085#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2273083#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2273081#L906-3 assume !(0 == ~E_2~0); 2273079#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2273077#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2273075#L921-3 assume !(0 == ~E_5~0); 2273073#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2273071#L931-3 assume !(0 == ~E_7~0); 2273069#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2273067#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2273064#L420-30 assume 1 == ~m_pc~0; 2273061#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2273059#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2273057#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2273054#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2273052#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2273050#L439-30 assume !(1 == ~t1_pc~0); 2273048#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 2273046#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2273044#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2273042#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 2273040#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2273036#L458-30 assume !(1 == ~t2_pc~0); 2273034#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 2273032#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2273030#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2273027#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 2273025#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2273023#L477-30 assume !(1 == ~t3_pc~0); 2273021#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 2273019#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2273017#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2273015#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 2273013#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2273011#L496-30 assume !(1 == ~t4_pc~0); 2273008#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 2273006#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2273005#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2273004#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2273002#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2272999#L515-30 assume !(1 == ~t5_pc~0); 2272997#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 2272995#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2272994#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2272993#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 2272991#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2272990#L534-30 assume !(1 == ~t6_pc~0); 2272989#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 2272988#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2272987#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2272983#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 2272981#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2272979#L553-30 assume !(1 == ~t7_pc~0); 2272976#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 2272972#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2272970#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2272968#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 2272966#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2272964#L572-30 assume !(1 == ~t8_pc~0); 2272962#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 2272960#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2272958#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2272957#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2272954#L1127-32 assume !(1 == ~M_E~0); 2272950#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2272948#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2272946#L964-3 assume !(1 == ~T3_E~0); 2272944#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2272942#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2272940#L979-3 assume !(1 == ~T6_E~0); 2272938#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2272936#L989-3 assume !(1 == ~T8_E~0); 2272934#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2272932#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2272930#L1004-3 assume !(1 == ~E_2~0); 2272928#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2272925#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2272923#L1019-3 assume !(1 == ~E_5~0); 2272921#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2272919#L1029-3 assume !(1 == ~E_7~0); 2272917#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2272915#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2272912#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2272910#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2272908#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2272905#L1324 assume !(0 == start_simulation_~tmp~3); 2272902#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2272899#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2272897#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2272895#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2272893#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2272891#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 2272889#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2272886#L1337 assume !(0 != start_simulation_~tmp___0~1); 2265962#L1305-1 [2019-12-07 13:00:51,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:51,614 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 11 times [2019-12-07 13:00:51,614 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:51,614 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984541906] [2019-12-07 13:00:51,614 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:51,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:51,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:51,631 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:51,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:51,632 INFO L82 PathProgramCache]: Analyzing trace with hash 643519822, now seen corresponding path program 1 times [2019-12-07 13:00:51,632 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:51,632 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953088853] [2019-12-07 13:00:51,632 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:51,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:51,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:51,669 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953088853] [2019-12-07 13:00:51,669 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:51,669 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:51,669 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452802539] [2019-12-07 13:00:51,669 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:51,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:51,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:51,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:51,670 INFO L87 Difference]: Start difference. First operand 83053 states and 108846 transitions. cyclomatic complexity: 25825 Second operand 5 states. [2019-12-07 13:00:52,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:52,129 INFO L93 Difference]: Finished difference Result 208838 states and 273571 transitions. [2019-12-07 13:00:52,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:52,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208838 states and 273571 transitions. [2019-12-07 13:00:52,837 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206720 [2019-12-07 13:00:53,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208838 states to 208838 states and 273571 transitions. [2019-12-07 13:00:53,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 208838 [2019-12-07 13:00:53,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 208838 [2019-12-07 13:00:53,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208838 states and 273571 transitions. [2019-12-07 13:00:53,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:53,442 INFO L688 BuchiCegarLoop]: Abstraction has 208838 states and 273571 transitions. [2019-12-07 13:00:53,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208838 states and 273571 transitions. [2019-12-07 13:00:54,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208838 to 85936. [2019-12-07 13:00:54,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85936 states. [2019-12-07 13:00:54,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85936 states to 85936 states and 111729 transitions. [2019-12-07 13:00:54,503 INFO L711 BuchiCegarLoop]: Abstraction has 85936 states and 111729 transitions. [2019-12-07 13:00:54,504 INFO L591 BuchiCegarLoop]: Abstraction has 85936 states and 111729 transitions. [2019-12-07 13:00:54,504 INFO L424 BuchiCegarLoop]: ======== Iteration 33============ [2019-12-07 13:00:54,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85936 states and 111729 transitions. [2019-12-07 13:00:54,673 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 85184 [2019-12-07 13:00:54,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:54,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:54,674 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:54,674 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:54,675 INFO L794 eck$LassoCheckResult]: Stem: 2557810#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2557733#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2557734#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2557970#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 2557287#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2557288#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2558073#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2557971#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2557681#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2557682#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2558173#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2557931#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2557563#L639-1 assume !(0 == ~M_E~0); 2557564#L856-1 assume !(0 == ~T1_E~0); 2557691#L861-1 assume !(0 == ~T2_E~0); 2557692#L866-1 assume !(0 == ~T3_E~0); 2558204#L871-1 assume !(0 == ~T4_E~0); 2557957#L876-1 assume !(0 == ~T5_E~0); 2557792#L881-1 assume !(0 == ~T6_E~0); 2557429#L886-1 assume !(0 == ~T7_E~0); 2557430#L891-1 assume !(0 == ~T8_E~0); 2558031#L896-1 assume !(0 == ~E_M~0); 2557760#L901-1 assume !(0 == ~E_1~0); 2557386#L906-1 assume !(0 == ~E_2~0); 2557387#L911-1 assume !(0 == ~E_3~0); 2558262#L916-1 assume !(0 == ~E_4~0); 2557870#L921-1 assume !(0 == ~E_5~0); 2557496#L926-1 assume !(0 == ~E_6~0); 2557497#L931-1 assume !(0 == ~E_7~0); 2558349#L936-1 assume !(0 == ~E_8~0); 2558118#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2557457#L420 assume !(1 == ~m_pc~0); 2557458#L420-2 is_master_triggered_~__retres1~0 := 0; 2557464#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2558455#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2558436#L1063 assume !(0 != activate_threads_~tmp~1); 2558437#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2557750#L439 assume !(1 == ~t1_pc~0); 2557751#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 2557754#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2558301#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2558248#L1071 assume !(0 != activate_threads_~tmp___0~0); 2558234#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2557939#L458 assume !(1 == ~t2_pc~0); 2557915#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 2557916#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2558421#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2557801#L1079 assume !(0 != activate_threads_~tmp___1~0); 2557802#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2557803#L477 assume !(1 == ~t3_pc~0); 2558061#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 2557353#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2557354#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2557447#L1087 assume !(0 != activate_threads_~tmp___2~0); 2558450#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2558231#L496 assume !(1 == ~t4_pc~0); 2558180#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 2557573#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2557574#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2558129#L1095 assume !(0 != activate_threads_~tmp___3~0); 2558130#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2558131#L515 assume !(1 == ~t5_pc~0); 2558438#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 2557961#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2557759#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2557724#L1103 assume !(0 != activate_threads_~tmp___4~0); 2557704#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2557414#L534 assume !(1 == ~t6_pc~0); 2557405#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 2557406#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2557933#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2557934#L1111 assume !(0 != activate_threads_~tmp___5~0); 2558280#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2557661#L553 assume !(1 == ~t7_pc~0); 2557384#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 2557667#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2558074#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2557909#L1119 assume !(0 != activate_threads_~tmp___6~0); 2557888#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2557845#L572 assume !(1 == ~t8_pc~0); 2557846#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 2557849#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2558228#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2557319#L1127 assume !(0 != activate_threads_~tmp___7~0); 2557320#L1127-2 assume !(1 == ~M_E~0); 2557321#L954-1 assume !(1 == ~T1_E~0); 2558201#L959-1 assume !(1 == ~T2_E~0); 2557955#L964-1 assume !(1 == ~T3_E~0); 2557785#L969-1 assume !(1 == ~T4_E~0); 2557425#L974-1 assume !(1 == ~T5_E~0); 2557426#L979-1 assume !(1 == ~T6_E~0); 2558028#L984-1 assume !(1 == ~T7_E~0); 2557764#L989-1 assume !(1 == ~T8_E~0); 2557592#L994-1 assume !(1 == ~E_M~0); 2557593#L999-1 assume !(1 == ~E_1~0); 2558266#L1004-1 assume !(1 == ~E_2~0); 2557894#L1009-1 assume !(1 == ~E_3~0); 2557504#L1014-1 assume !(1 == ~E_4~0); 2557505#L1019-1 assume !(1 == ~E_5~0); 2558353#L1024-1 assume !(1 == ~E_6~0); 2558114#L1029-1 assume !(1 == ~E_7~0); 2557857#L1034-1 assume !(1 == ~E_8~0); 2557858#L1305-1 [2019-12-07 13:00:54,675 INFO L796 eck$LassoCheckResult]: Loop: 2557858#L1305-1 assume !false; 2568119#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2568118#L831 assume !false; 2568117#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2568115#L652 assume !(0 == ~m_st~0); 2568116#L656 assume !(0 == ~t1_st~0); 2570824#L660 assume !(0 == ~t2_st~0); 2570821#L664 assume !(0 == ~t3_st~0); 2570819#L668 assume !(0 == ~t4_st~0); 2570817#L672 assume !(0 == ~t5_st~0); 2570815#L676 assume !(0 == ~t6_st~0); 2570813#L680 assume !(0 == ~t7_st~0); 2570810#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2570808#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2570806#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2570804#L714 assume !(0 != eval_~tmp~0); 2570802#L846 start_simulation_~kernel_st~0 := 2; 2570800#L592-1 start_simulation_~kernel_st~0 := 3; 2570799#L856-2 assume !(0 == ~M_E~0); 2570798#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2570794#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2570792#L866-3 assume !(0 == ~T3_E~0); 2570787#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2570785#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2570782#L881-3 assume !(0 == ~T6_E~0); 2570781#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2570780#L891-3 assume !(0 == ~T8_E~0); 2570778#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2570777#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2570776#L906-3 assume !(0 == ~E_2~0); 2570775#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2570774#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2570773#L921-3 assume !(0 == ~E_5~0); 2570772#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2570770#L931-3 assume !(0 == ~E_7~0); 2570769#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2570768#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2570767#L420-30 assume 1 == ~m_pc~0; 2570765#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2570764#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2570763#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2570761#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2570760#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2570759#L439-30 assume !(1 == ~t1_pc~0); 2570758#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 2570757#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2570756#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2570755#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 2570754#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2570752#L458-30 assume !(1 == ~t2_pc~0); 2570751#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 2570750#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2570749#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2570748#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 2570747#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2570746#L477-30 assume !(1 == ~t3_pc~0); 2570745#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 2570744#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2570743#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2570742#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 2570741#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2570740#L496-30 assume !(1 == ~t4_pc~0); 2570739#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 2570737#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2570735#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2570733#L1095-30 assume !(0 != activate_threads_~tmp___3~0); 2570730#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2570727#L515-30 assume !(1 == ~t5_pc~0); 2570725#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 2570723#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2570721#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2570719#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 2570717#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2570715#L534-30 assume !(1 == ~t6_pc~0); 2570713#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 2570711#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2570709#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2570707#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 2570705#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2570703#L553-30 assume !(1 == ~t7_pc~0); 2570700#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 2570698#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2570696#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2570694#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 2570693#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2570692#L572-30 assume !(1 == ~t8_pc~0); 2570691#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 2570690#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2570689#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2570688#L1127-30 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2570687#L1127-32 assume !(1 == ~M_E~0); 2568229#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2568228#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2568187#L964-3 assume !(1 == ~T3_E~0); 2568185#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2568183#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2568181#L979-3 assume !(1 == ~T6_E~0); 2568179#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2568177#L989-3 assume !(1 == ~T8_E~0); 2568175#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2568173#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2568171#L1004-3 assume !(1 == ~E_2~0); 2568169#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2568167#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2568165#L1019-3 assume !(1 == ~E_5~0); 2568163#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2568161#L1029-3 assume !(1 == ~E_7~0); 2568158#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2568156#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2568153#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2568151#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2568149#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2568146#L1324 assume !(0 == start_simulation_~tmp~3); 2568143#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2568140#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2568138#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2568136#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2568134#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2568133#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 2568132#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2568128#L1337 assume !(0 != start_simulation_~tmp___0~1); 2557858#L1305-1 [2019-12-07 13:00:54,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:54,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 12 times [2019-12-07 13:00:54,675 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:54,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354649969] [2019-12-07 13:00:54,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:54,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:54,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:54,692 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:54,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:54,692 INFO L82 PathProgramCache]: Analyzing trace with hash 684194572, now seen corresponding path program 1 times [2019-12-07 13:00:54,692 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:54,692 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998430495] [2019-12-07 13:00:54,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:54,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:54,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:54,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998430495] [2019-12-07 13:00:54,724 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:54,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:00:54,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144667384] [2019-12-07 13:00:54,725 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:00:54,725 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:00:54,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:00:54,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:00:54,725 INFO L87 Difference]: Start difference. First operand 85936 states and 111729 transitions. cyclomatic complexity: 25825 Second operand 5 states. [2019-12-07 13:00:55,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:00:55,079 INFO L93 Difference]: Finished difference Result 139232 states and 181952 transitions. [2019-12-07 13:00:55,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:00:55,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139232 states and 181952 transitions. [2019-12-07 13:00:55,479 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137968 [2019-12-07 13:00:55,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139232 states to 139232 states and 181952 transitions. [2019-12-07 13:00:55,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139232 [2019-12-07 13:00:55,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139232 [2019-12-07 13:00:55,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139232 states and 181952 transitions. [2019-12-07 13:00:55,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:00:55,855 INFO L688 BuchiCegarLoop]: Abstraction has 139232 states and 181952 transitions. [2019-12-07 13:00:55,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139232 states and 181952 transitions. [2019-12-07 13:00:56,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139232 to 87472. [2019-12-07 13:00:56,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87472 states. [2019-12-07 13:00:56,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87472 states to 87472 states and 112816 transitions. [2019-12-07 13:00:56,539 INFO L711 BuchiCegarLoop]: Abstraction has 87472 states and 112816 transitions. [2019-12-07 13:00:56,539 INFO L591 BuchiCegarLoop]: Abstraction has 87472 states and 112816 transitions. [2019-12-07 13:00:56,539 INFO L424 BuchiCegarLoop]: ======== Iteration 34============ [2019-12-07 13:00:56,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87472 states and 112816 transitions. [2019-12-07 13:00:56,715 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86720 [2019-12-07 13:00:56,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:00:56,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:00:56,716 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:56,717 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:00:56,717 INFO L794 eck$LassoCheckResult]: Stem: 2783021#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2782923#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2782924#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2783202#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 2782469#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2782470#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2783329#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2783203#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2782876#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2782877#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2783438#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2783160#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2782752#L639-1 assume !(0 == ~M_E~0); 2782753#L856-1 assume !(0 == ~T1_E~0); 2782883#L861-1 assume !(0 == ~T2_E~0); 2782884#L866-1 assume !(0 == ~T3_E~0); 2783468#L871-1 assume !(0 == ~T4_E~0); 2783186#L876-1 assume !(0 == ~T5_E~0); 2782996#L881-1 assume !(0 == ~T6_E~0); 2782615#L886-1 assume !(0 == ~T7_E~0); 2782616#L891-1 assume !(0 == ~T8_E~0); 2783283#L896-1 assume !(0 == ~E_M~0); 2782955#L901-1 assume !(0 == ~E_1~0); 2782569#L906-1 assume !(0 == ~E_2~0); 2782570#L911-1 assume !(0 == ~E_3~0); 2783542#L916-1 assume !(0 == ~E_4~0); 2783096#L921-1 assume !(0 == ~E_5~0); 2782683#L926-1 assume !(0 == ~E_6~0); 2782684#L931-1 assume !(0 == ~E_7~0); 2783635#L936-1 assume !(0 == ~E_8~0); 2783378#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2782644#L420 assume !(1 == ~m_pc~0); 2782645#L420-2 is_master_triggered_~__retres1~0 := 0; 2782651#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2783451#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2783536#L1063 assume !(0 != activate_threads_~tmp~1); 2783750#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2782944#L439 assume !(1 == ~t1_pc~0); 2782945#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 2782948#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2783586#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2783521#L1071 assume !(0 != activate_threads_~tmp___0~0); 2783506#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2783168#L458 assume !(1 == ~t2_pc~0); 2783144#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 2783145#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2783737#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2783009#L1079 assume !(0 != activate_threads_~tmp___1~0); 2783010#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2783012#L477 assume !(1 == ~t3_pc~0); 2783316#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 2782536#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2782537#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2782635#L1087 assume !(0 != activate_threads_~tmp___2~0); 2783769#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2783502#L496 assume !(1 == ~t4_pc~0); 2783446#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 2782763#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2782764#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2783393#L1095 assume !(0 != activate_threads_~tmp___3~0); 2783394#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2783395#L515 assume !(1 == ~t5_pc~0); 2783755#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 2783190#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2782954#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2782914#L1103 assume !(0 != activate_threads_~tmp___4~0); 2782894#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2782600#L534 assume !(1 == ~t6_pc~0); 2782591#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 2782592#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2783162#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2783163#L1111 assume !(0 != activate_threads_~tmp___5~0); 2783562#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2782854#L553 assume !(1 == ~t7_pc~0); 2782567#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 2782860#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2783330#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2783137#L1119 assume !(0 != activate_threads_~tmp___6~0); 2783113#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2783069#L572 assume !(1 == ~t8_pc~0); 2783070#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 2783073#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2783497#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2782501#L1127 assume !(0 != activate_threads_~tmp___7~0); 2782502#L1127-2 assume !(1 == ~M_E~0); 2782503#L954-1 assume !(1 == ~T1_E~0); 2783463#L959-1 assume !(1 == ~T2_E~0); 2783184#L964-1 assume !(1 == ~T3_E~0); 2782988#L969-1 assume !(1 == ~T4_E~0); 2782611#L974-1 assume !(1 == ~T5_E~0); 2782612#L979-1 assume !(1 == ~T6_E~0); 2783279#L984-1 assume !(1 == ~T7_E~0); 2782959#L989-1 assume !(1 == ~T8_E~0); 2782784#L994-1 assume !(1 == ~E_M~0); 2782785#L999-1 assume !(1 == ~E_1~0); 2783548#L1004-1 assume !(1 == ~E_2~0); 2783120#L1009-1 assume !(1 == ~E_3~0); 2782692#L1014-1 assume !(1 == ~E_4~0); 2782693#L1019-1 assume !(1 == ~E_5~0); 2783643#L1024-1 assume !(1 == ~E_6~0); 2783374#L1029-1 assume !(1 == ~E_7~0); 2783082#L1034-1 assume !(1 == ~E_8~0); 2783083#L1305-1 [2019-12-07 13:00:56,717 INFO L796 eck$LassoCheckResult]: Loop: 2783083#L1305-1 assume !false; 2791251#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2791252#L831 assume !false; 2791228#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2791229#L652 assume !(0 == ~m_st~0); 2790558#L656 assume !(0 == ~t1_st~0); 2790555#L660 assume !(0 == ~t2_st~0); 2790554#L664 assume !(0 == ~t3_st~0); 2790553#L668 assume !(0 == ~t4_st~0); 2790552#L672 assume !(0 == ~t5_st~0); 2790551#L676 assume !(0 == ~t6_st~0); 2790550#L680 assume !(0 == ~t7_st~0); 2790547#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2790546#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2790545#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2790543#L714 assume !(0 != eval_~tmp~0); 2790541#L846 start_simulation_~kernel_st~0 := 2; 2790534#L592-1 start_simulation_~kernel_st~0 := 3; 2790499#L856-2 assume !(0 == ~M_E~0); 2790394#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2790391#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2790389#L866-3 assume !(0 == ~T3_E~0); 2790387#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2790385#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2790383#L881-3 assume !(0 == ~T6_E~0); 2790381#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2790379#L891-3 assume !(0 == ~T8_E~0); 2790377#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2790375#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2790372#L906-3 assume !(0 == ~E_2~0); 2790370#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2790368#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2790366#L921-3 assume !(0 == ~E_5~0); 2790364#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2790362#L931-3 assume !(0 == ~E_7~0); 2790359#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2790357#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2790355#L420-30 assume 1 == ~m_pc~0; 2790305#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2790299#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2790295#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2790294#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2790293#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2790292#L439-30 assume !(1 == ~t1_pc~0); 2790291#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 2790289#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2790288#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2790287#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 2790286#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2790284#L458-30 assume !(1 == ~t2_pc~0); 2790283#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 2790281#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2790279#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2790277#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 2790276#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2790274#L477-30 assume !(1 == ~t3_pc~0); 2790271#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 2790173#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2790162#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2790152#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 2790143#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2790134#L496-30 assume !(1 == ~t4_pc~0); 2790126#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 2790120#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2790113#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2790102#L1095-30 assume !(0 != activate_threads_~tmp___3~0); 2790095#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2788932#L515-30 assume !(1 == ~t5_pc~0); 2788924#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 2788922#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2788920#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2788917#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 2788915#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2788913#L534-30 assume !(1 == ~t6_pc~0); 2788912#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 2788911#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2788910#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2788909#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 2788908#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2788899#L553-30 assume !(1 == ~t7_pc~0); 2788896#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 2788894#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2788891#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2788889#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 2788887#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2788885#L572-30 assume !(1 == ~t8_pc~0); 2788883#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 2788882#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2788881#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2788879#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 2788878#L1127-32 assume !(1 == ~M_E~0); 2788558#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2788877#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2788876#L964-3 assume !(1 == ~T3_E~0); 2788874#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2788872#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2788871#L979-3 assume !(1 == ~T6_E~0); 2788870#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2788868#L989-3 assume !(1 == ~T8_E~0); 2788866#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2788865#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2788864#L1004-3 assume !(1 == ~E_2~0); 2788863#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2788861#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2788859#L1019-3 assume !(1 == ~E_5~0); 2788857#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2788856#L1029-3 assume !(1 == ~E_7~0); 2788854#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2788852#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2788849#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2788847#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2788845#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2788842#L1324 assume !(0 == start_simulation_~tmp~3); 2788843#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2791439#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2791442#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2791437#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2791438#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2791420#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 2791421#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2791410#L1337 assume !(0 != start_simulation_~tmp___0~1); 2783083#L1305-1 [2019-12-07 13:00:56,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:56,717 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654852, now seen corresponding path program 13 times [2019-12-07 13:00:56,717 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:56,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859011897] [2019-12-07 13:00:56,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:56,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:56,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:56,734 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:56,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:56,734 INFO L82 PathProgramCache]: Analyzing trace with hash 958954186, now seen corresponding path program 1 times [2019-12-07 13:00:56,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:56,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639066682] [2019-12-07 13:00:56,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:56,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:56,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:00:56,756 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:00:56,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:56,756 INFO L82 PathProgramCache]: Analyzing trace with hash -1382562713, now seen corresponding path program 1 times [2019-12-07 13:00:56,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:00:56,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311183267] [2019-12-07 13:00:56,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:00:56,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:56,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:00:56,797 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311183267] [2019-12-07 13:00:56,797 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:00:56,797 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:00:56,798 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451289409] [2019-12-07 13:00:57,562 WARN L192 SmtUtils]: Spent 756.00 ms on a formula simplification. DAG size of input: 261 DAG size of output: 245 [2019-12-07 13:00:57,835 WARN L192 SmtUtils]: Spent 262.00 ms on a formula simplification that was a NOOP. DAG size: 211 [2019-12-07 13:00:57,844 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 13:00:57,845 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 13:00:57,845 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 13:00:57,845 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 13:00:57,845 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-12-07 13:00:57,845 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:57,845 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 13:00:57,845 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 13:00:57,845 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.08.cil-2.c_Iteration34_Loop [2019-12-07 13:00:57,845 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 13:00:57,845 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 13:00:57,863 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,868 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,869 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,870 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,872 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,874 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,878 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,882 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,883 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,884 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,885 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,887 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,888 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,891 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,892 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,893 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,895 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,896 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,898 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,899 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,900 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,903 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,906 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,909 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,911 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,914 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,917 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,920 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,921 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,924 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,926 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,928 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,929 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,930 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,931 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,935 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,940 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,943 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,944 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,948 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,953 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,954 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,955 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,956 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,957 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,959 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,962 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,970 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,972 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,974 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,980 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,982 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,985 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,986 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,990 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,993 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,994 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,998 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:57,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,002 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,008 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,010 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,014 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,017 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,018 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,021 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,023 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,024 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,026 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,029 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,031 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,568 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 13:00:58,568 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,573 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,573 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,579 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,579 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,585 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,585 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,587 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,588 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,592 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,592 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,596 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,596 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-5} Honda state: {~t4_st~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,600 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,600 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,603 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,604 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_pc~0=-8} Honda state: {~t4_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,608 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,608 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,611 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,611 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_st~0=7} Honda state: {~t8_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,615 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,615 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,620 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,620 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_#res=0, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=0, ULTIMATE.start_activate_threads_~tmp___5~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,628 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,629 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,634 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,634 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___7~0=0, ULTIMATE.start_is_transmit8_triggered_#res=0, ULTIMATE.start_is_transmit8_triggered_~__retres1~8=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___7~0=0, ULTIMATE.start_is_transmit8_triggered_#res=0, ULTIMATE.start_is_transmit8_triggered_~__retres1~8=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,639 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,639 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,642 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,642 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret18=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret18=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,647 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,647 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,650 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,650 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,825 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,825 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,828 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,828 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,833 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,833 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,840 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,840 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet9=0} Honda state: {ULTIMATE.start_eval_#t~nondet9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,845 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,845 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,847 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,847 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7=0} Honda state: {ULTIMATE.start_eval_#t~nondet7=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,851 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,851 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,854 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,854 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,857 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,858 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,860 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,860 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet5=0} Honda state: {ULTIMATE.start_eval_#t~nondet5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,864 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,864 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,867 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,867 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_pc~0=-8} Honda state: {~t8_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,871 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,871 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,875 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,875 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-5} Honda state: {~t1_st~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,879 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,879 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,881 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,882 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet3=0} Honda state: {ULTIMATE.start_eval_#t~nondet3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,885 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,885 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,888 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,888 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=-2} Honda state: {~t7_pc~0=-2} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,892 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,892 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,895 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,895 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,898 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,899 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,901 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,901 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_9~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_9~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,905 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,905 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,907 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,908 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret21=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret21=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,911 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,911 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,914 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,915 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=-8} Honda state: {~t3_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,918 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,918 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,921 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,921 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,925 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,925 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,928 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,928 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit7_triggered_#res=0, ULTIMATE.start_activate_threads_~tmp___6~0=0} Honda state: {ULTIMATE.start_is_transmit7_triggered_#res=0, ULTIMATE.start_activate_threads_~tmp___6~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,933 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,933 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,937 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,937 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=-5} Honda state: {~t5_st~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,941 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,941 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,944 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-12-07 13:00:58,944 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_2~0=-1} Honda state: {~E_2~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,948 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-12-07 13:00:58,948 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,955 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-12-07 13:00:58,955 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-12-07 13:00:58,960 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-12-07 13:00:58,961 INFO L210 LassoAnalysis]: Preferences: [2019-12-07 13:00:58,961 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-12-07 13:00:58,961 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-12-07 13:00:58,961 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-12-07 13:00:58,962 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-12-07 13:00:58,962 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:58,962 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-12-07 13:00:58,962 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-12-07 13:00:58,962 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.08.cil-2.c_Iteration34_Loop [2019-12-07 13:00:58,962 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-12-07 13:00:58,962 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-12-07 13:00:58,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,968 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,971 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,973 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,980 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,981 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,986 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,991 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,992 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,997 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:58,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,000 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,003 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,005 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,006 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,007 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,009 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,012 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,014 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,015 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,018 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,021 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,025 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,029 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,030 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,034 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,035 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,038 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,040 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,041 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,042 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,045 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,047 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,050 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,053 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,060 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,064 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,065 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,067 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,068 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,070 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,071 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,072 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,073 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,076 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,077 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,079 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,082 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,084 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,092 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,094 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,095 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,099 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,101 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,102 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,103 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,106 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,107 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,109 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,111 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,112 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,113 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,118 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,119 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,121 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,123 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,124 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,128 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,129 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,132 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,135 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,138 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,139 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,142 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,145 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,148 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,150 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,151 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-12-07 13:00:59,655 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-12-07 13:00:59,658 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,662 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,663 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,663 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,664 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,664 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,664 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,666 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,666 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,667 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,671 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,672 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,672 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,672 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,672 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,672 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,673 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,673 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,674 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,677 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,678 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,679 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,679 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,679 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,679 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,679 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,679 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,681 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,684 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,685 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,685 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,685 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,685 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,685 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,686 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,686 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,687 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,692 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,693 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,693 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,694 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,694 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,694 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,695 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,695 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,696 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,700 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,701 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,701 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,702 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,702 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,702 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,702 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,702 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,704 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,707 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,708 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,708 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,708 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,708 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,709 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,709 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,709 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,710 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,713 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,714 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,714 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,714 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,715 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,715 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,715 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,715 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,716 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,719 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,720 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,720 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,721 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,721 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,721 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,722 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,722 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,723 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 39 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,727 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,727 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,728 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,728 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,728 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,728 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,728 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,728 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,729 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 40 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,732 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,734 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,734 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,734 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,734 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,734 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,734 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,734 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,736 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 41 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,740 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,741 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,741 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,742 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,742 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,742 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,743 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 42 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,748 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,749 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,749 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,749 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,749 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,749 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,750 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,750 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,752 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 43 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,755 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,756 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,756 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,756 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,756 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,756 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,757 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,757 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,758 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 44 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,761 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,762 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,763 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,763 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,763 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,763 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,763 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,763 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,765 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 45 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,768 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,769 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,769 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,769 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,769 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,769 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,770 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,770 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,771 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 46 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,775 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,776 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,776 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,776 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,776 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,776 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,776 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,776 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,777 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 47 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,781 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,782 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,782 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,782 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,782 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,782 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,783 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,783 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,784 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 48 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,787 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,789 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,789 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,789 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,789 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,789 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,790 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,790 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,791 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 49 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,795 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,796 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,796 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,796 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,796 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,796 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,797 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,797 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,798 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 50 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,801 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,803 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,803 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,803 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,803 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,803 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,803 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,803 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,805 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 51 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,808 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,809 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,809 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,809 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,809 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,809 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,810 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,810 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,811 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 52 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,814 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,815 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,815 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,815 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,815 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,815 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,816 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,816 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,817 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 53 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,820 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,822 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,822 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,822 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,822 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,822 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,823 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,823 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,824 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 54 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,827 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,828 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,828 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,828 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,828 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,828 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,829 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,829 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,830 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 55 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,898 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,899 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,899 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,899 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,900 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,900 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,900 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,900 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,901 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 56 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,904 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,906 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,906 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,906 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,906 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-12-07 13:00:59,906 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,906 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-12-07 13:00:59,906 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,908 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 57 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,911 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-12-07 13:00:59,912 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-12-07 13:00:59,912 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-12-07 13:00:59,912 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-12-07 13:00:59,912 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-12-07 13:00:59,912 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-12-07 13:00:59,913 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-12-07 13:00:59,913 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-12-07 13:00:59,914 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-12-07 13:00:59,917 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-12-07 13:00:59,917 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/z3 Starting monitored process 58 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-12-07 13:00:59,922 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-12-07 13:00:59,922 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-12-07 13:00:59,922 INFO L510 LassoAnalysis]: Proved termination. [2019-12-07 13:00:59,923 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_M~0) = -1*~E_M~0 + 1 Supporting invariants [] [2019-12-07 13:00:59,925 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-12-07 13:00:59,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:00:59,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:00:59,994 INFO L264 TraceCheckSpWp]: Trace formula consists of 278 conjuncts, 2 conjunts are in the unsatisfiable core [2019-12-07 13:00:59,997 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 13:01:00,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:00,031 INFO L264 TraceCheckSpWp]: Trace formula consists of 252 conjuncts, 4 conjunts are in the unsatisfiable core [2019-12-07 13:01:00,033 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 13:01:00,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:00,065 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-12-07 13:01:00,066 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 87472 states and 112816 transitions. cyclomatic complexity: 25376 Second operand 5 states. [2019-12-07 13:01:01,039 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 87472 states and 112816 transitions. cyclomatic complexity: 25376. Second operand 5 states. Result 300354 states and 388627 transitions. Complement of second has 5 states. [2019-12-07 13:01:01,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-12-07 13:01:01,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-12-07 13:01:01,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 2487 transitions. [2019-12-07 13:01:01,044 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2487 transitions. Stem has 102 letters. Loop has 121 letters. [2019-12-07 13:01:01,047 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 13:01:01,048 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2487 transitions. Stem has 223 letters. Loop has 121 letters. [2019-12-07 13:01:01,049 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 13:01:01,049 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 2487 transitions. Stem has 102 letters. Loop has 242 letters. [2019-12-07 13:01:01,050 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-12-07 13:01:01,051 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 300354 states and 388627 transitions. [2019-12-07 13:01:01,936 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 215408 [2019-12-07 13:01:02,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 300354 states to 300290 states and 388563 transitions. [2019-12-07 13:01:02,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217121 [2019-12-07 13:01:02,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217442 [2019-12-07 13:01:02,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 300290 states and 388563 transitions. [2019-12-07 13:01:02,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:02,733 INFO L688 BuchiCegarLoop]: Abstraction has 300290 states and 388563 transitions. [2019-12-07 13:01:02,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 300290 states and 388563 transitions. [2019-12-07 13:01:04,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 300290 to 252721. [2019-12-07 13:01:04,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 252721 states. [2019-12-07 13:01:04,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252721 states to 252721 states and 327026 transitions. [2019-12-07 13:01:04,796 INFO L711 BuchiCegarLoop]: Abstraction has 252721 states and 327026 transitions. [2019-12-07 13:01:04,796 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:04,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:04,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:04,796 INFO L87 Difference]: Start difference. First operand 252721 states and 327026 transitions. Second operand 3 states. [2019-12-07 13:01:05,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:05,440 INFO L93 Difference]: Finished difference Result 264913 states and 340850 transitions. [2019-12-07 13:01:05,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:05,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 264913 states and 340850 transitions. [2019-12-07 13:01:08,346 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 176736 [2019-12-07 13:01:08,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 264913 states to 264913 states and 340850 transitions. [2019-12-07 13:01:08,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178129 [2019-12-07 13:01:08,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178129 [2019-12-07 13:01:08,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 264913 states and 340850 transitions. [2019-12-07 13:01:08,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:08,794 INFO L688 BuchiCegarLoop]: Abstraction has 264913 states and 340850 transitions. [2019-12-07 13:01:08,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264913 states and 340850 transitions. [2019-12-07 13:01:10,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264913 to 252721. [2019-12-07 13:01:10,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 252721 states. [2019-12-07 13:01:10,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252721 states to 252721 states and 326258 transitions. [2019-12-07 13:01:10,498 INFO L711 BuchiCegarLoop]: Abstraction has 252721 states and 326258 transitions. [2019-12-07 13:01:10,498 INFO L591 BuchiCegarLoop]: Abstraction has 252721 states and 326258 transitions. [2019-12-07 13:01:10,498 INFO L424 BuchiCegarLoop]: ======== Iteration 35============ [2019-12-07 13:01:10,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252721 states and 326258 transitions. [2019-12-07 13:01:10,989 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 168608 [2019-12-07 13:01:10,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:10,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:10,991 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:10,991 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:10,991 INFO L794 eck$LassoCheckResult]: Stem: 3689644#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 3689475#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3689476#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3689955#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 3688625#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3688626#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3690163#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3689956#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3689380#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3689381#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3690357#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3689881#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3689156#L639-1 assume !(0 == ~M_E~0); 3689157#L856-1 assume !(0 == ~T1_E~0); 3689396#L861-1 assume !(0 == ~T2_E~0); 3689397#L866-1 assume !(0 == ~T3_E~0); 3690413#L871-1 assume !(0 == ~T4_E~0); 3689929#L876-1 assume !(0 == ~T5_E~0); 3689596#L881-1 assume !(0 == ~T6_E~0); 3688895#L886-1 assume !(0 == ~T7_E~0); 3688896#L891-1 assume !(0 == ~T8_E~0); 3690080#L896-1 assume !(0 == ~E_M~0); 3689527#L901-1 assume !(0 == ~E_1~0); 3688814#L906-1 assume !(0 == ~E_2~0); 3688815#L911-1 assume !(0 == ~E_3~0); 3690528#L916-1 assume !(0 == ~E_4~0); 3689764#L921-1 assume !(0 == ~E_5~0); 3689025#L926-1 assume !(0 == ~E_6~0); 3689026#L931-1 assume !(0 == ~E_7~0); 3690674#L936-1 assume !(0 == ~E_8~0); 3690249#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3688952#L420 assume !(1 == ~m_pc~0); 3688953#L420-2 is_master_triggered_~__retres1~0 := 0; 3688963#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3690919#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3690881#L1063 assume !(0 != activate_threads_~tmp~1); 3690882#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3689506#L439 assume !(1 == ~t1_pc~0); 3689507#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 3689514#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3690611#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3690499#L1071 assume !(0 != activate_threads_~tmp___0~0); 3690474#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3689894#L458 assume !(1 == ~t2_pc~0); 3689850#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 3689851#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3690848#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3689620#L1079 assume !(0 != activate_threads_~tmp___1~0); 3689621#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3689624#L477 assume !(1 == ~t3_pc~0); 3690140#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 3688756#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3688757#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3688930#L1087 assume !(0 != activate_threads_~tmp___2~0); 3690905#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3690469#L496 assume !(1 == ~t4_pc~0); 3690367#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 3689178#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3689179#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3690268#L1095 assume !(0 != activate_threads_~tmp___3~0); 3690269#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3690270#L515 assume !(1 == ~t5_pc~0); 3690887#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 3689937#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3689526#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3689457#L1103 assume !(0 != activate_threads_~tmp___4~0); 3689422#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3688868#L534 assume !(1 == ~t6_pc~0); 3688851#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 3688852#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3689884#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3689885#L1111 assume !(0 != activate_threads_~tmp___5~0); 3690567#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3689338#L553 assume !(1 == ~t7_pc~0); 3688809#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 3689348#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3690164#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3689837#L1119 assume !(0 != activate_threads_~tmp___6~0); 3689797#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3689719#L572 assume !(1 == ~t8_pc~0); 3689720#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 3689723#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3690463#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3688690#L1127 assume !(0 != activate_threads_~tmp___7~0); 3688691#L1127-2 assume !(1 == ~M_E~0); 3688692#L954-1 assume !(1 == ~T1_E~0); 3690404#L959-1 assume !(1 == ~T2_E~0); 3689926#L964-1 assume !(1 == ~T3_E~0); 3689583#L969-1 assume !(1 == ~T4_E~0); 3688889#L974-1 assume !(1 == ~T5_E~0); 3688890#L979-1 assume !(1 == ~T6_E~0); 3690071#L984-1 assume !(1 == ~T7_E~0); 3689536#L989-1 assume !(1 == ~T8_E~0); 3689207#L994-1 assume !(1 == ~E_M~0); 3689208#L999-1 assume !(1 == ~E_1~0); 3690538#L1004-1 assume !(1 == ~E_2~0); 3689809#L1009-1 assume !(1 == ~E_3~0); 3689039#L1014-1 assume !(1 == ~E_4~0); 3689040#L1019-1 assume !(1 == ~E_5~0); 3690684#L1024-1 assume !(1 == ~E_6~0); 3690241#L1029-1 assume !(1 == ~E_7~0); 3689738#L1034-1 assume 1 == ~E_8~0;~E_8~0 := 2; 3689739#L1305-1 [2019-12-07 13:01:10,992 INFO L796 eck$LassoCheckResult]: Loop: 3689739#L1305-1 assume !false; 3779810#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 3779805#L831 assume !false; 3779803#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3779801#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3779799#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3779797#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3779795#L714 assume 0 != eval_~tmp~0; 3779793#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3779790#L722 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 3779787#L76 assume 0 == ~m_pc~0; 3779775#L112 assume !false; 3779773#L88 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3779771#L420-3 assume 1 == ~m_pc~0; 3779769#L421-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3779770#L431-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3781881#L432-1 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3779758#L1063-3 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3779755#L1063-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3779753#L439-3 assume !(1 == ~t1_pc~0); 3779749#L439-5 is_transmit1_triggered_~__retres1~1 := 0; 3779747#L450-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3779745#L451-1 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3779743#L1071-3 assume !(0 != activate_threads_~tmp___0~0); 3779740#L1071-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3779738#L458-3 assume !(1 == ~t2_pc~0); 3779734#L458-5 is_transmit2_triggered_~__retres1~2 := 0; 3779732#L469-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3779730#L470-1 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3779728#L1079-3 assume !(0 != activate_threads_~tmp___1~0); 3779726#L1079-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3779724#L477-3 assume !(1 == ~t3_pc~0); 3779722#L477-5 is_transmit3_triggered_~__retres1~3 := 0; 3779720#L488-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3779718#L489-1 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3779716#L1087-3 assume !(0 != activate_threads_~tmp___2~0); 3779714#L1087-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3779712#L496-3 assume !(1 == ~t4_pc~0); 3779706#L496-5 is_transmit4_triggered_~__retres1~4 := 0; 3779704#L507-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3779702#L508-1 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3779700#L1095-3 assume !(0 != activate_threads_~tmp___3~0); 3779696#L1095-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3779694#L515-3 assume !(1 == ~t5_pc~0); 3779692#L515-5 is_transmit5_triggered_~__retres1~5 := 0; 3779690#L526-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3779688#L527-1 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3779686#L1103-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3779684#L1103-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3779682#L534-3 assume !(1 == ~t6_pc~0); 3779680#L534-5 is_transmit6_triggered_~__retres1~6 := 0; 3779678#L545-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3779676#L546-1 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3779674#L1111-3 assume !(0 != activate_threads_~tmp___5~0); 3779672#L1111-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3779670#L553-3 assume !(1 == ~t7_pc~0); 3779666#L553-5 is_transmit7_triggered_~__retres1~7 := 0; 3779664#L564-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3779662#L565-1 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3779660#L1119-3 assume !(0 != activate_threads_~tmp___6~0); 3779658#L1119-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3779656#L572-3 assume !(1 == ~t8_pc~0); 3779654#L572-5 is_transmit8_triggered_~__retres1~8 := 0; 3779652#L583-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3778756#L584-1 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3778624#L1127-3 assume !(0 != activate_threads_~tmp___7~0); 3778619#L1127-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 3778617#L719 assume !(0 == ~t1_st~0); 3778616#L733 assume !(0 == ~t2_st~0); 3778869#L747 assume !(0 == ~t3_st~0); 3778860#L761 assume !(0 == ~t4_st~0); 3778855#L775 assume !(0 == ~t5_st~0); 3778848#L789 assume !(0 == ~t6_st~0); 3778845#L803 assume !(0 == ~t7_st~0); 3778839#L817 assume !(0 == ~t8_st~0); 3778837#L831 assume !false; 3778836#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3778835#L652 assume !(0 == ~m_st~0); 3778830#L656 assume !(0 == ~t1_st~0); 3778831#L660 assume !(0 == ~t2_st~0); 3778834#L664 assume !(0 == ~t3_st~0); 3778828#L668 assume !(0 == ~t4_st~0); 3778829#L672 assume !(0 == ~t5_st~0); 3778833#L676 assume !(0 == ~t6_st~0); 3778826#L680 assume !(0 == ~t7_st~0); 3778827#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 3778832#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3778625#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 3778626#L714 assume !(0 != eval_~tmp~0); 3779651#L846 start_simulation_~kernel_st~0 := 2; 3779650#L592-1 start_simulation_~kernel_st~0 := 3; 3779649#L856-2 assume !(0 == ~M_E~0); 3779648#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3779647#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3779646#L866-3 assume !(0 == ~T3_E~0); 3779645#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3779644#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3779643#L881-3 assume !(0 == ~T6_E~0); 3779642#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3779641#L891-3 assume !(0 == ~T8_E~0); 3779640#L896-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3779639#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3779638#L906-3 assume !(0 == ~E_2~0); 3779637#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3779636#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3779635#L921-3 assume !(0 == ~E_5~0); 3779634#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3779633#L931-3 assume !(0 == ~E_7~0); 3779632#L936-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3779631#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3779630#L420-30 assume 1 == ~m_pc~0; 3779628#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3779629#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3779985#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3779983#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3779981#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3779979#L439-30 assume !(1 == ~t1_pc~0); 3779977#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 3779975#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3779973#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3779972#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 3779971#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3779969#L458-30 assume !(1 == ~t2_pc~0); 3779968#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 3779966#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3779963#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3779961#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 3779959#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3779958#L477-30 assume !(1 == ~t3_pc~0); 3779957#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 3779955#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3779954#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3779953#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 3779952#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3779950#L496-30 assume !(1 == ~t4_pc~0); 3779947#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 3779946#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3779945#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3779941#L1095-30 assume !(0 != activate_threads_~tmp___3~0); 3779938#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3779936#L515-30 assume !(1 == ~t5_pc~0); 3779934#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 3779930#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3779928#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3779926#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 3779924#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3779922#L534-30 assume !(1 == ~t6_pc~0); 3779920#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 3779918#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3779916#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3779913#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 3779911#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3779909#L553-30 assume !(1 == ~t7_pc~0); 3779906#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 3779904#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3779902#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3779900#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 3779898#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3779896#L572-30 assume !(1 == ~t8_pc~0); 3779894#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 3779892#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3779890#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3779888#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 3779885#L1127-32 assume !(1 == ~M_E~0); 3779881#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3779879#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3779876#L964-3 assume !(1 == ~T3_E~0); 3779874#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3779872#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3779870#L979-3 assume !(1 == ~T6_E~0); 3779868#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3779866#L989-3 assume !(1 == ~T8_E~0); 3779864#L994-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3779862#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3779860#L1004-3 assume !(1 == ~E_2~0); 3779858#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3779856#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3779854#L1019-3 assume !(1 == ~E_5~0); 3779852#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3779850#L1029-3 assume !(1 == ~E_7~0); 3779847#L1034-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3779845#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3779843#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3779841#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3779839#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3779836#L1324 assume !(0 == start_simulation_~tmp~3); 3779833#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3779831#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3779829#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3779827#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 3779825#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3779824#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 3779823#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3779819#L1337 assume !(0 != start_simulation_~tmp___0~1); 3689739#L1305-1 [2019-12-07 13:01:10,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:10,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1087654850, now seen corresponding path program 1 times [2019-12-07 13:01:10,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:10,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86705683] [2019-12-07 13:01:10,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:10,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:11,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:11,021 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86705683] [2019-12-07 13:01:11,021 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:11,021 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 13:01:11,022 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269012313] [2019-12-07 13:01:11,022 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:01:11,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:11,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1457293737, now seen corresponding path program 1 times [2019-12-07 13:01:11,022 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:11,022 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761500900] [2019-12-07 13:01:11,022 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:11,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:11,052 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:11,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761500900] [2019-12-07 13:01:11,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:11,052 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:11,052 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647496144] [2019-12-07 13:01:11,052 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:01:11,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:11,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:11,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:11,053 INFO L87 Difference]: Start difference. First operand 252721 states and 326258 transitions. cyclomatic complexity: 73633 Second operand 3 states. [2019-12-07 13:01:11,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:11,479 INFO L93 Difference]: Finished difference Result 208769 states and 267792 transitions. [2019-12-07 13:01:11,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:11,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208769 states and 267792 transitions. [2019-12-07 13:01:12,094 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 126192 [2019-12-07 13:01:12,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208769 states to 208769 states and 267792 transitions. [2019-12-07 13:01:12,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127201 [2019-12-07 13:01:12,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127201 [2019-12-07 13:01:12,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208769 states and 267792 transitions. [2019-12-07 13:01:12,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:12,595 INFO L688 BuchiCegarLoop]: Abstraction has 208769 states and 267792 transitions. [2019-12-07 13:01:12,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208769 states and 267792 transitions. [2019-12-07 13:01:14,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208769 to 208769. [2019-12-07 13:01:14,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208769 states. [2019-12-07 13:01:14,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208769 states to 208769 states and 267792 transitions. [2019-12-07 13:01:14,439 INFO L711 BuchiCegarLoop]: Abstraction has 208769 states and 267792 transitions. [2019-12-07 13:01:14,439 INFO L591 BuchiCegarLoop]: Abstraction has 208769 states and 267792 transitions. [2019-12-07 13:01:14,439 INFO L424 BuchiCegarLoop]: ======== Iteration 36============ [2019-12-07 13:01:14,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 208769 states and 267792 transitions. [2019-12-07 13:01:14,849 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 126192 [2019-12-07 13:01:14,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:14,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:14,851 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:14,851 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:14,852 INFO L794 eck$LassoCheckResult]: Stem: 4151091#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4150928#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4150929#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4151403#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 4150122#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150123#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4151609#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4151404#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4150841#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4150842#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4151806#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4151332#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4150628#L639-1 assume !(0 == ~M_E~0); 4150629#L856-1 assume !(0 == ~T1_E~0); 4150857#L861-1 assume !(0 == ~T2_E~0); 4150858#L866-1 assume !(0 == ~T3_E~0); 4151857#L871-1 assume !(0 == ~T4_E~0); 4151381#L876-1 assume !(0 == ~T5_E~0); 4151051#L881-1 assume !(0 == ~T6_E~0); 4150389#L886-1 assume !(0 == ~T7_E~0); 4150390#L891-1 assume !(0 == ~T8_E~0); 4151531#L896-1 assume !(0 == ~E_M~0); 4150981#L901-1 assume !(0 == ~E_1~0); 4150306#L906-1 assume !(0 == ~E_2~0); 4150307#L911-1 assume !(0 == ~E_3~0); 4151970#L916-1 assume !(0 == ~E_4~0); 4151215#L921-1 assume !(0 == ~E_5~0); 4150516#L926-1 assume !(0 == ~E_6~0); 4150517#L931-1 assume !(0 == ~E_7~0); 4152126#L936-1 assume !(0 == ~E_8~0); 4151695#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4150442#L420 assume !(1 == ~m_pc~0); 4150443#L420-2 is_master_triggered_~__retres1~0 := 0; 4150453#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4152346#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4152312#L1063 assume !(0 != activate_threads_~tmp~1); 4152313#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4150962#L439 assume !(1 == ~t1_pc~0); 4150963#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 4150968#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4152055#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4151941#L1071 assume !(0 != activate_threads_~tmp___0~0); 4151915#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4151345#L458 assume !(1 == ~t2_pc~0); 4151300#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 4151301#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4152285#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4151074#L1079 assume !(0 != activate_threads_~tmp___1~0); 4151075#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4151078#L477 assume !(1 == ~t3_pc~0); 4151587#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 4150246#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4150247#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4150422#L1087 assume !(0 != activate_threads_~tmp___2~0); 4152336#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4151908#L496 assume !(1 == ~t4_pc~0); 4151817#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 4150643#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4150644#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4151715#L1095 assume !(0 != activate_threads_~tmp___3~0); 4151716#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4151717#L515 assume !(1 == ~t5_pc~0); 4152317#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 4151386#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4150980#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4150911#L1103 assume !(0 != activate_threads_~tmp___4~0); 4150879#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4150362#L534 assume !(1 == ~t6_pc~0); 4150344#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 4150345#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4151335#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4151336#L1111 assume !(0 != activate_threads_~tmp___5~0); 4152011#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4150805#L553 assume !(1 == ~t7_pc~0); 4150303#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 4150815#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4151610#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4151288#L1119 assume !(0 != activate_threads_~tmp___6~0); 4151248#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4151167#L572 assume !(1 == ~t8_pc~0); 4151168#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 4151171#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4151903#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4150185#L1127 assume !(0 != activate_threads_~tmp___7~0); 4150186#L1127-2 assume !(1 == ~M_E~0); 4150187#L954-1 assume !(1 == ~T1_E~0); 4151850#L959-1 assume !(1 == ~T2_E~0); 4151377#L964-1 assume !(1 == ~T3_E~0); 4151033#L969-1 assume !(1 == ~T4_E~0); 4150383#L974-1 assume !(1 == ~T5_E~0); 4150384#L979-1 assume !(1 == ~T6_E~0); 4151523#L984-1 assume !(1 == ~T7_E~0); 4150988#L989-1 assume !(1 == ~T8_E~0); 4150673#L994-1 assume !(1 == ~E_M~0); 4150674#L999-1 assume !(1 == ~E_1~0); 4151980#L1004-1 assume !(1 == ~E_2~0); 4151259#L1009-1 assume !(1 == ~E_3~0); 4150530#L1014-1 assume !(1 == ~E_4~0); 4150531#L1019-1 assume !(1 == ~E_5~0); 4152138#L1024-1 assume !(1 == ~E_6~0); 4151686#L1029-1 assume !(1 == ~E_7~0); 4151188#L1034-1 assume !(1 == ~E_8~0); 4151189#L1305-1 assume !false; 4158751#L1306 [2019-12-07 13:01:14,852 INFO L796 eck$LassoCheckResult]: Loop: 4158751#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4243968#L831 assume !false; 4243966#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4243962#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4243961#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4243960#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4243956#L714 assume 0 != eval_~tmp~0; 4243810#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4243808#L722 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 4235236#L76 assume 0 == ~m_pc~0; 4235229#L112 assume !false; 4235227#L88 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4235225#L420-3 assume !(1 == ~m_pc~0); 4235220#L420-5 is_master_triggered_~__retres1~0 := 0; 4235221#L431-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4243404#L432-1 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4235211#L1063-3 assume !(0 != activate_threads_~tmp~1); 4235207#L1063-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4235208#L439-3 assume !(1 == ~t1_pc~0); 4235200#L439-5 is_transmit1_triggered_~__retres1~1 := 0; 4235201#L450-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4235192#L451-1 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4235193#L1071-3 assume !(0 != activate_threads_~tmp___0~0); 4235186#L1071-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4235187#L458-3 assume !(1 == ~t2_pc~0); 4243303#L458-5 is_transmit2_triggered_~__retres1~2 := 0; 4235177#L469-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4235178#L470-1 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4235171#L1079-3 assume !(0 != activate_threads_~tmp___1~0); 4235172#L1079-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4235165#L477-3 assume !(1 == ~t3_pc~0); 4235166#L477-5 is_transmit3_triggered_~__retres1~3 := 0; 4235159#L488-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4235160#L489-1 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4235153#L1087-3 assume !(0 != activate_threads_~tmp___2~0); 4235154#L1087-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4235147#L496-3 assume !(1 == ~t4_pc~0); 4235142#L496-5 is_transmit4_triggered_~__retres1~4 := 0; 4235143#L507-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4243257#L508-1 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4243253#L1095-3 assume !(0 != activate_threads_~tmp___3~0); 4243250#L1095-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4243248#L515-3 assume !(1 == ~t5_pc~0); 4243246#L515-5 is_transmit5_triggered_~__retres1~5 := 0; 4243243#L526-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4243242#L527-1 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4235122#L1103-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4235123#L1103-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4235114#L534-3 assume !(1 == ~t6_pc~0); 4235115#L534-5 is_transmit6_triggered_~__retres1~6 := 0; 4235104#L545-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4235105#L546-1 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4235096#L1111-3 assume !(0 != activate_threads_~tmp___5~0); 4235097#L1111-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4235091#L553-3 assume !(1 == ~t7_pc~0); 4235088#L553-5 is_transmit7_triggered_~__retres1~7 := 0; 4235086#L564-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4235087#L565-1 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4241809#L1119-3 assume !(0 != activate_threads_~tmp___6~0); 4241807#L1119-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4241805#L572-3 assume !(1 == ~t8_pc~0); 4241803#L572-5 is_transmit8_triggered_~__retres1~8 := 0; 4241801#L583-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4241799#L584-1 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4241797#L1127-3 assume !(0 != activate_threads_~tmp___7~0); 4241795#L1127-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 4241792#L719 assume !(0 == ~t1_st~0); 4241780#L733 assume !(0 == ~t2_st~0); 4241779#L747 assume !(0 == ~t3_st~0); 4241714#L761 assume !(0 == ~t4_st~0); 4241713#L775 assume !(0 == ~t5_st~0); 4234900#L789 assume !(0 == ~t6_st~0); 4241712#L803 assume !(0 == ~t7_st~0); 4235099#L817 assume !(0 == ~t8_st~0); 4235095#L831 assume !false; 4235092#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4235089#L652 assume !(0 == ~m_st~0); 4235076#L656 assume !(0 == ~t1_st~0); 4235077#L660 assume !(0 == ~t2_st~0); 4235080#L664 assume !(0 == ~t3_st~0); 4235073#L668 assume !(0 == ~t4_st~0); 4235075#L672 assume !(0 == ~t5_st~0); 4235079#L676 assume !(0 == ~t6_st~0); 4244985#L680 assume !(0 == ~t7_st~0); 4244982#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 4244980#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4244978#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4244976#L714 assume !(0 != eval_~tmp~0); 4244790#L846 start_simulation_~kernel_st~0 := 2; 4244788#L592-1 start_simulation_~kernel_st~0 := 3; 4244786#L856-2 assume !(0 == ~M_E~0); 4244785#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4244784#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4244740#L866-3 assume !(0 == ~T3_E~0); 4244734#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4244729#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4244719#L881-3 assume !(0 == ~T6_E~0); 4244713#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4244708#L891-3 assume !(0 == ~T8_E~0); 4244705#L896-3 assume !(0 == ~E_M~0); 4244184#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4244182#L906-3 assume !(0 == ~E_2~0); 4244180#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4244179#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4244176#L921-3 assume !(0 == ~E_5~0); 4244174#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4244173#L931-3 assume !(0 == ~E_7~0); 4244172#L936-3 assume !(0 == ~E_8~0); 4244170#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4244168#L420-30 assume 1 == ~m_pc~0; 4244165#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4244164#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4244163#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4244160#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4244158#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4244156#L439-30 assume !(1 == ~t1_pc~0); 4244155#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 4244153#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4244151#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4244149#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 4244147#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4244143#L458-30 assume !(1 == ~t2_pc~0); 4244142#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 4244139#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4244137#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4244135#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 4244133#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4244131#L477-30 assume !(1 == ~t3_pc~0); 4244129#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 4244127#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4244125#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4244123#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 4244121#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4244119#L496-30 assume 1 == ~t4_pc~0; 4244116#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4244114#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4244111#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4244102#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4244100#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4244098#L515-30 assume !(1 == ~t5_pc~0); 4244096#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 4244092#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4244090#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4244088#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 4244086#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4244084#L534-30 assume !(1 == ~t6_pc~0); 4244082#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 4244080#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4244078#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4244075#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 4244073#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4244071#L553-30 assume !(1 == ~t7_pc~0); 4244068#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 4244066#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4244064#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4244062#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 4244060#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4244058#L572-30 assume !(1 == ~t8_pc~0); 4244056#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 4244054#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4244052#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4244050#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 4244047#L1127-32 assume !(1 == ~M_E~0); 4244043#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4244041#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4244038#L964-3 assume !(1 == ~T3_E~0); 4244036#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4244034#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4244032#L979-3 assume !(1 == ~T6_E~0); 4244030#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4244028#L989-3 assume !(1 == ~T8_E~0); 4244026#L994-3 assume !(1 == ~E_M~0); 4244024#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4244022#L1004-3 assume !(1 == ~E_2~0); 4244020#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4244018#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4244016#L1019-3 assume !(1 == ~E_5~0); 4244014#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4244012#L1029-3 assume !(1 == ~E_7~0); 4244009#L1034-3 assume !(1 == ~E_8~0); 4244007#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4244005#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4244003#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4244001#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4243998#L1324 assume !(0 == start_simulation_~tmp~3); 4243995#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4243993#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4243991#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4243989#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4243987#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4243986#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 4243985#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4243981#L1337 assume !(0 != start_simulation_~tmp___0~1); 4243979#L1305-1 assume !false; 4158751#L1306 [2019-12-07 13:01:14,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:14,852 INFO L82 PathProgramCache]: Analyzing trace with hash -642437461, now seen corresponding path program 1 times [2019-12-07 13:01:14,852 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:14,853 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997156703] [2019-12-07 13:01:14,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:14,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:14,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:14,874 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:14,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:14,875 INFO L82 PathProgramCache]: Analyzing trace with hash 146751099, now seen corresponding path program 1 times [2019-12-07 13:01:14,875 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:14,875 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267218023] [2019-12-07 13:01:14,875 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:14,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:14,916 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:14,917 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267218023] [2019-12-07 13:01:14,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:14,917 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:01:14,917 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397384996] [2019-12-07 13:01:14,917 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:01:14,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:14,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:01:14,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:01:14,917 INFO L87 Difference]: Start difference. First operand 208769 states and 267792 transitions. cyclomatic complexity: 59103 Second operand 5 states. [2019-12-07 13:01:15,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:15,493 INFO L93 Difference]: Finished difference Result 290881 states and 374303 transitions. [2019-12-07 13:01:15,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:01:15,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290881 states and 374303 transitions. [2019-12-07 13:01:16,282 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 175408 [2019-12-07 13:01:16,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290881 states to 290881 states and 374303 transitions. [2019-12-07 13:01:16,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177121 [2019-12-07 13:01:16,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177121 [2019-12-07 13:01:16,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 290881 states and 374303 transitions. [2019-12-07 13:01:16,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:16,882 INFO L688 BuchiCegarLoop]: Abstraction has 290881 states and 374303 transitions. [2019-12-07 13:01:17,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290881 states and 374303 transitions. [2019-12-07 13:01:18,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290881 to 209249. [2019-12-07 13:01:18,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209249 states. [2019-12-07 13:01:18,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209249 states to 209249 states and 266127 transitions. [2019-12-07 13:01:18,954 INFO L711 BuchiCegarLoop]: Abstraction has 209249 states and 266127 transitions. [2019-12-07 13:01:18,954 INFO L591 BuchiCegarLoop]: Abstraction has 209249 states and 266127 transitions. [2019-12-07 13:01:18,954 INFO L424 BuchiCegarLoop]: ======== Iteration 37============ [2019-12-07 13:01:18,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209249 states and 266127 transitions. [2019-12-07 13:01:19,358 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 126480 [2019-12-07 13:01:19,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:19,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:19,360 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:19,360 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:19,361 INFO L794 eck$LassoCheckResult]: Stem: 4650771#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4650605#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4650606#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4651085#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 4649786#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4649787#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4651292#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4651086#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4650511#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4650512#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4651477#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4651010#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4650289#L639-1 assume !(0 == ~M_E~0); 4650290#L856-1 assume !(0 == ~T1_E~0); 4650527#L861-1 assume !(0 == ~T2_E~0); 4650528#L866-1 assume !(0 == ~T3_E~0); 4651527#L871-1 assume !(0 == ~T4_E~0); 4651059#L876-1 assume !(0 == ~T5_E~0); 4650730#L881-1 assume !(0 == ~T6_E~0); 4650056#L886-1 assume !(0 == ~T7_E~0); 4650057#L891-1 assume !(0 == ~T8_E~0); 4651211#L896-1 assume !(0 == ~E_M~0); 4650660#L901-1 assume !(0 == ~E_1~0); 4649974#L906-1 assume !(0 == ~E_2~0); 4649975#L911-1 assume !(0 == ~E_3~0); 4651643#L916-1 assume !(0 == ~E_4~0); 4650894#L921-1 assume !(0 == ~E_5~0); 4650179#L926-1 assume !(0 == ~E_6~0); 4650180#L931-1 assume !(0 == ~E_7~0); 4651791#L936-1 assume !(0 == ~E_8~0); 4651379#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4650109#L420 assume !(1 == ~m_pc~0); 4650110#L420-2 is_master_triggered_~__retres1~0 := 0; 4650120#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4652018#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4651983#L1063 assume !(0 != activate_threads_~tmp~1); 4651984#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4650639#L439 assume !(1 == ~t1_pc~0); 4650640#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 4650645#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4651718#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4651608#L1071 assume !(0 != activate_threads_~tmp___0~0); 4651580#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4651023#L458 assume !(1 == ~t2_pc~0); 4650980#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 4650981#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4651959#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4650752#L1079 assume !(0 != activate_threads_~tmp___1~0); 4650753#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4650756#L477 assume !(1 == ~t3_pc~0); 4651271#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 4649913#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4649914#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4650088#L1087 assume !(0 != activate_threads_~tmp___2~0); 4652001#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4651574#L496 assume !(1 == ~t4_pc~0); 4651488#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 4650303#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4650304#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4651400#L1095 assume !(0 != activate_threads_~tmp___3~0); 4651401#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4651402#L515 assume !(1 == ~t5_pc~0); 4651986#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 4651064#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4650659#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4650588#L1103 assume !(0 != activate_threads_~tmp___4~0); 4650553#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4650029#L534 assume !(1 == ~t6_pc~0); 4650011#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 4650012#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4651013#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4651014#L1111 assume !(0 != activate_threads_~tmp___5~0); 4651677#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4650470#L553 assume !(1 == ~t7_pc~0); 4649971#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 4650480#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4651293#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4650969#L1119 assume !(0 != activate_threads_~tmp___6~0); 4650928#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4650851#L572 assume !(1 == ~t8_pc~0); 4650852#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 4650855#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4651568#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4649852#L1127 assume !(0 != activate_threads_~tmp___7~0); 4649853#L1127-2 assume !(1 == ~M_E~0); 4649854#L954-1 assume !(1 == ~T1_E~0); 4651521#L959-1 assume !(1 == ~T2_E~0); 4651056#L964-1 assume !(1 == ~T3_E~0); 4650715#L969-1 assume !(1 == ~T4_E~0); 4650050#L974-1 assume !(1 == ~T5_E~0); 4650051#L979-1 assume !(1 == ~T6_E~0); 4651204#L984-1 assume !(1 == ~T7_E~0); 4650667#L989-1 assume !(1 == ~T8_E~0); 4650334#L994-1 assume !(1 == ~E_M~0); 4650335#L999-1 assume !(1 == ~E_1~0); 4651652#L1004-1 assume !(1 == ~E_2~0); 4650940#L1009-1 assume !(1 == ~E_3~0); 4650193#L1014-1 assume !(1 == ~E_4~0); 4650194#L1019-1 assume !(1 == ~E_5~0); 4651800#L1024-1 assume !(1 == ~E_6~0); 4651370#L1029-1 assume !(1 == ~E_7~0); 4650869#L1034-1 assume !(1 == ~E_8~0); 4650870#L1305-1 assume !false; 4672034#L1306 [2019-12-07 13:01:19,361 INFO L796 eck$LassoCheckResult]: Loop: 4672034#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4740185#L831 assume !false; 4740184#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4740183#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4740182#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4740181#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4740180#L714 assume 0 != eval_~tmp~0; 4740179#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4740175#L722 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 4740174#L76 assume 0 == ~m_pc~0; 4740168#L112 assume !false; 4740166#L88 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4740164#L420-3 assume !(1 == ~m_pc~0); 4740160#L420-5 is_master_triggered_~__retres1~0 := 0; 4740158#L431-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4740156#L432-1 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4740154#L1063-3 assume !(0 != activate_threads_~tmp~1); 4740151#L1063-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4740149#L439-3 assume !(1 == ~t1_pc~0); 4740148#L439-5 is_transmit1_triggered_~__retres1~1 := 0; 4740145#L450-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4740143#L451-1 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4740141#L1071-3 assume !(0 != activate_threads_~tmp___0~0); 4740139#L1071-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4740137#L458-3 assume !(1 == ~t2_pc~0); 4740134#L458-5 is_transmit2_triggered_~__retres1~2 := 0; 4740132#L469-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4740130#L470-1 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4740128#L1079-3 assume !(0 != activate_threads_~tmp___1~0); 4740126#L1079-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4740124#L477-3 assume !(1 == ~t3_pc~0); 4740122#L477-5 is_transmit3_triggered_~__retres1~3 := 0; 4740118#L488-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4740116#L489-1 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4740114#L1087-3 assume !(0 != activate_threads_~tmp___2~0); 4740112#L1087-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4740109#L496-3 assume !(1 == ~t4_pc~0); 4740105#L496-5 is_transmit4_triggered_~__retres1~4 := 0; 4740103#L507-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4740101#L508-1 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4740099#L1095-3 assume !(0 != activate_threads_~tmp___3~0); 4740096#L1095-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4740094#L515-3 assume !(1 == ~t5_pc~0); 4740092#L515-5 is_transmit5_triggered_~__retres1~5 := 0; 4740090#L526-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4740088#L527-1 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4740086#L1103-3 assume !(0 != activate_threads_~tmp___4~0); 4740084#L1103-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4740082#L534-3 assume !(1 == ~t6_pc~0); 4740080#L534-5 is_transmit6_triggered_~__retres1~6 := 0; 4740077#L545-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4740075#L546-1 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4740073#L1111-3 assume !(0 != activate_threads_~tmp___5~0); 4740071#L1111-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4740069#L553-3 assume !(1 == ~t7_pc~0); 4740066#L553-5 is_transmit7_triggered_~__retres1~7 := 0; 4740064#L564-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4740062#L565-1 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4740060#L1119-3 assume !(0 != activate_threads_~tmp___6~0); 4740058#L1119-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4740056#L572-3 assume !(1 == ~t8_pc~0); 4740055#L572-5 is_transmit8_triggered_~__retres1~8 := 0; 4740054#L583-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4740052#L584-1 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4740050#L1127-3 assume !(0 != activate_threads_~tmp___7~0); 4740049#L1127-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 4740045#L719 assume !(0 == ~t1_st~0); 4740038#L733 assume !(0 == ~t2_st~0); 4740037#L747 assume !(0 == ~t3_st~0); 4739770#L761 assume !(0 == ~t4_st~0); 4739768#L775 assume !(0 == ~t5_st~0); 4739762#L789 assume !(0 == ~t6_st~0); 4739529#L803 assume !(0 == ~t7_st~0); 4739522#L817 assume !(0 == ~t8_st~0); 4739519#L831 assume !false; 4739518#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4739517#L652 assume !(0 == ~m_st~0); 4739515#L656 assume !(0 == ~t1_st~0); 4739514#L660 assume !(0 == ~t2_st~0); 4739513#L664 assume !(0 == ~t3_st~0); 4739512#L668 assume !(0 == ~t4_st~0); 4739511#L672 assume !(0 == ~t5_st~0); 4739509#L676 assume !(0 == ~t6_st~0); 4739507#L680 assume !(0 == ~t7_st~0); 4739505#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 4739504#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4739503#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4739500#L714 assume !(0 != eval_~tmp~0); 4739498#L846 start_simulation_~kernel_st~0 := 2; 4739496#L592-1 start_simulation_~kernel_st~0 := 3; 4739495#L856-2 assume !(0 == ~M_E~0); 4739493#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4739491#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4739489#L866-3 assume !(0 == ~T3_E~0); 4739487#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4739485#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4739483#L881-3 assume !(0 == ~T6_E~0); 4739480#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4739478#L891-3 assume !(0 == ~T8_E~0); 4739476#L896-3 assume !(0 == ~E_M~0); 4739472#L901-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4739470#L906-3 assume !(0 == ~E_2~0); 4739468#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4739466#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4739464#L921-3 assume !(0 == ~E_5~0); 4739462#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4739460#L931-3 assume !(0 == ~E_7~0); 4739458#L936-3 assume !(0 == ~E_8~0); 4739455#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4739453#L420-30 assume 1 == ~m_pc~0; 4739450#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4739447#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4739445#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4739442#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4739440#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4739438#L439-30 assume !(1 == ~t1_pc~0); 4739436#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 4739434#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4739432#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4739430#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 4739428#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4739424#L458-30 assume !(1 == ~t2_pc~0); 4739422#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 4739420#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4739417#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4739415#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 4739413#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4739411#L477-30 assume !(1 == ~t3_pc~0); 4739409#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 4739407#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4739405#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4739403#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 4739401#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4739399#L496-30 assume !(1 == ~t4_pc~0); 4739395#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 4739393#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4739392#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4739390#L1095-30 assume !(0 != activate_threads_~tmp___3~0); 4739388#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4739384#L515-30 assume !(1 == ~t5_pc~0); 4739382#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 4739380#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4739378#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4739376#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 4739374#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4739372#L534-30 assume !(1 == ~t6_pc~0); 4739370#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 4739368#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4739366#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4739364#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 4739361#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4739359#L553-30 assume !(1 == ~t7_pc~0); 4739356#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 4739354#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4739352#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4739350#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 4739348#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4739346#L572-30 assume !(1 == ~t8_pc~0); 4739344#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 4739342#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4739340#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4739338#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 4739336#L1127-32 assume !(1 == ~M_E~0); 4739152#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4739333#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4739331#L964-3 assume !(1 == ~T3_E~0); 4739330#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4739329#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4739327#L979-3 assume !(1 == ~T6_E~0); 4739325#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4739323#L989-3 assume !(1 == ~T8_E~0); 4739321#L994-3 assume !(1 == ~E_M~0); 4739319#L999-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4739317#L1004-3 assume !(1 == ~E_2~0); 4739315#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4739313#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4739311#L1019-3 assume !(1 == ~E_5~0); 4739309#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4739306#L1029-3 assume !(1 == ~E_7~0); 4739304#L1034-3 assume !(1 == ~E_8~0); 4739302#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4739299#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4739297#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4739295#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4739292#L1324 assume !(0 == start_simulation_~tmp~3); 4739293#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4740208#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4740206#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4740204#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4740202#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4740201#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 4740200#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4740196#L1337 assume !(0 != start_simulation_~tmp___0~1); 4740194#L1305-1 assume !false; 4672034#L1306 [2019-12-07 13:01:19,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:19,361 INFO L82 PathProgramCache]: Analyzing trace with hash -642437461, now seen corresponding path program 2 times [2019-12-07 13:01:19,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:19,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432553826] [2019-12-07 13:01:19,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:19,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:19,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:19,381 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:19,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:19,382 INFO L82 PathProgramCache]: Analyzing trace with hash -2123414276, now seen corresponding path program 1 times [2019-12-07 13:01:19,382 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:19,382 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935401605] [2019-12-07 13:01:19,382 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:19,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:19,412 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:19,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935401605] [2019-12-07 13:01:19,412 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:19,413 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:19,413 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244080442] [2019-12-07 13:01:19,413 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:01:19,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:19,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:19,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:19,413 INFO L87 Difference]: Start difference. First operand 209249 states and 266127 transitions. cyclomatic complexity: 56958 Second operand 3 states. [2019-12-07 13:01:19,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:19,824 INFO L93 Difference]: Finished difference Result 205793 states and 258925 transitions. [2019-12-07 13:01:19,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:19,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205793 states and 258925 transitions. [2019-12-07 13:01:20,447 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 124368 [2019-12-07 13:01:20,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205793 states to 205793 states and 258925 transitions. [2019-12-07 13:01:20,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125377 [2019-12-07 13:01:20,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125377 [2019-12-07 13:01:20,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205793 states and 258925 transitions. [2019-12-07 13:01:20,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:20,886 INFO L688 BuchiCegarLoop]: Abstraction has 205793 states and 258925 transitions. [2019-12-07 13:01:20,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205793 states and 258925 transitions. [2019-12-07 13:01:22,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205793 to 205793. [2019-12-07 13:01:22,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205793 states. [2019-12-07 13:01:22,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205793 states to 205793 states and 258925 transitions. [2019-12-07 13:01:22,618 INFO L711 BuchiCegarLoop]: Abstraction has 205793 states and 258925 transitions. [2019-12-07 13:01:22,618 INFO L591 BuchiCegarLoop]: Abstraction has 205793 states and 258925 transitions. [2019-12-07 13:01:22,618 INFO L424 BuchiCegarLoop]: ======== Iteration 38============ [2019-12-07 13:01:22,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 205793 states and 258925 transitions. [2019-12-07 13:01:23,034 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 124368 [2019-12-07 13:01:23,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:23,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:23,037 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:23,037 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:23,037 INFO L794 eck$LassoCheckResult]: Stem: 5065803#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 5065643#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5065644#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5066111#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 5064834#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5064835#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5066321#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5066112#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5065553#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5065554#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5066517#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5066040#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5065341#L639-1 assume !(0 == ~M_E~0); 5065342#L856-1 assume !(0 == ~T1_E~0); 5065568#L861-1 assume !(0 == ~T2_E~0); 5065569#L866-1 assume !(0 == ~T3_E~0); 5066569#L871-1 assume !(0 == ~T4_E~0); 5066086#L876-1 assume !(0 == ~T5_E~0); 5065767#L881-1 assume !(0 == ~T6_E~0); 5065098#L886-1 assume !(0 == ~T7_E~0); 5065099#L891-1 assume !(0 == ~T8_E~0); 5066240#L896-1 assume !(0 == ~E_M~0); 5065698#L901-1 assume !(0 == ~E_1~0); 5065021#L906-1 assume !(0 == ~E_2~0); 5065022#L911-1 assume !(0 == ~E_3~0); 5066682#L916-1 assume !(0 == ~E_4~0); 5065919#L921-1 assume !(0 == ~E_5~0); 5065226#L926-1 assume !(0 == ~E_6~0); 5065227#L931-1 assume !(0 == ~E_7~0); 5066831#L936-1 assume !(0 == ~E_8~0); 5066409#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5065154#L420 assume !(1 == ~m_pc~0); 5065155#L420-2 is_master_triggered_~__retres1~0 := 0; 5065165#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5067067#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5067020#L1063 assume !(0 != activate_threads_~tmp~1); 5067021#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5065677#L439 assume !(1 == ~t1_pc~0); 5065678#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 5065683#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5066752#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5066651#L1071 assume !(0 != activate_threads_~tmp___0~0); 5066625#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5066053#L458 assume !(1 == ~t2_pc~0); 5066008#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 5066009#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5066988#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5065787#L1079 assume !(0 != activate_threads_~tmp___1~0); 5065788#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5065791#L477 assume !(1 == ~t3_pc~0); 5066299#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 5064961#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5064962#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5065134#L1087 assume !(0 != activate_threads_~tmp___2~0); 5067047#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5066620#L496 assume !(1 == ~t4_pc~0); 5066527#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 5065357#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5065358#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5066430#L1095 assume !(0 != activate_threads_~tmp___3~0); 5066431#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5066432#L515 assume !(1 == ~t5_pc~0); 5067025#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 5066093#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5065697#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5065628#L1103 assume !(0 != activate_threads_~tmp___4~0); 5065592#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5065071#L534 assume !(1 == ~t6_pc~0); 5065056#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 5065057#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5066043#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5066044#L1111 assume !(0 != activate_threads_~tmp___5~0); 5066709#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5065518#L553 assume !(1 == ~t7_pc~0); 5065018#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 5065528#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5066322#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5065996#L1119 assume !(0 != activate_threads_~tmp___6~0); 5065953#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5065874#L572 assume !(1 == ~t8_pc~0); 5065875#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 5065878#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5066615#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5064899#L1127 assume !(0 != activate_threads_~tmp___7~0); 5064900#L1127-2 assume !(1 == ~M_E~0); 5064901#L954-1 assume !(1 == ~T1_E~0); 5066562#L959-1 assume !(1 == ~T2_E~0); 5066083#L964-1 assume !(1 == ~T3_E~0); 5065751#L969-1 assume !(1 == ~T4_E~0); 5065092#L974-1 assume !(1 == ~T5_E~0); 5065093#L979-1 assume !(1 == ~T6_E~0); 5066230#L984-1 assume !(1 == ~T7_E~0); 5065705#L989-1 assume !(1 == ~T8_E~0); 5065390#L994-1 assume !(1 == ~E_M~0); 5065391#L999-1 assume !(1 == ~E_1~0); 5066690#L1004-1 assume !(1 == ~E_2~0); 5065964#L1009-1 assume !(1 == ~E_3~0); 5065245#L1014-1 assume !(1 == ~E_4~0); 5065246#L1019-1 assume !(1 == ~E_5~0); 5066838#L1024-1 assume !(1 == ~E_6~0); 5066402#L1029-1 assume !(1 == ~E_7~0); 5065893#L1034-1 assume !(1 == ~E_8~0); 5065894#L1305-1 assume !false; 5069307#L1306 [2019-12-07 13:01:23,037 INFO L796 eck$LassoCheckResult]: Loop: 5069307#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 5157749#L831 assume !false; 5157748#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5157747#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5157746#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5157745#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5157744#L714 assume 0 != eval_~tmp~0; 5157743#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5157741#L722 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 5157742#L76 assume 0 == ~m_pc~0; 5177009#L112 assume !false; 5177008#L88 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5177007#L420-3 assume !(1 == ~m_pc~0); 5177004#L420-5 is_master_triggered_~__retres1~0 := 0; 5177003#L431-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5176999#L432-1 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5176997#L1063-3 assume !(0 != activate_threads_~tmp~1); 5176994#L1063-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5176992#L439-3 assume !(1 == ~t1_pc~0); 5176988#L439-5 is_transmit1_triggered_~__retres1~1 := 0; 5176986#L450-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5176983#L451-1 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5176981#L1071-3 assume !(0 != activate_threads_~tmp___0~0); 5176979#L1071-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5176978#L458-3 assume !(1 == ~t2_pc~0); 5148662#L458-5 is_transmit2_triggered_~__retres1~2 := 0; 5148660#L469-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5148659#L470-1 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5148657#L1079-3 assume !(0 != activate_threads_~tmp___1~0); 5148658#L1079-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5169447#L477-3 assume !(1 == ~t3_pc~0); 5169445#L477-5 is_transmit3_triggered_~__retres1~3 := 0; 5148643#L488-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5148640#L489-1 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5148641#L1087-3 assume !(0 != activate_threads_~tmp___2~0); 5148633#L1087-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5148632#L496-3 assume 1 == ~t4_pc~0; 5148631#L497-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5148628#L507-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5148625#L508-1 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5148626#L1095-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5156238#L1095-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5156237#L515-3 assume !(1 == ~t5_pc~0); 5156236#L515-5 is_transmit5_triggered_~__retres1~5 := 0; 5156235#L526-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5156234#L527-1 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5156233#L1103-3 assume !(0 != activate_threads_~tmp___4~0); 5156232#L1103-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5156231#L534-3 assume !(1 == ~t6_pc~0); 5156230#L534-5 is_transmit6_triggered_~__retres1~6 := 0; 5156229#L545-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5156228#L546-1 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5156227#L1111-3 assume !(0 != activate_threads_~tmp___5~0); 5156226#L1111-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5156225#L553-3 assume !(1 == ~t7_pc~0); 5156223#L553-5 is_transmit7_triggered_~__retres1~7 := 0; 5156222#L564-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5156221#L565-1 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5156218#L1119-3 assume !(0 != activate_threads_~tmp___6~0); 5156216#L1119-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5156214#L572-3 assume !(1 == ~t8_pc~0); 5156211#L572-5 is_transmit8_triggered_~__retres1~8 := 0; 5156209#L583-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5156207#L584-1 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5156202#L1127-3 assume !(0 != activate_threads_~tmp___7~0); 5156200#L1127-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 5156197#L719 assume !(0 == ~t1_st~0); 5148485#L733 assume !(0 == ~t2_st~0); 5148486#L747 assume !(0 == ~t3_st~0); 5149342#L761 assume !(0 == ~t4_st~0); 5149340#L775 assume !(0 == ~t5_st~0); 5149324#L789 assume !(0 == ~t6_st~0); 5149294#L803 assume !(0 == ~t7_st~0); 5148671#L817 assume !(0 == ~t8_st~0); 5148668#L831 assume !false; 5148663#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5148664#L652 assume !(0 == ~m_st~0); 5149221#L656 assume !(0 == ~t1_st~0); 5149219#L660 assume !(0 == ~t2_st~0); 5149217#L664 assume !(0 == ~t3_st~0); 5149214#L668 assume !(0 == ~t4_st~0); 5149212#L672 assume !(0 == ~t5_st~0); 5149210#L676 assume !(0 == ~t6_st~0); 5149208#L680 assume !(0 == ~t7_st~0); 5149205#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 5149203#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5149201#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5149199#L714 assume !(0 != eval_~tmp~0); 5149197#L846 start_simulation_~kernel_st~0 := 2; 5149195#L592-1 start_simulation_~kernel_st~0 := 3; 5149193#L856-2 assume !(0 == ~M_E~0); 5149192#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5149191#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5149190#L866-3 assume !(0 == ~T3_E~0); 5149189#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5149187#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5149186#L881-3 assume !(0 == ~T6_E~0); 5149185#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5149184#L891-3 assume !(0 == ~T8_E~0); 5149183#L896-3 assume !(0 == ~E_M~0); 5149178#L901-3 assume !(0 == ~E_1~0); 5149176#L906-3 assume !(0 == ~E_2~0); 5149175#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5149174#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5149172#L921-3 assume !(0 == ~E_5~0); 5149170#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5149169#L931-3 assume !(0 == ~E_7~0); 5149168#L936-3 assume !(0 == ~E_8~0); 5149166#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5149163#L420-30 assume 1 == ~m_pc~0; 5149160#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5149158#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5149153#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5149150#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5149148#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5149146#L439-30 assume !(1 == ~t1_pc~0); 5149144#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 5149142#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5149140#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5149138#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 5149137#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5149004#L458-30 assume !(1 == ~t2_pc~0); 5149002#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 5149000#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5148997#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5148995#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 5148993#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5148991#L477-30 assume !(1 == ~t3_pc~0); 5148989#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 5148987#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5148985#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5148983#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 5148981#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5148979#L496-30 assume !(1 == ~t4_pc~0); 5148975#L496-32 is_transmit4_triggered_~__retres1~4 := 0; 5148973#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5148972#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5148971#L1095-30 assume !(0 != activate_threads_~tmp___3~0); 5148966#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5148964#L515-30 assume !(1 == ~t5_pc~0); 5148962#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 5148960#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5148957#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5148955#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 5148953#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5148951#L534-30 assume !(1 == ~t6_pc~0); 5148949#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 5148947#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5148945#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5148943#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 5148941#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5148939#L553-30 assume !(1 == ~t7_pc~0); 5148936#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 5148934#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5148932#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5148930#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 5148927#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5148925#L572-30 assume !(1 == ~t8_pc~0); 5148923#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 5148921#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5148919#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5148917#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 5148915#L1127-32 assume !(1 == ~M_E~0); 5148911#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5148909#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5148907#L964-3 assume !(1 == ~T3_E~0); 5148905#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5148902#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5148900#L979-3 assume !(1 == ~T6_E~0); 5148898#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5148896#L989-3 assume !(1 == ~T8_E~0); 5148894#L994-3 assume !(1 == ~E_M~0); 5148887#L999-3 assume !(1 == ~E_1~0); 5148886#L1004-3 assume !(1 == ~E_2~0); 5148885#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5148884#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5148883#L1019-3 assume !(1 == ~E_5~0); 5148880#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5148878#L1029-3 assume !(1 == ~E_7~0); 5148876#L1034-3 assume !(1 == ~E_8~0); 5148874#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5148871#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5148872#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5157856#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5148864#L1324 assume !(0 == start_simulation_~tmp~3); 5148860#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5148858#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5148856#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5148854#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5148852#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5148850#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 5148848#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5148845#L1337 assume !(0 != start_simulation_~tmp___0~1); 5148846#L1305-1 assume !false; 5069307#L1306 [2019-12-07 13:01:23,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:23,038 INFO L82 PathProgramCache]: Analyzing trace with hash -642437461, now seen corresponding path program 3 times [2019-12-07 13:01:23,038 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:23,038 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081012280] [2019-12-07 13:01:23,038 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:23,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:23,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:23,064 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:23,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:23,065 INFO L82 PathProgramCache]: Analyzing trace with hash 1589067483, now seen corresponding path program 1 times [2019-12-07 13:01:23,065 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:23,065 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303050915] [2019-12-07 13:01:23,065 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:23,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:23,100 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:23,100 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303050915] [2019-12-07 13:01:23,100 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:23,100 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:23,101 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522664688] [2019-12-07 13:01:23,101 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:01:23,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:23,101 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:23,101 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:23,101 INFO L87 Difference]: Start difference. First operand 205793 states and 258925 transitions. cyclomatic complexity: 53212 Second operand 3 states. [2019-12-07 13:01:23,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:23,729 INFO L93 Difference]: Finished difference Result 379409 states and 474845 transitions. [2019-12-07 13:01:23,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:23,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 379409 states and 474845 transitions. [2019-12-07 13:01:24,809 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 229536 [2019-12-07 13:01:25,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 379409 states to 379409 states and 474845 transitions. [2019-12-07 13:01:25,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231441 [2019-12-07 13:01:25,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231441 [2019-12-07 13:01:25,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 379409 states and 474845 transitions. [2019-12-07 13:01:25,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:25,909 INFO L688 BuchiCegarLoop]: Abstraction has 379409 states and 474845 transitions. [2019-12-07 13:01:26,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379409 states and 474845 transitions. [2019-12-07 13:01:27,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379409 to 368977. [2019-12-07 13:01:27,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368977 states. [2019-12-07 13:01:28,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368977 states to 368977 states and 463101 transitions. [2019-12-07 13:01:28,234 INFO L711 BuchiCegarLoop]: Abstraction has 368977 states and 463101 transitions. [2019-12-07 13:01:28,234 INFO L591 BuchiCegarLoop]: Abstraction has 368977 states and 463101 transitions. [2019-12-07 13:01:28,234 INFO L424 BuchiCegarLoop]: ======== Iteration 39============ [2019-12-07 13:01:28,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368977 states and 463101 transitions. [2019-12-07 13:01:30,467 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 223264 [2019-12-07 13:01:30,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:30,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:30,468 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:30,468 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:30,469 INFO L794 eck$LassoCheckResult]: Stem: 5651012#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 5650857#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5650858#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5651301#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 5650042#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5650043#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5651514#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5651302#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5650772#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5650773#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5651724#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5651227#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5650560#L639-1 assume !(0 == ~M_E~0); 5650561#L856-1 assume !(0 == ~T1_E~0); 5650786#L861-1 assume !(0 == ~T2_E~0); 5650787#L866-1 assume !(0 == ~T3_E~0); 5651779#L871-1 assume !(0 == ~T4_E~0); 5651273#L876-1 assume !(0 == ~T5_E~0); 5650980#L881-1 assume !(0 == ~T6_E~0); 5650313#L886-1 assume !(0 == ~T7_E~0); 5650314#L891-1 assume !(0 == ~T8_E~0); 5651436#L896-1 assume !(0 == ~E_M~0); 5650909#L901-1 assume !(0 == ~E_1~0); 5650231#L906-1 assume !(0 == ~E_2~0); 5650232#L911-1 assume !(0 == ~E_3~0); 5651893#L916-1 assume !(0 == ~E_4~0); 5651108#L921-1 assume !(0 == ~E_5~0); 5650445#L926-1 assume !(0 == ~E_6~0); 5650446#L931-1 assume !(0 == ~E_7~0); 5652036#L936-1 assume !(0 == ~E_8~0); 5651611#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5650369#L420 assume !(1 == ~m_pc~0); 5650370#L420-2 is_master_triggered_~__retres1~0 := 0; 5650380#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5652259#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5652214#L1063 assume !(0 != activate_threads_~tmp~1); 5652215#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5650890#L439 assume !(1 == ~t1_pc~0); 5650891#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 5650897#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5651966#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5651866#L1071 assume !(0 != activate_threads_~tmp___0~0); 5651841#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5651240#L458 assume !(1 == ~t2_pc~0); 5651193#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 5651194#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5652199#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5650999#L1079 assume !(0 != activate_threads_~tmp___1~0); 5651000#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5651004#L477 assume !(1 == ~t3_pc~0); 5651493#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 5650170#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5650171#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5650348#L1087 assume !(0 != activate_threads_~tmp___2~0); 5652235#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5651835#L496 assume !(1 == ~t4_pc~0); 5651734#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 5650575#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5650576#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5651633#L1095 assume !(0 != activate_threads_~tmp___3~0); 5651634#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5651635#L515 assume !(1 == ~t5_pc~0); 5652216#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 5651282#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5650908#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5650838#L1103 assume !(0 != activate_threads_~tmp___4~0); 5650808#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5650286#L534 assume !(1 == ~t6_pc~0); 5650268#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 5650269#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5651230#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5651231#L1111 assume !(0 != activate_threads_~tmp___5~0); 5651922#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5650734#L553 assume !(1 == ~t7_pc~0); 5650228#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 5650744#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5651515#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5651182#L1119 assume !(0 != activate_threads_~tmp___6~0); 5651143#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5651068#L572 assume !(1 == ~t8_pc~0); 5651069#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 5651072#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5651830#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5650108#L1127 assume !(0 != activate_threads_~tmp___7~0); 5650109#L1127-2 assume !(1 == ~M_E~0); 5650110#L954-1 assume !(1 == ~T1_E~0); 5651772#L959-1 assume !(1 == ~T2_E~0); 5651270#L964-1 assume !(1 == ~T3_E~0); 5650966#L969-1 assume !(1 == ~T4_E~0); 5650307#L974-1 assume !(1 == ~T5_E~0); 5650308#L979-1 assume !(1 == ~T6_E~0); 5651428#L984-1 assume !(1 == ~T7_E~0); 5650916#L989-1 assume !(1 == ~T8_E~0); 5650605#L994-1 assume !(1 == ~E_M~0); 5650606#L999-1 assume !(1 == ~E_1~0); 5651901#L1004-1 assume !(1 == ~E_2~0); 5651154#L1009-1 assume !(1 == ~E_3~0); 5650459#L1014-1 assume !(1 == ~E_4~0); 5650460#L1019-1 assume !(1 == ~E_5~0); 5652049#L1024-1 assume !(1 == ~E_6~0); 5651603#L1029-1 assume !(1 == ~E_7~0); 5651085#L1034-1 assume !(1 == ~E_8~0); 5651086#L1305-1 assume !false; 5657083#L1306 [2019-12-07 13:01:30,469 INFO L796 eck$LassoCheckResult]: Loop: 5657083#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 5798490#L831 assume !false; 5798488#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5798486#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5798482#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5798480#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5798478#L714 assume 0 != eval_~tmp~0; 5798476#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5798473#L722 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;havoc master_#t~nondet0, master_#t~nondet1, master_~tmp_var~0;master_~tmp_var~0 := master_#t~nondet0;havoc master_#t~nondet0; 5798471#L76 assume 0 == ~m_pc~0; 5798464#L112 assume !false; 5798462#L88 ~token~0 := master_#t~nondet1;havoc master_#t~nondet1;~local~0 := ~token~0;~E_1~0 := 1;havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5798460#L420-3 assume !(1 == ~m_pc~0); 5798456#L420-5 is_master_triggered_~__retres1~0 := 0; 5798454#L431-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5798452#L432-1 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5798450#L1063-3 assume !(0 != activate_threads_~tmp~1); 5798447#L1063-5 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5798444#L439-3 assume !(1 == ~t1_pc~0); 5798442#L439-5 is_transmit1_triggered_~__retres1~1 := 0; 5798440#L450-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5798438#L451-1 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5798436#L1071-3 assume !(0 != activate_threads_~tmp___0~0); 5798434#L1071-5 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5798432#L458-3 assume !(1 == ~t2_pc~0); 5798429#L458-5 is_transmit2_triggered_~__retres1~2 := 0; 5798427#L469-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5798425#L470-1 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5798423#L1079-3 assume !(0 != activate_threads_~tmp___1~0); 5798422#L1079-5 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5798421#L477-3 assume !(1 == ~t3_pc~0); 5798419#L477-5 is_transmit3_triggered_~__retres1~3 := 0; 5798417#L488-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5798416#L489-1 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5798415#L1087-3 assume !(0 != activate_threads_~tmp___2~0); 5798414#L1087-5 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5798412#L496-3 assume !(1 == ~t4_pc~0); 5798408#L496-5 is_transmit4_triggered_~__retres1~4 := 0; 5798420#L507-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5798418#L508-1 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5798342#L1095-3 assume !(0 != activate_threads_~tmp___3~0); 5798329#L1095-5 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5798319#L515-3 assume !(1 == ~t5_pc~0); 5798312#L515-5 is_transmit5_triggered_~__retres1~5 := 0; 5798306#L526-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5798300#L527-1 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5798291#L1103-3 assume !(0 != activate_threads_~tmp___4~0); 5798285#L1103-5 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5798279#L534-3 assume !(1 == ~t6_pc~0); 5798274#L534-5 is_transmit6_triggered_~__retres1~6 := 0; 5798270#L545-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5798269#L546-1 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5798268#L1111-3 assume !(0 != activate_threads_~tmp___5~0); 5798266#L1111-5 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5798263#L553-3 assume !(1 == ~t7_pc~0); 5798252#L553-5 is_transmit7_triggered_~__retres1~7 := 0; 5798243#L564-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5798233#L565-1 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5798224#L1119-3 assume !(0 != activate_threads_~tmp___6~0); 5798217#L1119-5 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5798211#L572-3 assume !(1 == ~t8_pc~0); 5798205#L572-5 is_transmit8_triggered_~__retres1~8 := 0; 5798196#L583-1 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5798191#L584-1 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5798186#L1127-3 assume !(0 != activate_threads_~tmp___7~0); 5798115#L1127-5 ~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 5798103#L719 assume !(0 == ~t1_st~0); 5798088#L733 assume !(0 == ~t2_st~0); 5798073#L747 assume !(0 == ~t3_st~0); 5798063#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 5797820#L778 assume 0 != eval_~tmp_ndt_5~0;~t4_st~0 := 1; 5797825#L240 assume 0 == ~t4_pc~0; 5797823#L251-1 assume !false; 5797821#L252 ~t4_pc~0 := 1;~t4_st~0 := 2; 5797817#L775 assume !(0 == ~t5_st~0); 5797808#L789 assume !(0 == ~t6_st~0); 5797805#L803 assume !(0 == ~t7_st~0); 5797799#L817 assume !(0 == ~t8_st~0); 5797796#L831 assume !false; 5797794#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5797793#L652 assume !(0 == ~m_st~0); 5797791#L656 assume !(0 == ~t1_st~0); 5797789#L660 assume !(0 == ~t2_st~0); 5797787#L664 assume !(0 == ~t3_st~0); 5797784#L668 assume !(0 == ~t4_st~0); 5797782#L672 assume !(0 == ~t5_st~0); 5797780#L676 assume !(0 == ~t6_st~0); 5797777#L680 assume !(0 == ~t7_st~0); 5797774#L684 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 5797772#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5797770#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5797767#L714 assume !(0 != eval_~tmp~0); 5797765#L846 start_simulation_~kernel_st~0 := 2; 5797761#L592-1 start_simulation_~kernel_st~0 := 3; 5797759#L856-2 assume !(0 == ~M_E~0); 5797757#L856-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5797755#L861-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5797752#L866-3 assume !(0 == ~T3_E~0); 5797750#L871-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5797748#L876-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5797744#L881-3 assume !(0 == ~T6_E~0); 5797742#L886-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5797739#L891-3 assume !(0 == ~T8_E~0); 5797738#L896-3 assume !(0 == ~E_M~0); 5797737#L901-3 assume !(0 == ~E_1~0); 5797736#L906-3 assume !(0 == ~E_2~0); 5797735#L911-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5797733#L916-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5797732#L921-3 assume !(0 == ~E_5~0); 5797731#L926-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5797730#L931-3 assume !(0 == ~E_7~0); 5797729#L936-3 assume !(0 == ~E_8~0); 5797728#L941-3 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5797726#L420-30 assume 1 == ~m_pc~0; 5797721#L421-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5797722#L431-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5798743#L432-10 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5798741#L1063-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5798739#L1063-32 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5798737#L439-30 assume !(1 == ~t1_pc~0); 5798735#L439-32 is_transmit1_triggered_~__retres1~1 := 0; 5798733#L450-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5798731#L451-10 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5798729#L1071-30 assume !(0 != activate_threads_~tmp___0~0); 5798727#L1071-32 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5798725#L458-30 assume !(1 == ~t2_pc~0); 5798724#L458-32 is_transmit2_triggered_~__retres1~2 := 0; 5798722#L469-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5798720#L470-10 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5798716#L1079-30 assume !(0 != activate_threads_~tmp___1~0); 5798714#L1079-32 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5798712#L477-30 assume !(1 == ~t3_pc~0); 5798710#L477-32 is_transmit3_triggered_~__retres1~3 := 0; 5798706#L488-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5798704#L489-10 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5798702#L1087-30 assume !(0 != activate_threads_~tmp___2~0); 5798700#L1087-32 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5798698#L496-30 assume 1 == ~t4_pc~0; 5798695#L497-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5798693#L507-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5798691#L508-10 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5798688#L1095-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5798686#L1095-32 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5798684#L515-30 assume !(1 == ~t5_pc~0); 5798682#L515-32 is_transmit5_triggered_~__retres1~5 := 0; 5798680#L526-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5798678#L527-10 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5798675#L1103-30 assume !(0 != activate_threads_~tmp___4~0); 5798673#L1103-32 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5798671#L534-30 assume !(1 == ~t6_pc~0); 5798669#L534-32 is_transmit6_triggered_~__retres1~6 := 0; 5798667#L545-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5798665#L546-10 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5798663#L1111-30 assume !(0 != activate_threads_~tmp___5~0); 5798661#L1111-32 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5798659#L553-30 assume !(1 == ~t7_pc~0); 5798656#L553-32 is_transmit7_triggered_~__retres1~7 := 0; 5798654#L564-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5798651#L565-10 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5798649#L1119-30 assume !(0 != activate_threads_~tmp___6~0); 5798647#L1119-32 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5798645#L572-30 assume !(1 == ~t8_pc~0); 5798643#L572-32 is_transmit8_triggered_~__retres1~8 := 0; 5798641#L583-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5798639#L584-10 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5798637#L1127-30 assume !(0 != activate_threads_~tmp___7~0); 5798635#L1127-32 assume !(1 == ~M_E~0); 5798631#L954-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5798629#L959-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5798627#L964-3 assume !(1 == ~T3_E~0); 5798625#L969-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5798623#L974-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5798621#L979-3 assume !(1 == ~T6_E~0); 5798619#L984-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5798617#L989-3 assume !(1 == ~T8_E~0); 5798616#L994-3 assume !(1 == ~E_M~0); 5798613#L999-3 assume !(1 == ~E_1~0); 5798611#L1004-3 assume !(1 == ~E_2~0); 5798609#L1009-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5798607#L1014-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5798605#L1019-3 assume !(1 == ~E_5~0); 5798603#L1024-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5798601#L1029-3 assume !(1 == ~E_7~0); 5798598#L1034-3 assume !(1 == ~E_8~0); 5798596#L1039-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5798594#L652-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5798592#L699-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5798590#L700-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5798587#L1324 assume !(0 == start_simulation_~tmp~3); 5798584#L1324-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5798582#L652-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5798580#L699-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 5798578#L700-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5798576#L1279 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5798574#L1286 stop_simulation_#res := stop_simulation_~__retres2~0; 5798572#L1287 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5798569#L1337 assume !(0 != start_simulation_~tmp___0~1); 5798567#L1305-1 assume !false; 5657083#L1306 [2019-12-07 13:01:30,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:30,469 INFO L82 PathProgramCache]: Analyzing trace with hash -642437461, now seen corresponding path program 4 times [2019-12-07 13:01:30,469 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:30,469 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87445767] [2019-12-07 13:01:30,470 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:30,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:30,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:30,484 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:30,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:30,485 INFO L82 PathProgramCache]: Analyzing trace with hash 41580070, now seen corresponding path program 1 times [2019-12-07 13:01:30,485 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:30,485 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123704828] [2019-12-07 13:01:30,485 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:30,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:30,519 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 13:01:30,519 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123704828] [2019-12-07 13:01:30,519 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:30,519 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:30,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412984559] [2019-12-07 13:01:30,519 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-12-07 13:01:30,520 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:30,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:30,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:30,520 INFO L87 Difference]: Start difference. First operand 368977 states and 463101 transitions. cyclomatic complexity: 94204 Second operand 3 states. [2019-12-07 13:01:31,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:31,633 INFO L93 Difference]: Finished difference Result 673456 states and 838042 transitions. [2019-12-07 13:01:31,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:31,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 673456 states and 838042 transitions. [2019-12-07 13:01:33,765 INFO L131 ngComponentsAnalysis]: Automaton has 176 accepting balls. 359216 [2019-12-07 13:01:34,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 673456 states to 647344 states and 805626 transitions. [2019-12-07 13:01:34,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 382288 [2019-12-07 13:01:35,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 382288 [2019-12-07 13:01:35,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 647344 states and 805626 transitions. [2019-12-07 13:01:35,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-12-07 13:01:35,094 INFO L688 BuchiCegarLoop]: Abstraction has 647344 states and 805626 transitions. [2019-12-07 13:01:35,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 647344 states and 805626 transitions. [2019-12-07 13:01:38,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 647344 to 646960. [2019-12-07 13:01:38,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 646960 states. [2019-12-07 13:01:45,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 646960 states to 646960 states and 805242 transitions. [2019-12-07 13:01:45,179 INFO L711 BuchiCegarLoop]: Abstraction has 646960 states and 805242 transitions. [2019-12-07 13:01:45,179 INFO L591 BuchiCegarLoop]: Abstraction has 646960 states and 805242 transitions. [2019-12-07 13:01:45,179 INFO L424 BuchiCegarLoop]: ======== Iteration 40============ [2019-12-07 13:01:45,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 646960 states and 805242 transitions. [2019-12-07 13:01:46,104 INFO L131 ngComponentsAnalysis]: Automaton has 176 accepting balls. 358896 [2019-12-07 13:01:46,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:46,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:46,106 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:46,106 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:46,106 INFO L794 eck$LassoCheckResult]: Stem: 6693469#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6693309#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6693310#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6693782#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 6692481#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6692482#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6693991#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6693783#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6693197#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6693198#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6694197#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6693696#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6692993#L639-1 assume !(0 == ~M_E~0); 6692994#L856-1 assume !(0 == ~T1_E~0); 6693214#L861-1 assume !(0 == ~T2_E~0); 6693215#L866-1 assume !(0 == ~T3_E~0); 6694259#L871-1 assume !(0 == ~T4_E~0); 6693752#L876-1 assume !(0 == ~T5_E~0); 6693428#L881-1 assume !(0 == ~T6_E~0); 6692749#L886-1 assume !(0 == ~T7_E~0); 6692750#L891-1 assume !(0 == ~T8_E~0); 6693902#L896-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6693903#L901-1 assume !(0 == ~E_1~0); 6694804#L906-1 assume !(0 == ~E_2~0); 6694802#L911-1 assume !(0 == ~E_3~0); 6694390#L916-1 assume !(0 == ~E_4~0); 6694391#L921-1 assume !(0 == ~E_5~0); 6694796#L926-1 assume !(0 == ~E_6~0); 6694795#L931-1 assume !(0 == ~E_7~0); 6694547#L936-1 assume !(0 == ~E_8~0); 6694548#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6692801#L420 assume !(1 == ~m_pc~0); 6692802#L420-2 is_master_triggered_~__retres1~0 := 0; 6692812#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6694381#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6694382#L1063 assume !(0 != activate_threads_~tmp~1); 6694735#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6694736#L439 assume !(1 == ~t1_pc~0); 6694812#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 6694478#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6694479#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6694355#L1071 assume !(0 != activate_threads_~tmp___0~0); 6694356#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6693709#L458 assume !(1 == ~t2_pc~0); 6693710#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 6694706#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6694707#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6693447#L1079 assume !(0 != activate_threads_~tmp___1~0); 6693448#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6693964#L477 assume !(1 == ~t3_pc~0); 6693965#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 6693972#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6692780#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6692781#L1087 assume !(0 != activate_threads_~tmp___2~0); 6694763#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6694764#L496 assume !(1 == ~t4_pc~0); 6694208#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 6694289#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6694791#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6694792#L1095 assume !(0 != activate_threads_~tmp___3~0); 6694110#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6694111#L515 assume !(1 == ~t5_pc~0); 6694743#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 6694744#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6693357#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6693286#L1103 assume !(0 != activate_threads_~tmp___4~0); 6693246#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6693247#L534 assume !(1 == ~t6_pc~0); 6694807#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 6694060#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6694061#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6694423#L1111 assume !(0 != activate_threads_~tmp___5~0); 6694424#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6693149#L553 assume !(1 == ~t7_pc~0); 6692662#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 6694378#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6693994#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6693995#L1119 assume !(0 != activate_threads_~tmp___6~0); 6693607#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6693608#L572 assume !(1 == ~t8_pc~0); 6693537#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 6693538#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6694310#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6694311#L1127 assume !(0 != activate_threads_~tmp___7~0); 6692545#L1127-2 assume !(1 == ~M_E~0); 6692546#L954-1 assume !(1 == ~T1_E~0); 6694605#L959-1 assume !(1 == ~T2_E~0); 6694800#L964-1 assume !(1 == ~T3_E~0); 6693414#L969-1 assume !(1 == ~T4_E~0); 6693415#L974-1 assume !(1 == ~T5_E~0); 6694598#L979-1 assume !(1 == ~T6_E~0); 6693897#L984-1 assume !(1 == ~T7_E~0); 6693365#L989-1 assume !(1 == ~T8_E~0); 6693039#L994-1 assume 1 == ~E_M~0;~E_M~0 := 2; 6693040#L999-1 assume !(1 == ~E_1~0); 6694400#L1004-1 assume !(1 == ~E_2~0); 6693620#L1009-1 assume !(1 == ~E_3~0); 6692897#L1014-1 assume !(1 == ~E_4~0); 6692898#L1019-1 assume !(1 == ~E_5~0); 6694556#L1024-1 assume !(1 == ~E_6~0); 6694079#L1029-1 assume !(1 == ~E_7~0); 6693550#L1034-1 assume !(1 == ~E_8~0); 6693551#L1305-1 assume !false; 6726445#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 6726443#L831 [2019-12-07 13:01:46,106 INFO L796 eck$LassoCheckResult]: Loop: 6726443#L831 assume !false; 6726441#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6726439#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6726437#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6726435#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 6726433#L714 assume 0 != eval_~tmp~0; 6726431#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 6726428#L722 assume !(0 != eval_~tmp_ndt_1~0); 6726426#L719 assume !(0 == ~t1_st~0); 6726281#L733 assume !(0 == ~t2_st~0); 6726279#L747 assume !(0 == ~t3_st~0); 6723708#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 6723706#L778 assume !(0 != eval_~tmp_ndt_5~0); 6723699#L775 assume !(0 == ~t5_st~0); 6723693#L789 assume !(0 == ~t6_st~0); 6726454#L803 assume !(0 == ~t7_st~0); 6726446#L817 assume !(0 == ~t8_st~0); 6726443#L831 [2019-12-07 13:01:46,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:46,106 INFO L82 PathProgramCache]: Analyzing trace with hash -466645086, now seen corresponding path program 1 times [2019-12-07 13:01:46,106 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:46,106 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631474572] [2019-12-07 13:01:46,106 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:46,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:46,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:46,123 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631474572] [2019-12-07 13:01:46,123 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:46,123 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:01:46,123 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322180509] [2019-12-07 13:01:46,123 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:01:46,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:46,123 INFO L82 PathProgramCache]: Analyzing trace with hash -1613288712, now seen corresponding path program 1 times [2019-12-07 13:01:46,123 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:46,123 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213628375] [2019-12-07 13:01:46,123 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:46,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:46,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:46,127 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:46,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:46,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:46,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:46,186 INFO L87 Difference]: Start difference. First operand 646960 states and 805242 transitions. cyclomatic complexity: 158490 Second operand 3 states. [2019-12-07 13:01:46,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:46,648 INFO L93 Difference]: Finished difference Result 260512 states and 323592 transitions. [2019-12-07 13:01:46,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:46,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 260512 states and 323592 transitions. [2019-12-07 13:01:47,353 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 159408 [2019-12-07 13:01:47,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 260512 states to 165983 states and 206054 transitions. [2019-12-07 13:01:47,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 165983 [2019-12-07 13:01:47,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 165983 [2019-12-07 13:01:47,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 165983 states and 206054 transitions. [2019-12-07 13:01:47,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:01:47,815 INFO L688 BuchiCegarLoop]: Abstraction has 165983 states and 206054 transitions. [2019-12-07 13:01:47,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165983 states and 206054 transitions. [2019-12-07 13:01:49,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165983 to 118103. [2019-12-07 13:01:49,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118103 states. [2019-12-07 13:01:49,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118103 states to 118103 states and 146150 transitions. [2019-12-07 13:01:49,191 INFO L711 BuchiCegarLoop]: Abstraction has 118103 states and 146150 transitions. [2019-12-07 13:01:49,191 INFO L591 BuchiCegarLoop]: Abstraction has 118103 states and 146150 transitions. [2019-12-07 13:01:49,192 INFO L424 BuchiCegarLoop]: ======== Iteration 41============ [2019-12-07 13:01:49,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118103 states and 146150 transitions. [2019-12-07 13:01:49,452 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 114424 [2019-12-07 13:01:49,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:49,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:49,453 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:49,453 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:49,453 INFO L794 eck$LassoCheckResult]: Stem: 7600453#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 7600373#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7600374#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7600606#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 7599955#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7599956#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7600698#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7600607#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7600327#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7600328#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7600813#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7600565#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7600228#L639-1 assume !(0 == ~M_E~0); 7600229#L856-1 assume !(0 == ~T1_E~0); 7600333#L861-1 assume !(0 == ~T2_E~0); 7600334#L866-1 assume !(0 == ~T3_E~0); 7600846#L871-1 assume !(0 == ~T4_E~0); 7600592#L876-1 assume !(0 == ~T5_E~0); 7600434#L881-1 assume !(0 == ~T6_E~0); 7600098#L886-1 assume !(0 == ~T7_E~0); 7600099#L891-1 assume !(0 == ~T8_E~0); 7600663#L896-1 assume !(0 == ~E_M~0); 7600399#L901-1 assume !(0 == ~E_1~0); 7600054#L906-1 assume !(0 == ~E_2~0); 7600055#L911-1 assume !(0 == ~E_3~0); 7600905#L916-1 assume !(0 == ~E_4~0); 7600506#L921-1 assume !(0 == ~E_5~0); 7600168#L926-1 assume !(0 == ~E_6~0); 7600169#L931-1 assume !(0 == ~E_7~0); 7600977#L936-1 assume !(0 == ~E_8~0); 7600747#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7600128#L420 assume !(1 == ~m_pc~0); 7600129#L420-2 is_master_triggered_~__retres1~0 := 0; 7600135#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7600831#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7600900#L1063 assume !(0 != activate_threads_~tmp~1); 7601063#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7600388#L439 assume !(1 == ~t1_pc~0); 7600389#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 7600392#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7600949#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7600888#L1071 assume !(0 != activate_threads_~tmp___0~0); 7600874#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7600573#L458 assume !(1 == ~t2_pc~0); 7600547#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 7600548#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7601053#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7600443#L1079 assume !(0 != activate_threads_~tmp___1~0); 7600444#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7600446#L477 assume !(1 == ~t3_pc~0); 7600687#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 7600024#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7600025#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7600117#L1087 assume !(0 != activate_threads_~tmp___2~0); 7601071#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7600871#L496 assume !(1 == ~t4_pc~0); 7600820#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 7600239#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7600240#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7600759#L1095 assume !(0 != activate_threads_~tmp___3~0); 7600760#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7600761#L515 assume !(1 == ~t5_pc~0); 7601065#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 7600597#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7600398#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7600360#L1103 assume !(0 != activate_threads_~tmp___4~0); 7600345#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7600083#L534 assume !(1 == ~t6_pc~0); 7600074#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 7600075#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7600567#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7600568#L1111 assume !(0 != activate_threads_~tmp___5~0); 7600922#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7600309#L553 assume !(1 == ~t7_pc~0); 7600052#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 7600315#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7600700#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7600541#L1119 assume !(0 != activate_threads_~tmp___6~0); 7600520#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7600482#L572 assume !(1 == ~t8_pc~0); 7600483#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 7600485#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7600868#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7599987#L1127 assume !(0 != activate_threads_~tmp___7~0); 7599988#L1127-2 assume !(1 == ~M_E~0); 7599989#L954-1 assume !(1 == ~T1_E~0); 7600843#L959-1 assume !(1 == ~T2_E~0); 7600590#L964-1 assume !(1 == ~T3_E~0); 7600428#L969-1 assume !(1 == ~T4_E~0); 7600094#L974-1 assume !(1 == ~T5_E~0); 7600095#L979-1 assume !(1 == ~T6_E~0); 7600661#L984-1 assume !(1 == ~T7_E~0); 7600403#L989-1 assume !(1 == ~T8_E~0); 7600252#L994-1 assume !(1 == ~E_M~0); 7600253#L999-1 assume !(1 == ~E_1~0); 7600909#L1004-1 assume !(1 == ~E_2~0); 7600526#L1009-1 assume !(1 == ~E_3~0); 7600178#L1014-1 assume !(1 == ~E_4~0); 7600179#L1019-1 assume !(1 == ~E_5~0); 7600982#L1024-1 assume !(1 == ~E_6~0); 7600742#L1029-1 assume !(1 == ~E_7~0); 7600491#L1034-1 assume !(1 == ~E_8~0); 7600492#L1305-1 assume !false; 7606793#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 7606792#L831 [2019-12-07 13:01:49,453 INFO L796 eck$LassoCheckResult]: Loop: 7606792#L831 assume !false; 7606790#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7606788#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7606787#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 7606786#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7606784#L714 assume 0 != eval_~tmp~0; 7606783#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7606781#L722 assume !(0 != eval_~tmp_ndt_1~0); 7606780#L719 assume !(0 == ~t1_st~0); 7606360#L733 assume !(0 == ~t2_st~0); 7606339#L747 assume !(0 == ~t3_st~0); 7606128#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 7606126#L778 assume !(0 != eval_~tmp_ndt_5~0); 7606124#L775 assume !(0 == ~t5_st~0); 7606122#L789 assume !(0 == ~t6_st~0); 7606799#L803 assume !(0 == ~t7_st~0); 7606794#L817 assume !(0 == ~t8_st~0); 7606792#L831 [2019-12-07 13:01:49,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:49,454 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 1 times [2019-12-07 13:01:49,454 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:49,454 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008566041] [2019-12-07 13:01:49,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:49,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:49,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:49,473 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:49,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:49,473 INFO L82 PathProgramCache]: Analyzing trace with hash -1613288712, now seen corresponding path program 2 times [2019-12-07 13:01:49,473 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:49,473 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278395336] [2019-12-07 13:01:49,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:49,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:49,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:49,477 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:49,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:49,477 INFO L82 PathProgramCache]: Analyzing trace with hash 793919731, now seen corresponding path program 1 times [2019-12-07 13:01:49,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:49,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694647454] [2019-12-07 13:01:49,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:49,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:49,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:49,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694647454] [2019-12-07 13:01:49,502 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:49,502 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:49,502 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213518433] [2019-12-07 13:01:49,565 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:49,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:49,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:49,565 INFO L87 Difference]: Start difference. First operand 118103 states and 146150 transitions. cyclomatic complexity: 28095 Second operand 3 states. [2019-12-07 13:01:49,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:49,955 INFO L93 Difference]: Finished difference Result 215025 states and 264102 transitions. [2019-12-07 13:01:49,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:49,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215025 states and 264102 transitions. [2019-12-07 13:01:50,616 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 203768 [2019-12-07 13:01:51,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215025 states to 215025 states and 264102 transitions. [2019-12-07 13:01:51,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215025 [2019-12-07 13:01:51,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215025 [2019-12-07 13:01:51,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215025 states and 264102 transitions. [2019-12-07 13:01:51,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:01:51,226 INFO L688 BuchiCegarLoop]: Abstraction has 215025 states and 264102 transitions. [2019-12-07 13:01:51,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215025 states and 264102 transitions. [2019-12-07 13:01:52,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215025 to 215025. [2019-12-07 13:01:52,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215025 states. [2019-12-07 13:01:52,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215025 states to 215025 states and 264102 transitions. [2019-12-07 13:01:52,925 INFO L711 BuchiCegarLoop]: Abstraction has 215025 states and 264102 transitions. [2019-12-07 13:01:52,925 INFO L591 BuchiCegarLoop]: Abstraction has 215025 states and 264102 transitions. [2019-12-07 13:01:52,925 INFO L424 BuchiCegarLoop]: ======== Iteration 42============ [2019-12-07 13:01:52,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215025 states and 264102 transitions. [2019-12-07 13:01:53,426 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 203768 [2019-12-07 13:01:53,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:53,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:53,427 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:53,427 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:53,427 INFO L794 eck$LassoCheckResult]: Stem: 7933605#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 7933518#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7933519#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7933771#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 7933091#L599-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 7933092#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7985555#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7985554#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7985553#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7985552#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7985551#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7985550#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7985549#L639-1 assume !(0 == ~M_E~0); 7985548#L856-1 assume !(0 == ~T1_E~0); 7985547#L861-1 assume !(0 == ~T2_E~0); 7985546#L866-1 assume !(0 == ~T3_E~0); 7985545#L871-1 assume !(0 == ~T4_E~0); 7985544#L876-1 assume !(0 == ~T5_E~0); 7985543#L881-1 assume !(0 == ~T6_E~0); 7985542#L886-1 assume !(0 == ~T7_E~0); 7985541#L891-1 assume !(0 == ~T8_E~0); 7985540#L896-1 assume !(0 == ~E_M~0); 7985539#L901-1 assume !(0 == ~E_1~0); 7985538#L906-1 assume !(0 == ~E_2~0); 7985537#L911-1 assume !(0 == ~E_3~0); 7985536#L916-1 assume !(0 == ~E_4~0); 7985535#L921-1 assume !(0 == ~E_5~0); 7985534#L926-1 assume !(0 == ~E_6~0); 7985533#L931-1 assume !(0 == ~E_7~0); 7985532#L936-1 assume !(0 == ~E_8~0); 7985531#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7985530#L420 assume !(1 == ~m_pc~0); 7985528#L420-2 is_master_triggered_~__retres1~0 := 0; 7985527#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7985526#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7985525#L1063 assume !(0 != activate_threads_~tmp~1); 7985524#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7985523#L439 assume !(1 == ~t1_pc~0); 7985522#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 7985521#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7985520#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7985519#L1071 assume !(0 != activate_threads_~tmp___0~0); 7985518#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7985517#L458 assume !(1 == ~t2_pc~0); 7985515#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 7985514#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7985513#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7985512#L1079 assume !(0 != activate_threads_~tmp___1~0); 7985511#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7985510#L477 assume !(1 == ~t3_pc~0); 7985509#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 7985508#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7985507#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7985506#L1087 assume !(0 != activate_threads_~tmp___2~0); 7985505#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7985502#L496 assume !(1 == ~t4_pc~0); 7985501#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 7985500#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7985499#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7985498#L1095 assume !(0 != activate_threads_~tmp___3~0); 7985496#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7985495#L515 assume !(1 == ~t5_pc~0); 7985494#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 7985493#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7985492#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7985491#L1103 assume !(0 != activate_threads_~tmp___4~0); 7985490#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7985489#L534 assume !(1 == ~t6_pc~0); 7985488#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 7985487#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7985486#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7985485#L1111 assume !(0 != activate_threads_~tmp___5~0); 7985484#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7985483#L553 assume !(1 == ~t7_pc~0); 7985481#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 7985480#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7985479#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7985478#L1119 assume !(0 != activate_threads_~tmp___6~0); 7985477#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7985476#L572 assume !(1 == ~t8_pc~0); 7985475#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 7985474#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7985473#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7985472#L1127 assume !(0 != activate_threads_~tmp___7~0); 7985471#L1127-2 assume !(1 == ~M_E~0); 7985470#L954-1 assume !(1 == ~T1_E~0); 7985469#L959-1 assume !(1 == ~T2_E~0); 7985468#L964-1 assume !(1 == ~T3_E~0); 7985467#L969-1 assume !(1 == ~T4_E~0); 7985466#L974-1 assume !(1 == ~T5_E~0); 7985465#L979-1 assume !(1 == ~T6_E~0); 7985464#L984-1 assume !(1 == ~T7_E~0); 7985463#L989-1 assume !(1 == ~T8_E~0); 7985462#L994-1 assume !(1 == ~E_M~0); 7985461#L999-1 assume !(1 == ~E_1~0); 7985460#L1004-1 assume !(1 == ~E_2~0); 7985459#L1009-1 assume !(1 == ~E_3~0); 7985458#L1014-1 assume !(1 == ~E_4~0); 7985457#L1019-1 assume !(1 == ~E_5~0); 7985456#L1024-1 assume !(1 == ~E_6~0); 7985455#L1029-1 assume !(1 == ~E_7~0); 7985454#L1034-1 assume !(1 == ~E_8~0); 7985453#L1305-1 assume !false; 7985319#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 7985317#L831 [2019-12-07 13:01:53,428 INFO L796 eck$LassoCheckResult]: Loop: 7985317#L831 assume !false; 7985315#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7985313#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7985311#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 7985309#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 7985307#L714 assume 0 != eval_~tmp~0; 7985305#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 7985303#L722 assume !(0 != eval_~tmp_ndt_1~0); 7985299#L719 assume !(0 == ~t1_st~0); 7985294#L733 assume !(0 == ~t2_st~0); 7985293#L747 assume !(0 == ~t3_st~0); 7985290#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 7985144#L778 assume !(0 != eval_~tmp_ndt_5~0); 7985289#L775 assume !(0 == ~t5_st~0); 7985448#L789 assume !(0 == ~t6_st~0); 7985327#L803 assume !(0 == ~t7_st~0); 7985320#L817 assume !(0 == ~t8_st~0); 7985317#L831 [2019-12-07 13:01:53,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:53,428 INFO L82 PathProgramCache]: Analyzing trace with hash -838194844, now seen corresponding path program 1 times [2019-12-07 13:01:53,428 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:53,428 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170616687] [2019-12-07 13:01:53,428 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:53,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:53,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:53,442 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170616687] [2019-12-07 13:01:53,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:53,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:53,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158792602] [2019-12-07 13:01:53,442 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-12-07 13:01:53,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:53,443 INFO L82 PathProgramCache]: Analyzing trace with hash -1613288712, now seen corresponding path program 3 times [2019-12-07 13:01:53,443 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:53,443 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838333890] [2019-12-07 13:01:53,443 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:53,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:53,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:53,447 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:53,508 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:53,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:53,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:53,508 INFO L87 Difference]: Start difference. First operand 215025 states and 264102 transitions. cyclomatic complexity: 49165 Second operand 3 states. [2019-12-07 13:01:53,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:53,744 INFO L93 Difference]: Finished difference Result 137623 states and 169045 transitions. [2019-12-07 13:01:53,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:53,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137623 states and 169045 transitions. [2019-12-07 13:01:54,148 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 132512 [2019-12-07 13:01:54,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137623 states to 137623 states and 169045 transitions. [2019-12-07 13:01:54,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137623 [2019-12-07 13:01:54,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137623 [2019-12-07 13:01:54,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 137623 states and 169045 transitions. [2019-12-07 13:01:54,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:01:54,538 INFO L688 BuchiCegarLoop]: Abstraction has 137623 states and 169045 transitions. [2019-12-07 13:01:54,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137623 states and 169045 transitions. [2019-12-07 13:01:55,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137623 to 137623. [2019-12-07 13:01:55,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137623 states. [2019-12-07 13:01:55,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137623 states to 137623 states and 169045 transitions. [2019-12-07 13:01:55,661 INFO L711 BuchiCegarLoop]: Abstraction has 137623 states and 169045 transitions. [2019-12-07 13:01:55,661 INFO L591 BuchiCegarLoop]: Abstraction has 137623 states and 169045 transitions. [2019-12-07 13:01:55,661 INFO L424 BuchiCegarLoop]: ======== Iteration 43============ [2019-12-07 13:01:55,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 137623 states and 169045 transitions. [2019-12-07 13:01:55,963 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 132512 [2019-12-07 13:01:55,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:01:55,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:01:55,964 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:55,964 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:01:55,964 INFO L794 eck$LassoCheckResult]: Stem: 8286261#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8286172#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8286173#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8286424#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 8285745#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8285746#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8286534#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8286425#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8286125#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8286126#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8286635#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8286379#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8286023#L639-1 assume !(0 == ~M_E~0); 8286024#L856-1 assume !(0 == ~T1_E~0); 8286132#L861-1 assume !(0 == ~T2_E~0); 8286133#L866-1 assume !(0 == ~T3_E~0); 8286668#L871-1 assume !(0 == ~T4_E~0); 8286408#L876-1 assume !(0 == ~T5_E~0); 8286241#L881-1 assume !(0 == ~T6_E~0); 8285889#L886-1 assume !(0 == ~T7_E~0); 8285890#L891-1 assume !(0 == ~T8_E~0); 8286488#L896-1 assume !(0 == ~E_M~0); 8286204#L901-1 assume !(0 == ~E_1~0); 8285844#L906-1 assume !(0 == ~E_2~0); 8285845#L911-1 assume !(0 == ~E_3~0); 8286732#L916-1 assume !(0 == ~E_4~0); 8286315#L921-1 assume !(0 == ~E_5~0); 8285963#L926-1 assume !(0 == ~E_6~0); 8285964#L931-1 assume !(0 == ~E_7~0); 8286817#L936-1 assume !(0 == ~E_8~0); 8286577#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8285923#L420 assume !(1 == ~m_pc~0); 8285924#L420-2 is_master_triggered_~__retres1~0 := 0; 8285930#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8286647#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8286728#L1063 assume !(0 != activate_threads_~tmp~1); 8286907#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8286191#L439 assume !(1 == ~t1_pc~0); 8286192#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 8286196#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8286775#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8286718#L1071 assume !(0 != activate_threads_~tmp___0~0); 8286703#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8286388#L458 assume !(1 == ~t2_pc~0); 8286362#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 8286363#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8286894#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8286251#L1079 assume !(0 != activate_threads_~tmp___1~0); 8286252#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8286255#L477 assume !(1 == ~t3_pc~0); 8286520#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 8285811#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8285812#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8285911#L1087 assume !(0 != activate_threads_~tmp___2~0); 8286918#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8286700#L496 assume !(1 == ~t4_pc~0); 8286642#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 8286032#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8286033#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8286589#L1095 assume !(0 != activate_threads_~tmp___3~0); 8286590#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8286591#L515 assume !(1 == ~t5_pc~0); 8286908#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 8286414#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8286203#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8286162#L1103 assume !(0 != activate_threads_~tmp___4~0); 8286145#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8285874#L534 assume !(1 == ~t6_pc~0); 8285864#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 8285865#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8286382#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8286383#L1111 assume !(0 != activate_threads_~tmp___5~0); 8286751#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8286103#L553 assume !(1 == ~t7_pc~0); 8285842#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 8286110#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8286535#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8286356#L1119 assume !(0 != activate_threads_~tmp___6~0); 8286333#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8286292#L572 assume !(1 == ~t8_pc~0); 8286293#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 8286295#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8286697#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8285777#L1127 assume !(0 != activate_threads_~tmp___7~0); 8285778#L1127-2 assume !(1 == ~M_E~0); 8285779#L954-1 assume !(1 == ~T1_E~0); 8286663#L959-1 assume !(1 == ~T2_E~0); 8286406#L964-1 assume !(1 == ~T3_E~0); 8286232#L969-1 assume !(1 == ~T4_E~0); 8285885#L974-1 assume !(1 == ~T5_E~0); 8285886#L979-1 assume !(1 == ~T6_E~0); 8286484#L984-1 assume !(1 == ~T7_E~0); 8286208#L989-1 assume !(1 == ~T8_E~0); 8286048#L994-1 assume !(1 == ~E_M~0); 8286049#L999-1 assume !(1 == ~E_1~0); 8286735#L1004-1 assume !(1 == ~E_2~0); 8286340#L1009-1 assume !(1 == ~E_3~0); 8285971#L1014-1 assume !(1 == ~E_4~0); 8285972#L1019-1 assume !(1 == ~E_5~0); 8286821#L1024-1 assume !(1 == ~E_6~0); 8286573#L1029-1 assume !(1 == ~E_7~0); 8286302#L1034-1 assume !(1 == ~E_8~0); 8286303#L1305-1 assume !false; 8346855#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8346853#L831 [2019-12-07 13:01:55,965 INFO L796 eck$LassoCheckResult]: Loop: 8346853#L831 assume !false; 8346851#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8346848#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8346846#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8346843#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8346841#L714 assume 0 != eval_~tmp~0; 8346838#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8346835#L722 assume !(0 != eval_~tmp_ndt_1~0); 8346832#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 8346829#L736 assume !(0 != eval_~tmp_ndt_2~0); 8346693#L733 assume !(0 == ~t2_st~0); 8346691#L747 assume !(0 == ~t3_st~0); 8346687#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 8346635#L778 assume !(0 != eval_~tmp_ndt_5~0); 8346685#L775 assume !(0 == ~t5_st~0); 8346871#L789 assume !(0 == ~t6_st~0); 8346862#L803 assume !(0 == ~t7_st~0); 8346856#L817 assume !(0 == ~t8_st~0); 8346853#L831 [2019-12-07 13:01:55,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:55,965 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 2 times [2019-12-07 13:01:55,965 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:55,965 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210975957] [2019-12-07 13:01:55,965 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:55,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:55,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:55,983 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:55,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:55,983 INFO L82 PathProgramCache]: Analyzing trace with hash 112442453, now seen corresponding path program 1 times [2019-12-07 13:01:55,983 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:55,983 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505395637] [2019-12-07 13:01:55,983 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:55,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:55,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:01:55,987 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:01:55,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:01:55,987 INFO L82 PathProgramCache]: Analyzing trace with hash 1721460154, now seen corresponding path program 1 times [2019-12-07 13:01:55,987 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:01:55,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439009210] [2019-12-07 13:01:55,988 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:01:55,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:01:56,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:01:56,011 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439009210] [2019-12-07 13:01:56,011 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:01:56,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:01:56,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368075255] [2019-12-07 13:01:56,081 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:01:56,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:01:56,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:01:56,082 INFO L87 Difference]: Start difference. First operand 137623 states and 169045 transitions. cyclomatic complexity: 31470 Second operand 3 states. [2019-12-07 13:01:56,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:01:56,512 INFO L93 Difference]: Finished difference Result 244463 states and 299781 transitions. [2019-12-07 13:01:56,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:01:56,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244463 states and 299781 transitions. [2019-12-07 13:01:57,258 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 234352 [2019-12-07 13:01:57,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244463 states to 244463 states and 299781 transitions. [2019-12-07 13:01:57,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 244463 [2019-12-07 13:01:57,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 244463 [2019-12-07 13:01:57,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 244463 states and 299781 transitions. [2019-12-07 13:01:57,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:01:57,938 INFO L688 BuchiCegarLoop]: Abstraction has 244463 states and 299781 transitions. [2019-12-07 13:01:58,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244463 states and 299781 transitions. [2019-12-07 13:01:59,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244463 to 244463. [2019-12-07 13:01:59,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 244463 states. [2019-12-07 13:01:59,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244463 states to 244463 states and 299781 transitions. [2019-12-07 13:01:59,868 INFO L711 BuchiCegarLoop]: Abstraction has 244463 states and 299781 transitions. [2019-12-07 13:01:59,868 INFO L591 BuchiCegarLoop]: Abstraction has 244463 states and 299781 transitions. [2019-12-07 13:01:59,868 INFO L424 BuchiCegarLoop]: ======== Iteration 44============ [2019-12-07 13:01:59,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 244463 states and 299781 transitions. [2019-12-07 13:02:00,432 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 234352 [2019-12-07 13:02:00,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:02:00,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:02:00,433 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:00,433 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:00,433 INFO L794 eck$LassoCheckResult]: Stem: 8668353#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8668262#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8668263#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8668521#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 8667839#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8667840#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8668622#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8668522#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8668216#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8668217#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8668720#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8668472#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8668113#L639-1 assume !(0 == ~M_E~0); 8668114#L856-1 assume !(0 == ~T1_E~0); 8668223#L861-1 assume !(0 == ~T2_E~0); 8668224#L866-1 assume !(0 == ~T3_E~0); 8668754#L871-1 assume !(0 == ~T4_E~0); 8668504#L876-1 assume !(0 == ~T5_E~0); 8668333#L881-1 assume !(0 == ~T6_E~0); 8667983#L886-1 assume !(0 == ~T7_E~0); 8667984#L891-1 assume !(0 == ~T8_E~0); 8668582#L896-1 assume !(0 == ~E_M~0); 8668294#L901-1 assume !(0 == ~E_1~0); 8667938#L906-1 assume !(0 == ~E_2~0); 8667939#L911-1 assume !(0 == ~E_3~0); 8668811#L916-1 assume !(0 == ~E_4~0); 8668409#L921-1 assume !(0 == ~E_5~0); 8668054#L926-1 assume !(0 == ~E_6~0); 8668055#L931-1 assume !(0 == ~E_7~0); 8668899#L936-1 assume !(0 == ~E_8~0); 8668664#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8668011#L420 assume !(1 == ~m_pc~0); 8668012#L420-2 is_master_triggered_~__retres1~0 := 0; 8668018#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8668732#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8668808#L1063 assume !(0 != activate_threads_~tmp~1); 8668996#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8668281#L439 assume !(1 == ~t1_pc~0); 8668282#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 8668286#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8668858#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8668798#L1071 assume !(0 != activate_threads_~tmp___0~0); 8668783#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8668481#L458 assume !(1 == ~t2_pc~0); 8668456#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 8668457#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8668987#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8668344#L1079 assume !(0 != activate_threads_~tmp___1~0); 8668345#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8668347#L477 assume !(1 == ~t3_pc~0); 8668610#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 8667905#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8667906#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8668002#L1087 assume !(0 != activate_threads_~tmp___2~0); 8669007#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8668780#L496 assume !(1 == ~t4_pc~0); 8668727#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 8668121#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8668122#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8668675#L1095 assume !(0 != activate_threads_~tmp___3~0); 8668676#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8668677#L515 assume !(1 == ~t5_pc~0); 8668998#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 8668510#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8668293#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8668252#L1103 assume !(0 != activate_threads_~tmp___4~0); 8668236#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8667968#L534 assume !(1 == ~t6_pc~0); 8667959#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 8667960#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8668475#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8668476#L1111 assume !(0 != activate_threads_~tmp___5~0); 8668832#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8668196#L553 assume !(1 == ~t7_pc~0); 8667936#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 8668203#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8668623#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8668449#L1119 assume !(0 != activate_threads_~tmp___6~0); 8668427#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8668386#L572 assume !(1 == ~t8_pc~0); 8668387#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 8668389#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8668777#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8667871#L1127 assume !(0 != activate_threads_~tmp___7~0); 8667872#L1127-2 assume !(1 == ~M_E~0); 8667873#L954-1 assume !(1 == ~T1_E~0); 8668750#L959-1 assume !(1 == ~T2_E~0); 8668502#L964-1 assume !(1 == ~T3_E~0); 8668325#L969-1 assume !(1 == ~T4_E~0); 8667979#L974-1 assume !(1 == ~T5_E~0); 8667980#L979-1 assume !(1 == ~T6_E~0); 8668580#L984-1 assume !(1 == ~T7_E~0); 8668299#L989-1 assume !(1 == ~T8_E~0); 8668138#L994-1 assume !(1 == ~E_M~0); 8668139#L999-1 assume !(1 == ~E_1~0); 8668819#L1004-1 assume !(1 == ~E_2~0); 8668433#L1009-1 assume !(1 == ~E_3~0); 8668064#L1014-1 assume !(1 == ~E_4~0); 8668065#L1019-1 assume !(1 == ~E_5~0); 8668904#L1024-1 assume !(1 == ~E_6~0); 8668660#L1029-1 assume !(1 == ~E_7~0); 8668396#L1034-1 assume !(1 == ~E_8~0); 8668397#L1305-1 assume !false; 8718240#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8718238#L831 [2019-12-07 13:02:00,433 INFO L796 eck$LassoCheckResult]: Loop: 8718238#L831 assume !false; 8718236#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8718234#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8718232#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8718230#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8718228#L714 assume 0 != eval_~tmp~0; 8718227#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8718225#L722 assume !(0 != eval_~tmp_ndt_1~0); 8718221#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 8718218#L736 assume !(0 != eval_~tmp_ndt_2~0); 8713500#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 8713497#L750 assume !(0 != eval_~tmp_ndt_3~0); 8713495#L747 assume !(0 == ~t3_st~0); 8713491#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 8713418#L778 assume !(0 != eval_~tmp_ndt_5~0); 8713489#L775 assume !(0 == ~t5_st~0); 8713903#L789 assume !(0 == ~t6_st~0); 8718248#L803 assume !(0 == ~t7_st~0); 8718241#L817 assume !(0 == ~t8_st~0); 8718238#L831 [2019-12-07 13:02:00,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:00,433 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 3 times [2019-12-07 13:02:00,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:00,434 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601779342] [2019-12-07 13:02:00,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:00,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:00,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:00,452 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:00,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:00,453 INFO L82 PathProgramCache]: Analyzing trace with hash 665102990, now seen corresponding path program 1 times [2019-12-07 13:02:00,453 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:00,453 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363042622] [2019-12-07 13:02:00,453 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:00,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:00,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:00,457 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:00,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:00,458 INFO L82 PathProgramCache]: Analyzing trace with hash -994955831, now seen corresponding path program 1 times [2019-12-07 13:02:00,458 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:00,458 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230649669] [2019-12-07 13:02:00,458 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:00,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:02:00,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:02:00,482 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230649669] [2019-12-07 13:02:00,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:02:00,482 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:02:00,482 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591191592] [2019-12-07 13:02:00,587 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:02:00,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:02:00,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:02:00,587 INFO L87 Difference]: Start difference. First operand 244463 states and 299781 transitions. cyclomatic complexity: 55366 Second operand 3 states. [2019-12-07 13:02:01,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:02:01,172 INFO L93 Difference]: Finished difference Result 325167 states and 398605 transitions. [2019-12-07 13:02:01,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:02:01,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 325167 states and 398605 transitions. [2019-12-07 13:02:02,363 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 310696 [2019-12-07 13:02:02,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 325167 states to 325167 states and 398605 transitions. [2019-12-07 13:02:02,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 325167 [2019-12-07 13:02:02,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 325167 [2019-12-07 13:02:02,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 325167 states and 398605 transitions. [2019-12-07 13:02:03,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:02:03,021 INFO L688 BuchiCegarLoop]: Abstraction has 325167 states and 398605 transitions. [2019-12-07 13:02:03,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325167 states and 398605 transitions. [2019-12-07 13:02:04,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325167 to 313343. [2019-12-07 13:02:04,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 313343 states. [2019-12-07 13:02:05,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313343 states to 313343 states and 384893 transitions. [2019-12-07 13:02:05,329 INFO L711 BuchiCegarLoop]: Abstraction has 313343 states and 384893 transitions. [2019-12-07 13:02:05,329 INFO L591 BuchiCegarLoop]: Abstraction has 313343 states and 384893 transitions. [2019-12-07 13:02:05,329 INFO L424 BuchiCegarLoop]: ======== Iteration 45============ [2019-12-07 13:02:05,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 313343 states and 384893 transitions. [2019-12-07 13:02:06,027 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 298872 [2019-12-07 13:02:06,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:02:06,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:02:06,028 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:06,028 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:06,028 INFO L794 eck$LassoCheckResult]: Stem: 9237992#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 9237906#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9237907#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9238161#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 9237477#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9237478#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9238279#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9238162#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9237858#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9237859#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9238382#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9238116#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9237755#L639-1 assume !(0 == ~M_E~0); 9237756#L856-1 assume !(0 == ~T1_E~0); 9237864#L861-1 assume !(0 == ~T2_E~0); 9237865#L866-1 assume !(0 == ~T3_E~0); 9238417#L871-1 assume !(0 == ~T4_E~0); 9238146#L876-1 assume !(0 == ~T5_E~0); 9237969#L881-1 assume !(0 == ~T6_E~0); 9237618#L886-1 assume !(0 == ~T7_E~0); 9237619#L891-1 assume !(0 == ~T8_E~0); 9238234#L896-1 assume !(0 == ~E_M~0); 9237932#L901-1 assume !(0 == ~E_1~0); 9237573#L906-1 assume !(0 == ~E_2~0); 9237574#L911-1 assume !(0 == ~E_3~0); 9238484#L916-1 assume !(0 == ~E_4~0); 9238051#L921-1 assume !(0 == ~E_5~0); 9237692#L926-1 assume !(0 == ~E_6~0); 9237693#L931-1 assume !(0 == ~E_7~0); 9238565#L936-1 assume !(0 == ~E_8~0); 9238331#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9237649#L420 assume !(1 == ~m_pc~0); 9237650#L420-2 is_master_triggered_~__retres1~0 := 0; 9237656#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9238400#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9238480#L1063 assume !(0 != activate_threads_~tmp~1); 9238661#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9237921#L439 assume !(1 == ~t1_pc~0); 9237922#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 9237925#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9238527#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9238469#L1071 assume !(0 != activate_threads_~tmp___0~0); 9238452#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9238125#L458 assume !(1 == ~t2_pc~0); 9238097#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 9238098#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9238650#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9237981#L1079 assume !(0 != activate_threads_~tmp___1~0); 9237982#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9237984#L477 assume !(1 == ~t3_pc~0); 9238267#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 9237546#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9237547#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9237639#L1087 assume !(0 != activate_threads_~tmp___2~0); 9238675#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9238449#L496 assume !(1 == ~t4_pc~0); 9238389#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 9237767#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9237768#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9238339#L1095 assume !(0 != activate_threads_~tmp___3~0); 9238340#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9238341#L515 assume !(1 == ~t5_pc~0); 9238665#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 9238152#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9237931#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9237894#L1103 assume !(0 != activate_threads_~tmp___4~0); 9237877#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9237603#L534 assume !(1 == ~t6_pc~0); 9237593#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 9237594#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9238119#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9238120#L1111 assume !(0 != activate_threads_~tmp___5~0); 9238499#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9237839#L553 assume !(1 == ~t7_pc~0); 9237571#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 9237846#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9238281#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9238091#L1119 assume !(0 != activate_threads_~tmp___6~0); 9238066#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9238024#L572 assume !(1 == ~t8_pc~0); 9238025#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 9238027#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9238446#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9237509#L1127 assume !(0 != activate_threads_~tmp___7~0); 9237510#L1127-2 assume !(1 == ~M_E~0); 9237511#L954-1 assume !(1 == ~T1_E~0); 9238415#L959-1 assume !(1 == ~T2_E~0); 9238143#L964-1 assume !(1 == ~T3_E~0); 9237962#L969-1 assume !(1 == ~T4_E~0); 9237614#L974-1 assume !(1 == ~T5_E~0); 9237615#L979-1 assume !(1 == ~T6_E~0); 9238228#L984-1 assume !(1 == ~T7_E~0); 9237935#L989-1 assume !(1 == ~T8_E~0); 9237783#L994-1 assume !(1 == ~E_M~0); 9237784#L999-1 assume !(1 == ~E_1~0); 9238488#L1004-1 assume !(1 == ~E_2~0); 9238073#L1009-1 assume !(1 == ~E_3~0); 9237703#L1014-1 assume !(1 == ~E_4~0); 9237704#L1019-1 assume !(1 == ~E_5~0); 9238568#L1024-1 assume !(1 == ~E_6~0); 9238326#L1029-1 assume !(1 == ~E_7~0); 9238036#L1034-1 assume !(1 == ~E_8~0); 9238037#L1305-1 assume !false; 9262045#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9262038#L831 [2019-12-07 13:02:06,028 INFO L796 eck$LassoCheckResult]: Loop: 9262038#L831 assume !false; 9262028#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9262019#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9262012#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9262001#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9261991#L714 assume 0 != eval_~tmp~0; 9261981#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9261972#L722 assume !(0 != eval_~tmp_ndt_1~0); 9261962#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 9261951#L736 assume !(0 != eval_~tmp_ndt_2~0); 9261829#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 9261820#L750 assume !(0 != eval_~tmp_ndt_3~0); 9261814#L747 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 9261802#L764 assume !(0 != eval_~tmp_ndt_4~0); 9261086#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 9261084#L778 assume !(0 != eval_~tmp_ndt_5~0); 9261081#L775 assume !(0 == ~t5_st~0); 9261078#L789 assume !(0 == ~t6_st~0); 9261077#L803 assume !(0 == ~t7_st~0); 9262046#L817 assume !(0 == ~t8_st~0); 9262038#L831 [2019-12-07 13:02:06,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:06,029 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 4 times [2019-12-07 13:02:06,029 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:06,029 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901675425] [2019-12-07 13:02:06,029 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:06,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:06,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:06,046 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:06,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:06,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1367287617, now seen corresponding path program 1 times [2019-12-07 13:02:06,047 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:06,047 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671003303] [2019-12-07 13:02:06,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:06,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:06,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:06,051 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:06,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:06,052 INFO L82 PathProgramCache]: Analyzing trace with hash -1289503516, now seen corresponding path program 1 times [2019-12-07 13:02:06,052 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:06,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561866121] [2019-12-07 13:02:06,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:06,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:02:06,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:02:06,074 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561866121] [2019-12-07 13:02:06,075 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:02:06,075 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:02:06,075 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791876352] [2019-12-07 13:02:06,163 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:02:06,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:02:06,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:02:06,163 INFO L87 Difference]: Start difference. First operand 313343 states and 384893 transitions. cyclomatic complexity: 71598 Second operand 3 states. [2019-12-07 13:02:06,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:02:06,985 INFO L93 Difference]: Finished difference Result 404943 states and 496765 transitions. [2019-12-07 13:02:06,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:02:06,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 404943 states and 496765 transitions. [2019-12-07 13:02:08,596 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 383992 [2019-12-07 13:02:09,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 404943 states to 404943 states and 496765 transitions. [2019-12-07 13:02:09,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 404943 [2019-12-07 13:02:09,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 404943 [2019-12-07 13:02:09,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 404943 states and 496765 transitions. [2019-12-07 13:02:09,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:02:09,507 INFO L688 BuchiCegarLoop]: Abstraction has 404943 states and 496765 transitions. [2019-12-07 13:02:09,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404943 states and 496765 transitions. [2019-12-07 13:02:12,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404943 to 404943. [2019-12-07 13:02:12,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 404943 states. [2019-12-07 13:02:13,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 404943 states to 404943 states and 496765 transitions. [2019-12-07 13:02:13,441 INFO L711 BuchiCegarLoop]: Abstraction has 404943 states and 496765 transitions. [2019-12-07 13:02:13,441 INFO L591 BuchiCegarLoop]: Abstraction has 404943 states and 496765 transitions. [2019-12-07 13:02:13,441 INFO L424 BuchiCegarLoop]: ======== Iteration 46============ [2019-12-07 13:02:13,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 404943 states and 496765 transitions. [2019-12-07 13:02:14,181 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 383992 [2019-12-07 13:02:14,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:02:14,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:02:14,182 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:14,182 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:14,182 INFO L794 eck$LassoCheckResult]: Stem: 9956281#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 9956191#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9956192#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9956451#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 9955771#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9955772#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9956564#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9956452#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9956149#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9956150#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9956669#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9956407#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9956045#L639-1 assume !(0 == ~M_E~0); 9956046#L856-1 assume !(0 == ~T1_E~0); 9956156#L861-1 assume !(0 == ~T2_E~0); 9956157#L866-1 assume !(0 == ~T3_E~0); 9956704#L871-1 assume !(0 == ~T4_E~0); 9956437#L876-1 assume !(0 == ~T5_E~0); 9956260#L881-1 assume !(0 == ~T6_E~0); 9955910#L886-1 assume !(0 == ~T7_E~0); 9955911#L891-1 assume !(0 == ~T8_E~0); 9956522#L896-1 assume !(0 == ~E_M~0); 9956222#L901-1 assume !(0 == ~E_1~0); 9955866#L906-1 assume !(0 == ~E_2~0); 9955867#L911-1 assume !(0 == ~E_3~0); 9956764#L916-1 assume !(0 == ~E_4~0); 9956341#L921-1 assume !(0 == ~E_5~0); 9955984#L926-1 assume !(0 == ~E_6~0); 9955985#L931-1 assume !(0 == ~E_7~0); 9956846#L936-1 assume !(0 == ~E_8~0); 9956608#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9955941#L420 assume !(1 == ~m_pc~0); 9955942#L420-2 is_master_triggered_~__retres1~0 := 0; 9955948#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9956682#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9956758#L1063 assume !(0 != activate_threads_~tmp~1); 9956931#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9956212#L439 assume !(1 == ~t1_pc~0); 9956213#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 9956216#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9956803#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9956747#L1071 assume !(0 != activate_threads_~tmp___0~0); 9956732#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9956416#L458 assume !(1 == ~t2_pc~0); 9956388#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 9956389#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9956924#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9956271#L1079 assume !(0 != activate_threads_~tmp___1~0); 9956272#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9956274#L477 assume !(1 == ~t3_pc~0); 9956553#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 9955836#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9955837#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9955932#L1087 assume !(0 != activate_threads_~tmp___2~0); 9956943#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9956729#L496 assume !(1 == ~t4_pc~0); 9956676#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 9956055#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9956056#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9956617#L1095 assume !(0 != activate_threads_~tmp___3~0); 9956618#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9956619#L515 assume !(1 == ~t5_pc~0); 9956933#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 9956442#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9956221#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9956182#L1103 assume !(0 != activate_threads_~tmp___4~0); 9956168#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9955895#L534 assume !(1 == ~t6_pc~0); 9955885#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 9955886#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9956410#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9956411#L1111 assume !(0 != activate_threads_~tmp___5~0); 9956779#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9956129#L553 assume !(1 == ~t7_pc~0); 9955864#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 9956136#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9956565#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9956382#L1119 assume !(0 != activate_threads_~tmp___6~0); 9956359#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9956315#L572 assume !(1 == ~t8_pc~0); 9956316#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 9956318#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9956726#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9955802#L1127 assume !(0 != activate_threads_~tmp___7~0); 9955803#L1127-2 assume !(1 == ~M_E~0); 9955804#L954-1 assume !(1 == ~T1_E~0); 9956700#L959-1 assume !(1 == ~T2_E~0); 9956435#L964-1 assume !(1 == ~T3_E~0); 9956251#L969-1 assume !(1 == ~T4_E~0); 9955906#L974-1 assume !(1 == ~T5_E~0); 9955907#L979-1 assume !(1 == ~T6_E~0); 9956518#L984-1 assume !(1 == ~T7_E~0); 9956226#L989-1 assume !(1 == ~T8_E~0); 9956073#L994-1 assume !(1 == ~E_M~0); 9956074#L999-1 assume !(1 == ~E_1~0); 9956768#L1004-1 assume !(1 == ~E_2~0); 9956365#L1009-1 assume !(1 == ~E_3~0); 9955994#L1014-1 assume !(1 == ~E_4~0); 9955995#L1019-1 assume !(1 == ~E_5~0); 9956851#L1024-1 assume !(1 == ~E_6~0); 9956604#L1029-1 assume !(1 == ~E_7~0); 9956327#L1034-1 assume !(1 == ~E_8~0); 9956328#L1305-1 assume !false; 9986864#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9986862#L831 [2019-12-07 13:02:14,182 INFO L796 eck$LassoCheckResult]: Loop: 9986862#L831 assume !false; 9986860#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9986858#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9986856#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 9986854#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9986851#L714 assume 0 != eval_~tmp~0; 9986849#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9986846#L722 assume !(0 != eval_~tmp_ndt_1~0); 9986847#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 10034268#L736 assume !(0 != eval_~tmp_ndt_2~0); 9986984#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 9986981#L750 assume !(0 != eval_~tmp_ndt_3~0); 9986979#L747 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 9986976#L764 assume !(0 != eval_~tmp_ndt_4~0); 9986973#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 9986917#L778 assume !(0 != eval_~tmp_ndt_5~0); 9986971#L775 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 10037346#L792 assume !(0 != eval_~tmp_ndt_6~0); 10037345#L789 assume !(0 == ~t6_st~0); 9956864#L803 assume !(0 == ~t7_st~0); 9955897#L817 assume !(0 == ~t8_st~0); 9986862#L831 [2019-12-07 13:02:14,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:14,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 5 times [2019-12-07 13:02:14,183 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:14,183 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391257542] [2019-12-07 13:02:14,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:14,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:14,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:14,199 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:14,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:14,200 INFO L82 PathProgramCache]: Analyzing trace with hash 330696986, now seen corresponding path program 1 times [2019-12-07 13:02:14,200 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:14,200 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035468740] [2019-12-07 13:02:14,200 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:14,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:14,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:14,203 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:14,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:14,204 INFO L82 PathProgramCache]: Analyzing trace with hash -1552963179, now seen corresponding path program 1 times [2019-12-07 13:02:14,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:14,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934414107] [2019-12-07 13:02:14,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:14,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:02:14,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:02:14,232 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934414107] [2019-12-07 13:02:14,232 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:02:14,232 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:02:14,232 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865372449] [2019-12-07 13:02:14,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:02:14,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:02:14,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:02:14,331 INFO L87 Difference]: Start difference. First operand 404943 states and 496765 transitions. cyclomatic complexity: 91870 Second operand 3 states. [2019-12-07 13:02:15,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:02:15,417 INFO L93 Difference]: Finished difference Result 559583 states and 686891 transitions. [2019-12-07 13:02:15,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:02:15,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559583 states and 686891 transitions. [2019-12-07 13:02:20,195 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 528780 [2019-12-07 13:02:21,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559583 states to 559583 states and 686891 transitions. [2019-12-07 13:02:21,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559583 [2019-12-07 13:02:21,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559583 [2019-12-07 13:02:21,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559583 states and 686891 transitions. [2019-12-07 13:02:21,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:02:21,572 INFO L688 BuchiCegarLoop]: Abstraction has 559583 states and 686891 transitions. [2019-12-07 13:02:21,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559583 states and 686891 transitions. [2019-12-07 13:02:24,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559583 to 549271. [2019-12-07 13:02:24,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 549271 states. [2019-12-07 13:02:25,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549271 states to 549271 states and 674715 transitions. [2019-12-07 13:02:25,370 INFO L711 BuchiCegarLoop]: Abstraction has 549271 states and 674715 transitions. [2019-12-07 13:02:25,370 INFO L591 BuchiCegarLoop]: Abstraction has 549271 states and 674715 transitions. [2019-12-07 13:02:25,371 INFO L424 BuchiCegarLoop]: ======== Iteration 47============ [2019-12-07 13:02:25,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 549271 states and 674715 transitions. [2019-12-07 13:02:26,802 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 518468 [2019-12-07 13:02:26,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:02:26,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:02:26,803 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:26,803 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:26,804 INFO L794 eck$LassoCheckResult]: Stem: 10920824#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10920734#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10920735#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10920993#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 10920305#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10920306#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10921107#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10920994#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10920688#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10920689#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10921228#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10920949#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10920583#L639-1 assume !(0 == ~M_E~0); 10920584#L856-1 assume !(0 == ~T1_E~0); 10920694#L861-1 assume !(0 == ~T2_E~0); 10920695#L866-1 assume !(0 == ~T3_E~0); 10921263#L871-1 assume !(0 == ~T4_E~0); 10920979#L876-1 assume !(0 == ~T5_E~0); 10920801#L881-1 assume !(0 == ~T6_E~0); 10920447#L886-1 assume !(0 == ~T7_E~0); 10920448#L891-1 assume !(0 == ~T8_E~0); 10921063#L896-1 assume !(0 == ~E_M~0); 10920765#L901-1 assume !(0 == ~E_1~0); 10920403#L906-1 assume !(0 == ~E_2~0); 10920404#L911-1 assume !(0 == ~E_3~0); 10921326#L916-1 assume !(0 == ~E_4~0); 10920889#L921-1 assume !(0 == ~E_5~0); 10920519#L926-1 assume !(0 == ~E_6~0); 10920520#L931-1 assume !(0 == ~E_7~0); 10921410#L936-1 assume !(0 == ~E_8~0); 10921164#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10920476#L420 assume !(1 == ~m_pc~0); 10920477#L420-2 is_master_triggered_~__retres1~0 := 0; 10920483#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10921245#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10921321#L1063 assume !(0 != activate_threads_~tmp~1); 10921534#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10920753#L439 assume !(1 == ~t1_pc~0); 10920754#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 10920758#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10921373#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10921312#L1071 assume !(0 != activate_threads_~tmp___0~0); 10921297#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10920958#L458 assume !(1 == ~t2_pc~0); 10920930#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 10920931#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10921515#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10920810#L1079 assume !(0 != activate_threads_~tmp___1~0); 10920811#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10920813#L477 assume !(1 == ~t3_pc~0); 10921094#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 10920376#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10920377#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10920465#L1087 assume !(0 != activate_threads_~tmp___2~0); 10921550#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10921293#L496 assume !(1 == ~t4_pc~0); 10921235#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 10920594#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10920595#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10921173#L1095 assume !(0 != activate_threads_~tmp___3~0); 10921174#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10921175#L515 assume !(1 == ~t5_pc~0); 10921540#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 10920983#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10920764#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10920723#L1103 assume !(0 != activate_threads_~tmp___4~0); 10920708#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10920432#L534 assume !(1 == ~t6_pc~0); 10920422#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 10920423#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10920952#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10920953#L1111 assume !(0 != activate_threads_~tmp___5~0); 10921347#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10920667#L553 assume !(1 == ~t7_pc~0); 10920401#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 10920674#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10921109#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10920924#L1119 assume !(0 != activate_threads_~tmp___6~0); 10920903#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 10920860#L572 assume !(1 == ~t8_pc~0); 10920861#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 10920863#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 10921289#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10920339#L1127 assume !(0 != activate_threads_~tmp___7~0); 10920340#L1127-2 assume !(1 == ~M_E~0); 10920341#L954-1 assume !(1 == ~T1_E~0); 10921259#L959-1 assume !(1 == ~T2_E~0); 10920977#L964-1 assume !(1 == ~T3_E~0); 10920794#L969-1 assume !(1 == ~T4_E~0); 10920443#L974-1 assume !(1 == ~T5_E~0); 10920444#L979-1 assume !(1 == ~T6_E~0); 10921060#L984-1 assume !(1 == ~T7_E~0); 10920769#L989-1 assume !(1 == ~T8_E~0); 10920608#L994-1 assume !(1 == ~E_M~0); 10920609#L999-1 assume !(1 == ~E_1~0); 10921331#L1004-1 assume !(1 == ~E_2~0); 10920909#L1009-1 assume !(1 == ~E_3~0); 10920530#L1014-1 assume !(1 == ~E_4~0); 10920531#L1019-1 assume !(1 == ~E_5~0); 10921416#L1024-1 assume !(1 == ~E_6~0); 10921158#L1029-1 assume !(1 == ~E_7~0); 10920873#L1034-1 assume !(1 == ~E_8~0); 10920874#L1305-1 assume !false; 10972326#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 10972324#L831 [2019-12-07 13:02:26,804 INFO L796 eck$LassoCheckResult]: Loop: 10972324#L831 assume !false; 10972322#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10972320#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 10972318#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10972316#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 10972314#L714 assume 0 != eval_~tmp~0; 10972312#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 10972309#L722 assume !(0 != eval_~tmp_ndt_1~0); 10972307#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 10972305#L736 assume !(0 != eval_~tmp_ndt_2~0); 10972303#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 10972119#L750 assume !(0 != eval_~tmp_ndt_3~0); 10972300#L747 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 10972297#L764 assume !(0 != eval_~tmp_ndt_4~0); 10972295#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 10972206#L778 assume !(0 != eval_~tmp_ndt_5~0); 10972293#L775 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 10972342#L792 assume !(0 != eval_~tmp_ndt_6~0); 10972341#L789 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 10972336#L806 assume !(0 != eval_~tmp_ndt_7~0); 10972333#L803 assume !(0 == ~t7_st~0); 10972327#L817 assume !(0 == ~t8_st~0); 10972324#L831 [2019-12-07 13:02:26,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:26,804 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 6 times [2019-12-07 13:02:26,804 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:26,804 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194285521] [2019-12-07 13:02:26,804 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:26,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:26,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:26,821 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:26,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:26,821 INFO L82 PathProgramCache]: Analyzing trace with hash 1654156905, now seen corresponding path program 1 times [2019-12-07 13:02:26,821 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:26,821 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378576599] [2019-12-07 13:02:26,821 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:26,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:26,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:26,825 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:26,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:26,825 INFO L82 PathProgramCache]: Analyzing trace with hash -904733362, now seen corresponding path program 1 times [2019-12-07 13:02:26,825 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:26,825 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211331302] [2019-12-07 13:02:26,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:26,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:02:26,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:02:26,848 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211331302] [2019-12-07 13:02:26,848 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:02:26,848 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:02:26,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528014474] [2019-12-07 13:02:26,958 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:02:26,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:02:26,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:02:26,958 INFO L87 Difference]: Start difference. First operand 549271 states and 674715 transitions. cyclomatic complexity: 125492 Second operand 3 states. [2019-12-07 13:02:29,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:02:29,567 INFO L93 Difference]: Finished difference Result 976257 states and 1199081 transitions. [2019-12-07 13:02:29,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:02:29,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 976257 states and 1199081 transitions. [2019-12-07 13:02:37,366 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 914762 [2019-12-07 13:02:39,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 976257 states to 976257 states and 1199081 transitions. [2019-12-07 13:02:39,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 976257 [2019-12-07 13:02:39,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 976257 [2019-12-07 13:02:39,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 976257 states and 1199081 transitions. [2019-12-07 13:02:39,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:02:39,910 INFO L688 BuchiCegarLoop]: Abstraction has 976257 states and 1199081 transitions. [2019-12-07 13:02:40,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 976257 states and 1199081 transitions. [2019-12-07 13:02:45,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 976257 to 976257. [2019-12-07 13:02:45,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 976257 states. [2019-12-07 13:02:47,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976257 states to 976257 states and 1199081 transitions. [2019-12-07 13:02:47,392 INFO L711 BuchiCegarLoop]: Abstraction has 976257 states and 1199081 transitions. [2019-12-07 13:02:47,392 INFO L591 BuchiCegarLoop]: Abstraction has 976257 states and 1199081 transitions. [2019-12-07 13:02:47,392 INFO L424 BuchiCegarLoop]: ======== Iteration 48============ [2019-12-07 13:02:47,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 976257 states and 1199081 transitions. [2019-12-07 13:02:53,070 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 914762 [2019-12-07 13:02:53,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:02:53,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:02:53,070 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:53,071 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:02:53,071 INFO L794 eck$LassoCheckResult]: Stem: 12446359#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12446274#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12446275#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12446531#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 12445841#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12445842#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12446643#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12446532#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12446224#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12446225#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12446745#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12446485#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 12446118#L639-1 assume !(0 == ~M_E~0); 12446119#L856-1 assume !(0 == ~T1_E~0); 12446231#L861-1 assume !(0 == ~T2_E~0); 12446232#L866-1 assume !(0 == ~T3_E~0); 12446779#L871-1 assume !(0 == ~T4_E~0); 12446514#L876-1 assume !(0 == ~T5_E~0); 12446338#L881-1 assume !(0 == ~T6_E~0); 12445981#L886-1 assume !(0 == ~T7_E~0); 12445982#L891-1 assume !(0 == ~T8_E~0); 12446600#L896-1 assume !(0 == ~E_M~0); 12446301#L901-1 assume !(0 == ~E_1~0); 12445937#L906-1 assume !(0 == ~E_2~0); 12445938#L911-1 assume !(0 == ~E_3~0); 12446842#L916-1 assume !(0 == ~E_4~0); 12446420#L921-1 assume !(0 == ~E_5~0); 12446055#L926-1 assume !(0 == ~E_6~0); 12446056#L931-1 assume !(0 == ~E_7~0); 12446925#L936-1 assume !(0 == ~E_8~0); 12446686#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12446012#L420 assume !(1 == ~m_pc~0); 12446013#L420-2 is_master_triggered_~__retres1~0 := 0; 12446019#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12446756#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12446837#L1063 assume !(0 != activate_threads_~tmp~1); 12447025#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12446290#L439 assume !(1 == ~t1_pc~0); 12446291#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 12446294#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12446885#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12446824#L1071 assume !(0 != activate_threads_~tmp___0~0); 12446808#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12446494#L458 assume !(1 == ~t2_pc~0); 12446467#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 12446468#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12447010#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12446350#L1079 assume !(0 != activate_threads_~tmp___1~0); 12446351#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12446353#L477 assume !(1 == ~t3_pc~0); 12446632#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 12445907#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12445908#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12446000#L1087 assume !(0 != activate_threads_~tmp___2~0); 12447036#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12446805#L496 assume !(1 == ~t4_pc~0); 12446752#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 12446127#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12446128#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12446697#L1095 assume !(0 != activate_threads_~tmp___3~0); 12446698#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12446699#L515 assume !(1 == ~t5_pc~0); 12447028#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 12446519#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12446300#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12446261#L1103 assume !(0 != activate_threads_~tmp___4~0); 12446244#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12445966#L534 assume !(1 == ~t6_pc~0); 12445956#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 12445957#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12446488#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12446489#L1111 assume !(0 != activate_threads_~tmp___5~0); 12446863#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12446203#L553 assume !(1 == ~t7_pc~0); 12445935#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 12446210#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12446644#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12446461#L1119 assume !(0 != activate_threads_~tmp___6~0); 12446438#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12446392#L572 assume !(1 == ~t8_pc~0); 12446393#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 12446396#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12446802#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12445873#L1127 assume !(0 != activate_threads_~tmp___7~0); 12445874#L1127-2 assume !(1 == ~M_E~0); 12445875#L954-1 assume !(1 == ~T1_E~0); 12446773#L959-1 assume !(1 == ~T2_E~0); 12446512#L964-1 assume !(1 == ~T3_E~0); 12446330#L969-1 assume !(1 == ~T4_E~0); 12445977#L974-1 assume !(1 == ~T5_E~0); 12445978#L979-1 assume !(1 == ~T6_E~0); 12446595#L984-1 assume !(1 == ~T7_E~0); 12446305#L989-1 assume !(1 == ~T8_E~0); 12446145#L994-1 assume !(1 == ~E_M~0); 12446146#L999-1 assume !(1 == ~E_1~0); 12446848#L1004-1 assume !(1 == ~E_2~0); 12446445#L1009-1 assume !(1 == ~E_3~0); 12446066#L1014-1 assume !(1 == ~E_4~0); 12446067#L1019-1 assume !(1 == ~E_5~0); 12446931#L1024-1 assume !(1 == ~E_6~0); 12446682#L1029-1 assume !(1 == ~E_7~0); 12446407#L1034-1 assume !(1 == ~E_8~0); 12446408#L1305-1 assume !false; 12554955#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 12554953#L831 [2019-12-07 13:02:53,071 INFO L796 eck$LassoCheckResult]: Loop: 12554953#L831 assume !false; 12554951#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12554949#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 12554947#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12554945#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 12554943#L714 assume 0 != eval_~tmp~0; 12554941#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 12554938#L722 assume !(0 != eval_~tmp_ndt_1~0); 12554937#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 12554936#L736 assume !(0 != eval_~tmp_ndt_2~0); 12554934#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 12550950#L750 assume !(0 != eval_~tmp_ndt_3~0); 12554933#L747 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 12554929#L764 assume !(0 != eval_~tmp_ndt_4~0); 12554928#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 12553148#L778 assume !(0 != eval_~tmp_ndt_5~0); 12554927#L775 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 12595725#L792 assume !(0 != eval_~tmp_ndt_6~0); 12595726#L789 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 13175450#L806 assume !(0 != eval_~tmp_ndt_7~0); 12554965#L803 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 12554961#L820 assume !(0 != eval_~tmp_ndt_8~0); 12554956#L817 assume !(0 == ~t8_st~0); 12554953#L831 [2019-12-07 13:02:53,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:53,071 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 7 times [2019-12-07 13:02:53,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:53,071 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478492633] [2019-12-07 13:02:53,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:53,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:53,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:53,087 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:53,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:53,087 INFO L82 PathProgramCache]: Analyzing trace with hash -260982928, now seen corresponding path program 1 times [2019-12-07 13:02:53,087 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:53,087 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31113691] [2019-12-07 13:02:53,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:53,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:53,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:02:53,091 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:02:53,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:02:53,091 INFO L82 PathProgramCache]: Analyzing trace with hash 2017797419, now seen corresponding path program 1 times [2019-12-07 13:02:53,091 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:02:53,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252997930] [2019-12-07 13:02:53,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:02:53,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:02:53,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:02:53,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1252997930] [2019-12-07 13:02:53,114 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:02:53,114 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:02:53,115 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658038600] [2019-12-07 13:02:53,240 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:02:53,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:02:53,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:02:53,240 INFO L87 Difference]: Start difference. First operand 976257 states and 1199081 transitions. cyclomatic complexity: 222872 Second operand 3 states. [2019-12-07 13:02:56,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:02:56,408 INFO L93 Difference]: Finished difference Result 1379786 states and 1693972 transitions. [2019-12-07 13:02:56,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:02:56,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1379786 states and 1693972 transitions. [2019-12-07 13:03:01,187 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1315091 [2019-12-07 13:03:04,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1379786 states to 1379786 states and 1693972 transitions. [2019-12-07 13:03:04,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1379786 [2019-12-07 13:03:04,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1379786 [2019-12-07 13:03:04,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1379786 states and 1693972 transitions. [2019-12-07 13:03:05,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-12-07 13:03:05,227 INFO L688 BuchiCegarLoop]: Abstraction has 1379786 states and 1693972 transitions. [2019-12-07 13:03:05,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1379786 states and 1693972 transitions. [2019-12-07 13:03:21,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1379786 to 1379786. [2019-12-07 13:03:21,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1379786 states. [2019-12-07 13:03:24,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1379786 states to 1379786 states and 1693972 transitions. [2019-12-07 13:03:24,234 INFO L711 BuchiCegarLoop]: Abstraction has 1379786 states and 1693972 transitions. [2019-12-07 13:03:24,234 INFO L591 BuchiCegarLoop]: Abstraction has 1379786 states and 1693972 transitions. [2019-12-07 13:03:24,234 INFO L424 BuchiCegarLoop]: ======== Iteration 49============ [2019-12-07 13:03:24,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1379786 states and 1693972 transitions. [2019-12-07 13:03:27,652 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1315091 [2019-12-07 13:03:27,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-12-07 13:03:27,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-12-07 13:03:27,653 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:03:27,653 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:03:27,653 INFO L794 eck$LassoCheckResult]: Stem: 14802391#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14802311#L-1 havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14802312#L1268 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14802557#L592 assume 1 == ~m_i~0;~m_st~0 := 0; 14801892#L599-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14801893#L604-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14802669#L609-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14802558#L614-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14802266#L619-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14802267#L624-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14802772#L629-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14802508#L634-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 14802166#L639-1 assume !(0 == ~M_E~0); 14802167#L856-1 assume !(0 == ~T1_E~0); 14802272#L861-1 assume !(0 == ~T2_E~0); 14802273#L866-1 assume !(0 == ~T3_E~0); 14802805#L871-1 assume !(0 == ~T4_E~0); 14802538#L876-1 assume !(0 == ~T5_E~0); 14802372#L881-1 assume !(0 == ~T6_E~0); 14802032#L886-1 assume !(0 == ~T7_E~0); 14802033#L891-1 assume !(0 == ~T8_E~0); 14802629#L896-1 assume !(0 == ~E_M~0); 14802337#L901-1 assume !(0 == ~E_1~0); 14801987#L906-1 assume !(0 == ~E_2~0); 14801988#L911-1 assume !(0 == ~E_3~0); 14802865#L916-1 assume !(0 == ~E_4~0); 14802448#L921-1 assume !(0 == ~E_5~0); 14802104#L926-1 assume !(0 == ~E_6~0); 14802105#L931-1 assume !(0 == ~E_7~0); 14802957#L936-1 assume !(0 == ~E_8~0); 14802716#L941-1 havoc activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14802062#L420 assume !(1 == ~m_pc~0); 14802063#L420-2 is_master_triggered_~__retres1~0 := 0; 14802069#L431 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14802787#L432 activate_threads_#t~ret12 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14802861#L1063 assume !(0 != activate_threads_~tmp~1); 14803059#L1063-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14802326#L439 assume !(1 == ~t1_pc~0); 14802327#L439-2 is_transmit1_triggered_~__retres1~1 := 0; 14802330#L450 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14802918#L451 activate_threads_#t~ret13 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14802853#L1071 assume !(0 != activate_threads_~tmp___0~0); 14802837#L1071-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14802517#L458 assume !(1 == ~t2_pc~0); 14802490#L458-2 is_transmit2_triggered_~__retres1~2 := 0; 14802491#L469 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14803049#L470 activate_threads_#t~ret14 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14802381#L1079 assume !(0 != activate_threads_~tmp___1~0); 14802382#L1079-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14802384#L477 assume !(1 == ~t3_pc~0); 14802657#L477-2 is_transmit3_triggered_~__retres1~3 := 0; 14801959#L488 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14801960#L489 activate_threads_#t~ret15 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14802052#L1087 assume !(0 != activate_threads_~tmp___2~0); 14803069#L1087-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14802834#L496 assume !(1 == ~t4_pc~0); 14802779#L496-2 is_transmit4_triggered_~__retres1~4 := 0; 14802176#L507 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14802084#L508 activate_threads_#t~ret16 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14802085#L1095 assume !(0 != activate_threads_~tmp___3~0); 14802726#L1095-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14802727#L515 assume !(1 == ~t5_pc~0); 14803063#L515-2 is_transmit5_triggered_~__retres1~5 := 0; 14802544#L526 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14802336#L527 activate_threads_#t~ret17 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14802298#L1103 assume !(0 != activate_threads_~tmp___4~0); 14802284#L1103-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14802017#L534 assume !(1 == ~t6_pc~0); 14802007#L534-2 is_transmit6_triggered_~__retres1~6 := 0; 14802008#L545 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14802511#L546 activate_threads_#t~ret18 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14802512#L1111 assume !(0 != activate_threads_~tmp___5~0); 14802893#L1111-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14802247#L553 assume !(1 == ~t7_pc~0); 14801985#L553-2 is_transmit7_triggered_~__retres1~7 := 0; 14802254#L564 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14802671#L565 activate_threads_#t~ret19 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14802484#L1119 assume !(0 != activate_threads_~tmp___6~0); 14802463#L1119-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 14802420#L572 assume !(1 == ~t8_pc~0); 14802421#L572-2 is_transmit8_triggered_~__retres1~8 := 0; 14802423#L583 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14802830#L584 activate_threads_#t~ret20 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14801923#L1127 assume !(0 != activate_threads_~tmp___7~0); 14801924#L1127-2 assume !(1 == ~M_E~0); 14801925#L954-1 assume !(1 == ~T1_E~0); 14802801#L959-1 assume !(1 == ~T2_E~0); 14802536#L964-1 assume !(1 == ~T3_E~0); 14802366#L969-1 assume !(1 == ~T4_E~0); 14802028#L974-1 assume !(1 == ~T5_E~0); 14802029#L979-1 assume !(1 == ~T6_E~0); 14802625#L984-1 assume !(1 == ~T7_E~0); 14802341#L989-1 assume !(1 == ~T8_E~0); 14802189#L994-1 assume !(1 == ~E_M~0); 14802190#L999-1 assume !(1 == ~E_1~0); 14802871#L1004-1 assume !(1 == ~E_2~0); 14802469#L1009-1 assume !(1 == ~E_3~0); 14802114#L1014-1 assume !(1 == ~E_4~0); 14802115#L1019-1 assume !(1 == ~E_5~0); 14802964#L1024-1 assume !(1 == ~E_6~0); 14802712#L1029-1 assume !(1 == ~E_7~0); 14802433#L1034-1 assume !(1 == ~E_8~0); 14802434#L1305-1 assume !false; 15895430#L1306 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_#t~nondet6, eval_~tmp_ndt_4~0, eval_#t~nondet7, eval_~tmp_ndt_5~0, eval_#t~nondet8, eval_~tmp_ndt_6~0, eval_#t~nondet9, eval_~tmp_ndt_7~0, eval_#t~nondet10, eval_~tmp_ndt_8~0, eval_#t~nondet11, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 15895429#L831 [2019-12-07 13:03:27,653 INFO L796 eck$LassoCheckResult]: Loop: 15895429#L831 assume !false; 15895428#L710 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15895427#L652 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15895424#L699 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15895423#L700 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 15895422#L714 assume 0 != eval_~tmp~0; 15895421#L714-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 15895417#L722 assume !(0 != eval_~tmp_ndt_1~0); 15895418#L719 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 15214849#L736 assume !(0 != eval_~tmp_ndt_2~0); 15033982#L733 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 15033979#L750 assume !(0 != eval_~tmp_ndt_3~0); 15033977#L747 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 15033974#L764 assume !(0 != eval_~tmp_ndt_4~0); 15033972#L761 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 15033930#L778 assume !(0 != eval_~tmp_ndt_5~0); 15033970#L775 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 15036884#L792 assume !(0 != eval_~tmp_ndt_6~0); 15036882#L789 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 15036878#L806 assume !(0 != eval_~tmp_ndt_7~0); 15036880#L803 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 15895433#L820 assume !(0 != eval_~tmp_ndt_8~0); 15895432#L817 assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 15895431#L834 assume !(0 != eval_~tmp_ndt_9~0); 15895429#L831 [2019-12-07 13:03:27,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:03:27,653 INFO L82 PathProgramCache]: Analyzing trace with hash 1559275686, now seen corresponding path program 8 times [2019-12-07 13:03:27,653 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:03:27,654 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280868128] [2019-12-07 13:03:27,654 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:03:27,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,672 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:03:27,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:03:27,672 INFO L82 PathProgramCache]: Analyzing trace with hash 499459091, now seen corresponding path program 1 times [2019-12-07 13:03:27,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:03:27,673 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377557351] [2019-12-07 13:03:27,673 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:03:27,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,676 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:03:27,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:03:27,677 INFO L82 PathProgramCache]: Analyzing trace with hash -1872794184, now seen corresponding path program 1 times [2019-12-07 13:03:27,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:03:27,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579632998] [2019-12-07 13:03:27,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:03:27,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:03:27,698 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:03:28,958 WARN L192 SmtUtils]: Spent 1.13 s on a formula simplification. DAG size of input: 291 DAG size of output: 192 [2019-12-07 13:03:29,148 WARN L192 SmtUtils]: Spent 186.00 ms on a formula simplification that was a NOOP. DAG size: 154 [2019-12-07 13:03:29,189 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 01:03:29 BoogieIcfgContainer [2019-12-07 13:03:29,189 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-12-07 13:03:29,189 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 13:03:29,189 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 13:03:29,190 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 13:03:29,190 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:00:26" (3/4) ... [2019-12-07 13:03:29,193 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-12-07 13:03:29,249 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_bcc92602-86da-45cb-ad9b-58ed97caea18/bin/uautomizer/witness.graphml [2019-12-07 13:03:29,249 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 13:03:29,250 INFO L168 Benchmark]: Toolchain (without parser) took 183972.91 ms. Allocated memory was 1.0 GB in the beginning and 11.1 GB in the end (delta: 10.1 GB). Free memory was 946.3 MB in the beginning and 4.0 GB in the end (delta: -3.0 GB). Peak memory consumption was 7.0 GB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,250 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 13:03:29,250 INFO L168 Benchmark]: CACSL2BoogieTranslator took 299.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -129.1 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,250 INFO L168 Benchmark]: Boogie Procedure Inliner took 55.20 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,250 INFO L168 Benchmark]: Boogie Preprocessor took 57.71 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,251 INFO L168 Benchmark]: RCFGBuilder took 1034.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 860.9 MB in the end (delta: 198.3 MB). Peak memory consumption was 198.3 MB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,251 INFO L168 Benchmark]: BuchiAutomizer took 182463.42 ms. Allocated memory was 1.1 GB in the beginning and 11.1 GB in the end (delta: 10.0 GB). Free memory was 860.9 MB in the beginning and 4.0 GB in the end (delta: -3.1 GB). Peak memory consumption was 8.3 GB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,251 INFO L168 Benchmark]: Witness Printer took 59.71 ms. Allocated memory is still 11.1 GB. Free memory was 4.0 GB in the beginning and 4.0 GB in the end (delta: 9.3 MB). Peak memory consumption was 9.3 MB. Max. memory is 11.5 GB. [2019-12-07 13:03:29,253 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 299.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 91.2 MB). Free memory was 946.3 MB in the beginning and 1.1 GB in the end (delta: -129.1 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 55.20 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 57.71 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.7 MB). Peak memory consumption was 10.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1034.67 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 860.9 MB in the end (delta: 198.3 MB). Peak memory consumption was 198.3 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 182463.42 ms. Allocated memory was 1.1 GB in the beginning and 11.1 GB in the end (delta: 10.0 GB). Free memory was 860.9 MB in the beginning and 4.0 GB in the end (delta: -3.1 GB). Peak memory consumption was 8.3 GB. Max. memory is 11.5 GB. * Witness Printer took 59.71 ms. Allocated memory is still 11.1 GB. Free memory was 4.0 GB in the beginning and 4.0 GB in the end (delta: 9.3 MB). Peak memory consumption was 9.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 49 terminating modules (48 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_M + 1 and consists of 3 locations. 48 modules have a trivial ranking function, the largest among these consists of 11 locations. The remainder module has 1379786 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 182.4s and 49 iterations. TraceHistogramMax:2. Analysis of lassos took 8.5s. Construction of modules took 1.4s. Büchi inclusion checks took 18.3s. Highest rank in rank-based complementation 3. Minimization of det autom 42. Minimization of nondet autom 7. Automata minimization 74.5s AutomataMinimizationTime, 49 MinimizatonAttempts, 856421 StatesRemovedByMinimization, 25 NontrivialMinimizations. Non-live state removal took 52.9s Buchi closure took 2.9s. Biggest automaton had 1379786 states and ocurred in iteration 48. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 73860 SDtfs, 86312 SDslu, 91247 SDs, 0 SdLazy, 2064 SolverSat, 894 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time LassoAnalysisResults: nont1 unkn0 SFLI16 SFLT0 conc7 concLT1 SILN2 SILU0 SILI22 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital306 mio100 ax100 hnf100 lsp3 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 5ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 26 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 709]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, __retres1=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45a5e8d8=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2918ce9c=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, T8_E=2, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t8_i=1, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18d4c420=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a3ac4bf=0, t8_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5639f013=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@361110ee=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@8da3011=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2469171f=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3dc9c1dd=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, tmp___7=0, __retres1=0, token=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, t8_st=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24e3a24=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d00f2f6=0, tmp___0=0, tmp=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41807a98=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60d2a1cd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@53fb0f64=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@15053fcd=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44726991=0, E_8=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10d078ae=0, tmp___0=0, t1_pc=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@440c147f=0, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, tmp_ndt_9=0, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, __retres1=0, t2_pc=0, __retres1=0, E_M=2, tmp___1=0, \result=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65cadec3=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6429ebad=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@78b3387=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 709]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int t8_pc = 0; [L23] int m_st ; [L24] int t1_st ; [L25] int t2_st ; [L26] int t3_st ; [L27] int t4_st ; [L28] int t5_st ; [L29] int t6_st ; [L30] int t7_st ; [L31] int t8_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int t4_i ; [L37] int t5_i ; [L38] int t6_i ; [L39] int t7_i ; [L40] int t8_i ; [L41] int M_E = 2; [L42] int T1_E = 2; [L43] int T2_E = 2; [L44] int T3_E = 2; [L45] int T4_E = 2; [L46] int T5_E = 2; [L47] int T6_E = 2; [L48] int T7_E = 2; [L49] int T8_E = 2; [L50] int E_M = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L69] int token ; [L71] int local ; [L1350] int __retres1 ; [L1258] m_i = 1 [L1259] t1_i = 1 [L1260] t2_i = 1 [L1261] t3_i = 1 [L1262] t4_i = 1 [L1263] t5_i = 1 [L1264] t6_i = 1 [L1265] t7_i = 1 [L1266] t8_i = 1 [L1291] int kernel_st ; [L1292] int tmp ; [L1293] int tmp___0 ; [L1297] kernel_st = 0 [L599] COND TRUE m_i == 1 [L600] m_st = 0 [L604] COND TRUE t1_i == 1 [L605] t1_st = 0 [L609] COND TRUE t2_i == 1 [L610] t2_st = 0 [L614] COND TRUE t3_i == 1 [L615] t3_st = 0 [L619] COND TRUE t4_i == 1 [L620] t4_st = 0 [L624] COND TRUE t5_i == 1 [L625] t5_st = 0 [L629] COND TRUE t6_i == 1 [L630] t6_st = 0 [L634] COND TRUE t7_i == 1 [L635] t7_st = 0 [L639] COND TRUE t8_i == 1 [L640] t8_st = 0 [L856] COND FALSE !(M_E == 0) [L861] COND FALSE !(T1_E == 0) [L866] COND FALSE !(T2_E == 0) [L871] COND FALSE !(T3_E == 0) [L876] COND FALSE !(T4_E == 0) [L881] COND FALSE !(T5_E == 0) [L886] COND FALSE !(T6_E == 0) [L891] COND FALSE !(T7_E == 0) [L896] COND FALSE !(T8_E == 0) [L901] COND FALSE !(E_M == 0) [L906] COND FALSE !(E_1 == 0) [L911] COND FALSE !(E_2 == 0) [L916] COND FALSE !(E_3 == 0) [L921] COND FALSE !(E_4 == 0) [L926] COND FALSE !(E_5 == 0) [L931] COND FALSE !(E_6 == 0) [L936] COND FALSE !(E_7 == 0) [L941] COND FALSE !(E_8 == 0) [L1049] int tmp ; [L1050] int tmp___0 ; [L1051] int tmp___1 ; [L1052] int tmp___2 ; [L1053] int tmp___3 ; [L1054] int tmp___4 ; [L1055] int tmp___5 ; [L1056] int tmp___6 ; [L1057] int tmp___7 ; [L417] int __retres1 ; [L420] COND FALSE !(m_pc == 1) [L430] __retres1 = 0 [L432] return (__retres1); [L1061] tmp = is_master_triggered() [L1063] COND FALSE !(\read(tmp)) [L436] int __retres1 ; [L439] COND FALSE !(t1_pc == 1) [L449] __retres1 = 0 [L451] return (__retres1); [L1069] tmp___0 = is_transmit1_triggered() [L1071] COND FALSE !(\read(tmp___0)) [L455] int __retres1 ; [L458] COND FALSE !(t2_pc == 1) [L468] __retres1 = 0 [L470] return (__retres1); [L1077] tmp___1 = is_transmit2_triggered() [L1079] COND FALSE !(\read(tmp___1)) [L474] int __retres1 ; [L477] COND FALSE !(t3_pc == 1) [L487] __retres1 = 0 [L489] return (__retres1); [L1085] tmp___2 = is_transmit3_triggered() [L1087] COND FALSE !(\read(tmp___2)) [L493] int __retres1 ; [L496] COND FALSE !(t4_pc == 1) [L506] __retres1 = 0 [L508] return (__retres1); [L1093] tmp___3 = is_transmit4_triggered() [L1095] COND FALSE !(\read(tmp___3)) [L512] int __retres1 ; [L515] COND FALSE !(t5_pc == 1) [L525] __retres1 = 0 [L527] return (__retres1); [L1101] tmp___4 = is_transmit5_triggered() [L1103] COND FALSE !(\read(tmp___4)) [L531] int __retres1 ; [L534] COND FALSE !(t6_pc == 1) [L544] __retres1 = 0 [L546] return (__retres1); [L1109] tmp___5 = is_transmit6_triggered() [L1111] COND FALSE !(\read(tmp___5)) [L550] int __retres1 ; [L553] COND FALSE !(t7_pc == 1) [L563] __retres1 = 0 [L565] return (__retres1); [L1117] tmp___6 = is_transmit7_triggered() [L1119] COND FALSE !(\read(tmp___6)) [L569] int __retres1 ; [L572] COND FALSE !(t8_pc == 1) [L582] __retres1 = 0 [L584] return (__retres1); [L1125] tmp___7 = is_transmit8_triggered() [L1127] COND FALSE !(\read(tmp___7)) [L954] COND FALSE !(M_E == 1) [L959] COND FALSE !(T1_E == 1) [L964] COND FALSE !(T2_E == 1) [L969] COND FALSE !(T3_E == 1) [L974] COND FALSE !(T4_E == 1) [L979] COND FALSE !(T5_E == 1) [L984] COND FALSE !(T6_E == 1) [L989] COND FALSE !(T7_E == 1) [L994] COND FALSE !(T8_E == 1) [L999] COND FALSE !(E_M == 1) [L1004] COND FALSE !(E_1 == 1) [L1009] COND FALSE !(E_2 == 1) [L1014] COND FALSE !(E_3 == 1) [L1019] COND FALSE !(E_4 == 1) [L1024] COND FALSE !(E_5 == 1) [L1029] COND FALSE !(E_6 == 1) [L1034] COND FALSE !(E_7 == 1) [L1039] COND FALSE !(E_8 == 1) [L1305] COND TRUE 1 [L1308] kernel_st = 1 [L705] int tmp ; Loop: [L709] COND TRUE 1 [L649] int __retres1 ; [L652] COND TRUE m_st == 0 [L653] __retres1 = 1 [L700] return (__retres1); [L712] tmp = exists_runnable_thread() [L714] COND TRUE \read(tmp) [L719] COND TRUE m_st == 0 [L720] int tmp_ndt_1; [L721] tmp_ndt_1 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_1)) [L733] COND TRUE t1_st == 0 [L734] int tmp_ndt_2; [L735] tmp_ndt_2 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_2)) [L747] COND TRUE t2_st == 0 [L748] int tmp_ndt_3; [L749] tmp_ndt_3 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_3)) [L761] COND TRUE t3_st == 0 [L762] int tmp_ndt_4; [L763] tmp_ndt_4 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_4)) [L775] COND TRUE t4_st == 0 [L776] int tmp_ndt_5; [L777] tmp_ndt_5 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_5)) [L789] COND TRUE t5_st == 0 [L790] int tmp_ndt_6; [L791] tmp_ndt_6 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_6)) [L803] COND TRUE t6_st == 0 [L804] int tmp_ndt_7; [L805] tmp_ndt_7 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_7)) [L817] COND TRUE t7_st == 0 [L818] int tmp_ndt_8; [L819] tmp_ndt_8 = __VERIFIER_nondet_int() [L820] COND FALSE !(\read(tmp_ndt_8)) [L831] COND TRUE t8_st == 0 [L832] int tmp_ndt_9; [L833] tmp_ndt_9 = __VERIFIER_nondet_int() [L834] COND FALSE !(\read(tmp_ndt_9)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...