./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6b5699aa Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-6b5699a [2019-11-26 02:12:47,706 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-26 02:12:47,708 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-26 02:12:47,724 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-26 02:12:47,724 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-26 02:12:47,726 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-26 02:12:47,728 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-26 02:12:47,736 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-26 02:12:47,741 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-26 02:12:47,746 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-26 02:12:47,747 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-26 02:12:47,748 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-26 02:12:47,748 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-26 02:12:47,751 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-26 02:12:47,752 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-26 02:12:47,753 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-26 02:12:47,754 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-26 02:12:47,755 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-26 02:12:47,757 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-26 02:12:47,761 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-26 02:12:47,765 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-26 02:12:47,768 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-26 02:12:47,769 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-26 02:12:47,770 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-26 02:12:47,772 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-26 02:12:47,773 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-26 02:12:47,773 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-26 02:12:47,774 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-26 02:12:47,775 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-26 02:12:47,776 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-26 02:12:47,777 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-26 02:12:47,777 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-26 02:12:47,778 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-26 02:12:47,779 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-26 02:12:47,780 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-26 02:12:47,780 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-26 02:12:47,781 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-26 02:12:47,781 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-26 02:12:47,781 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-26 02:12:47,782 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-26 02:12:47,783 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-26 02:12:47,784 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/config/svcomp-Reach-32bit-Taipan_Default.epf [2019-11-26 02:12:47,810 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-26 02:12:47,820 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-26 02:12:47,821 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-11-26 02:12:47,821 INFO L138 SettingsManager]: * User list type=DISABLED [2019-11-26 02:12:47,821 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-11-26 02:12:47,822 INFO L138 SettingsManager]: * Explicit value domain=true [2019-11-26 02:12:47,822 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-11-26 02:12:47,822 INFO L138 SettingsManager]: * Octagon Domain=false [2019-11-26 02:12:47,822 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2019-11-26 02:12:47,822 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-11-26 02:12:47,823 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2019-11-26 02:12:47,823 INFO L138 SettingsManager]: * Interval Domain=false [2019-11-26 02:12:47,823 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2019-11-26 02:12:47,823 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2019-11-26 02:12:47,824 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2019-11-26 02:12:47,824 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-26 02:12:47,825 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-26 02:12:47,825 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-26 02:12:47,826 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-26 02:12:47,826 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-26 02:12:47,826 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-26 02:12:47,827 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-26 02:12:47,827 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-26 02:12:47,827 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-26 02:12:47,827 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-26 02:12:47,828 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-26 02:12:47,828 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-26 02:12:47,828 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-26 02:12:47,828 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-26 02:12:47,829 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-26 02:12:47,829 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-26 02:12:47,829 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-26 02:12:47,829 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-26 02:12:47,830 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2019-11-26 02:12:47,830 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-26 02:12:47,830 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-26 02:12:47,830 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-11-26 02:12:47,831 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2019-11-26 02:12:48,017 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-26 02:12:48,033 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-26 02:12:48,037 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-26 02:12:48,038 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-26 02:12:48,038 INFO L275 PluginConnector]: CDTParser initialized [2019-11-26 02:12:48,039 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-26 02:12:48,105 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/data/948279703/afe958016dbe40c3b0222181f45b5557/FLAG683c7f8c6 [2019-11-26 02:12:48,570 INFO L306 CDTParser]: Found 1 translation units. [2019-11-26 02:12:48,571 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-26 02:12:48,582 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/data/948279703/afe958016dbe40c3b0222181f45b5557/FLAG683c7f8c6 [2019-11-26 02:12:48,968 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/data/948279703/afe958016dbe40c3b0222181f45b5557 [2019-11-26 02:12:48,970 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-26 02:12:48,972 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-26 02:12:48,973 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-26 02:12:48,978 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-26 02:12:48,981 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-26 02:12:48,982 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 02:12:48" (1/1) ... [2019-11-26 02:12:48,984 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60777a94 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:48, skipping insertion in model container [2019-11-26 02:12:48,985 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 02:12:48" (1/1) ... [2019-11-26 02:12:48,991 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-26 02:12:49,031 INFO L179 MainTranslator]: Built tables and reachable declarations [2019-11-26 02:12:49,353 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-26 02:12:49,359 INFO L201 MainTranslator]: Completed pre-run [2019-11-26 02:12:49,404 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-26 02:12:49,425 INFO L205 MainTranslator]: Completed translation [2019-11-26 02:12:49,426 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49 WrapperNode [2019-11-26 02:12:49,426 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-26 02:12:49,427 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-26 02:12:49,427 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-26 02:12:49,427 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-26 02:12:49,436 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,444 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,484 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-26 02:12:49,484 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-26 02:12:49,484 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-26 02:12:49,485 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-26 02:12:49,493 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,493 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,499 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,499 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,513 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,527 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,532 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... [2019-11-26 02:12:49,539 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-26 02:12:49,540 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-26 02:12:49,540 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-26 02:12:49,540 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-26 02:12:49,541 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-26 02:12:49,624 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-26 02:12:49,626 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-26 02:12:52,182 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-26 02:12:52,182 INFO L284 CfgBuilder]: Removed 148 assume(true) statements. [2019-11-26 02:12:52,183 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 02:12:52 BoogieIcfgContainer [2019-11-26 02:12:52,184 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-26 02:12:52,185 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-26 02:12:52,185 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-26 02:12:52,188 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-26 02:12:52,188 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.11 02:12:48" (1/3) ... [2019-11-26 02:12:52,188 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a57733 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 02:12:52, skipping insertion in model container [2019-11-26 02:12:52,189 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 02:12:49" (2/3) ... [2019-11-26 02:12:52,189 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a57733 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 02:12:52, skipping insertion in model container [2019-11-26 02:12:52,189 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 02:12:52" (3/3) ... [2019-11-26 02:12:52,190 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2019-11-26 02:12:52,199 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-26 02:12:52,206 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-26 02:12:52,216 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-26 02:12:52,241 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-26 02:12:52,241 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-26 02:12:52,242 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-26 02:12:52,242 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-26 02:12:52,242 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-26 02:12:52,242 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-26 02:12:52,242 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-26 02:12:52,243 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-26 02:12:52,266 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states. [2019-11-26 02:12:52,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-26 02:12:52,277 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:52,278 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:52,278 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:52,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:52,284 INFO L82 PathProgramCache]: Analyzing trace with hash -321320626, now seen corresponding path program 1 times [2019-11-26 02:12:52,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:52,294 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634295086] [2019-11-26 02:12:52,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:52,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:52,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:52,521 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634295086] [2019-11-26 02:12:52,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:52,523 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:52,524 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312592129] [2019-11-26 02:12:52,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:52,531 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:52,544 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:52,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:52,547 INFO L87 Difference]: Start difference. First operand 178 states. Second operand 3 states. [2019-11-26 02:12:52,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:52,703 INFO L93 Difference]: Finished difference Result 481 states and 740 transitions. [2019-11-26 02:12:52,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:52,705 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-26 02:12:52,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:52,726 INFO L225 Difference]: With dead ends: 481 [2019-11-26 02:12:52,726 INFO L226 Difference]: Without dead ends: 305 [2019-11-26 02:12:52,730 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:52,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2019-11-26 02:12:52,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 302. [2019-11-26 02:12:52,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2019-11-26 02:12:52,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 452 transitions. [2019-11-26 02:12:52,824 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 452 transitions. Word has length 28 [2019-11-26 02:12:52,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:52,824 INFO L462 AbstractCegarLoop]: Abstraction has 302 states and 452 transitions. [2019-11-26 02:12:52,824 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:52,825 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 452 transitions. [2019-11-26 02:12:52,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-26 02:12:52,826 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:52,826 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:52,827 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:52,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:52,827 INFO L82 PathProgramCache]: Analyzing trace with hash -1911715603, now seen corresponding path program 1 times [2019-11-26 02:12:52,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:52,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095101820] [2019-11-26 02:12:52,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:52,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:52,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:52,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095101820] [2019-11-26 02:12:52,884 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:52,884 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:52,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998507435] [2019-11-26 02:12:52,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:52,887 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:52,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:52,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:52,887 INFO L87 Difference]: Start difference. First operand 302 states and 452 transitions. Second operand 3 states. [2019-11-26 02:12:52,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:52,980 INFO L93 Difference]: Finished difference Result 824 states and 1233 transitions. [2019-11-26 02:12:52,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:52,981 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-26 02:12:52,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:52,985 INFO L225 Difference]: With dead ends: 824 [2019-11-26 02:12:52,985 INFO L226 Difference]: Without dead ends: 535 [2019-11-26 02:12:52,988 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:52,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 535 states. [2019-11-26 02:12:53,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 535 to 531. [2019-11-26 02:12:53,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 531 states. [2019-11-26 02:12:53,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 784 transitions. [2019-11-26 02:12:53,066 INFO L78 Accepts]: Start accepts. Automaton has 531 states and 784 transitions. Word has length 28 [2019-11-26 02:12:53,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:53,066 INFO L462 AbstractCegarLoop]: Abstraction has 531 states and 784 transitions. [2019-11-26 02:12:53,067 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:53,067 INFO L276 IsEmpty]: Start isEmpty. Operand 531 states and 784 transitions. [2019-11-26 02:12:53,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-26 02:12:53,068 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:53,069 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:53,069 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:53,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:53,069 INFO L82 PathProgramCache]: Analyzing trace with hash -771363892, now seen corresponding path program 1 times [2019-11-26 02:12:53,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:53,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854458001] [2019-11-26 02:12:53,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:53,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:53,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:53,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854458001] [2019-11-26 02:12:53,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:53,131 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:53,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081098416] [2019-11-26 02:12:53,131 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:53,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:53,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:53,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:53,132 INFO L87 Difference]: Start difference. First operand 531 states and 784 transitions. Second operand 3 states. [2019-11-26 02:12:53,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:53,207 INFO L93 Difference]: Finished difference Result 1531 states and 2255 transitions. [2019-11-26 02:12:53,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:53,208 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2019-11-26 02:12:53,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:53,213 INFO L225 Difference]: With dead ends: 1531 [2019-11-26 02:12:53,214 INFO L226 Difference]: Without dead ends: 1016 [2019-11-26 02:12:53,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:53,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1016 states. [2019-11-26 02:12:53,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1016 to 1012. [2019-11-26 02:12:53,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1012 states. [2019-11-26 02:12:53,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1012 states to 1012 states and 1463 transitions. [2019-11-26 02:12:53,247 INFO L78 Accepts]: Start accepts. Automaton has 1012 states and 1463 transitions. Word has length 28 [2019-11-26 02:12:53,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:53,247 INFO L462 AbstractCegarLoop]: Abstraction has 1012 states and 1463 transitions. [2019-11-26 02:12:53,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:53,247 INFO L276 IsEmpty]: Start isEmpty. Operand 1012 states and 1463 transitions. [2019-11-26 02:12:53,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2019-11-26 02:12:53,251 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:53,251 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:53,252 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:53,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:53,252 INFO L82 PathProgramCache]: Analyzing trace with hash -430432055, now seen corresponding path program 1 times [2019-11-26 02:12:53,252 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:53,252 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872880390] [2019-11-26 02:12:53,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:53,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:53,363 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:53,363 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872880390] [2019-11-26 02:12:53,363 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:53,364 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-26 02:12:53,364 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425036151] [2019-11-26 02:12:53,364 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-26 02:12:53,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:53,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-26 02:12:53,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:12:53,365 INFO L87 Difference]: Start difference. First operand 1012 states and 1463 transitions. Second operand 4 states. [2019-11-26 02:12:53,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:53,514 INFO L93 Difference]: Finished difference Result 3196 states and 4662 transitions. [2019-11-26 02:12:53,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-26 02:12:53,514 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2019-11-26 02:12:53,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:53,528 INFO L225 Difference]: With dead ends: 3196 [2019-11-26 02:12:53,528 INFO L226 Difference]: Without dead ends: 2202 [2019-11-26 02:12:53,531 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:12:53,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2202 states. [2019-11-26 02:12:53,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2202 to 1188. [2019-11-26 02:12:53,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1188 states. [2019-11-26 02:12:53,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1188 states to 1188 states and 1767 transitions. [2019-11-26 02:12:53,585 INFO L78 Accepts]: Start accepts. Automaton has 1188 states and 1767 transitions. Word has length 38 [2019-11-26 02:12:53,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:53,586 INFO L462 AbstractCegarLoop]: Abstraction has 1188 states and 1767 transitions. [2019-11-26 02:12:53,586 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-26 02:12:53,587 INFO L276 IsEmpty]: Start isEmpty. Operand 1188 states and 1767 transitions. [2019-11-26 02:12:53,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-26 02:12:53,592 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:53,592 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:53,592 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:53,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:53,593 INFO L82 PathProgramCache]: Analyzing trace with hash 807646039, now seen corresponding path program 1 times [2019-11-26 02:12:53,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:53,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970386679] [2019-11-26 02:12:53,594 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:53,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:53,684 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:53,686 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970386679] [2019-11-26 02:12:53,686 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:53,686 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:53,686 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1886114250] [2019-11-26 02:12:53,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:53,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:53,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:53,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:53,688 INFO L87 Difference]: Start difference. First operand 1188 states and 1767 transitions. Second operand 3 states. [2019-11-26 02:12:53,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:53,789 INFO L93 Difference]: Finished difference Result 2784 states and 4217 transitions. [2019-11-26 02:12:53,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:53,790 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 57 [2019-11-26 02:12:53,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:53,800 INFO L225 Difference]: With dead ends: 2784 [2019-11-26 02:12:53,801 INFO L226 Difference]: Without dead ends: 1614 [2019-11-26 02:12:53,803 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:53,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1614 states. [2019-11-26 02:12:53,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1614 to 1500. [2019-11-26 02:12:53,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2019-11-26 02:12:53,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2295 transitions. [2019-11-26 02:12:53,871 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 2295 transitions. Word has length 57 [2019-11-26 02:12:53,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:53,873 INFO L462 AbstractCegarLoop]: Abstraction has 1500 states and 2295 transitions. [2019-11-26 02:12:53,873 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:53,873 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 2295 transitions. [2019-11-26 02:12:53,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-26 02:12:53,877 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:53,877 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:53,878 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:53,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:53,878 INFO L82 PathProgramCache]: Analyzing trace with hash 1836899025, now seen corresponding path program 1 times [2019-11-26 02:12:53,878 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:53,879 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856997769] [2019-11-26 02:12:53,879 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:53,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:53,954 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:53,954 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [856997769] [2019-11-26 02:12:53,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:53,955 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:53,955 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332051333] [2019-11-26 02:12:53,955 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:53,956 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:53,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:53,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:53,956 INFO L87 Difference]: Start difference. First operand 1500 states and 2295 transitions. Second operand 3 states. [2019-11-26 02:12:54,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:54,096 INFO L93 Difference]: Finished difference Result 3846 states and 5955 transitions. [2019-11-26 02:12:54,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:54,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 57 [2019-11-26 02:12:54,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:54,114 INFO L225 Difference]: With dead ends: 3846 [2019-11-26 02:12:54,114 INFO L226 Difference]: Without dead ends: 2364 [2019-11-26 02:12:54,117 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:54,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2364 states. [2019-11-26 02:12:54,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2364 to 2060. [2019-11-26 02:12:54,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2060 states. [2019-11-26 02:12:54,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2060 states to 2060 states and 3223 transitions. [2019-11-26 02:12:54,231 INFO L78 Accepts]: Start accepts. Automaton has 2060 states and 3223 transitions. Word has length 57 [2019-11-26 02:12:54,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:54,234 INFO L462 AbstractCegarLoop]: Abstraction has 2060 states and 3223 transitions. [2019-11-26 02:12:54,234 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:54,234 INFO L276 IsEmpty]: Start isEmpty. Operand 2060 states and 3223 transitions. [2019-11-26 02:12:54,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-26 02:12:54,240 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:54,240 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:54,240 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:54,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:54,241 INFO L82 PathProgramCache]: Analyzing trace with hash 179970460, now seen corresponding path program 1 times [2019-11-26 02:12:54,241 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:54,241 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189445250] [2019-11-26 02:12:54,249 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:54,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:54,333 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:54,333 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189445250] [2019-11-26 02:12:54,333 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:54,334 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:54,334 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583602157] [2019-11-26 02:12:54,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:54,334 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:54,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:54,335 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:54,335 INFO L87 Difference]: Start difference. First operand 2060 states and 3223 transitions. Second operand 3 states. [2019-11-26 02:12:54,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:54,448 INFO L93 Difference]: Finished difference Result 3108 states and 4886 transitions. [2019-11-26 02:12:54,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:54,449 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-26 02:12:54,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:54,461 INFO L225 Difference]: With dead ends: 3108 [2019-11-26 02:12:54,461 INFO L226 Difference]: Without dead ends: 2060 [2019-11-26 02:12:54,463 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:54,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2060 states. [2019-11-26 02:12:54,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2060 to 2030. [2019-11-26 02:12:54,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2030 states. [2019-11-26 02:12:54,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2030 states to 2030 states and 3141 transitions. [2019-11-26 02:12:54,555 INFO L78 Accepts]: Start accepts. Automaton has 2030 states and 3141 transitions. Word has length 58 [2019-11-26 02:12:54,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:54,557 INFO L462 AbstractCegarLoop]: Abstraction has 2030 states and 3141 transitions. [2019-11-26 02:12:54,557 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:54,557 INFO L276 IsEmpty]: Start isEmpty. Operand 2030 states and 3141 transitions. [2019-11-26 02:12:54,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-26 02:12:54,563 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:54,563 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:54,564 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:54,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:54,564 INFO L82 PathProgramCache]: Analyzing trace with hash 1468164989, now seen corresponding path program 1 times [2019-11-26 02:12:54,564 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:54,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311320916] [2019-11-26 02:12:54,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:54,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:54,620 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-26 02:12:54,621 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311320916] [2019-11-26 02:12:54,622 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:54,622 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:54,622 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643021309] [2019-11-26 02:12:54,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:54,623 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:54,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:54,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:54,623 INFO L87 Difference]: Start difference. First operand 2030 states and 3141 transitions. Second operand 3 states. [2019-11-26 02:12:54,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:54,752 INFO L93 Difference]: Finished difference Result 3032 states and 4706 transitions. [2019-11-26 02:12:54,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:54,753 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-26 02:12:54,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:54,766 INFO L225 Difference]: With dead ends: 3032 [2019-11-26 02:12:54,766 INFO L226 Difference]: Without dead ends: 2030 [2019-11-26 02:12:54,768 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:54,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2030 states. [2019-11-26 02:12:54,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2030 to 2030. [2019-11-26 02:12:54,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2030 states. [2019-11-26 02:12:54,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2030 states to 2030 states and 3123 transitions. [2019-11-26 02:12:54,890 INFO L78 Accepts]: Start accepts. Automaton has 2030 states and 3123 transitions. Word has length 58 [2019-11-26 02:12:54,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:54,890 INFO L462 AbstractCegarLoop]: Abstraction has 2030 states and 3123 transitions. [2019-11-26 02:12:54,890 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:54,891 INFO L276 IsEmpty]: Start isEmpty. Operand 2030 states and 3123 transitions. [2019-11-26 02:12:54,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-11-26 02:12:54,896 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:54,896 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:54,896 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:54,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:54,897 INFO L82 PathProgramCache]: Analyzing trace with hash -1056359343, now seen corresponding path program 1 times [2019-11-26 02:12:54,897 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:54,897 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261158666] [2019-11-26 02:12:54,898 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:54,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:54,985 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:54,985 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261158666] [2019-11-26 02:12:54,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:54,986 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-26 02:12:54,990 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436188559] [2019-11-26 02:12:54,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-26 02:12:54,992 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:54,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-26 02:12:54,993 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-26 02:12:54,993 INFO L87 Difference]: Start difference. First operand 2030 states and 3123 transitions. Second operand 5 states. [2019-11-26 02:12:55,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:55,431 INFO L93 Difference]: Finished difference Result 6738 states and 10336 transitions. [2019-11-26 02:12:55,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-26 02:12:55,431 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 59 [2019-11-26 02:12:55,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:55,452 INFO L225 Difference]: With dead ends: 6738 [2019-11-26 02:12:55,452 INFO L226 Difference]: Without dead ends: 3322 [2019-11-26 02:12:55,457 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2019-11-26 02:12:55,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states. [2019-11-26 02:12:55,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 1821. [2019-11-26 02:12:55,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1821 states. [2019-11-26 02:12:55,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1821 states to 1821 states and 2680 transitions. [2019-11-26 02:12:55,563 INFO L78 Accepts]: Start accepts. Automaton has 1821 states and 2680 transitions. Word has length 59 [2019-11-26 02:12:55,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:55,564 INFO L462 AbstractCegarLoop]: Abstraction has 1821 states and 2680 transitions. [2019-11-26 02:12:55,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-26 02:12:55,565 INFO L276 IsEmpty]: Start isEmpty. Operand 1821 states and 2680 transitions. [2019-11-26 02:12:55,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-11-26 02:12:55,568 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:55,568 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:55,569 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:55,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:55,569 INFO L82 PathProgramCache]: Analyzing trace with hash 1291449910, now seen corresponding path program 1 times [2019-11-26 02:12:55,569 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:55,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662190554] [2019-11-26 02:12:55,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:55,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:55,615 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:55,615 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662190554] [2019-11-26 02:12:55,615 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:55,615 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-26 02:12:55,616 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154777891] [2019-11-26 02:12:55,616 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-26 02:12:55,616 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:55,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-26 02:12:55,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:12:55,617 INFO L87 Difference]: Start difference. First operand 1821 states and 2680 transitions. Second operand 4 states. [2019-11-26 02:12:55,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:55,835 INFO L93 Difference]: Finished difference Result 5544 states and 8292 transitions. [2019-11-26 02:12:55,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-26 02:12:55,835 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 60 [2019-11-26 02:12:55,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:55,856 INFO L225 Difference]: With dead ends: 5544 [2019-11-26 02:12:55,856 INFO L226 Difference]: Without dead ends: 3741 [2019-11-26 02:12:55,859 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:12:55,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3741 states. [2019-11-26 02:12:55,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3741 to 2457. [2019-11-26 02:12:55,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2457 states. [2019-11-26 02:12:55,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 2457 states and 3688 transitions. [2019-11-26 02:12:55,994 INFO L78 Accepts]: Start accepts. Automaton has 2457 states and 3688 transitions. Word has length 60 [2019-11-26 02:12:55,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:55,994 INFO L462 AbstractCegarLoop]: Abstraction has 2457 states and 3688 transitions. [2019-11-26 02:12:55,994 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-26 02:12:55,994 INFO L276 IsEmpty]: Start isEmpty. Operand 2457 states and 3688 transitions. [2019-11-26 02:12:56,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-26 02:12:56,001 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:56,001 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:56,001 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:56,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:56,002 INFO L82 PathProgramCache]: Analyzing trace with hash 766995459, now seen corresponding path program 1 times [2019-11-26 02:12:56,002 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:56,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421650108] [2019-11-26 02:12:56,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:56,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:56,050 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-26 02:12:56,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421650108] [2019-11-26 02:12:56,051 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:56,051 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:56,051 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198107357] [2019-11-26 02:12:56,051 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:56,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:56,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:56,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,052 INFO L87 Difference]: Start difference. First operand 2457 states and 3688 transitions. Second operand 3 states. [2019-11-26 02:12:56,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:56,187 INFO L93 Difference]: Finished difference Result 3987 states and 6013 transitions. [2019-11-26 02:12:56,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:56,187 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-26 02:12:56,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:56,200 INFO L225 Difference]: With dead ends: 3987 [2019-11-26 02:12:56,201 INFO L226 Difference]: Without dead ends: 2457 [2019-11-26 02:12:56,204 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2457 states. [2019-11-26 02:12:56,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2457 to 2457. [2019-11-26 02:12:56,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2457 states. [2019-11-26 02:12:56,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 2457 states and 3661 transitions. [2019-11-26 02:12:56,328 INFO L78 Accepts]: Start accepts. Automaton has 2457 states and 3661 transitions. Word has length 81 [2019-11-26 02:12:56,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:56,329 INFO L462 AbstractCegarLoop]: Abstraction has 2457 states and 3661 transitions. [2019-11-26 02:12:56,329 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:56,329 INFO L276 IsEmpty]: Start isEmpty. Operand 2457 states and 3661 transitions. [2019-11-26 02:12:56,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-26 02:12:56,333 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:56,333 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:56,334 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:56,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:56,334 INFO L82 PathProgramCache]: Analyzing trace with hash 530250019, now seen corresponding path program 1 times [2019-11-26 02:12:56,334 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:56,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045508042] [2019-11-26 02:12:56,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:56,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:56,376 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:56,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2045508042] [2019-11-26 02:12:56,376 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:56,377 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:56,377 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132759900] [2019-11-26 02:12:56,377 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:56,377 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:56,378 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:56,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,378 INFO L87 Difference]: Start difference. First operand 2457 states and 3661 transitions. Second operand 3 states. [2019-11-26 02:12:56,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:56,532 INFO L93 Difference]: Finished difference Result 3985 states and 5957 transitions. [2019-11-26 02:12:56,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:56,532 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-26 02:12:56,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:56,545 INFO L225 Difference]: With dead ends: 3985 [2019-11-26 02:12:56,545 INFO L226 Difference]: Without dead ends: 2455 [2019-11-26 02:12:56,548 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2455 states. [2019-11-26 02:12:56,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2455 to 2415. [2019-11-26 02:12:56,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2415 states. [2019-11-26 02:12:56,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2415 states to 2415 states and 3538 transitions. [2019-11-26 02:12:56,719 INFO L78 Accepts]: Start accepts. Automaton has 2415 states and 3538 transitions. Word has length 81 [2019-11-26 02:12:56,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:56,719 INFO L462 AbstractCegarLoop]: Abstraction has 2415 states and 3538 transitions. [2019-11-26 02:12:56,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:56,719 INFO L276 IsEmpty]: Start isEmpty. Operand 2415 states and 3538 transitions. [2019-11-26 02:12:56,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2019-11-26 02:12:56,723 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:56,723 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:56,723 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:56,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:56,724 INFO L82 PathProgramCache]: Analyzing trace with hash 2039038588, now seen corresponding path program 1 times [2019-11-26 02:12:56,724 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:56,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113120095] [2019-11-26 02:12:56,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:56,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:56,763 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-26 02:12:56,763 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113120095] [2019-11-26 02:12:56,763 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:56,763 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:56,763 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899482412] [2019-11-26 02:12:56,764 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:56,764 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:56,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:56,764 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,764 INFO L87 Difference]: Start difference. First operand 2415 states and 3538 transitions. Second operand 3 states. [2019-11-26 02:12:56,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:56,961 INFO L93 Difference]: Finished difference Result 6949 states and 10173 transitions. [2019-11-26 02:12:56,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:56,962 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 82 [2019-11-26 02:12:56,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:56,975 INFO L225 Difference]: With dead ends: 6949 [2019-11-26 02:12:56,976 INFO L226 Difference]: Without dead ends: 4543 [2019-11-26 02:12:56,980 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:56,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4543 states. [2019-11-26 02:12:57,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4543 to 4499. [2019-11-26 02:12:57,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4499 states. [2019-11-26 02:12:57,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4499 states to 4499 states and 6522 transitions. [2019-11-26 02:12:57,170 INFO L78 Accepts]: Start accepts. Automaton has 4499 states and 6522 transitions. Word has length 82 [2019-11-26 02:12:57,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:57,171 INFO L462 AbstractCegarLoop]: Abstraction has 4499 states and 6522 transitions. [2019-11-26 02:12:57,171 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:57,171 INFO L276 IsEmpty]: Start isEmpty. Operand 4499 states and 6522 transitions. [2019-11-26 02:12:57,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-11-26 02:12:57,178 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:57,178 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:57,178 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:57,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:57,179 INFO L82 PathProgramCache]: Analyzing trace with hash -544802934, now seen corresponding path program 1 times [2019-11-26 02:12:57,179 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:57,179 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681722755] [2019-11-26 02:12:57,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:57,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:57,230 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:57,231 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681722755] [2019-11-26 02:12:57,231 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:57,231 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-26 02:12:57,231 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052264850] [2019-11-26 02:12:57,231 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-26 02:12:57,232 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:57,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-26 02:12:57,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-26 02:12:57,232 INFO L87 Difference]: Start difference. First operand 4499 states and 6522 transitions. Second operand 5 states. [2019-11-26 02:12:57,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:57,690 INFO L93 Difference]: Finished difference Result 13233 states and 19204 transitions. [2019-11-26 02:12:57,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-26 02:12:57,691 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 83 [2019-11-26 02:12:57,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:57,702 INFO L225 Difference]: With dead ends: 13233 [2019-11-26 02:12:57,702 INFO L226 Difference]: Without dead ends: 6639 [2019-11-26 02:12:57,760 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2019-11-26 02:12:57,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6639 states. [2019-11-26 02:12:57,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6639 to 3797. [2019-11-26 02:12:57,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3797 states. [2019-11-26 02:12:57,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 3797 states and 5292 transitions. [2019-11-26 02:12:57,935 INFO L78 Accepts]: Start accepts. Automaton has 3797 states and 5292 transitions. Word has length 83 [2019-11-26 02:12:57,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:57,935 INFO L462 AbstractCegarLoop]: Abstraction has 3797 states and 5292 transitions. [2019-11-26 02:12:57,935 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-26 02:12:57,936 INFO L276 IsEmpty]: Start isEmpty. Operand 3797 states and 5292 transitions. [2019-11-26 02:12:57,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-11-26 02:12:57,941 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:57,941 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:57,942 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:57,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:57,942 INFO L82 PathProgramCache]: Analyzing trace with hash -1745744671, now seen corresponding path program 1 times [2019-11-26 02:12:57,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:57,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101968683] [2019-11-26 02:12:57,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:57,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:57,978 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:12:57,978 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101968683] [2019-11-26 02:12:57,978 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:57,979 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:57,979 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985531434] [2019-11-26 02:12:57,979 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:57,979 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:57,979 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:57,980 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:57,980 INFO L87 Difference]: Start difference. First operand 3797 states and 5292 transitions. Second operand 3 states. [2019-11-26 02:12:58,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:58,141 INFO L93 Difference]: Finished difference Result 6493 states and 9097 transitions. [2019-11-26 02:12:58,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:58,142 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2019-11-26 02:12:58,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:58,149 INFO L225 Difference]: With dead ends: 6493 [2019-11-26 02:12:58,149 INFO L226 Difference]: Without dead ends: 3797 [2019-11-26 02:12:58,152 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:58,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-26 02:12:58,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3757. [2019-11-26 02:12:58,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3757 states. [2019-11-26 02:12:58,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3757 states to 3757 states and 5110 transitions. [2019-11-26 02:12:58,315 INFO L78 Accepts]: Start accepts. Automaton has 3757 states and 5110 transitions. Word has length 106 [2019-11-26 02:12:58,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:58,316 INFO L462 AbstractCegarLoop]: Abstraction has 3757 states and 5110 transitions. [2019-11-26 02:12:58,316 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:58,316 INFO L276 IsEmpty]: Start isEmpty. Operand 3757 states and 5110 transitions. [2019-11-26 02:12:58,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2019-11-26 02:12:58,323 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:58,324 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:58,324 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:58,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:58,324 INFO L82 PathProgramCache]: Analyzing trace with hash -1015864797, now seen corresponding path program 1 times [2019-11-26 02:12:58,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:58,325 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871226710] [2019-11-26 02:12:58,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:58,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:58,375 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-26 02:12:58,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871226710] [2019-11-26 02:12:58,378 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:58,378 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:58,378 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721742881] [2019-11-26 02:12:58,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:58,379 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:58,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:58,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:58,379 INFO L87 Difference]: Start difference. First operand 3757 states and 5110 transitions. Second operand 3 states. [2019-11-26 02:12:58,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:58,557 INFO L93 Difference]: Finished difference Result 6405 states and 8725 transitions. [2019-11-26 02:12:58,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:58,558 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 106 [2019-11-26 02:12:58,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:58,565 INFO L225 Difference]: With dead ends: 6405 [2019-11-26 02:12:58,565 INFO L226 Difference]: Without dead ends: 3757 [2019-11-26 02:12:58,568 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:58,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3757 states. [2019-11-26 02:12:58,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3757 to 3757. [2019-11-26 02:12:58,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3757 states. [2019-11-26 02:12:58,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3757 states to 3757 states and 5040 transitions. [2019-11-26 02:12:58,713 INFO L78 Accepts]: Start accepts. Automaton has 3757 states and 5040 transitions. Word has length 106 [2019-11-26 02:12:58,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:58,714 INFO L462 AbstractCegarLoop]: Abstraction has 3757 states and 5040 transitions. [2019-11-26 02:12:58,714 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:58,714 INFO L276 IsEmpty]: Start isEmpty. Operand 3757 states and 5040 transitions. [2019-11-26 02:12:58,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-11-26 02:12:58,721 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:58,721 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:58,722 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:58,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:58,722 INFO L82 PathProgramCache]: Analyzing trace with hash 1598475233, now seen corresponding path program 1 times [2019-11-26 02:12:58,722 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:58,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845113047] [2019-11-26 02:12:58,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:58,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:58,782 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-26 02:12:58,783 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845113047] [2019-11-26 02:12:58,783 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:58,783 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-26 02:12:58,783 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096617338] [2019-11-26 02:12:58,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:58,784 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:58,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:58,785 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:58,785 INFO L87 Difference]: Start difference. First operand 3757 states and 5040 transitions. Second operand 3 states. [2019-11-26 02:12:59,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:12:59,184 INFO L93 Difference]: Finished difference Result 10808 states and 14581 transitions. [2019-11-26 02:12:59,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:12:59,184 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 109 [2019-11-26 02:12:59,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:12:59,199 INFO L225 Difference]: With dead ends: 10808 [2019-11-26 02:12:59,199 INFO L226 Difference]: Without dead ends: 7055 [2019-11-26 02:12:59,205 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:59,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7055 states. [2019-11-26 02:12:59,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7055 to 7051. [2019-11-26 02:12:59,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7051 states. [2019-11-26 02:12:59,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7051 states to 7051 states and 9461 transitions. [2019-11-26 02:12:59,508 INFO L78 Accepts]: Start accepts. Automaton has 7051 states and 9461 transitions. Word has length 109 [2019-11-26 02:12:59,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:12:59,509 INFO L462 AbstractCegarLoop]: Abstraction has 7051 states and 9461 transitions. [2019-11-26 02:12:59,509 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:12:59,509 INFO L276 IsEmpty]: Start isEmpty. Operand 7051 states and 9461 transitions. [2019-11-26 02:12:59,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2019-11-26 02:12:59,519 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:12:59,519 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:12:59,519 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:12:59,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:12:59,520 INFO L82 PathProgramCache]: Analyzing trace with hash 1504978467, now seen corresponding path program 1 times [2019-11-26 02:12:59,520 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:12:59,520 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362412439] [2019-11-26 02:12:59,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:12:59,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:12:59,560 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2019-11-26 02:12:59,560 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362412439] [2019-11-26 02:12:59,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:12:59,561 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:12:59,561 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977647932] [2019-11-26 02:12:59,561 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:12:59,562 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:12:59,563 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:12:59,563 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:12:59,563 INFO L87 Difference]: Start difference. First operand 7051 states and 9461 transitions. Second operand 3 states. [2019-11-26 02:13:00,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:13:00,050 INFO L93 Difference]: Finished difference Result 20801 states and 27875 transitions. [2019-11-26 02:13:00,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:13:00,051 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 109 [2019-11-26 02:13:00,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:13:00,077 INFO L225 Difference]: With dead ends: 20801 [2019-11-26 02:13:00,078 INFO L226 Difference]: Without dead ends: 13767 [2019-11-26 02:13:00,084 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:13:00,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13767 states. [2019-11-26 02:13:00,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13767 to 12927. [2019-11-26 02:13:00,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12927 states. [2019-11-26 02:13:00,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12927 states to 12927 states and 17213 transitions. [2019-11-26 02:13:00,505 INFO L78 Accepts]: Start accepts. Automaton has 12927 states and 17213 transitions. Word has length 109 [2019-11-26 02:13:00,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:13:00,505 INFO L462 AbstractCegarLoop]: Abstraction has 12927 states and 17213 transitions. [2019-11-26 02:13:00,505 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:13:00,506 INFO L276 IsEmpty]: Start isEmpty. Operand 12927 states and 17213 transitions. [2019-11-26 02:13:00,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-26 02:13:00,521 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:13:00,521 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:13:00,521 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:13:00,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:13:00,522 INFO L82 PathProgramCache]: Analyzing trace with hash 1980777405, now seen corresponding path program 1 times [2019-11-26 02:13:00,522 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:13:00,522 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956543569] [2019-11-26 02:13:00,522 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:13:00,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:13:00,572 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:13:00,572 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956543569] [2019-11-26 02:13:00,572 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:13:00,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-26 02:13:00,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874370618] [2019-11-26 02:13:00,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-26 02:13:00,573 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:13:00,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-26 02:13:00,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:00,574 INFO L87 Difference]: Start difference. First operand 12927 states and 17213 transitions. Second operand 4 states. [2019-11-26 02:13:01,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:13:01,572 INFO L93 Difference]: Finished difference Result 36137 states and 49181 transitions. [2019-11-26 02:13:01,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-26 02:13:01,573 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 110 [2019-11-26 02:13:01,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:13:01,607 INFO L225 Difference]: With dead ends: 36137 [2019-11-26 02:13:01,607 INFO L226 Difference]: Without dead ends: 23241 [2019-11-26 02:13:01,622 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:01,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23241 states. [2019-11-26 02:13:02,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23241 to 17759. [2019-11-26 02:13:02,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17759 states. [2019-11-26 02:13:02,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17759 states to 17759 states and 24125 transitions. [2019-11-26 02:13:02,370 INFO L78 Accepts]: Start accepts. Automaton has 17759 states and 24125 transitions. Word has length 110 [2019-11-26 02:13:02,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:13:02,371 INFO L462 AbstractCegarLoop]: Abstraction has 17759 states and 24125 transitions. [2019-11-26 02:13:02,371 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-26 02:13:02,371 INFO L276 IsEmpty]: Start isEmpty. Operand 17759 states and 24125 transitions. [2019-11-26 02:13:02,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-26 02:13:02,394 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:13:02,394 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:13:02,394 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:13:02,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:13:02,394 INFO L82 PathProgramCache]: Analyzing trace with hash 953352303, now seen corresponding path program 1 times [2019-11-26 02:13:02,394 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:13:02,395 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660453599] [2019-11-26 02:13:02,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:13:02,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:13:02,475 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:13:02,475 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660453599] [2019-11-26 02:13:02,476 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:13:02,476 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-26 02:13:02,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974967129] [2019-11-26 02:13:02,477 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-26 02:13:02,477 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:13:02,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-26 02:13:02,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:02,477 INFO L87 Difference]: Start difference. First operand 17759 states and 24125 transitions. Second operand 4 states. [2019-11-26 02:13:03,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:13:03,626 INFO L93 Difference]: Finished difference Result 42677 states and 58003 transitions. [2019-11-26 02:13:03,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-26 02:13:03,627 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 111 [2019-11-26 02:13:03,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:13:03,649 INFO L225 Difference]: With dead ends: 42677 [2019-11-26 02:13:03,650 INFO L226 Difference]: Without dead ends: 18677 [2019-11-26 02:13:03,670 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:03,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18677 states. [2019-11-26 02:13:04,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18677 to 14071. [2019-11-26 02:13:04,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14071 states. [2019-11-26 02:13:04,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14071 states to 14071 states and 18373 transitions. [2019-11-26 02:13:04,420 INFO L78 Accepts]: Start accepts. Automaton has 14071 states and 18373 transitions. Word has length 111 [2019-11-26 02:13:04,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:13:04,421 INFO L462 AbstractCegarLoop]: Abstraction has 14071 states and 18373 transitions. [2019-11-26 02:13:04,421 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-26 02:13:04,421 INFO L276 IsEmpty]: Start isEmpty. Operand 14071 states and 18373 transitions. [2019-11-26 02:13:04,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-26 02:13:04,440 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:13:04,441 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:13:04,441 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:13:04,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:13:04,441 INFO L82 PathProgramCache]: Analyzing trace with hash -471155920, now seen corresponding path program 1 times [2019-11-26 02:13:04,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:13:04,442 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309142632] [2019-11-26 02:13:04,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:13:04,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:13:04,511 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-26 02:13:04,512 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309142632] [2019-11-26 02:13:04,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:13:04,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-26 02:13:04,513 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710389626] [2019-11-26 02:13:04,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-26 02:13:04,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:13:04,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-26 02:13:04,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:13:04,514 INFO L87 Difference]: Start difference. First operand 14071 states and 18373 transitions. Second operand 3 states. [2019-11-26 02:13:05,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:13:05,227 INFO L93 Difference]: Finished difference Result 24871 states and 32610 transitions. [2019-11-26 02:13:05,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-26 02:13:05,227 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 135 [2019-11-26 02:13:05,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:13:05,239 INFO L225 Difference]: With dead ends: 24871 [2019-11-26 02:13:05,239 INFO L226 Difference]: Without dead ends: 14055 [2019-11-26 02:13:05,248 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-26 02:13:05,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14055 states. [2019-11-26 02:13:05,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14055 to 13863. [2019-11-26 02:13:05,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13863 states. [2019-11-26 02:13:05,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13863 states to 13863 states and 17549 transitions. [2019-11-26 02:13:05,805 INFO L78 Accepts]: Start accepts. Automaton has 13863 states and 17549 transitions. Word has length 135 [2019-11-26 02:13:05,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:13:05,805 INFO L462 AbstractCegarLoop]: Abstraction has 13863 states and 17549 transitions. [2019-11-26 02:13:05,805 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-26 02:13:05,805 INFO L276 IsEmpty]: Start isEmpty. Operand 13863 states and 17549 transitions. [2019-11-26 02:13:05,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 136 [2019-11-26 02:13:05,813 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:13:05,813 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:13:05,813 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:13:05,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:13:05,814 INFO L82 PathProgramCache]: Analyzing trace with hash -137745167, now seen corresponding path program 1 times [2019-11-26 02:13:05,814 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:13:05,814 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795764295] [2019-11-26 02:13:05,814 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:13:05,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-26 02:13:05,884 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-26 02:13:05,884 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795764295] [2019-11-26 02:13:05,885 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-26 02:13:05,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-26 02:13:05,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768918232] [2019-11-26 02:13:05,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-26 02:13:05,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2019-11-26 02:13:05,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-26 02:13:05,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:05,887 INFO L87 Difference]: Start difference. First operand 13863 states and 17549 transitions. Second operand 4 states. [2019-11-26 02:13:06,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-26 02:13:06,514 INFO L93 Difference]: Finished difference Result 24399 states and 30906 transitions. [2019-11-26 02:13:06,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-26 02:13:06,516 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 135 [2019-11-26 02:13:06,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-26 02:13:06,525 INFO L225 Difference]: With dead ends: 24399 [2019-11-26 02:13:06,525 INFO L226 Difference]: Without dead ends: 13823 [2019-11-26 02:13:06,530 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-26 02:13:06,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13823 states. [2019-11-26 02:13:07,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13823 to 13823. [2019-11-26 02:13:07,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13823 states. [2019-11-26 02:13:07,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13823 states to 13823 states and 17213 transitions. [2019-11-26 02:13:07,015 INFO L78 Accepts]: Start accepts. Automaton has 13823 states and 17213 transitions. Word has length 135 [2019-11-26 02:13:07,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-26 02:13:07,016 INFO L462 AbstractCegarLoop]: Abstraction has 13823 states and 17213 transitions. [2019-11-26 02:13:07,016 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-26 02:13:07,016 INFO L276 IsEmpty]: Start isEmpty. Operand 13823 states and 17213 transitions. [2019-11-26 02:13:07,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2019-11-26 02:13:07,024 INFO L402 BasicCegarLoop]: Found error trace [2019-11-26 02:13:07,024 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-26 02:13:07,024 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-26 02:13:07,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-26 02:13:07,025 INFO L82 PathProgramCache]: Analyzing trace with hash -1009703305, now seen corresponding path program 1 times [2019-11-26 02:13:07,025 INFO L163 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2019-11-26 02:13:07,025 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045566282] [2019-11-26 02:13:07,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-26 02:13:07,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-26 02:13:07,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-26 02:13:07,155 INFO L174 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2019-11-26 02:13:07,156 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-26 02:13:07,295 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.11 02:13:07 BoogieIcfgContainer [2019-11-26 02:13:07,295 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-26 02:13:07,296 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-26 02:13:07,296 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-26 02:13:07,296 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-26 02:13:07,297 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 02:12:52" (3/4) ... [2019-11-26 02:13:07,298 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-26 02:13:07,498 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_07c1da24-4195-4618-be81-f0edbb04a9b5/bin/utaipan/witness.graphml [2019-11-26 02:13:07,498 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-26 02:13:07,500 INFO L168 Benchmark]: Toolchain (without parser) took 18527.56 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 950.1 MB in the beginning and 1.8 GB in the end (delta: -822.7 MB). Peak memory consumption was 719.3 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,501 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-26 02:13:07,501 INFO L168 Benchmark]: CACSL2BoogieTranslator took 453.56 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -171.9 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,501 INFO L168 Benchmark]: Boogie Procedure Inliner took 57.42 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-26 02:13:07,502 INFO L168 Benchmark]: Boogie Preprocessor took 55.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,502 INFO L168 Benchmark]: RCFGBuilder took 2643.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 864.6 MB in the end (delta: 250.8 MB). Peak memory consumption was 250.8 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,502 INFO L168 Benchmark]: TraceAbstraction took 15110.55 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 864.6 MB in the beginning and 1.8 GB in the end (delta: -952.5 MB). Peak memory consumption was 452.6 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,503 INFO L168 Benchmark]: Witness Printer took 202.31 ms. Allocated memory is still 2.6 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 44.3 MB). Peak memory consumption was 44.3 MB. Max. memory is 11.5 GB. [2019-11-26 02:13:07,504 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 453.56 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 136.8 MB). Free memory was 950.1 MB in the beginning and 1.1 GB in the end (delta: -171.9 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 57.42 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.51 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 2643.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 864.6 MB in the end (delta: 250.8 MB). Peak memory consumption was 250.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 15110.55 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.4 GB). Free memory was 864.6 MB in the beginning and 1.8 GB in the end (delta: -952.5 MB). Peak memory consumption was 452.6 MB. Max. memory is 11.5 GB. * Witness Printer took 202.31 ms. Allocated memory is still 2.6 GB. Free memory was 1.8 GB in the beginning and 1.8 GB in the end (delta: 44.3 MB). Peak memory consumption was 44.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L228] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L247] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L266] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L285] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L304] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L90] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L101] COND TRUE 1 [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L125] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L136] COND TRUE 1 [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L160] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L171] COND TRUE 1 [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L195] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L206] COND TRUE 1 [L208] t4_pc = 1 [L209] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND TRUE \read(tmp_ndt_1) [L416] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L49] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L60] COND TRUE 1 [L63] E_1 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND TRUE E_1 == 1 [L249] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND TRUE \read(tmp___0) [L614] t1_st = 0 [L263] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L65] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L68] COND TRUE 1 [L70] m_pc = 1 [L71] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND TRUE \read(tmp_ndt_2) [L430] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L90] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L93] COND TRUE t1_pc == 1 [L109] E_2 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND TRUE E_2 == 1 [L268] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND TRUE \read(tmp___1) [L622] t2_st = 0 [L282] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L111] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L101] COND TRUE 1 [L103] t1_pc = 1 [L104] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND TRUE \read(tmp_ndt_3) [L444] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L125] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L128] COND TRUE t2_pc == 1 [L144] E_3 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND TRUE E_3 == 1 [L287] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND TRUE \read(tmp___2) [L630] t3_st = 0 [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L146] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L136] COND TRUE 1 [L138] t2_pc = 1 [L139] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND TRUE \read(tmp_ndt_4) [L458] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L160] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L163] COND TRUE t3_pc == 1 [L179] E_4 = 1 [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L228] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L229] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L238] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L247] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L248] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L257] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L266] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L267] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L276] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L285] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L286] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L295] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L304] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L305] COND TRUE E_4 == 1 [L306] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND TRUE \read(tmp___3) [L638] t4_st = 0 [L181] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L171] COND TRUE 1 [L173] t3_pc = 1 [L174] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND TRUE \read(tmp_ndt_5) [L472] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L195] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L198] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 178 locations, 1 error locations. Result: UNSAFE, OverallTime: 15.0s, OverallIterations: 23, TraceHistogramMax: 3, AutomataDifference: 7.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7914 SDtfs, 5120 SDslu, 6535 SDs, 0 SdLazy, 686 SolverSat, 195 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 79 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=17759occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.1s AutomataMinimizationTime, 22 MinimizatonAttempts, 18348 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 1858 NumberOfCodeBlocks, 1858 NumberOfCodeBlocksAsserted, 23 NumberOfCheckSat, 1697 ConstructedInterpolants, 0 QuantifiedInterpolants, 257147 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 22 InterpolantComputations, 22 PerfectInterpolantSequences, 265/265 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...